coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

Patch set updated for coreboot: intel/littleplains: Update with recent changes to mohonpeak
by Martin Roth 07 Dec '15

07 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12635 -gerrit commit f480f95fdb9a49b99ca575d60655a1d21b61c044 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 14:02:16 2015 -0700 intel/littleplains: Update with recent changes to mohonpeak - Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/Kconfig | 10 +++------- src/mainboard/intel/littleplains/config_seabios | 5 +++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig index 2fc5cb1..bde944c 100644 --- a/src/mainboard/intel/littleplains/Kconfig +++ b/src/mainboard/intel/littleplains/Kconfig @@ -58,16 +58,12 @@ config UART_FOR_CONSOLE help The Little Plains board uses COM2 (2f8) for the serial console. -config SEABIOS_MALLOC_UPPERMEMORY - bool - default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" help The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment. -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff60040 - endif # BOARD_INTEL_LITTLEPLAINS diff --git a/src/mainboard/intel/littleplains/config_seabios b/src/mainboard/intel/littleplains/config_seabios new file mode 100644 index 0000000..f688f2b --- /dev/null +++ b/src/mainboard/intel/littleplains/config_seabios @@ -0,0 +1,5 @@ +# The Avoton/Rangeley chip does not allow devices to write into the 0xe000 +# segment. This means that USB/SATA devices will not work in SeaBIOS unless +# we put the SeaBIOS buffer area down in the 0x9000 segment. + +# CONFIG_MALLOC_UPPERMEMORY is not set

1 0

Patch merged into coreboot/master: MAINTAINERS: Designate Intel maintainers for FSP 1.0 Rangeley
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit 980a8c1d0290a7335c2b7b8712c744897ecadbc5 Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 08:33:35 2015 -0700 MAINTAINERS: Designate Intel maintainers for FSP 1.0 Rangeley After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I7af7b37a5e3a233cc29adb20dd5bb8fa07dbdd53 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12643 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian <david.guckian(a)intel.com> See https://review.coreboot.org/12643 for details. -gerrit

1 0

New patch to review for coreboot: AMD/bettong: Add missing uart.c for UART
by Zheng Bao 07 Dec '15

07 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12669 -gerrit commit 5f05aef81542996384b85059031d7d7f4661fc31 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Dec 7 23:01:07 2015 +0800 AMD/bettong: Add missing uart.c for UART Change-Id: Ie49732c6874f2b443e314eb3412ddee054d9c0bb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/pi/hudson/uart.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c new file mode 100644 index 0000000..5d88204 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); +} + +unsigned int uart_platform_refclk(void) +{ + return 48000000; +}

1 0

New patch to review for coreboot: AMD/bettong: Remove the useless period (trivial)
by Zheng Bao 07 Dec '15

07 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12668 -gerrit commit 318e18ae3707e2d8e737ccdf9c8b0453586a829e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Dec 7 22:59:45 2015 +0800 AMD/bettong: Remove the useless period (trivial) It seems that no one add period in Kconfig. Change-Id: Ie9c585a8e6f1a73036b92b2873dc19284d82dc39 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/pi/hudson/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 94a313d..aa55339 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -229,7 +229,7 @@ config AZ_PIN endif config HUDSON_UART - bool "UART controller on Kern." + bool "UART controller on Kern" default n depends on SOUTHBRIDGE_AMD_PI_KERN select DRIVERS_UART_8250MEM

1 0

Patch set updated for coreboot: uart8250mem: Change the delay for uart (Don't merge)
by Zheng Bao 07 Dec '15

07 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12343 -gerrit commit 5a311441b061f8cbf3d4a10420a10394355cbd8e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sat Nov 21 12:23:10 2015 +0800 uart8250mem: Change the delay for uart (Don't merge) Change-Id: I6131adbe24a0ee6dfd47d00265fd8583ef22ec0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/drivers/uart/uart8250mem.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 278ddb8..9cb29f0 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -32,6 +32,12 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) +static void my_delay(int delay) +{ + while (delay --) + outb(0xaa, 0x80); +} + #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) static uint8_t uart8250_read(void *base, uint8_t reg) { @@ -63,7 +69,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_tx_byte(base)) - udelay(1); + my_delay(1); uart8250_write(base, UART8250_TBR, data); } @@ -71,7 +77,7 @@ static void uart8250_mem_tx_flush(void *base) { unsigned long int i = FIFO_TIMEOUT; while(i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT)) - udelay(1); + my_delay(1); } static int uart8250_mem_can_rx_byte(void *base) @@ -83,7 +89,7 @@ static unsigned char uart8250_mem_rx_byte(void *base) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base)) - udelay(1); + my_delay(1); if (i) return uart8250_read(base, UART8250_RBR); else

1 0

New patch to review for coreboot: AMD/bettong: Remove the device definitions in ASL
by Zheng Bao 07 Dec '15

07 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12667 -gerrit commit 55095a496cb1dc282a866c082f7f96d900e35389 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Dec 7 07:35:31 2015 -0500 AMD/bettong: Remove the device definitions in ASL If we include the device definitions in ASL, there is "Error Code 12 This device cannot find enough free resources" in device manager. After the definitions are removed, we can still see the i2c, uart, gpio entries in device manager. I assume this definitions are already provided by AGESA is SSDT. Since this fixes the warning message in device manager, we can abandon the change below. ---------------------- https://review.coreboot.org/#/c/11747/ AMD/Bettong: DSDT table: Reserved MMIO space for FCH ----------------------- Change-Id: Icc1e6d7790a24cb0b77ca2ed400ad99f09a806de Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/acpi/carrizo_fch.asl | 101 ------------------------- src/mainboard/amd/bettong/dsdt.asl | 3 - 2 files changed, 104 deletions(-) diff --git a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl deleted file mode 100644 index 5bfb366..0000000 --- a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -Device(GPIO) { - Name (_HID, "AMD0030") - Name (_CID, "AMD0030") - Name(_UID, 0) - - Method (_CRS, 0x0, NotSerialized) { - Name (RBUF, ResourceTemplate () { - // - // Interrupt resource. In this example, banks 0 & 1 share the same - // interrupt to the parent controller and similarly banks 2 & 3. - // - // N.B. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform - // - Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} - - // - // Memory resource. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform. - // - Memory32Fixed(ReadWrite, 0xFED81500, 0x300) - }) - - Return (RBUF) - } - - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(FUR0) { - Name(_HID,"AMD0020") - Name(_UID,0x0) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {10} - Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000) - }) - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(FUR1) { - Name(_HID,"AMD0020") - Name(_UID,0x1) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {11} - Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000) - }) - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(I2CA) { - Name(_HID,"AMD0010") - Name(_UID,0x0) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {3} - Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) - }) - - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} - -Device(I2CB) -{ - Name(_HID,"AMD0010") - Name(_UID,0x1) - Name(_CRS, ResourceTemplate() { - IRQ(Edge, ActiveHigh, Exclusive) {15} - Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000) - }) - Method (_STA, 0x0, NotSerialized) { - Return (0x0F) - } -} diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl index 2e6c96c..888d5cd 100644 --- a/src/mainboard/amd/bettong/dsdt.asl +++ b/src/mainboard/amd/bettong/dsdt.asl @@ -69,9 +69,6 @@ DefinitionBlock ( /* Describe PCI INT[A-H] for the Southbridge */ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> - /* Describe the devices in the Southbridge */ - #include "acpi/carrizo_fch.asl" - } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */

1 0

Patch set updated for coreboot: amdfwtool: Fill all the romsig entries as 0
by Zheng Bao 07 Dec '15

07 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12665 -gerrit commit f719b07955a298e5b6159e6b18228e29e7264530 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Dec 7 05:17:23 2015 -0500 amdfwtool: Fill all the romsig entries as 0 I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant with the case before the amdfwtool is used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f958aba..b08a961 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -377,6 +377,9 @@ int main(int argc, char **argv) current = AMD_ROMSIG_OFFSET; amd_romsig = rom + AMD_ROMSIG_OFFSET; amd_romsig[0] = 0x55AA55AA; /* romsig */ + amd_romsig[1] = 0; + amd_romsig[2] = 0; + amd_romsig[3] = 0; current += 0x20; /* size of ROMSIG */

1 0

New patch to review for coreboot: amdfwtool: Fill all the romsig entries as 0
by Zheng Bao 07 Dec '15

07 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12665 -gerrit commit d813ea0b167304f62748f2fa97e05ecebe71a834 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Dec 7 05:11:20 2015 -0500 amdfwtool: Fill all the romsig entries as 0 I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f958aba..7b04921 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -377,6 +377,10 @@ int main(int argc, char **argv) current = AMD_ROMSIG_OFFSET; amd_romsig = rom + AMD_ROMSIG_OFFSET; amd_romsig[0] = 0x55AA55AA; /* romsig */ + amd_romsig[1] = 0; + amd_romsig[2] = 0; + amd_romsig[3] = 0; + amd_romsig[4] = 0; current += 0x20; /* size of ROMSIG */

1 0

Patch set updated for coreboot: mohonpeak/Kconfig: Whitespace fixes
by Martin Roth 07 Dec '15

07 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12655 -gerrit commit 0e8bacbb7249eaeab780cda1c8cd0daff06e8e02 Author: Martin Roth <martinroth(a)google.com> Date: Sun Dec 6 12:14:42 2015 -0700 mohonpeak/Kconfig: Whitespace fixes Auto-indent did me wrong, and I didn't notice it. Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/mohonpeak/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 8f6e077..3916fa3 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -71,10 +71,10 @@ config UART_FOR_CONSOLE help The Mohon Peak board uses COM2 (2f8) for the serial console. - config PAYLOAD_CONFIGFILE - string - default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" - help +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" + help The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

1 0

New patch to review for coreboot: intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside Kconfig
by Martin Roth 07 Dec '15

07 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12664 -gerrit commit 6762831e59c9f7773cae8410fac2cd19fe38e15b Author: Martin Roth <martinroth(a)google.com> Date: Sun Dec 6 19:44:02 2015 -0700 intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside Kconfig The CONFIG_ is only used for Kconfig symbols outside of Kconfig. If used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when it was used in the C code. Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/strago/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 1512a46..364e242 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -53,7 +53,7 @@ config VBOOT_RAMSTAGE_INDEX config VBOOT_REFCODE_INDEX hex default 0x3 -if !CONFIG_GOP_SUPPORT +if !GOP_SUPPORT config VGA_BIOS_FILE string default "3rdparty/blobs/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT @@ -62,5 +62,5 @@ config VGA_BIOS_ID string default "8086,22b1" if C0_DISP_SUPPORT default "8086,22b0" if !C0_DISP_SUPPORT -endif +endif # GOP_SUPPORT endif # BOARD_INTEL_STRAGO

1 0

← Newer
1
...
49
50
51
52
53
54
55
...
76
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2015