coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

Patch set updated for coreboot: Switch to fmap based firmware layout
by Patrick Georgi 07 Dec '15

07 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11692 -gerrit commit 5032a9bdb31c02cc328816850fd798d45ad49d53 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Sep 16 18:10:52 2015 +0200 Switch to fmap based firmware layout We still add a master header for compatibility purposes, and the default layouts don't cover anything non-coreboot (eg. IFD regions) yet. The default layouts can be overridden by specifying an fmd file, from which the fmap is generated. Future work: - map IFD regions to fmap regions - non-x86: build minimalistic trampolines that jump into the first cbfs file, so the bootblock can be part of CBFS instead of reserving a whole 64K for it. - teach coreboot's cbfs code to work without the master header - teach coreboot's cbfs code to work on different fmap regions Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 90 +++++++++++++++++++++++++++++++++++++++++-- util/cbfstool/default-x86.fmd | 15 ++++++++ util/cbfstool/default.fmd | 18 +++++++++ 3 files changed, 119 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6a553fb..217e779 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -619,10 +619,92 @@ prebuild-files = \ $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) - $(CBFSTOOL) $@.tmp create \ - -B $(objcbfs)/bootblock.bin \ - $(CBFSTOOL_PRE1_OPTS) +ifeq ($(CONFIG_FMDFILE),) +# For a description of the flash layout described by these variables, check +# the $(DEFAULT_FLASHMAP) .fmd files. +ifeq ($(CONFIG_ARCH_X86),y) +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd +# entire flash +FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE) +FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE)) +else +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd +# entire flash +FMAP_ROM_ADDR := 0 +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := 0 +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0x20000 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) +FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +endif + +$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) + sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ + $(DEFAULT_FLASHMAP) > $@.tmp + mv $@.tmp $@ +else +$(obj)/fmap.fmd: $(CONFIG_FMDFILE) + cp $< $@ +endif + +# generated at the same time as fmap.fmap +$(obj)/fmap.h: $(obj)/fmap.fmap + +$(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) + $(FMAPTOOL) -h $(obj)/fmap.h $< $@ + +$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap + $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap +ifeq ($(CONFIG_ARCH_X86),y) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) +else + # don't add bootblock to cbfs yet, it's just a waste of space + true $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b 0 + $(CBFSTOOL) $@.tmp write -u \ + -r BOOTBLOCK \ + -f $(objcbfs)/bootblock.bin + # make space for the CBFS master header pointer. "ptr_" is just + # arbitrary 4 bytes that will be overwritten by add-master-header. + printf "ptr_" > $@.tmp.2 + $(CBFSTOOL) $@.tmp add \ + -f $@.tmp.2 \ + -n "header pointer" \ + -t "cbfs header" \ + -b -4 + rm -f $@.tmp.2 +endif + $(CBFSTOOL) $@.tmp add-master-header $(prebuild-files) true mv $@.tmp $@ else diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd new file mode 100644 index 0000000..f344ab2 --- /dev/null +++ b/util/cbfstool/default-x86.fmd @@ -0,0 +1,15 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd new file mode 100644 index 0000000..32ddfa4 --- /dev/null +++ b/util/cbfstool/default.fmd @@ -0,0 +1,18 @@ +# layout for firmware when flash address space matches used address layout +# +-------------+ <-- 0 +# | unspecified | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 128K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + BOOTBLOCK 128K + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +}

1 0

Patch merged into coreboot/master: xcompile: Don't warn on missing power8 compiler
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit 359737d89700998048e1b04d8d0ae49b461cbbcb Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 12:38:27 2015 -0700 xcompile: Don't warn on missing power8 compiler Until there's a reason to, don't print a warning about the missing power8 compiler. Change-Id: I47c60e0a16892f0fa228e1439e0424926bca00a4 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12634 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/12634 for details. -gerrit

1 0

Patch set updated for coreboot: toolchain.inc: verify tool variable validity before using it.
by Martin Roth 07 Dec '15

07 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12649 -gerrit commit 7cfd8304b4d9681a64bad5426b16e5fcd3e6ab0a Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 14:29:37 2015 -0700 toolchain.inc: verify tool variable validity before using it. If the toolchain for a stage/architecture wasn't present, we'd call the shell with '-v', generating an ugly warning: /bin/sh: - : invalid option Usage: /bin/sh [GNU long option] [option] ... /bin/sh [GNU long option] [option] script-file ... GNU long options: ... Change-Id: Icd6d7a00083ee1695591ff96da36b7868be0c2f0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- toolchain.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index 1b73ce9..7246580 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -155,10 +155,10 @@ IASLFAIL:=0 ifeq ($(CONFIG_COMPILER_GCC),y) ifneq ($(CONFIG_ANY_TOOLCHAIN),y) $(foreach arch,$(sort $(foreach stage,$(COREBOOT_STANDARD_STAGES),$(ARCH-$(stage)-y))), \ - $(if $(shell $(CC_$(arch)) -v 2>&1 |grep -q "gcc version .*coreboot toolchain" || echo not-coreboot), \ + $(if $(shell if [ -n "$(CC_$(arch))" ]; then $(CC_$(arch)) -v 2>&1 |grep -q "gcc version .*coreboot toolchain" || echo not-coreboot; else echo not-coreboot; fi), \ $(eval COMPILERFAIL:=1)$(warning Please use the coreboot toolchain for '$(arch)'))) #if iasl doesn't match the current coreboot version, fail the test -$(if $(shell $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || echo not-coreboot), \ +$(if $(shell if [ -n "$(IASL)" ]; then $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || echo not-coreboot; else echo not-coreboot; fi), \ $(eval COMPILERFAIL:=1)$(eval IASLFAIL:=1)$(warning Please use the coreboot toolchain version of iasl - $(shell util/crossgcc/buildgcc -s iasl))) endif endif

1 0

Patch set updated for coreboot: intel/littleplains: Update with recent changes to mohonpeak
by Martin Roth 07 Dec '15

07 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12635 -gerrit commit 74d4748afa8d0b5dc963113ca160bb45dbb6140f Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 14:02:16 2015 -0700 intel/littleplains: Update with recent changes to mohonpeak - Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/Kconfig | 10 +++------- src/mainboard/intel/littleplains/config_seabios | 5 +++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig index 2fc5cb1..bde944c 100644 --- a/src/mainboard/intel/littleplains/Kconfig +++ b/src/mainboard/intel/littleplains/Kconfig @@ -58,16 +58,12 @@ config UART_FOR_CONSOLE help The Little Plains board uses COM2 (2f8) for the serial console. -config SEABIOS_MALLOC_UPPERMEMORY - bool - default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" help The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment. -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff60040 - endif # BOARD_INTEL_LITTLEPLAINS diff --git a/src/mainboard/intel/littleplains/config_seabios b/src/mainboard/intel/littleplains/config_seabios new file mode 100644 index 0000000..f688f2b --- /dev/null +++ b/src/mainboard/intel/littleplains/config_seabios @@ -0,0 +1,5 @@ +# The Avoton/Rangeley chip does not allow devices to write into the 0xe000 +# segment. This means that USB/SATA devices will not work in SeaBIOS unless +# we put the SeaBIOS buffer area down in the 0x9000 segment. + +# CONFIG_MALLOC_UPPERMEMORY is not set

1 0

Patch set updated for coreboot: soc/intel/common: Remove USE_FMAP - symbol doesn't exist
by Martin Roth 07 Dec '15

07 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12663 -gerrit commit 60af838fd8adbbbefc8769e930f79f08a189e5ef Author: Martin Roth <martinroth(a)google.com> Date: Sun Dec 6 19:18:37 2015 -0700 soc/intel/common: Remove USE_FMAP - symbol doesn't exist The USE_FMAP Kconfig symbol doesn't exist, so remove things that are depending on it not being enabled. Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/common/Kconfig | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 96d2b8e..028e915 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -8,26 +8,19 @@ if SOC_INTEL_COMMON config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n - help - If CONFIG_USE_FMAP is enabled, it is assumed that a flashmap - containing an RW_MRC_CACHE entry that specifies the location and size - of the cache will be added to the image and present at runtime. if CACHE_MRC_SETTINGS config MRC_SETTINGS_CACHE_BASE hex - depends on !USE_FMAP default 0xfffe0000 config MRC_SETTINGS_CACHE_SIZE hex - depends on !USE_FMAP default 0x10000 config MRC_SETTINGS_PROTECT bool "Enable protection on MRC settings" - depends on !USE_FMAP default n endif # CACHE_MRC_SETTINGS

1 0

New patch to review for coreboot: sb/amd/sr5650: Allow resource allocator to assign bus numbers
by Timothy Pearson 07 Dec '15

07 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12673 -gerrit commit 5e75397a6a75ca35dc03f57164711f1d1b7202c8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Dec 7 12:22:23 2015 -0600 sb/amd/sr5650: Allow resource allocator to assign bus numbers At some point in the past disconnected PCIe bridges were completely disabled to work around a hang on bridge probe. This hang was resolved at some point, and the disconnected PCIe bridges should be enabled to receive a bus number per the RPR. This resolves a slew of warnings in the Linux boot log regarding invalid bridge configurations for disconnected bridge devices. Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/pcie.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 762e632..e198b87 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -768,11 +768,12 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) if (res) { AtiPcieCfg.PortDetect |= 1 << port; } else { - /* If the training failed the disable the bridge to prevent subsequent - * lockup on bridge configuration register read during the PCI bus scan + /* Even though nothing is attached to this port + * the port needs to be "enabled" to obtain + * a bus number from the PCI resource allocator */ training_ok = 0; - dev->enabled = 0; + dev->enabled = 1; } } }

1 0

New patch to review for coreboot: fsp_baytrail: The E3800 PCU-SPI does not have the BBAR register
by Ben Gardner 07 Dec '15

07 Dec '15

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12671 -gerrit commit b8a99004e3e790fc37c40cdd266c62af5de17457 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Mon Dec 7 11:33:45 2015 -0600 fsp_baytrail: The E3800 PCU-SPI does not have the BBAR register The BBAR regsiter (BIOS Base Address Configuration Register) defined in the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet. Accessing it seems harmless, but should likely be avoided. Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/spi.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 2719373..adbc0e2 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -77,8 +77,7 @@ typedef struct ich9_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; + uint8_t _reserved3[16]; uint32_t fdoc; uint32_t fdod; uint8_t _reserved4[8]; @@ -105,7 +104,6 @@ typedef struct ich_spi_controller { unsigned databytes; uint8_t *status; uint16_t *control; - uint32_t *bbar; } ich_spi_controller; static ich_spi_controller cntlr; @@ -248,17 +246,6 @@ static void read_reg(const void *src, void *value, uint32_t size) } } -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { ich_spi_slave *slave = malloc(sizeof(*slave)); @@ -304,9 +291,7 @@ void spi_init(void) cntlr.databytes = sizeof(ich9_spi->fdata); cntlr.status = &ich9_spi->ssfs; cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); } int spi_claim_bus(struct spi_slave *slave)

1 0

New patch to review for coreboot: AMD/bettong: Add work status in README
by Zheng Bao 07 Dec '15

07 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12670 -gerrit commit 0fc054f30b11ba7dd5f19a2ae355f392ee58276b Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Dec 8 00:20:28 2015 +0800 AMD/bettong: Add work status in README I have to admit that I have no ability to debug the final issue. It requires HDT to debug. But the HDT needs to connect to AMD external domain and get the permission. And I need to move on. Maybe I will still work on Coreboot. Change-Id: I8bf955f8068124c3f45366d91dbb3e86bbc4e252 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/README | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/amd/bettong/README b/src/mainboard/amd/bettong/README index d834af4..5b82f44 100644 --- a/src/mainboard/amd/bettong/README +++ b/src/mainboard/amd/bettong/README @@ -6,6 +6,23 @@ The version is identified by a tag. All the changes will be pushed to coreboot community. ===== +12/08/2015 + +All the changes for TCMEF1F0 has been merged except +https://review.coreboot.org/#/c/12343/ + +The udelay() uses lapic_timer to set timer. It seems +the the lapic timer reset to 0 and stop after AP is +launched. I don't quite understand why it happens. + +Anyone need to use the MMIO UART, please change the +udelay to simple IO delay, as the above link says. +For the board that does not use MMIO UART, please +ignore this link. + +I have tested the snapshot XXXXXXXXXXXXX(TODO). + +===== Version: TCMEF1F0 Release Date: 09/29/2015 Changes from last version:

1 0

Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit 369b561315ca68d0cdedc38208105a513c7139b5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Dec 6 00:47:17 2015 -0600 mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock The existing code incorrectly used standard PCI access calls in the bootblock. Use the I/O PCI access calls as the normal PCI access mechanisms have not yet been set up. Also ensure the recovery jumper GPIO has been set to input mode before reading it. Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12651 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/12651 for details. -gerrit

1 0

Patch merged into coreboot/master: 3rdparty/blobs: Update for latest Carrizo Blobs
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit 9f656c0316640959c0ef4ce0e099849468fe515a Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 12 14:44:49 2015 -0700 3rdparty/blobs: Update for latest Carrizo Blobs Update the 3rdparty/blobs submodule to bring in the latest CarrizoPI binaries. Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12425 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12425 for details. -gerrit

1 0

← Newer
1
...
48
49
50
51
52
53
54
...
76
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2015