coreboot-gerrit December 2015

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Patch set updated for coreboot: build system: Switch to fmap based firmware layout
by Patrick Georgi 08 Dec '15

08 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11692 -gerrit commit fdca8ec7a80af2b3f4fc83f76fd367125160106d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Sep 16 18:10:52 2015 +0200 build system: Switch to fmap based firmware layout We still add a master header for compatibility purposes, and the default layouts don't cover anything non-coreboot (eg. IFD regions) yet. The default layouts can be overridden by specifying an fmd file, from which the fmap is generated. Future work: - map IFD regions to fmap regions - non-x86: build minimalistic trampolines that jump into the first cbfs file, so the bootblock can be part of CBFS instead of reserving a whole 64K for it. - teach coreboot's cbfs code to work without the master header - teach coreboot's cbfs code to work on different fmap regions Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 90 +++++++++++++++++++++++++++++++++++++++++-- util/cbfstool/default-x86.fmd | 15 ++++++++ util/cbfstool/default.fmd | 18 +++++++++ 3 files changed, 119 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6a553fb..217e779 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -619,10 +619,92 @@ prebuild-files = \ $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) - $(CBFSTOOL) $@.tmp create \ - -B $(objcbfs)/bootblock.bin \ - $(CBFSTOOL_PRE1_OPTS) +ifeq ($(CONFIG_FMDFILE),) +# For a description of the flash layout described by these variables, check +# the $(DEFAULT_FLASHMAP) .fmd files. +ifeq ($(CONFIG_ARCH_X86),y) +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd +# entire flash +FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE) +FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE)) +else +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd +# entire flash +FMAP_ROM_ADDR := 0 +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := 0 +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0x20000 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) +FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +endif + +$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) + sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ + $(DEFAULT_FLASHMAP) > $@.tmp + mv $@.tmp $@ +else +$(obj)/fmap.fmd: $(CONFIG_FMDFILE) + cp $< $@ +endif + +# generated at the same time as fmap.fmap +$(obj)/fmap.h: $(obj)/fmap.fmap + +$(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) + $(FMAPTOOL) -h $(obj)/fmap.h $< $@ + +$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap + $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap +ifeq ($(CONFIG_ARCH_X86),y) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) +else + # don't add bootblock to cbfs yet, it's just a waste of space + true $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b 0 + $(CBFSTOOL) $@.tmp write -u \ + -r BOOTBLOCK \ + -f $(objcbfs)/bootblock.bin + # make space for the CBFS master header pointer. "ptr_" is just + # arbitrary 4 bytes that will be overwritten by add-master-header. + printf "ptr_" > $@.tmp.2 + $(CBFSTOOL) $@.tmp add \ + -f $@.tmp.2 \ + -n "header pointer" \ + -t "cbfs header" \ + -b -4 + rm -f $@.tmp.2 +endif + $(CBFSTOOL) $@.tmp add-master-header $(prebuild-files) true mv $@.tmp $@ else diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd new file mode 100644 index 0000000..f344ab2 --- /dev/null +++ b/util/cbfstool/default-x86.fmd @@ -0,0 +1,15 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd new file mode 100644 index 0000000..32ddfa4 --- /dev/null +++ b/util/cbfstool/default.fmd @@ -0,0 +1,18 @@ +# layout for firmware when flash address space matches used address layout +# +-------------+ <-- 0 +# | unspecified | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 128K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + BOOTBLOCK 128K + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +}

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Patch set updated for coreboot: cbfstool: make top-aligned address work per-region
by Patrick Georgi 08 Dec '15

08 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12683 -gerrit commit 340062357df701a6e6cb806bda409e2d56d18ea9 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Dec 7 23:14:07 2015 +0100 cbfstool: make top-aligned address work per-region The former interpretation sprung from the x86 way of doing things (assuming top-alignment to 4GB). Extend the mechanism to work with CBFS regions residing elsewhere. It's compatible with x86 because the default region there resides at the old location, so things fall in place. It also makes more complex layouts and non-x86 layouts work with negative base addresses. Change-Id: Ibcde973d85bad5d1195d657559f527695478f46c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/cbfstool.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index fb4c8b5..ba98667 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -101,7 +101,7 @@ static bool region_is_modern_cbfs(const char *region) /* * Converts between offsets from the start of the specified image region and - * "top-aligned" offsets from the top of the entire flash image. Works in either + * "top-aligned" offsets from the top of the image region. Works in either * direction: pass in one type of offset and receive the other type. * N.B. A top-aligned offset is always a positive number, and should not be * confused with a top-aliged *address*, which is its arithmetic inverse. */ @@ -110,6 +110,14 @@ static unsigned convert_to_from_top_aligned(const struct buffer *region, { assert(region); + /* cover the situation where a negative base address is given by the + * user. Callers of this function negate it, so it'll be a positive + * number smaller than the region. + */ + if ((offset > 0) && (offset < region->size)) { + return region->size - offset; + } + size_t image_size = partitioned_file_total_size(param.image_file); return image_size - region->offset - offset; }

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Patch merged into coreboot/master: amdfwtool: Fill the first 3 romsig entries as 0
by gerrit＠coreboot.org 08 Dec '15

08 Dec '15

the following patch was just integrated into master: commit 85f362e9b6ec69ead84f22d5cf0f5f1995d08b6d Author: zbao <fishbaozi(a)gmail.com> Date: Mon Dec 7 05:17:23 2015 -0500 amdfwtool: Fill the first 3 romsig entries as 0 I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant with the case before the amdfwtool is used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/12665 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12665 for details. -gerrit

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Patch set updated for coreboot: amdfwtool: Fill the first 3 romsig entries as 0
by Zheng Bao 08 Dec '15

08 Dec '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12665 -gerrit commit e2dda328d9d160f5f93c4c3ca435be909f43a731 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Dec 7 05:17:23 2015 -0500 amdfwtool: Fill the first 3 romsig entries as 0 I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant with the case before the amdfwtool is used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f958aba..b08a961 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -377,6 +377,9 @@ int main(int argc, char **argv) current = AMD_ROMSIG_OFFSET; amd_romsig = rom + AMD_ROMSIG_OFFSET; amd_romsig[0] = 0x55AA55AA; /* romsig */ + amd_romsig[1] = 0; + amd_romsig[2] = 0; + amd_romsig[3] = 0; current += 0x20; /* size of ROMSIG */

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New patch to review for coreboot: soc/intel/fsp_baytrail: Adjust root port INT routing
by Martin Roth 07 Dec '15

07 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12684 -gerrit commit 3bfced94ab3621c90a417199fdeb18d3ff00e336 Author: Martin Roth <martinroth(a)google.com> Date: Mon Dec 7 16:50:47 2015 -0700 soc/intel/fsp_baytrail: Adjust root port INT routing Adjust the root port INT routing based on Bay Trail spec: Document Number: 538136, Rev. 3.9 Table 241. Interrupt Generated for INT[A-D] Interrupts INTA INTB INTC INTD Root Port 1 INTA# INTB# INTC# INTD# Root Port 2 INTD# INTA# INTB# INTC# Root Port 3 INTC# INTD# INTA# INTB# Root Port 4 INTB# INTC# INTD# INTA# Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/fsp_baytrail/southcluster.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 6182948..a49f6d7 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -208,6 +208,15 @@ static void write_pci_config_irqs(void) if (targ_dev == NULL || new_int_pin < 1) continue; + /* + * Adjust the INT routing for the PCIe root ports + * See 'Interrupt Generated for INT[A-D] Interrupts' + * Table 241 in Document Number: 538136, Rev. 3.9 + */ + if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV) + new_int_pin = (new_int_pin + + PCI_FUNC(targ_dev->path.pci.devfn)) % 4; + /* Get the original INT_PIN for record keeping */ original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);

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Patch merged into coreboot/master: northbridge/amd/agesa/agesawrapper.c: Fix Kconfig symbols
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit 6215b88aee845046a73613f1508e6fa779427add Author: Martin Roth <martinroth(a)google.com> Date: Fri Nov 27 11:35:54 2015 -0700 northbridge/amd/agesa/agesawrapper.c: Fix Kconfig symbols The Kconfig symbols were missing an underscore, so were not getting evaluated properly. Change-Id: I619cf3f44f44f9c9699482d64164d3db28cd4c8f Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/12559 for details. -gerrit

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Patch merged into coreboot/master: AMD/bettong: Remove the useless period (trivial)
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit e1e9ed37daa4d8fa3aa367a16300408185a63e43 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Dec 7 22:59:45 2015 +0800 AMD/bettong: Remove the useless period (trivial) It seems that no one add period in Kconfig. Change-Id: Ie9c585a8e6f1a73036b92b2873dc19284d82dc39 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/12668 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/12668 for details. -gerrit

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Patch merged into coreboot/master: intel/littleplains: Update with recent changes to mohonpeak
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit b790fe944d7533b65b37885e0aae43d9826e2086 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 14:02:16 2015 -0700 intel/littleplains: Update with recent changes to mohonpeak - Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12635 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian <david.guckian(a)intel.com> See https://review.coreboot.org/12635 for details. -gerrit

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Patch merged into coreboot/master: intel/common/firmware: Add option to configure SPI for EM100
by gerrit＠coreboot.org 07 Dec '15

07 Dec '15

the following patch was just integrated into master: commit b9de78beb67fdf5057e01af7aae198eaacb76d14 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 14:27:45 2015 -0700 intel/common/firmware: Add option to configure SPI for EM100 Add a Kconfig option to set the firmware descriptor to allow EM100 use. Change-Id: If5d7cd6ad671f0328ee5be0b5e660dbc837fcac3 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/12637 for details. -gerrit

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New patch to review for coreboot: cbfstool: make top-aligned address work per-region
by Patrick Georgi 07 Dec '15

07 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12683 -gerrit commit 6a8c7dafe6bd2937b53ac06b656bd3bff9634829 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Dec 7 23:14:07 2015 +0100 cbfstool: make top-aligned address work per-region The former interpretation sprung from the x86 way of doing things (assuming top-alignment to 4GB). Extend the mechanism to work with CBFS regions residing elsewhere. It's compatible with x86 because the default region there resides at the old location, so things fall in place. It also makes more complex layouts and non-x86 layouts work with negative base addresses. Change-Id: Ibcde973d85bad5d1195d657559f527695478f46c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/cbfstool.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index fb4c8b5..79c2277 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -101,7 +101,7 @@ static bool region_is_modern_cbfs(const char *region) /* * Converts between offsets from the start of the specified image region and - * "top-aligned" offsets from the top of the entire flash image. Works in either + * "top-aligned" offsets from the top of the image region. Works in either * direction: pass in one type of offset and receive the other type. * N.B. A top-aligned offset is always a positive number, and should not be * confused with a top-aliged *address*, which is its arithmetic inverse. */ @@ -110,6 +110,10 @@ static unsigned convert_to_from_top_aligned(const struct buffer *region, { assert(region); + if ((offset > 0) && (offset < region->size)) { + return region->size - offset; + } + size_t image_size = partitioned_file_total_size(param.image_file); return image_size - region->offset - offset; }

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coreboot-gerrit December 2015