coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: lib: Implement framework for retrieving WiFi regulatory domain
by Hannah Williams 16 Dec '15

16 Dec '15

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12744 -gerrit commit 213c001152569ce27981ffa51d966ddaa53ceaa1 Author: Felix Durairaj <felixx.durairaj(a)intel.com> Date: Fri Nov 20 15:51:35 2015 -0800 lib: Implement framework for retrieving WiFi regulatory domain Platforms that need to initialize WRDD package with the regulatory domain information should implement function wifi_regulatory_domain. A weak implementation is provided here. Reviewed-on: https://chromium-review.googlesource.com/314384 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I84e2acd748856437b40bbf997bf23f158c711712 Signed-off-by: fdurairx <felixx.durairaj(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/include/wrdd.h | 30 ++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 2 ++ src/lib/wrdd.c | 22 ++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/src/include/wrdd.h b/src/include/wrdd.h new file mode 100644 index 0000000..97fa5dc --- /dev/null +++ b/src/include/wrdd.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _WRDD_H_ +#define _WRDD_H_ + +#include <stdint.h> + +/* Default regulatory domain ID */ +#define WRDD_DEFAULT_REGULATORY_DOMAIN 0x4150 +/* INDONESIA regulatory domain ID */ +#define WRDD_REGULATORY_DOMAIN_INDONESIA 0x4944 + +/* Retrieve the regulatory domain information */ +uint16_t wifi_regulatory_domain(void); + +#endif /* _WRDD_H_ */ + diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 724391f..de1cadf 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -178,6 +178,8 @@ romstage-y += halt.c ramstage-y += halt.c smm-y += halt.c +ramstage-y += wrdd.c + ifneq ($(CONFIG_ARCH_X86),y) # X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c new file mode 100644 index 0000000..da082f8 --- /dev/null +++ b/src/lib/wrdd.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <wrdd.h> + +uint16_t __attribute__((weak)) wifi_regulatory_domain(void) +{ + return WRDD_DEFAULT_REGULATORY_DOMAIN; +}

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New patch to review for coreboot: Chromeos: Implement wifi_regulatory_domain using "regions" key in VPD
by Hannah Williams 16 Dec '15

16 Dec '15

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12743 -gerrit commit e5b77cac7c58ca9d4d4f129f81862e68d68a5ab5 Author: Felix Durairaj <felixx.durairaj(a)intel.com> Date: Fri Nov 20 16:18:42 2015 -0800 Chromeos: Implement wifi_regulatory_domain using "regions" key in VPD Implement wifi_regulatory_domain function by getting country code from VPD Reviewed-on: https://chromium-review.googlesource.com/314385 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Ia6a24df110a3860d404d345571007ae8965e9564 Signed-off-by: fdurairx <felixx.durairaj(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/cros_vpd.h | 2 + src/vendorcode/google/chromeos/wrdd.c | 76 +++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index ef84798..8697297 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -38,6 +38,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c +ramstage-y += wrdd.c ifeq ($(CONFIG_ARCH_X86)$(CONFIG_ARCH_MIPS),) bootblock-y += watchdog.c ramstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index 19658c2..ca9c320 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -7,6 +7,8 @@ #ifndef __CROS_VPD_H__ #define __CROS_VPD_H__ +#define CROS_VPD_WIFI_DOMAINKEY "regions" + /* * Reads VPD string value by key. * diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c new file mode 100644 index 0000000..ab27cc0 --- /dev/null +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <cpu/cpu.h> +#include <types.h> +#include <string.h> +#include <wrdd.h> +#include "cros_vpd.h" + +/* + * wrdd_domain_value is ISO 3166-2 + * ISO 3166-2 code consists of two parts, separated by a hyphen + * The first part is the ISO 3166-1 alpha-2 code of the country; + * The second part is a string of up to three alphanumeric characters + */ +struct wrdd_code_value_pair { + const char *code; + u16 value; +}; + +/* Retrieve the regulatory domain information from VPD and + * return it as an uint16. + * WARNING: if domain information is not found in the VPD, + * this function will fall back to the default value + */ +uint16_t wifi_regulatory_domain(void) +{ + static struct wrdd_code_value_pair wrdd_table[] = { + { + /* Indonesia + * Alpha-2 code 'ID' + * Full name 'the Republic of Indonesia' + * Alpha-3 code 'IDN' + * Numeric code '360' + */ + .code = "id", + .value = WRDD_REGULATORY_DOMAIN_INDONESIA + } + }; + const char *wrdd_domain_key = CROS_VPD_WIFI_DOMAINKEY; + int i; + struct wrdd_code_value_pair *p; + /* wrdd_domain_value is ISO 3166-2 */ + char wrdd_domain_code[7]; + + /* If not found for any reason fall backto the default value */ + if (!cros_vpd_gets(wrdd_domain_key, wrdd_domain_code, + sizeof(wrdd_domain_code))) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", wrdd_domain_key); + return WRDD_DEFAULT_REGULATORY_DOMAIN; + } + printk(BIOS_DEBUG, "Found '%s'='%s' in VPD\n", + wrdd_domain_key, wrdd_domain_code); + + for (i = 0; i < ARRAY_SIZE(wrdd_table); i++) { + p = &wrdd_table[i]; + if (strncmp(p->code, wrdd_domain_code, + ARRAY_SIZE(wrdd_domain_code)) == 0) + return p->value; + } + return WRDD_DEFAULT_REGULATORY_DOMAIN; +}

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Patch set updated for coreboot: soc/intel/fsp_baytrail: Adjust root port INT routing
by Martin Roth 16 Dec '15

16 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12684 -gerrit commit 62d17f492a6f6c3490b61287444e38351d9bf60d Author: Martin Roth <martinroth(a)google.com> Date: Mon Dec 7 16:50:47 2015 -0700 soc/intel/fsp_baytrail: Adjust root port INT routing Adjust the root port INT routing based on Bay Trail spec: Document Number: 538136, Rev. 3.9 Table 241. Interrupt Generated for INT[A-D] Interrupts INTA INTB INTC INTD Root Port 1 INTA# INTB# INTC# INTD# Root Port 2 INTD# INTA# INTB# INTC# Root Port 3 INTC# INTD# INTA# INTB# Root Port 4 INTB# INTC# INTD# INTA# Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/fsp_baytrail/southcluster.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 3ad692f..f493d2b 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -208,6 +208,16 @@ static void write_pci_config_irqs(void) if (targ_dev == NULL || new_int_pin < 1) continue; + /* + * Adjust the INT routing for the PCIe root ports + * See 'Interrupt Generated for INT[A-D] Interrupts' + * Table 241 in Document Number: 538136, Rev. 3.9 + */ + if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV && + targ_dev != irq_dev) + new_int_pin = ((new_int_pin - 1 + + PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1; + /* Get the original INT_PIN for record keeping */ original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);

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Patch merged into coreboot/master: intel/fsp_baytrail: change indent to use tabs
by gerrit＠coreboot.org 16 Dec '15

16 Dec '15

the following patch was just integrated into master: commit 6fc544d3d4479b8561e96e817f699323d25901a0 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Dec 9 11:33:39 2015 -0600 intel/fsp_baytrail: change indent to use tabs Change-Id: If0d0a15442738bab0e34f1b05513e7f8e8fa9afc Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> Reviewed-on: https://review.coreboot.org/12698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12698 for details. -gerrit

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Patch merged into coreboot/master: northbridge/intel ACPI: Remove unused Local method
by gerrit＠coreboot.org 16 Dec '15

16 Dec '15

the following patch was just integrated into master: commit 35272fd2379b0409e9e927ed64139993ff1f2e31 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 10 08:28:53 2015 -0700 northbridge/intel ACPI: Remove unused Local method The remainder of the divide operation was being placed into a Local, but was never being used, causing an IASL warning. Since this field is optional, just remove the Local. Fixes IASL warning: dsdt.aml 640:Divide (Multiply (CTDN, 125), 100, Local0, PL2V) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: I0b43ef638b1bc3e1163c45f31f8da57aa0d39e22 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12706 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> See https://review.coreboot.org/12706 for details. -gerrit

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New patch to review for coreboot: Braswell: Disable SD card detect simulation in FSP
by Hannah Williams 16 Dec '15

16 Dec '15

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12742 -gerrit commit 7544c5259e1d979f06ee8df419957959a2561a22 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Wed Oct 28 15:02:35 2015 -0700 Braswell: Disable SD card detect simulation in FSP Debounce for SD card detect takes a long time and thus affects boot time. Disabling SD card detect simulation in FSP through UPD Reviewed-on: https://chromium-review.googlesource.com/311850 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 1 + src/mainboard/intel/strago/devicetree.cb | 1 + src/soc/intel/braswell/chip.c | 3 +++ src/soc/intel/braswell/chip.h | 1 + 4 files changed, 6 insertions(+) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c36ae3d..6ba7b7c 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_freq" = "25" # 25MHz clock diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index bcf92f1..5250415 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_freq" = "25" # 25MHz clock diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 6cf3e8a..1e04faa 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -152,6 +152,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->PMIC_I2CBus = config->PMIC_I2CBus; params->ISPEnable = config->ISPEnable; params->ISPPciDevConfig = config->ISPPciDevConfig; + params->PcdSdDetectChk = config->PcdSdDetectChk; } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, @@ -312,6 +313,8 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, old->ISPEnable, new->ISPEnable); fsp_display_upd_value("ISPPciDevConfig", 1, old->ISPPciDevConfig, new->ISPPciDevConfig); + soc_display_upd_value("PcdSdDetectChk", 1, + old->PcdSdDetectChk, new->PcdSdDetectChk); } /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..acbfee0 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -135,6 +135,7 @@ struct soc_intel_braswell_config { UINT8 PMIC_I2CBus; UINT8 ISPEnable; UINT8 ISPPciDevConfig; + UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/ }; extern struct chip_operations soc_intel_braswell_ops;

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Patch set updated for coreboot: Strago: Enable native mode on sd card cd line
by Hannah Williams 16 Dec '15

16 Dec '15

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12741 -gerrit commit 91ef414c44a1f9c45d25d2d7f68b2eb5524fd2de Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Wed Nov 4 14:25:15 2015 -0800 Strago: Enable native mode on sd card cd line Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Reviewed-on: https://chromium-review.googlesource.com/310847 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 2 +- src/soc/intel/braswell/include/soc/gpio.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c old mode 100755 new mode 100644 index 8b6a0e7..b686853 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -74,7 +74,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 08cfd0c..5c1d7d2 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -274,6 +274,11 @@ | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ .pad_conf1 = PAD_CONFIG1_DEFAULT0 } +#define NATIVE_INT_PU20K(mode, int_sel) {\ + .pad_conf0 = PAD_PULL_UP_20K | PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \ + | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + #define SPEAKER \ { .pad_conf0 = PAD_CONFIG0_DEFAULT0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }

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New patch to review for coreboot: Strago: Enable native mode on sd card cd line
by Hannah Williams 16 Dec '15

16 Dec '15

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12741 -gerrit commit cc9f49d135385626502380532f9c8ebc5e8c012c Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Wed Nov 4 14:25:15 2015 -0800 Strago: Enable native mode on sd card cd line Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Reviewed-on: https://chromium-review.googlesource.com/310847 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 36 ++++++++++++++----------------- src/soc/intel/braswell/include/soc/gpio.h | 5 +++++ 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c old mode 100755 new mode 100644 index 8b6a0e7..a9215ab --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -12,13 +12,15 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - */ + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. +*/ #include "irqroute.h" #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> -#include "onboard.h" #include "gpio.h" /* South East Community */ @@ -74,7 +76,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ @@ -112,11 +114,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ GPIO_NC, /* 52 I2C_NFC_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ @@ -128,9 +130,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + GPIO_NC, /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ @@ -169,9 +171,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = { /* 17 GPIO_SUS3 */ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + GPI(trig_edge_high, L2, P_20K_H, non_maskable, + en_edge_rx_data, NA , NA), /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC, @@ -242,7 +246,7 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_NC, /* 19 MF_GPIO_5 */ GPIO_NC, /* 20 MF_GPIO_9 */ GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ GPIO_NC, /* 23 MF_GPIO_8 */ GPIO_NC, /* 24 MF_GPIO_2 */ GPIO_NC, /* 25 MF_GPIO_6 */ @@ -261,13 +265,5 @@ static struct soc_gpio_config gpio_config = { struct soc_gpio_config *mainboard_get_gpios(void) { - - switch (board_id()) { - case BOARD_DVT: - return get_override_gpios_dvt(); - case BOARD_BCRD2: - return get_override_gpios_bcrd2(); - default: - return &gpio_config; - } + return &gpio_config; } diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 08cfd0c..5c1d7d2 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -274,6 +274,11 @@ | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ .pad_conf1 = PAD_CONFIG1_DEFAULT0 } +#define NATIVE_INT_PU20K(mode, int_sel) {\ + .pad_conf0 = PAD_PULL_UP_20K | PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \ + | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + #define SPEAKER \ { .pad_conf0 = PAD_CONFIG0_DEFAULT0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }

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New patch to review for coreboot: Braswell: add code to support customization of I2C data hold time
by Hannah Williams 16 Dec '15

16 Dec '15

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12740 -gerrit commit 6b04a3c3db7d9bc061f1308311e74293ea985032 Author: Kane Chen <kane.chen(a)intel.com> Date: Mon Oct 26 13:02:33 2015 +0800 Braswell: add code to support customization of I2C data hold time The I2C data hold time can be vary on different boards/devices. So, it needs to be customized by boards/devices TEST=compile ok and check IC_SDA_HOLD is changed if the hold time is defined in onboard.h Reviewed-on: https://chromium-review.googlesource.com/308623 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I66c799de400670916cebbcb529d4f59d5b0f081b Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- src/soc/intel/braswell/acpi/lpss.asl | 59 +++++++++++++++++++++++++++--------- 1 file changed, 45 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index a2d5f3f..34d1e4d 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -14,6 +14,37 @@ * GNU General Public License for more details. */ +/* The below definitions are used for customization + * Some boards/devices may need different data hold time + */ +#ifndef BOARD_I2C1_DATA_HOLD_TIME +#define BOARD_I2C1_DATA_HOLD_TIME 6 +#endif + +#ifndef BOARD_I2C2_DATA_HOLD_TIME +#define BOARD_I2C2_DATA_HOLD_TIME 6 +#endif + +#ifndef BOARD_I2C3_DATA_HOLD_TIME +#define BOARD_I2C3_DATA_HOLD_TIME 6 +#endif + +#ifndef BOARD_I2C4_DATA_HOLD_TIME +#define BOARD_I2C4_DATA_HOLD_TIME 6 +#endif + +#ifndef BOARD_I2C5_DATA_HOLD_TIME +#define BOARD_I2C5_DATA_HOLD_TIME 6 +#endif + +#ifndef BOARD_I2C6_DATA_HOLD_TIME +#define BOARD_I2C6_DATA_HOLD_TIME 6 +#endif + +#ifndef BOARD_I2C7_DATA_HOLD_TIME +#define BOARD_I2C7_DATA_HOLD_TIME 6 +#endif + Device (SDM1) { Name (_HID, "INTL9C60") @@ -85,10 +116,10 @@ Device (I2C1) Name (_DDN, "I2C Controller #1") /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C1_DATA_HOLD_TIME }) /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C1_DATA_HOLD_TIME }) Name (RBUF, ResourceTemplate() { @@ -144,10 +175,10 @@ Device (I2C2) Name (_DDN, "I2C Controller #2") /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C2_DATA_HOLD_TIME }) /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C2_DATA_HOLD_TIME }) Name (RBUF, ResourceTemplate() { @@ -203,10 +234,10 @@ Device (I2C3) Name (_DDN, "I2C Controller #3") /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C3_DATA_HOLD_TIME }) /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C3_DATA_HOLD_TIME }) Name (RBUF, ResourceTemplate() { @@ -262,10 +293,10 @@ Device (I2C4) Name (_DDN, "I2C Controller #4") /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C4_DATA_HOLD_TIME }) /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C4_DATA_HOLD_TIME }) Name (RBUF, ResourceTemplate() { @@ -321,10 +352,10 @@ Device (I2C5) Name (_DDN, "I2C Controller #5") /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C5_DATA_HOLD_TIME }) /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C5_DATA_HOLD_TIME }) Name (RBUF, ResourceTemplate() { @@ -380,10 +411,10 @@ Device (I2C6) Name (_DDN, "I2C Controller #6") /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C6_DATA_HOLD_TIME }) /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C6_DATA_HOLD_TIME }) Name (RBUF, ResourceTemplate() { @@ -439,10 +470,10 @@ Device (I2C7) Name (_DDN, "I2C Controller #7") /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C7_DATA_HOLD_TIME }) /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C7_DATA_HOLD_TIME }) Name (RBUF, ResourceTemplate() {

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New patch to review for coreboot: Braswell: Making interface to program USB2_COMPBG register
by Hannah Williams 16 Dec '15

16 Dec '15

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12739 -gerrit commit 962bff81e2c75d2057efc611b544ccf166039bd9 Author: shkim <sh_.kim(a)samsung.com> Date: Tue Sep 22 17:53:58 2015 +0900 Braswell: Making interface to program USB2_COMPBG register Making interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Reviewed-on: https://chromium-review.googlesource.com/300846 Reviewed-by: Shawn N <shawnn(a)chromium.org> Commit-Queue: shkim <sh_.kim(a)samsung.com> Tested-by: shkim <sh_.kim(a)samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Signed-off-by: shkim <sh_.kim(a)samsung.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/chip.h | 7 ++++ src/soc/intel/braswell/include/soc/iosf.h | 5 +++ src/soc/intel/braswell/iosf.c | 15 ++++++- src/soc/intel/braswell/xhci.c | 67 +++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..f676fc1 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -56,6 +56,13 @@ struct soc_intel_braswell_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; + + /* Program USB2_COMPBG register. + * [10:7] - select vref to AFE port + * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV, + * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV + */ + int usb_comp_bg; /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index add602f..e6758a6 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -69,6 +69,8 @@ uint32_t iosf_port58_read(int reg); void iosf_port58_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx); @@ -91,6 +93,7 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ +#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SSUS 0xa8 /* SUS */ @@ -109,6 +112,8 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) #define IOSF_OP_READ_SCC 0x06 #define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) +#define IOSF_OP_READ_USBPHY 0x06 +#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) /* * BUNIT Registers. diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 1e7b924..98d1610 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -122,6 +122,15 @@ void iosf_scc_write(int reg, uint32_t val) return iosf_write_port(IOSF_WRITE(SCC), reg, val); } +uint32_t iosf_usbphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USBPHY), reg); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); +} #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx) @@ -140,6 +149,8 @@ uint64_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_port58_read(step->reg); case IOSF_PORT_SCC: return iosf_scc_read(step->reg); + case IOSF_PORT_USBPHY: + return iosf_usbphy_read(step->reg); default: printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", step->id); @@ -169,7 +180,9 @@ void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_SCC: iosf_scc_write(step->reg, step->value); break; - + case IOSF_PORT_USBPHY: + iosf_usbphy_write(step->reg, step->value); + break; default: printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", step->id); diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c new file mode 100644 index 0000000..cac490b --- /dev/null +++ b/src/soc/intel/braswell/xhci.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> +#include <soc/xhci.h> + +#include "chip.h" + +static void xhci_init(device_t dev) +{ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + + struct soc_intel_braswell_config *config = dev->chip_info; + struct reg_script ops[] = { + REG_IOSF_WRITE(IOSF_PORT_USBPHY, 0x7f04, config->usb_comp_bg), + REG_SCRIPT_END + }; + + if (config && config->usb_comp_bg) { + printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg); + reg_script_run(ops); + } +} + +static struct device_operations xhci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xhci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver soc_xhci __pci_driver = { + .ops = &xhci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = XHCI_DEVID +};

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coreboot-gerrit December 2015