coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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752 discussions

Patch merged into coreboot/master: vendorcode: google: chromeos: Remove old fmap.c file
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit 74babffccbd9ff47369650bcb5bd6e016d757959 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Dec 16 19:43:46 2015 -0800 vendorcode: google: chromeos: Remove old fmap.c file This file became obsolete when FMAP code moved to src/lib/ and is no longer built by any Makefile. Let's remove it to avoid confusing people. Change-Id: I55639af28f9f3d4c4cb0429b805e3f120ecc374e Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/12753 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/12753 for details. -gerrit

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Patch merged into coreboot/master: Makefile.inc: Document extract_nth and the fields it extracts
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit fdaf9cca3663423453e3f1988832a6e267a024b6 Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 11 11:40:06 2015 -0700 Makefile.inc: Document extract_nth and the fields it extracts Change-Id: I0b5cffff95aca0ea0d6302b436797dada1850ba0 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12713 for details. -gerrit

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New patch to review for coreboot: Payloads: Add U-Boot as a coreboot-payload
by Martin Roth 17 Dec '15

17 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12714 -gerrit commit 2995f055ce3bcf588bca3264a331f7d38763b661 Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 11 12:24:33 2015 -0700 Payloads: Add U-Boot as a coreboot-payload - Add Kconfig and Makefile options to use U-Boot as a payload. - Add Kconfig option for extra cbfstool command line arguments. - Add Kconfig & Makefile option to load the payload as a flat binary. - Add u-boot directory to .gitignore. This is currently working for X-86 only. I haven't tried graphics. Tested in QEMU and on Minnowboard Max Change-Id: Ia122a4ad7cd7d96107c1552b0376c8106ca8fb92 Signed-off-by: Martin Roth <martinroth(a)google.com> --- .gitignore | 1 + Makefile.inc | 12 +++++-- payloads/external/Makefile.inc | 5 +++ payloads/external/U-Boot/Kconfig | 36 +++++++++++++++++++ payloads/external/U-Boot/Kconfig.name | 11 ++++++ payloads/external/U-Boot/Makefile.inc | 68 +++++++++++++++++++++++++++++++++++ src/Kconfig | 12 +++++++ 7 files changed, 143 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 114d78f..581c4a4 100644 --- a/.gitignore +++ b/.gitignore @@ -11,6 +11,7 @@ coreboot-builds/ payloads/external/FILO/filo/ payloads/external/GRUB2/grub2/ payloads/external/SeaBIOS/seabios/ +payloads/external/U-Boot/u-boot/ util/crossgcc/acpica-unix-*/ util/crossgcc/binutils-*/ util/crossgcc/build-*BINUTILS/ diff --git a/Makefile.inc b/Makefile.inc index 976280c..a362948 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -441,6 +441,7 @@ clean-for-update-target: rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean + $(MAKE) -C payloads/external/U-Boot -f Makefile.inc clean clean-target: rm -f $(obj)/coreboot* @@ -632,10 +633,10 @@ extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-) cbfs-add-cmd = \ printf " CBFS $(call extract_nth,2,$(file))\n"; \ $(CBFSTOOL) $@.tmp \ - add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload) \ + add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload)$(if $(filter flat-binary,$(call extract_nth,3,$(file))),-flat-binary) \ -f $(call extract_nth,1,$(file)) \ -n $(call extract_nth,2,$(file)) \ - $(if $(filter-out stage,$(call extract_nth,3,$(file))),-t $(call extract_nth,3,$(file))) \ + $(if $(filter-out flat-binary,$(filter-out stage,$(call extract_nth,3,$(file)))),-t $(call extract_nth,3,$(file))) \ $(if $(call extract_nth,4,$(file)),-c $(call extract_nth,4,$(file))) \ $(call extract_nth,7,$(file)) @@ -759,6 +760,9 @@ ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),) ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD) endif endif +ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))),) + ADDITIONAL_PAYLOAD_CONFIG+=$(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))) +endif ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) REFCODE_BLOB=$(obj)/refcode.rmod @@ -819,7 +823,11 @@ $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload $(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE) +ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) +$(CONFIG_CBFS_PREFIX)/payload-type := flat-binary +else $(CONFIG_CBFS_PREFIX)/payload-type := payload +endif $(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG) $(CONFIG_CBFS_PREFIX)/payload-options := $(ADDITIONAL_PAYLOAD_CONFIG) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 0854947..e573268 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -64,3 +64,8 @@ grub2: CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER) payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 + +payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: + $(MAKE) -C payloads/external/U-Boot -f Makefile.inc \ + CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ + CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig new file mode 100644 index 0000000..e9fc4ac --- /dev/null +++ b/payloads/external/U-Boot/Kconfig @@ -0,0 +1,36 @@ +config PAYLOAD_UBOOT + select PAYLOAD_IS_FLAT_BINARY + +if PAYLOAD_UBOOT + +choice + prompt "U-Boot version" + default UBOOT_STABLE + +config UBOOT_STABLE + bool "v2015.10" + help + Stable U-Boot version + +config UBOOT_MASTER + bool "master" + help + Newest U-Boot version + +endchoice + +config PAYLOAD_CONFIGFILE + string "U-Boot config file" + default "" + help + This option allows a platform to set Kconfig options for a basic + U-Boot payload. In general, if the option is used, the default + would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot" + +config PAYLOAD_FILE + default "payloads/external/U-Boot/u-boot/u-boot-dtb.bin" + +config PAYLOAD_OPTIONS + default "-l 0x1110000 -e 0x1110015" + +endif diff --git a/payloads/external/U-Boot/Kconfig.name b/payloads/external/U-Boot/Kconfig.name new file mode 100644 index 0000000..960869a --- /dev/null +++ b/payloads/external/U-Boot/Kconfig.name @@ -0,0 +1,11 @@ +config PAYLOAD_UBOOT + bool "U-Boot" + depends on ARCH_X86 + help + Select this option if you want to build a coreboot image + with a U-Boot payload. + + See http://coreboot.org/Payloads and U-Boot's documentation + at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86 + for more information. + diff --git a/payloads/external/U-Boot/Makefile.inc b/payloads/external/U-Boot/Makefile.inc new file mode 100644 index 0000000..84b64d8 --- /dev/null +++ b/payloads/external/U-Boot/Makefile.inc @@ -0,0 +1,68 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +TAG-$(CONFIG_UBOOT_MASTER)=origin/master +TAG-$(CONFIG_UBOOT_STABLE)=5ec0003b19cbdf06ccd6941237cbc0d1c3468e2d + +project_name=U-Boot +project_dir=u-boot +project_git_repo=http://git.denx.de/u-boot.git +project_config_file=$(project_dir)/.config + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +all: build + +$(project_dir): + echo " Cloning $(project_name) from Git" + git clone $(project_git_repo) $(project_dir) + +fetch: $(project_dir) + cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + then echo " Fetching new commits from the $(project_name) git repo"; git fetch; fi + +checkout: fetch + echo " Checking out $(project_name) revision $(TAG-y)" + cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + +config: checkout + rm -f $(project_config_file) +ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),) +ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","") + cat $(CONFIG_PAYLOAD_CONFIGFILE)" >> $(project_config_file) +else + echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist" + false +endif +endif + cat $(project_dir)/configs/coreboot-x86_defconfig >> $(project_config_file) + $(MAKE) -C $(project_dir) olddefconfig + +build: config + echo " MAKE $(project_name) $(TAG-y)" + $(MAKE) -C $(project_dir) + +clean: + test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0 + +distclean: + rm -rf $(project_dir) + +.PHONY: checkout config build clean distclean clone fetch diff --git a/src/Kconfig b/src/Kconfig index 818eb59..13de1f4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -716,6 +716,18 @@ config COMPRESSED_PAYLOAD_LZMA In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. +config PAYLOAD_OPTIONS + string + default "" + help + Additional cbfstool options for the payload + +config PAYLOAD_IS_FLAT_BINARY + def_bool n + help + Add the payload to cbfs as a flat binary type instead of as an + elf payload + endmenu menu "Debugging"

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Patch merged into coreboot/master: soc/intel/fsp_baytrail: Adjust root port INT routing
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit ffcd9393a41e20883c219a2f47a1510aef82dcd4 Author: Martin Roth <martinroth(a)google.com> Date: Mon Dec 7 16:50:47 2015 -0700 soc/intel/fsp_baytrail: Adjust root port INT routing Adjust the root port INT routing based on Bay Trail spec: Document Number: 538136, Rev. 3.9 Table 241. Interrupt Generated for INT[A-D] Interrupts INTA INTB INTC INTD Root Port 1 INTA# INTB# INTC# INTD# Root Port 2 INTD# INTA# INTB# INTC# Root Port 3 INTC# INTD# INTA# INTB# Root Port 4 INTB# INTC# INTD# INTA# Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12684 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Ben Gardner <gardner.ben(a)gmail.com> See https://review.coreboot.org/12684 for details. -gerrit

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New patch to review for coreboot: x86: add OPTION_STATIC_OPTION_TABLE_NAME
by Ben Gardner 17 Dec '15

17 Dec '15

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12756 -gerrit commit 1b713b7f8576677b7af3ac60b8436d7b946e5763 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Thu Dec 17 10:38:17 2015 -0600 x86: add OPTION_STATIC_OPTION_TABLE_NAME This option uses a function instead of the hard-coded "cmos.default" for the static option table. This allows, say, a jumper on the mainboard to select a CMOS default file that contains a 'debug' log level. Building and adding alternate cmos.default files is an exercise left to the reader. Change-Id: Ieb4d255c0e9dd1b5de4214a37635146fd840b52b Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/Kconfig | 8 ++++++++ src/arch/x86/include/arch/bootblock_common.h | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 46349c5..e1c94a5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -130,6 +130,14 @@ config STATIC_OPTION_TABLE every boot. Use this if you want the NVRAM configuration to never be modified from its default values. +config STATIC_OPTION_TABLE_NAME + bool "Use cmos_default_name() to get the CMOS filename" + default n + depends on STATIC_OPTION_TABLE + help + Enable this option and define cmos_default_name() to return the CBFS + filename to load the static option table. + config UNCOMPRESSED_RAMSTAGE bool default n diff --git a/src/arch/x86/include/arch/bootblock_common.h b/src/arch/x86/include/arch/bootblock_common.h index 939ba08..00cc7f44 100644 --- a/src/arch/x86/include/arch/bootblock_common.h +++ b/src/arch/x86/include/arch/bootblock_common.h @@ -34,10 +34,18 @@ static void bootblock_mainboard_init(void) #endif #if CONFIG_USE_OPTION_TABLE + +#if CONFIG_STATIC_OPTION_TABLE_NAME +const char *cmos_default_name(void); +#define CMOS_DEFAULT_NAME cmos_default_name() +#else +#define CMOS_DEFAULT_NAME "cmos.default" +#endif + static void sanitize_cmos(void) { if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { - unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); + unsigned char *cmos_default = (unsigned char*)walkcbfs(CMOS_DEFAULT_NAME); if (cmos_default) { int i; cmos_disable_rtc();

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New patch to review for coreboot: soc/imgtec/pistachio: add implementation for system reset
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12755 -gerrit commit 77c3c6e10c533baedd948b8fd00576a7ae6a88d8 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Dec 17 13:11:50 2015 +0000 soc/imgtec/pistachio: add implementation for system reset Implement system reset by calling the watchdog soft reset. Following the soft reset, the SoC will reset to the same logic state and therefore have the same effect as a hard (power-on) reset except for: - watchdog scratch registers will be unaffected (hard reset will clear them) - the real time clock will be unaffected BUG=none TEST=tested on Pistachio bring up board Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/reset.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c index 7bf4d03..fc581df 100644 --- a/src/soc/imgtec/pistachio/reset.c +++ b/src/soc/imgtec/pistachio/reset.c @@ -13,13 +13,15 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> #include <reset.h> +#define PISTACHIO_WD_ADDR 0xB8102100 +#define PISTACHIO_WD_SW_RST_OFFSET 0x0000 + void hard_reset(void) { - printk(BIOS_EMERG, "reset failed!\n"); - /* TBD */ - for (;;) - ; + /* Generate system reset */ + write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); }

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Patch set updated for coreboot: soc/imgtec/pistachio: Implement hard_reset()
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12723 -gerrit commit ad7f02373b6ac28c86e44e0eec3658cc3b9fcb73 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Dec 14 17:31:44 2015 -0800 soc/imgtec/pistachio: Implement hard_reset() Verified boot needs hard_reset() now, so offer a dummy implementation for the Imagination chip. Sorry, I don't have the specs for this chip anymore to make a real implementation, but I would like to keep this code from bit rotting. Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/imgtec/pistachio/Kconfig | 1 + src/soc/imgtec/pistachio/Makefile.inc | 1 + src/soc/imgtec/pistachio/reset.c | 25 +++++++++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index e26130b..2e28174 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -21,6 +21,7 @@ config CPU_IMGTEC_PISTACHIO select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB + select HAVE_HARD_RESET bool if CPU_IMGTEC_PISTACHIO diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index 1a5e2af..78e7789 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -33,6 +33,7 @@ bootblock-y += monotonic_timer.c ramstage-y += cbmem.c ramstage-y += monotonic_timer.c ramstage-y += soc.c +ramstage-y += reset.c romstage-y += cbmem.c romstage-y += ddr2_init.c diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c new file mode 100644 index 0000000..7bf4d03 --- /dev/null +++ b/src/soc/imgtec/pistachio/reset.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <reset.h> + +void hard_reset(void) +{ + printk(BIOS_EMERG, "reset failed!\n"); + /* TBD */ + for (;;) + ; +}

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Patch set updated for coreboot: siemens/mc_tcu3: Set GPIO_S0_SC[75] to output
by Werner Zeh 17 Dec '15

17 Dec '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12754 -gerrit commit 8734a7b42a457f2a8b8615694f016fbb0e1b70ba Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Dec 17 07:28:29 2015 +0100 siemens/mc_tcu3: Set GPIO_S0_SC[75] to output The usage of the pin has changed and therefore this pin needs to be set up as output and drive low initially. Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index fc5178f..c803998 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -127,7 +127,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# */ GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# */ GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD */ - GPIO_FUNC1, /* GPIO_S0_SC[075] SIO_UART2_TXD */ + GPIO_OUT_LOW, /* GPIO_S0_SC[075] SIO_UART2_TXD */ GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# */ GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# */ GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA */

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New patch to review for coreboot: siemens/mc_tcu3: Set GPIO_S0_SC[75] to output
by Werner Zeh 17 Dec '15

17 Dec '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12754 -gerrit commit cbc19b6f8e1f0613882c5e2a51d103aca98e955d Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Dec 17 07:28:29 2015 +0100 siemens/mc_tcu3: Set GPIO_S0_SC[75] to output The usage of the pin has changed and therefore this pin needs to be set up as output and drive low initially. Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index fc5178f..ba4e9fb 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -15,7 +15,7 @@ */ #include <stdlib.h> -#include <soc/gpio.h> +#include <baytrail/gpio.h> #include "irqroute.h" /* NCORE GPIOs */ @@ -127,7 +127,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# */ GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# */ GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD */ - GPIO_FUNC1, /* GPIO_S0_SC[075] SIO_UART2_TXD */ + GPIO_OUT_LOW, /* GPIO_S0_SC[075] SIO_UART2_TXD */ GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# */ GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# */ GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA */

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New patch to review for coreboot: vendorcode: google: chromeos: Remove old fmap.c file
by Julius Werner 17 Dec '15

17 Dec '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12753 -gerrit commit 45b0565e9737787ab40f10bebf2f081de81991c2 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Dec 16 19:43:46 2015 -0800 vendorcode: google: chromeos: Remove old fmap.c file This file became obsolete when FMAP code moved to src/lib/ and is no longer built by any Makefile. Let's remove it to avoid confusing people. Change-Id: I55639af28f9f3d4c4cb0429b805e3f120ecc374e Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/vendorcode/google/chromeos/fmap.c | 153 ---------------------------------- 1 file changed, 153 deletions(-) diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c deleted file mode 100644 index 2cc223e..0000000 --- a/src/vendorcode/google/chromeos/fmap.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stddef.h> -#include <string.h> -#include <console/console.h> -#include <cbfs.h> -#include "fmap.h" - -static int is_fmap_signature_valid(const struct fmap *fmap) -{ - const char reversed_sig[] = FMAP_REVERSED_SIGNATURE; - const char *p2 = reversed_sig + sizeof(FMAP_REVERSED_SIGNATURE) - 2; - const char *p1 = (char *)fmap; - - while (p2 >= reversed_sig) - if (*p1++ != *p2--) { - printk(BIOS_ERR, "No FMAP found at %p.\n", fmap); - return 1; - } - - printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %p.\n", - fmap->name, fmap->ver_major, fmap->ver_minor, fmap); - printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n", - (unsigned long long)fmap->base, fmap->size, fmap->nareas); - - return 0; -} - -/* Find FMAP data structure in ROM. - * See http://code.google.com/p/flashmap/ for more information on FMAP. - */ -const struct fmap *fmap_find(void) -{ - /* FIXME: Get rid of the hard codes. The "easy" way would be to - * do a binary search, but since ROM accesses are slow, we don't - * want to spend a lot of time looking for the FMAP. An elegant - * solution would be to store a pointer to the FMAP in the CBFS - * master header; that would require some more changes to cbfstool - * and possibly cros_bundle_firmware. - */ - const struct fmap *fmap; - struct cbfs_media media; - size_t size; - - if (init_default_cbfs_media(&media)) { - printk(BIOS_ERR, "failed to init default cbfs media\n"); - return NULL; - } - - media.open(&media); - fmap = media.map(&media, CONFIG_FLASHMAP_OFFSET, sizeof(*fmap)); - - if (fmap == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - printk(BIOS_ERR, "failed to map FMAP header\n"); - media.close(&media); - return NULL; - } - - if (is_fmap_signature_valid(fmap)) { - media.unmap(&media, fmap); - media.close(&media); - return NULL; - } - - size = sizeof(*fmap) + sizeof(struct fmap_area) * fmap->nareas; - media.unmap(&media, fmap); - fmap = media.map(&media, CONFIG_FLASHMAP_OFFSET, size); - - if (fmap == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - printk(BIOS_ERR, "failed to map FMAP (size=%zu)\n", size); - media.unmap(&media, fmap); - media.close(&media); - return NULL; - } - - media.close(&media); - return fmap; -} - -const struct fmap_area *find_fmap_area(const struct fmap *fmap, - const char name[]) -{ - const struct fmap_area *area = NULL; - - if (fmap) { - int i; - for (i = 0; i < fmap->nareas; i++) { - if (!strcmp((const char *)fmap->areas[i].name, name)) { - area = &fmap->areas[i]; - break; - } - } - } - - if (area) { - printk(BIOS_DEBUG, "FMAP: area %s found\n", name); - printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset); - printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size); - } else { - printk(BIOS_DEBUG, "FMAP: area %s not found\n", name); - } - - return area; -} - -int find_fmap_entry(const char name[], void **pointer) -{ - MAYBE_STATIC const struct fmap *fmap = NULL; - const struct fmap_area *area; - void *base = NULL; - - if (!fmap) - fmap = fmap_find(); - - area = find_fmap_area(fmap, name); - - if (!area) - return -1; - - /* Right now cros_bundle_firmware does not write a valid - * base address into the FMAP. Hence, if base is 0, assume - * 4GB-8MB as base address. - */ - if (fmap->base) { - base = (void *)(unsigned long)fmap->base; - printk(BIOS_DEBUG, "FMAP: %s base at %p\n", name, base); - } else { -#if CONFIG_ARCH_X86 - base = (void *)(0 - CONFIG_ROM_SIZE); - printk(BIOS_WARNING, "FMAP: No valid base address, using" - " 0x%p\n", base); -#endif - } - - *pointer = (void*) ((uintptr_t)base + area->offset); - printk(BIOS_DEBUG, "FMAP: %s at %p (offset %x)\n", - name, *pointer, area->offset); - return area->size; -}

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coreboot-gerrit December 2015