coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

New patch to review for coreboot: mainboard/google/urara: change SYS PLL to 700MHz
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12766 -gerrit commit 67ac42ec429a52e3ca0a1cdfa1158d58735ff2c8 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Wed Jul 15 12:12:02 2015 +0100 mainboard/google/urara: change SYS PLL to 700MHz This also requires a change in the dividers used for UART, USB, I2C setup. Tested on pistachio bring up board: PERIPH_SYS_CLK_OUT_MAIN output frequency = 350.000 MHz UART1_CLK_OUT output frequency = 1.842 MHz USB_PHY_CLK_OUT output frequency = 50.000 MHz SYS_CLK_OUT output frequency = 350.000 MHz DDR_CLK_OUT output frequency = 350.000 MHz ROM_CLK_OUT output frequency = 175.000 MHz Change-Id: Ib5e5186eceef89f7c33bf88391fab1fccb8649e4 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/mainboard/google/urara/bootblock.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 40696b6..7775916 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -172,7 +172,7 @@ static void bootblock_mainboard_init(void) { int ret; - /* System PLL divided by 2 -> 400 MHz */ + /* System PLL divided by 2 -> 350 MHz */ /* The same frequency will be the input frequency for the SPFI block */ system_clk_setup(1); @@ -181,8 +181,8 @@ static void bootblock_mainboard_init(void) * the values set or not by the boot ROM code */ mips_clk_setup(0, 0); - /* Setup system PLL at 800 MHz */ - ret = sys_pll_setup(2, 1); + /* Setup system PLL at 700 MHz */ + ret = sys_pll_setup(2, 1, 13, 350); if (ret != CLOCKS_OK) return; /* Setup MIPS PLL at 546 MHz */ @@ -193,9 +193,9 @@ static void bootblock_mainboard_init(void) /* Setup SPIM1 MFIOs */ spim1_mfio_setup(); /* Setup UART1 clock and MFIOs - * System PLL divided by 7 divided by 62 -> 1.8433 Mhz + * System PLL divided by 5 divided by 76 -> 1.8421 Mhz */ - uart1_clk_setup(6, 61); + uart1_clk_setup(4, 75); uart1_mfio_setup(); } @@ -213,23 +213,23 @@ static int init_extra_hardware(void) } /* Setup USB clock - * System clock divided by 8 -> 50 MHz + * System clock divided by 7 -> 50 MHz */ - if (usb_clk_setup(7, 2, 7) != CLOCKS_OK) { + if (usb_clk_setup(6, 2, 7) != CLOCKS_OK) { printk(BIOS_ERR, "%s: Failed to set up USB clock.\n", __func__); return -1; } /* Setup I2C clocks and MFIOs - * System PLL divided by 4 divided by 3 -> 33.33 MHz + * System clock divided by 4 divided by 3 -> 29.1(6) MHz */ i2c_clk_setup(3, 2, hardware->i2c_interface); i2c_mfio_setup(hardware->i2c_interface); /* Ethernet clocks setup: ENET as clock source */ - eth_clk_setup(0, 7); - /* ROM clock setup: system clock divided by 2 -> 200 MHz */ + eth_clk_setup(0, 6); + /* ROM clock setup: system clock divided by 2 -> 175 MHz */ /* Hash accelerator is driven from the ROM clock */ rom_clk_setup(1);

1 0

New patch to review for coreboot: imgtec/pistachio: sys_pll_setup receives refdiv and feedback
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12765 -gerrit commit 0838f58d37c695abb42007ab2782abe2f2de79c1 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Wed Jul 15 12:10:05 2015 +0100 imgtec/pistachio: sys_pll_setup receives refdiv and feedback Change the interface that sets up the system PLL to support a given reference devider value and given feedback value. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/clocks.c | 25 +++++++++++++++++-------- src/soc/imgtec/pistachio/include/soc/clocks.h | 2 +- 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 40c45b0..43bdc55 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -44,6 +44,13 @@ #define SYS_PLL_STATUS_ADDR 0xB8144038 #define SYS_PLL_STATUS_LOCK_MASK 0x00000001 +#define SYS_PLL_REFDIV_ADDR 0xB814403C +#define SYS_PLL_REFDIV_MASK 0x0000003F +#define SYS_PLL_REFDIV_SHIFT 0 +#define SYS_PLL_FEEDBACK_ADDR 0xB814403C +#define SYS_PLL_FEEDBACK_MASK 0x0003FFC0 +#define SYS_PLL_FEEDBACK_SHIFT 6 + #define MIPS_PLL_POSTDIV_ADDR 0xB8144004 #define MIPS_PLL_POSTDIV1_MASK 0x001C0000 #define MIPS_PLL_POSTDIV1_SHIFT 18 @@ -156,13 +163,13 @@ static struct pll_parameters pll_params[] = { .status_addr = SYS_PLL_STATUS_ADDR, .status_lock_mask = SYS_PLL_STATUS_LOCK_MASK, .refdivider = 0, /* Not defined yet */ - .refdiv_addr = 0, /* Not necessary */ - .refdiv_shift = 0, /* Not necessary */ - .refdiv_mask = 0, /* Not necessary */ - .feedback = 0, /* Not necessary */ - .feedback_addr = 0, /* Not necessary */ - .feedback_shift = 0, /* Not necessary */ - .feedback_mask = 0, /* Not necessary */ + .refdiv_addr = SYS_PLL_REFDIV_ADDR, + .refdiv_shift = SYS_PLL_REFDIV_SHIFT, + .refdiv_mask = SYS_PLL_REFDIV_MASK, + .feedback = 0, /* Not defined yet */ + .feedback_addr = SYS_PLL_FEEDBACK_ADDR, + .feedback_shift = SYS_PLL_FEEDBACK_SHIFT, + .feedback_mask = SYS_PLL_FEEDBACK_MASK }, [MIPS_PLL] = { @@ -263,8 +270,10 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) return CLOCKS_OK; } -int sys_pll_setup(u8 divider1, u8 divider2) +int sys_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) { + pll_params[SYS_PLL].refdivider = refdivider; + pll_params[SYS_PLL].feedback = feedback; return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2); } diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index f351a6f..fc07f0a 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -21,7 +21,7 @@ #include <stdint.h> /* Functions for PLL setting */ -int sys_pll_setup(u8 divider1, u8 divider2); +int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); /* Peripheral divider setting */

1 0

New patch to review for coreboot: imgtec/pistachio: DDR2, DDR3: DLL reset set
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12764 -gerrit commit bfc9c63b79647814ae92982b1224e322705ae6c9 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Tue May 26 12:20:19 2015 +0100 imgtec/pistachio: DDR2, DDR3: DLL reset set Bit 8 of the MR register is automatically set by the PHY during memory initilization but having it set in the register leads to a more clear understanding. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/ddr2_init.c | 2 +- src/soc/imgtec/pistachio/ddr3_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index 322d241..9549537 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -112,7 +112,7 @@ int init_ddr2(void) * 15:13 RSVD RSVD * 31:16 Reserved */ - write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000A62 | (BL8 ? 0x1 : 0x0)); + write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0)); /* MR1 : EMR Register * Generate to use with PHY and PCTL * 0 DE DLL Enable 0 Disable 1 diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c index e77a5cd..5cb36a0 100644 --- a/src/soc/imgtec/pistachio/ddr3_init.c +++ b/src/soc/imgtec/pistachio/ddr3_init.c @@ -119,7 +119,7 @@ int init_ddr3(void) * 15:13 RSVD RSVD * 31:16 Reserved */ - write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001420); + write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520); /* MR1 : DDR3 mode register 1 * Generate to use with PHY and PCTL * 0 DE DLL Enable 0 Disable 1

1 0

New patch to review for coreboot: imgtec/pistachio: DDR2, DDR3: DQS gate early
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12763 -gerrit commit 9b552bfe7e6a5d6b704b381222c56b26b354398d Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu May 21 13:29:45 2015 +0100 imgtec/pistachio: DDR2, DDR3: DQS gate early Switching on DQS Gate Early and DQS Gate Extension with 500R DQS/DSQN Resistors. This setup was recommended by Synopsys. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/ddr2_init.c | 16 +++++++++++----- src/soc/imgtec/pistachio/ddr3_init.c | 16 +++++++++++----- src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h | 3 +++ 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index e21b79b..322d241 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -143,8 +143,8 @@ int init_ddr2(void) * 2 ZUEN Def 1 * 3 LPIOPD DEf 1 0 * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention 000 - * 10:8 DQSGE DQS Early Gate + * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys + * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys * 11 NOBUB No Bubbles, adds latency 1 * 12 FXDLAT Fixed Read Latency 0 * 15:13 Reserved @@ -159,7 +159,9 @@ int init_ddr2(void) * 30 RSTOE RST# Output Enable 1 * 31 CKEOE CKE Output Enable 1 */ - write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000807); + write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); + /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ + write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); /* DTPR0 : DRAM Timing Params 0 * 1:0 tMRD 2 * 4:2 tRTP 3 @@ -235,6 +237,10 @@ int init_ddr2(void) /* PGSR : Wait for DRAM Init Done */ if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) return DDR_TIMEOUT; + /* Disable Impedance Calibration */ + write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); + write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); + /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, 0x00000001)) @@ -315,10 +321,10 @@ int init_ddr2(void) * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 */ write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /*TRTW : Read to Write turn around time Def 2 + /*TRTW : Read to Write turn around time Def 3 * Actual gap t_bl + t_rtw */ - write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000002); + write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); /* TCKE : CKE min pulse width DEf 3 */ write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); /* diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c index 0a5a444..e77a5cd 100644 --- a/src/soc/imgtec/pistachio/ddr3_init.c +++ b/src/soc/imgtec/pistachio/ddr3_init.c @@ -163,8 +163,8 @@ int init_ddr3(void) * 2 ZUEN Def 1 * 3 LPIOPD DEf 1 0 * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention 000 - * 10:8 DQSGE DQS Early Gate + * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys + * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys * 11 NOBUB No Bubbles, adds latency 1 * 12 FXDLAT Fixed Read Latency 0 * 15:13 Reserved @@ -179,7 +179,9 @@ int init_ddr3(void) * 30 RSTOE RST# Output Enable 1 * 31 CKEOE CKE Output Enable 1 */ - write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000807); + write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927); + /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ + write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); /* DTPR0 : DRAM Timing Params 0 * 1:0 tMRD 0 * 4:2 tRTP 2 @@ -333,10 +335,10 @@ int init_ddr3(void) * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 */ write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /* TRTW : Read to Write turn around time Def 2 + /* TRTW : Read to Write turn around time Def 3 * Actual gap t_bl + t_rtw */ - write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000002); + write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); /* TCKE : CKE min pulse width DEf 3 */ write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); /* TXPDLL : Slow Exit Power Down to first valid cmd delay @@ -498,6 +500,10 @@ int init_ddr3(void) /* STAT : Wait for Switch INIT to Config State */ if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F)) return DDR_TIMEOUT; + /* Disable Impedance Calibration */ + write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); + write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); + /* SCTL : UPCTL switch Config to ACCESS State */ write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); /* STAT : Wait for switch CFG -> GO State */ diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h index a0f661b..a9d18a0 100644 --- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h +++ b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h @@ -103,6 +103,7 @@ #define DDRPHY_DLLGCR_OFFSET (0x0010) #define DDRPHY_PTR0_OFFSET (0x0018) #define DDRPHY_PTR1_OFFSET (0x001C) +#define DDRPHY_DXCCR_OFFSET (0x0028) #define DDRPHY_DSGCR_OFFSET (0x002C) #define DDRPHY_DCR_OFFSET (0x0030) #define DDRPHY_DTPR0_OFFSET (0x0034) @@ -120,6 +121,8 @@ #define DDRPHY_BISTAR2_OFFSET (0x011C) #define DDRPHY_BISTUDPR_OFFSET (0x0120) #define DDRPHY_BISTGSR_OFFSET (0x0124) +#define DDRPHY_ZQ0CR0_OFFSET (0x0180) +#define DDRPHY_ZQ1CR0_OFFSET (0x0190) #define DDR_TIMEOUT_VALUE_US 100000

1 0

New patch to review for coreboot: imgtec/pistachio: increase CBFS cache
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12762 -gerrit commit c714b2db724bfc176dcd7d2a333162e1ef458fb6 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Aug 6 19:22:53 2015 +0100 imgtec/pistachio: increase CBFS cache Increase CBFS cache size to allow for a bigger payload. Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index ce0063f..edf9c41 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -26,8 +26,8 @@ SECTIONS DRAM_START(0x00000000) /* DMA coherent area: accessed via KSEG1. */ DMA_COHERENT(0x00100000, 1M) - POSTRAM_CBFS_CACHE(0x00200000, 192K) - RAMSTAGE(0x00230000, 128K) + POSTRAM_CBFS_CACHE(0x00200000, 512K) + RAMSTAGE(0x00280000, 128K) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock

1 0

New patch to review for coreboot: board_status.sh: Double quote variables to prevent globbing and word splitting.
by Martin Roth 17 Dec '15

17 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12761 -gerrit commit 7d8e24c7f40dae551d031cf8b7efe45af97742a0 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 17 12:49:15 2015 -0700 board_status.sh: Double quote variables to prevent globbing and word splitting. Quoting variables prevents word splitting and glob expansion, and prevents the script from breaking when input contains spaces, line feeds, glob characters and such. See shellcheck warning SC2086. Change-Id: I7256d2fc2a22bce7723950a534fef6d57cbd097f Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/board_status.sh | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 410488f..1fb599e 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -70,7 +70,7 @@ _cmd() fi if [ "$1" -eq "$REMOTE" ] && [ -n "$REMOTE_HOST" ]; then - ssh root@${REMOTE_HOST} "$2" > "$pipe_location" 2>&1 + ssh "root@${REMOTE_HOST}" "$2" > "$pipe_location" 2>&1 else $2 > "$pipe_location" 2>&1 fi @@ -227,12 +227,12 @@ fi test_cmd $LOCAL "$cbfstool_cmd" echo "Extracting config.txt from build/coreboot.rom" $cbfstool_cmd build/coreboot.rom extract -n config -f "${tmpdir}/config.txt" >/dev/null 2>&1 -mv ${tmpdir}/config.txt ${tmpdir}/config.short.txt -cp ${tmpdir}/config.short.txt ${tmpcfg} -yes "" | make DOTCONFIG=${tmpcfg} oldconfig 2>/dev/null >/dev/null -mv ${tmpcfg} ${tmpdir}/config.txt -rm -f ${tmpcfg}.old -$cbfstool_cmd build/coreboot.rom print > ${tmpdir}/cbfs.txt +mv "${tmpdir}/config.txt" "${tmpdir}/config.short.txt" +cp "${tmpdir}/config.short.txt" "${tmpcfg}" +yes "" | make "DOTCONFIG=${tmpcfg}" oldconfig 2>/dev/null >/dev/null +mv "${tmpcfg}" "${tmpdir}/config.txt" +rm -f "${tmpcfg}.old" +$cbfstool_cmd build/coreboot.rom print > "${tmpdir}/cbfs.txt" rom_contents=$($cbfstool_cmd build/coreboot.rom print 2>&1) if [ -n "$(echo $rom_contents | grep payload_config)" ]; then echo "Extracting payload_config from build/coreboot.rom" @@ -246,7 +246,7 @@ md5sum -b build/coreboot.rom > "${tmpdir}/rom_checksum.txt" # Obtain board and revision info to form the directory structure: # <vendor>/<board>/<revision>/<timestamp> -mainboard_dir="$(grep CONFIG_MAINBOARD_DIR ${tmpdir}/config.txt | awk -F '"' '{ print $2 }')" +mainboard_dir="$(grep CONFIG_MAINBOARD_DIR "${tmpdir}/config.txt" | awk -F '"' '{ print $2 }')" vendor=$(echo "$mainboard_dir" | awk -F '/' '{ print $1 }') mainboard=$(echo "$mainboard_dir" | awk -F '/' '{ print $2 }') @@ -267,12 +267,12 @@ mv "${tmpdir}/config.short.txt" "${tmpdir}/${results}" mv "${tmpdir}/cbfs.txt" "${tmpdir}/${results}" mv "${tmpdir}/rom_checksum.txt" "${tmpdir}/${results}" -touch ${tmpdir}/${results}/revision.txt -printf "Local revision: %s\n" "$($getrevision -l)" >> ${tmpdir}/${results}/revision.txt -printf "Tagged revision: %s\n" "${tagged_version}" >> ${tmpdir}/${results}/revision.txt -printf "Upstream revision: %s\n" $($getrevision -u) >> ${tmpdir}/${results}/revision.txt -printf "Upstream URL: %s\n" $($getrevision -U)>> ${tmpdir}/${results}/revision.txt -printf "Timestamp: %s\n" "$timestamp" >> ${tmpdir}/${results}/revision.txt +touch "${tmpdir}/${results}/revision.txt" +printf "Local revision: %s\n" "$($getrevision -l)" >> "${tmpdir}/${results}/revision.txt" +printf "Tagged revision: %s\n" "${tagged_version}" >> "${tmpdir}/${results}/revision.txt" +printf "Upstream revision: %s\n" "$($getrevision -u)" >> "${tmpdir}/${results}/revision.txt" +printf "Upstream URL: %s\n" "$($getrevision -U)" >> "${tmpdir}/${results}/revision.txt" +printf "Timestamp: %s\n" "$timestamp" >> "${tmpdir}/${results}/revision.txt" if [ -z "$SERIAL_DEVICE" ]; then echo "Verifying that CBMEM is available on remote device" @@ -301,7 +301,7 @@ if [ $UPLOAD_RESULTS -eq 1 ]; then # FIXME: the board-status directory might get big over time. # Is there a way we can push the results without fetching the # whole repo? - git clone $bsrepo + git clone "$bsrepo" if [ $? -ne 0 ]; then echo "Error cloning board-status repo, aborting." exit $EXIT_FAILURE @@ -334,7 +334,7 @@ fi cd "$coreboot_dir" if [ $CLOBBER_OUTPUT -eq 1 ]; then - rm -rf ${tmpdir} + rm -rf "${tmpdir}" else echo echo "output files are in ${tmpdir}/${results}"

1 0

New patch to review for coreboot: board_status.sh: checksum the rom and save it for later verification
by Martin Roth 17 Dec '15

17 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12760 -gerrit commit 87a0d0755754f0d8433b7280929989b8f738bd85 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 17 12:44:35 2015 -0700 board_status.sh: checksum the rom and save it for later verification This allows users who build the rom from the board-status repo to verify that their rom matches the original. Change-Id: I4e8564e389495909219f92ccdafb8e9568f8f0d0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/board_status.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 578e40a..410488f 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -242,6 +242,7 @@ if [ -n "$(echo $rom_contents | grep payload_version)" ]; then echo "Extracting payload_version from build/coreboot.rom" $cbfstool_cmd build/coreboot.rom extract -n payload_version -f "${tmpdir}/payload_version.txt" >/dev/null 2>&1 fi +md5sum -b build/coreboot.rom > "${tmpdir}/rom_checksum.txt" # Obtain board and revision info to form the directory structure: # <vendor>/<board>/<revision>/<timestamp> @@ -264,6 +265,7 @@ test -f "${tmpdir}/payload_config.txt" && mv "${tmpdir}/payload_config.txt" "${t test -f "${tmpdir}/payload_version.txt" && mv "${tmpdir}/payload_version.txt" "${tmpdir}/${results}" mv "${tmpdir}/config.short.txt" "${tmpdir}/${results}" mv "${tmpdir}/cbfs.txt" "${tmpdir}/${results}" +mv "${tmpdir}/rom_checksum.txt" "${tmpdir}/${results}" touch ${tmpdir}/${results}/revision.txt printf "Local revision: %s\n" "$($getrevision -l)" >> ${tmpdir}/${results}/revision.txt

1 0

New patch to review for coreboot: board_status.sh: Clean up output, show what the script is doing
by Martin Roth 17 Dec '15

17 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12759 -gerrit commit a93415d048963405f0bdd246f4d71ab1d6fadc87 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 17 12:38:45 2015 -0700 board_status.sh: Clean up output, show what the script is doing - Print what the script is doing so when it asks for the ssh password several times in a row, it's obvious that it's actually doing different things, not that the password failed. - Don't print the output from cbfstool - it's not useful. Change-Id: I785283475e14f242117682800c26db6b4f9f1e2c Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/board_status.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index fce45fb..578e40a 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -225,7 +225,8 @@ if test ! -x build/cbfstool; then make -C util/cbfstool/ && cp util/cbfstool/cbfstool build/cbfstool fi test_cmd $LOCAL "$cbfstool_cmd" -$cbfstool_cmd build/coreboot.rom extract -n config -f ${tmpdir}/config.txt +echo "Extracting config.txt from build/coreboot.rom" +$cbfstool_cmd build/coreboot.rom extract -n config -f "${tmpdir}/config.txt" >/dev/null 2>&1 mv ${tmpdir}/config.txt ${tmpdir}/config.short.txt cp ${tmpdir}/config.short.txt ${tmpcfg} yes "" | make DOTCONFIG=${tmpcfg} oldconfig 2>/dev/null >/dev/null @@ -272,13 +273,17 @@ printf "Upstream URL: %s\n" $($getrevision -U)>> ${tmpdir}/${results}/revision.t printf "Timestamp: %s\n" "$timestamp" >> ${tmpdir}/${results}/revision.txt if [ -z "$SERIAL_DEVICE" ]; then + echo "Verifying that CBMEM is available on remote device" test_cmd $REMOTE "cbmem" + echo "Getting coreboot boot log" cmd $REMOTE "cbmem -c" "${tmpdir}/${results}/coreboot_console.txt" + echo "Getting timestamp data" cmd_nonfatal $REMOTE "cbmem -t" "${tmpdir}/${results}/coreboot_timestamps.txt" else get_serial_bootlog "$SERIAL_DEVICE" "$SERIAL_PORT_SPEED" "${tmpdir}/${results}/coreboot_console.txt" fi +echo "Getting remote dmesg" cmd $REMOTE dmesg "${tmpdir}/${results}/kernel_log.txt" #

1 0

New patch to review for coreboot: board_status.sh: Extract payload config & version files
by Martin Roth 17 Dec '15

17 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12758 -gerrit commit c82eb59f4288079b45da5f5f03c55b1262a190fa Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 17 12:33:39 2015 -0700 board_status.sh: Extract payload config & version files If the payload_config and payload_version files are in coreboot.rom, extract and save them. Change-Id: I36b17ed189f94e2d4e873b0e219e5a9a2abe77a1 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/board_status.sh | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index d8bd3a8..fce45fb 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -232,6 +232,15 @@ yes "" | make DOTCONFIG=${tmpcfg} oldconfig 2>/dev/null >/dev/null mv ${tmpcfg} ${tmpdir}/config.txt rm -f ${tmpcfg}.old $cbfstool_cmd build/coreboot.rom print > ${tmpdir}/cbfs.txt +rom_contents=$($cbfstool_cmd build/coreboot.rom print 2>&1) +if [ -n "$(echo $rom_contents | grep payload_config)" ]; then + echo "Extracting payload_config from build/coreboot.rom" + $cbfstool_cmd build/coreboot.rom extract -n payload_config -f "${tmpdir}/payload_config.txt" >/dev/null 2>&1 +fi +if [ -n "$(echo $rom_contents | grep payload_version)" ]; then + echo "Extracting payload_version from build/coreboot.rom" + $cbfstool_cmd build/coreboot.rom extract -n payload_version -f "${tmpdir}/payload_version.txt" >/dev/null 2>&1 +fi # Obtain board and revision info to form the directory structure: # <vendor>/<board>/<revision>/<timestamp> @@ -250,6 +259,8 @@ echo "Temporarily placing output in ${tmpdir}/${results}" mkdir -p "${tmpdir}/${results}" mv "${tmpdir}/config.txt" "${tmpdir}/${results}" +test -f "${tmpdir}/payload_config.txt" && mv "${tmpdir}/payload_config.txt" "${tmpdir}/${results}" +test -f "${tmpdir}/payload_version.txt" && mv "${tmpdir}/payload_version.txt" "${tmpdir}/${results}" mv "${tmpdir}/config.short.txt" "${tmpdir}/${results}" mv "${tmpdir}/cbfs.txt" "${tmpdir}/${results}"

1 0

New patch to review for coreboot: board_status.sh: Update to fix serial port reads
by Martin Roth 17 Dec '15

17 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12757 -gerrit commit 207f6f8bcd7b4d40243194c117f2daa987252fd3 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 17 12:02:45 2015 -0700 board_status.sh: Update to fix serial port reads The old serial port read method lost characters from the boot log. This method works better for me. - Put get_serial_bootlog arguments into variable names for clarity. - Fully configure the serial port with stty: disable parity and flow control. - Change serial port read from reading with 'cat' to reading with 'read'. - Update help to show current default speed from the variable. tested under dash, bash, and zsh on several platfoms. Change-Id: I91ae63a3c226e61019dbdf69c405c3f20ba7db54 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/board_status.sh | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index ee27bc0..d8bd3a8 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -122,8 +122,12 @@ cmd_nonfatal() # $3: filename to direct output of command into get_serial_bootlog () { - if [ ! -c "$1" ]; then - echo "$1 is not a valid serial device" + local TTY=$1 + local SPEED=$2 + local FILENAME=$3 + + if [ ! -c "$TTY" ]; then + echo "$TTY is not a valid serial device" exit $EXIT_FAILURE fi @@ -136,27 +140,29 @@ get_serial_bootlog () { fi echo - echo "Waiting to receive boot log from $1" + echo "Waiting to receive boot log from $TTY" echo "Press [Enter] when the boot is complete and the" echo "system is ready for ssh to get the dmesg log." + echo if [ $tput_not_available -eq 0 ]; then tput sgr0 fi # set up the serial port - cmd $LOCAL "stty -F $1 $2 cs8 -cstopb" + stty -F $TTY $SPEED cs8 -cstopb -parenb clocal # read from the serial port - user must press enter when complete test_cmd $LOCAL "tee" - cat "$SERIAL_DEVICE" | tee "$3" & + while read LINE; do + echo "$LINE" | tee -a "$FILENAME" + done < "$SERIAL_DEVICE" & PID=$! - read - kill "$PID" 2>/dev/null & + read foo + kill "$PID" 2>/dev/null - # remove the binary zero value that gets inserted into the file. - sed -i 's/\x00//' "$3" + echo "Finished reading boot log." } show_help() { @@ -173,7 +179,7 @@ Options -s </dev/xxx> Obtain boot log via serial device. -S <speed> - Set the port speed for the serial device (Default is 115200). + Set the port speed for the serial device (Default is $SERIAL_PORT_SPEED). -u Upload results to coreboot.org. "

1 0

← Newer
1
...
22
23
24
25
26
27
28
...
76
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2015