coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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752 discussions

Patch merged into coreboot/master: Makefile.inc: Include build/dsdt.d if it exists
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit 92898b424b18760084af8e2d7c242e46bdc6a29b Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 9 13:05:00 2015 -0700 Makefile.inc: Include build/dsdt.d if it exists The dsdt dependency file is created, but wasn't being used to determine whether or not to update the dsdt file. If it's present, include it into the makefile so dsdt.aml gets rebuilt if any of the depencencies change. Change-Id: I76bc22541c6b9740841bda891a5b88030cb949cd Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12699 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12699 for details. -gerrit

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Patch merged into coreboot/master: soc/imgtec/pistachio: add implementation for system reset
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit 2e8d4ed794f7fe58a11bd84ea7da04840b5f7a00 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Dec 17 13:11:50 2015 +0000 soc/imgtec/pistachio: add implementation for system reset Implement system reset by calling the watchdog soft reset. Following the soft reset, the SoC will reset to the same logic state and therefore have the same effect as a hard (power-on) reset except for: - watchdog scratch registers will be unaffected (hard reset will clear them) - the real time clock will be unaffected BUG=none TEST=tested on Pistachio bring up board Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Reviewed-on: https://review.coreboot.org/12755 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> See https://review.coreboot.org/12755 for details. -gerrit

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Patch merged into coreboot/master: soc/imgtec/pistachio: Implement hard_reset()
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit 3bdd45e714ebfa38e352c705b8bb7374827bc1e3 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Dec 14 17:31:44 2015 -0800 soc/imgtec/pistachio: Implement hard_reset() Verified boot needs hard_reset() now, so offer a dummy implementation for the Imagination chip. Sorry, I don't have the specs for this chip anymore to make a real implementation, but I would like to keep this code from bit rotting. Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/12723 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> See https://review.coreboot.org/12723 for details. -gerrit

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New patch to review for coreboot: imgtec/pistachio: disable default RPU gate register values
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12773 -gerrit commit 2b629bd3ecb18d5ba8fd8e5c8815c9a14fdaad18 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Sun Nov 1 19:55:48 2015 +0000 imgtec/pistachio: disable default RPU gate register values The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/mainboard/google/urara/bootblock.c | 8 ++++++++ src/soc/imgtec/pistachio/clocks.c | 12 ++++++++++++ src/soc/imgtec/pistachio/include/soc/clocks.h | 1 + 3 files changed, 21 insertions(+) diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 7775916..121f35d 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -190,6 +190,14 @@ static void bootblock_mainboard_init(void) if (ret != CLOCKS_OK) return; + /* + * Move peripheral clock control from RPU to MIPS. + * The RPU gate register is not managed in Linux so disable its default + * values and assign MIPS gate register the default values. + * *Note*: All unused clocks will be gated by Linux + */ + setup_clk_gate_defaults(); + /* Setup SPIM1 MFIOs */ spim1_mfio_setup(); /* Setup UART1 clock and MFIOs diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index ab316e3..9f3da1a 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -82,6 +82,12 @@ #define MIPSCLKOUT_CTRL_ADDR 0xB8144208 #define MIPSCLKOUT_MASK 0x000000FF +/* Peripheral Clock gate reg */ +#define MIPS_CLOCK_GATE_ADDR 0xB8144900 +#define RPU_CLOCK_GATE_ADDR 0xB8144904 +#define MIPS_CLOCK_GATE_ALL_ON 0x3fff +#define RPU_CLOCK_GATE_ALL_OFF 0x0 + /* Definitions for USB clock setup */ #define USBPHYCLKOUT_CTRL_ADDR 0xB814422C #define USBPHYCLKOUT_MASK 0X0000003F @@ -499,3 +505,9 @@ void eth_clk_setup(u8 mux, u8 divider) write32(PISTACHIO_CLOCK_SWITCH, reg); } } + +void setup_clk_gate_defaults(void) +{ + write32(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON); + write32(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF); +} diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index fc07f0a..27ba6d6 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -32,6 +32,7 @@ void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface); int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); void rom_clk_setup(u8 divider); void eth_clk_setup(u8 mux, u8 divider); +void setup_clk_gate_defaults(void); enum { CLOCKS_OK = 0, PLL_TIMEOUT = -1,

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New patch to review for coreboot: imgtec/pistachio: memlayout: update GRAM size
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12772 -gerrit commit e5d41d543a2977cf6a54b51f777994803689fbf5 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Sun Nov 1 16:36:35 2015 +0000 imgtec/pistachio: memlayout: update GRAM size GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role of SRAM) was placed at a 4K aligned address, resulting in a size of 408KB. Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index a0b48b2..c84de40 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -39,7 +39,7 @@ SECTIONS ROMSTAGE(0x1a005000, 40K) VBOOT2_WORK(0x1a00f000, 12K) PRERAM_CBFS_CACHE(0x1a012000, 56K) - SRAM_END(0x1a020000) + SRAM_END(0x1a066000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. * This is identical to SRAM above, and thus also limited 64K and

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New patch to review for coreboot: imgtec/pistachio: I2C: fix base address for I2C clock setup
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12771 -gerrit commit ba55136fc13f317ea9e2c0ca5e8fe064a8737d56 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Tue Sep 15 13:56:30 2015 +0100 imgtec/pistachio: I2C: fix base address for I2C clock setup The base address for the I2C dividers (DIV1 and CLOCKOUT) was erroneously set to the toplevel clock controller base address and not to the correct peripherals clock controller base address. Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/clocks.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 74d241c..ab316e3 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -107,9 +107,9 @@ #define UART1CLKOUT_MASK 0x000003FF /* Definitions for I2C setup */ -#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144000 + 0x013C + (2*(i)*4)) +#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144800 + 0x013C + (2*(i)*4)) #define I2CCLKDIV1_MASK 0x0000007F -#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144000 + 0x0140 + (2*(i)*4)) +#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144800 + 0x0140 + (2*(i)*4)) #define I2CCLKOUT_MASK 0x0000007F /* Definitions for ROM clock setup */

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New patch to review for coreboot: imgtec/pistachio: identity map SOC registers region
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12770 -gerrit commit f96109ac327fa6f3b4074f489d362d4b81b0c5e0 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Dec 17 19:16:01 2015 +0000 imgtec/pistachio: identity map SOC registers region This region must be mapped uncached. This is necesary for an U-boot payload which will obtain all register base addresses as physical addresses from the device tree and will use them as such. Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/bootblock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index eceb814..23f6471 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -57,4 +57,6 @@ static void bootblock_mmu_init(void) assert(!identity_map((uint32_t)_sram, _sram_size, C0_ENTRYLO_COHERENCY_WB)); assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); + assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size, + C0_ENTRYLO_COHERENCY_UC)); }

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New patch to review for coreboot: mips: add coherency argument to identity mapping
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12769 -gerrit commit dd24a66ce5bb73703b16c9dcc5fa425d7086989c Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Jul 24 15:00:20 2015 +0100 mips: add coherency argument to identity mapping In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/arch/mips/include/arch/cpu.h | 18 ++++++++++++++---- src/arch/mips/include/arch/mmu.h | 2 +- src/arch/mips/mmu.c | 8 ++++---- src/soc/imgtec/pistachio/bootblock.c | 6 +++--- 4 files changed, 22 insertions(+), 12 deletions(-) diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 10fde8f..d43fd62 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -110,10 +110,20 @@ do { \ #define C0_ENTRYLO_PFN_SHIFT 6 -#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */ -#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */ -#define C0_ENTRYLO_V (0x1 << 1) /* Valid */ -#define C0_ENTRYLO_G (0x1 << 0) /* Global */ + +#define C0_ENTRYLO_COHERENCY_MASK 0x00000038 +#define C0_ENTRYLO_COHERENCY_SHIFT 3 +/* Cacheable, write-back, non-coherent */ +#define C0_ENTRYLO_COHERENCY_WB (0x3 << C0_ENTRYLO_COHERENCY_SHIFT) +/* Uncached, non-coherent */ +#define C0_ENTRYLO_COHERENCY_UC (0x2 << C0_ENTRYLO_COHERENCY_SHIFT) + +/* Writeable */ +#define C0_ENTRYLO_D (0x1 << 2) +/* Valid */ +#define C0_ENTRYLO_V (0x1 << 1) +/* Global */ +#define C0_ENTRYLO_G (0x1 << 0) #define C0_PAGEMASK_SHIFT 13 #define C0_PAGEMASK_MASK 0xffff diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h index ab17fec..8997e27 100644 --- a/src/arch/mips/include/arch/mmu.h +++ b/src/arch/mips/include/arch/mmu.h @@ -50,6 +50,6 @@ static inline uint32_t get_tlb_size(void) return tlbsize; } -int identity_map(uint32_t start, size_t len); +int identity_map(uint32_t start, size_t len, uint32_t coherency); #endif /* __MIPS_ARCH_MMU_H */ diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index 38f496d..b144fd3 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/mmu.h> #include <console/console.h> #include <stddef.h> @@ -70,22 +69,23 @@ static uint32_t pick_pagesize(uint32_t start, uint32_t len) * Identity map the memory from [start,start+len] in the TLB using the * largest suitable page size so as to conserve TLB entries. */ -int identity_map(uint32_t start, size_t len) +int identity_map(uint32_t start, size_t len, uint32_t coherency) { uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1; + coherency &= C0_ENTRYLO_COHERENCY_MASK; while (len > 0) { pgsize = pick_pagesize(start, len); entryhi = start; pfn = start >> 12; - entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | C0_ENTRYLO_WB | + entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency | C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G; start += pgsize; len -= MIN(len, pgsize); if (len >= pgsize) { pfn = start >> 12; entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) | - C0_ENTRYLO_WB | C0_ENTRYLO_D | C0_ENTRYLO_V | + coherency | C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G; start += pgsize; len -= MIN(len, pgsize); diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index 5d38278..eceb814 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -54,7 +54,7 @@ static void bootblock_mmu_init(void) dram_base += null_guard_size; dram_size -= null_guard_size; } - - assert(!identity_map(dram_base, dram_size)); - assert(!identity_map((uint32_t)_sram, _sram_size)); + assert(!identity_map((uint32_t)_sram, _sram_size, + C0_ENTRYLO_COHERENCY_WB)); + assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); }

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New patch to review for coreboot: imgtec/pistachio: add SOC_REGISTERS memory region
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12768 -gerrit commit c59f76f446bd266c2ba7ef351e4f872d7c12a905 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Jul 24 14:29:06 2015 +0100 imgtec/pistachio: add SOC_REGISTERS memory region When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/arch/mips/include/arch/memlayout.h | 2 ++ src/include/symbols.h | 4 ++++ src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 ++ 3 files changed, 8 insertions(+) diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index 1fc7c74..fe05bd8 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -26,4 +26,6 @@ #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) +#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4) + #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index aa055ec..662f44e 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -72,6 +72,10 @@ extern u8 _dma_coherent[]; extern u8 _edma_coherent[]; #define _dma_coherent_size (_edma_coherent - _dma_coherent) +extern u8 _soc_registers[]; +extern u8 _esoc_registers[]; +#define _soc_registers_size (_esoc_registers - _soc_registers) + extern u8 _framebuffer[]; extern u8 _eframebuffer[]; #define _framebuffer_size (_eframebuffer - _framebuffer) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index edf9c41..a0b48b2 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -29,6 +29,8 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00200000, 512K) RAMSTAGE(0x00280000, 128K) + /* 0x18100000 -> 0x18540000 */ + SOC_REGISTERS(0x18100000, 0x440000) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock * and then through the identity mapping in ROM stage.

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New patch to review for coreboot: imgtec/pistachio: use SYS PLL in integer mode
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12767 -gerrit commit bc2879302d221a1537ee202b0634d11a9272eeab Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Wed Jul 15 12:42:01 2015 +0100 imgtec/pistachio: use SYS PLL in integer mode Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/clocks.c | 40 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 43bdc55..74d241c 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -27,13 +27,19 @@ #define SYS_PLL_CTRL4_ADDR 0xB8144048 #define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000 #define SYS_PLL_PD_CTRL_ADDR 0xB8144044 -#define SYS_PLL_PD_CTRL_PD_MASK 0x0000003F +#define SYS_PLL_PD_CTRL_PD_MASK 0x00000039 +#define SYS_PLL_DACPD_ADDR 0xB8144044 +#define SYS_PLL_DACPD_MASK 0x00000002 +#define SYS_PLL_DSMPD_ADDR 0xB8144044 +#define SYS_PLL_DSMPD_MASK 0x00000004 #define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 #define MIPS_PLL_CTRL2_ADDR 0xB8144008 #define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000 #define MIPS_PLL_PD_CTRL_ADDR 0xB8144004 -#define MIPS_PLL_PD_CTRL_PD_MASK 0x0F000000 +#define MIPS_PLL_PD_CTRL_PD_MASK 0x0D000000 +#define MIPS_PLL_DSMPD_ADDR 0xB8144004 +#define MIPS_PLL_DSMPD_MASK 0x02000000 /* Definitions for PLL dividers */ #define SYS_PLL_POSTDIV_ADDR 0xB8144040 @@ -126,6 +132,10 @@ struct pll_parameters { u32 internal_bypass_mask; u32 power_down_ctrl_addr; u32 power_down_ctrl_mask; + u32 dacpd_addr; + u32 dacpd_mask; + u32 dsmpd_addr; + u32 dsmpd_mask; u32 postdiv_addr; u32 postdiv1_shift; u32 postdiv1_mask; @@ -155,6 +165,14 @@ static struct pll_parameters pll_params[] = { .internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK, .power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR, .power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK, + /* Noise cancellation */ + .dacpd_addr = SYS_PLL_DACPD_ADDR, + .dacpd_mask = SYS_PLL_DACPD_MASK, + .dsmpd_addr = SYS_PLL_DSMPD_ADDR, + /* 0 - Integer mode + * SYS_PLL_DSMPD_MASK - Fractional mode + */ + .dsmpd_mask = 0, .postdiv_addr = SYS_PLL_POSTDIV_ADDR, .postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT, .postdiv1_mask = SYS_PLL_POSTDIV1_MASK, @@ -178,6 +196,10 @@ static struct pll_parameters pll_params[] = { .internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK, .power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR, .power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK, + .dacpd_addr = 0, + .dacpd_mask = 0, + .dsmpd_addr = MIPS_PLL_DSMPD_ADDR, + .dsmpd_mask = MIPS_PLL_DSMPD_MASK, .postdiv_addr = MIPS_PLL_POSTDIV_ADDR, .postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT, .postdiv1_mask = MIPS_PLL_POSTDIV1_MASK, @@ -222,6 +244,20 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) reg &= ~(param->power_down_ctrl_mask); write32(param->power_down_ctrl_addr, reg); + /* Noise cancellation */ + if (param->dacpd_addr) { + reg = read32(param->dacpd_addr); + reg &= ~(param->dacpd_mask); + write32(param->dacpd_addr, reg); + } + + /* Functional mode */ + if (param->dsmpd_addr) { + reg = read32(param->dsmpd_addr); + reg &= ~(param->dsmpd_mask); + write32(param->dsmpd_addr, reg); + } + if (param->feedback_addr) { assert(!((param->feedback << param->feedback_shift) & ~(param->feedback_mask)));

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coreboot-gerrit December 2015