coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: imgtec/pistachio: add SOC_REGISTERS memory region
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12768 -gerrit commit 78cd04edcc1ee9e29416bf2be5bf543a4559c4a0 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Jul 24 14:29:06 2015 +0100 imgtec/pistachio: add SOC_REGISTERS memory region When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/arch/mips/include/arch/memlayout.h | 2 ++ src/include/symbols.h | 4 ++++ src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 ++ 3 files changed, 8 insertions(+) diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index 1fc7c74..fe05bd8 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -26,4 +26,6 @@ #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) +#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4) + #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index aa055ec..662f44e 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -72,6 +72,10 @@ extern u8 _dma_coherent[]; extern u8 _edma_coherent[]; #define _dma_coherent_size (_edma_coherent - _dma_coherent) +extern u8 _soc_registers[]; +extern u8 _esoc_registers[]; +#define _soc_registers_size (_esoc_registers - _soc_registers) + extern u8 _framebuffer[]; extern u8 _eframebuffer[]; #define _framebuffer_size (_eframebuffer - _framebuffer) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index edf9c41..a0b48b2 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -29,6 +29,8 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00200000, 512K) RAMSTAGE(0x00280000, 128K) + /* 0x18100000 -> 0x18540000 */ + SOC_REGISTERS(0x18100000, 0x440000) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock * and then through the identity mapping in ROM stage.

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Patch set updated for coreboot: imgtec/pistachio: I2C: fix base address for I2C clock setup
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12771 -gerrit commit bd32b84af17a9bc3616aeae60dbefe8a8fdae5bc Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Tue Sep 15 13:56:30 2015 +0100 imgtec/pistachio: I2C: fix base address for I2C clock setup The base address for the I2C dividers (DIV1 and CLOCKOUT) was erroneously set to the toplevel clock controller base address and not to the correct peripherals clock controller base address. Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/clocks.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 74d241c..ab316e3 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -107,9 +107,9 @@ #define UART1CLKOUT_MASK 0x000003FF /* Definitions for I2C setup */ -#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144000 + 0x013C + (2*(i)*4)) +#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144800 + 0x013C + (2*(i)*4)) #define I2CCLKDIV1_MASK 0x0000007F -#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144000 + 0x0140 + (2*(i)*4)) +#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144800 + 0x0140 + (2*(i)*4)) #define I2CCLKOUT_MASK 0x0000007F /* Definitions for ROM clock setup */

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Patch set updated for coreboot: imgtec/pistachio: identity map SOC registers region
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12770 -gerrit commit 6d768b0ff9bbea1e9f5263468527aff44f0a56c5 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Dec 17 19:16:01 2015 +0000 imgtec/pistachio: identity map SOC registers region This region must be mapped uncached. This is necesary for an U-boot payload which will obtain all register base addresses as physical addresses from the device tree and will use them as such. Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/bootblock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index eceb814..23f6471 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -57,4 +57,6 @@ static void bootblock_mmu_init(void) assert(!identity_map((uint32_t)_sram, _sram_size, C0_ENTRYLO_COHERENCY_WB)); assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); + assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size, + C0_ENTRYLO_COHERENCY_UC)); }

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Patch set updated for coreboot: imgtec/pistachio: disable default RPU gate register values
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12773 -gerrit commit 0ac78fed74686bd787ff6d8d3f577aeddb5ad3c3 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Sun Nov 1 19:55:48 2015 +0000 imgtec/pistachio: disable default RPU gate register values The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/mainboard/google/urara/bootblock.c | 8 ++++++++ src/soc/imgtec/pistachio/clocks.c | 12 ++++++++++++ src/soc/imgtec/pistachio/include/soc/clocks.h | 1 + 3 files changed, 21 insertions(+) diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 7775916..121f35d 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -190,6 +190,14 @@ static void bootblock_mainboard_init(void) if (ret != CLOCKS_OK) return; + /* + * Move peripheral clock control from RPU to MIPS. + * The RPU gate register is not managed in Linux so disable its default + * values and assign MIPS gate register the default values. + * *Note*: All unused clocks will be gated by Linux + */ + setup_clk_gate_defaults(); + /* Setup SPIM1 MFIOs */ spim1_mfio_setup(); /* Setup UART1 clock and MFIOs diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index ab316e3..9f3da1a 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -82,6 +82,12 @@ #define MIPSCLKOUT_CTRL_ADDR 0xB8144208 #define MIPSCLKOUT_MASK 0x000000FF +/* Peripheral Clock gate reg */ +#define MIPS_CLOCK_GATE_ADDR 0xB8144900 +#define RPU_CLOCK_GATE_ADDR 0xB8144904 +#define MIPS_CLOCK_GATE_ALL_ON 0x3fff +#define RPU_CLOCK_GATE_ALL_OFF 0x0 + /* Definitions for USB clock setup */ #define USBPHYCLKOUT_CTRL_ADDR 0xB814422C #define USBPHYCLKOUT_MASK 0X0000003F @@ -499,3 +505,9 @@ void eth_clk_setup(u8 mux, u8 divider) write32(PISTACHIO_CLOCK_SWITCH, reg); } } + +void setup_clk_gate_defaults(void) +{ + write32(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON); + write32(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF); +} diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index fc07f0a..27ba6d6 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -32,6 +32,7 @@ void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface); int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); void rom_clk_setup(u8 divider); void eth_clk_setup(u8 mux, u8 divider); +void setup_clk_gate_defaults(void); enum { CLOCKS_OK = 0, PLL_TIMEOUT = -1,

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Patch set updated for coreboot: imgtec/pistachio: memlayout: update GRAM size
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12772 -gerrit commit 5f2277d7d11acf466aef4d58756fb4934710244e Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Sun Nov 1 16:36:35 2015 +0000 imgtec/pistachio: memlayout: update GRAM size GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role of SRAM) was placed at a 4K aligned address, resulting in a size of 408KB. Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index a0b48b2..c84de40 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -39,7 +39,7 @@ SECTIONS ROMSTAGE(0x1a005000, 40K) VBOOT2_WORK(0x1a00f000, 12K) PRERAM_CBFS_CACHE(0x1a012000, 56K) - SRAM_END(0x1a020000) + SRAM_END(0x1a066000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. * This is identical to SRAM above, and thus also limited 64K and

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Patch set updated for coreboot: imgtec/pistachio: use SYS PLL in integer mode
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12767 -gerrit commit 37253b5d0a169b40fc4eda1023045d9869d9a77e Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Wed Jul 15 12:42:01 2015 +0100 imgtec/pistachio: use SYS PLL in integer mode Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/clocks.c | 40 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 43bdc55..74d241c 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -27,13 +27,19 @@ #define SYS_PLL_CTRL4_ADDR 0xB8144048 #define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000 #define SYS_PLL_PD_CTRL_ADDR 0xB8144044 -#define SYS_PLL_PD_CTRL_PD_MASK 0x0000003F +#define SYS_PLL_PD_CTRL_PD_MASK 0x00000039 +#define SYS_PLL_DACPD_ADDR 0xB8144044 +#define SYS_PLL_DACPD_MASK 0x00000002 +#define SYS_PLL_DSMPD_ADDR 0xB8144044 +#define SYS_PLL_DSMPD_MASK 0x00000004 #define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 #define MIPS_PLL_CTRL2_ADDR 0xB8144008 #define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000 #define MIPS_PLL_PD_CTRL_ADDR 0xB8144004 -#define MIPS_PLL_PD_CTRL_PD_MASK 0x0F000000 +#define MIPS_PLL_PD_CTRL_PD_MASK 0x0D000000 +#define MIPS_PLL_DSMPD_ADDR 0xB8144004 +#define MIPS_PLL_DSMPD_MASK 0x02000000 /* Definitions for PLL dividers */ #define SYS_PLL_POSTDIV_ADDR 0xB8144040 @@ -126,6 +132,10 @@ struct pll_parameters { u32 internal_bypass_mask; u32 power_down_ctrl_addr; u32 power_down_ctrl_mask; + u32 dacpd_addr; + u32 dacpd_mask; + u32 dsmpd_addr; + u32 dsmpd_mask; u32 postdiv_addr; u32 postdiv1_shift; u32 postdiv1_mask; @@ -155,6 +165,14 @@ static struct pll_parameters pll_params[] = { .internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK, .power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR, .power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK, + /* Noise cancellation */ + .dacpd_addr = SYS_PLL_DACPD_ADDR, + .dacpd_mask = SYS_PLL_DACPD_MASK, + .dsmpd_addr = SYS_PLL_DSMPD_ADDR, + /* 0 - Integer mode + * SYS_PLL_DSMPD_MASK - Fractional mode + */ + .dsmpd_mask = 0, .postdiv_addr = SYS_PLL_POSTDIV_ADDR, .postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT, .postdiv1_mask = SYS_PLL_POSTDIV1_MASK, @@ -178,6 +196,10 @@ static struct pll_parameters pll_params[] = { .internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK, .power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR, .power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK, + .dacpd_addr = 0, + .dacpd_mask = 0, + .dsmpd_addr = MIPS_PLL_DSMPD_ADDR, + .dsmpd_mask = MIPS_PLL_DSMPD_MASK, .postdiv_addr = MIPS_PLL_POSTDIV_ADDR, .postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT, .postdiv1_mask = MIPS_PLL_POSTDIV1_MASK, @@ -222,6 +244,20 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) reg &= ~(param->power_down_ctrl_mask); write32(param->power_down_ctrl_addr, reg); + /* Noise cancellation */ + if (param->dacpd_addr) { + reg = read32(param->dacpd_addr); + reg &= ~(param->dacpd_mask); + write32(param->dacpd_addr, reg); + } + + /* Functional mode */ + if (param->dsmpd_addr) { + reg = read32(param->dsmpd_addr); + reg &= ~(param->dsmpd_mask); + write32(param->dsmpd_addr, reg); + } + if (param->feedback_addr) { assert(!((param->feedback << param->feedback_shift) & ~(param->feedback_mask)));

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Patch set updated for coreboot: mainboard/google/urara: change SYS PLL to 700MHz
by Ionela Voinescu 17 Dec '15

17 Dec '15

Ionela Voinescu (ionela.voinescu(a)imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12765 -gerrit commit dbbd42aeb89e3d4ae51ac9002874962cd114a0ca Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Wed Jul 15 12:10:05 2015 +0100 mainboard/google/urara: change SYS PLL to 700MHz This requires changes the interface that sets up the system PLL to support a given reference devider value and given feedback value. Also, this requires a change in the dividers used for UART, USB, I2C setup. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/mainboard/google/urara/bootblock.c | 20 ++++++++++---------- src/soc/imgtec/pistachio/clocks.c | 25 +++++++++++++++++-------- src/soc/imgtec/pistachio/include/soc/clocks.h | 2 +- 3 files changed, 28 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 40696b6..7775916 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -172,7 +172,7 @@ static void bootblock_mainboard_init(void) { int ret; - /* System PLL divided by 2 -> 400 MHz */ + /* System PLL divided by 2 -> 350 MHz */ /* The same frequency will be the input frequency for the SPFI block */ system_clk_setup(1); @@ -181,8 +181,8 @@ static void bootblock_mainboard_init(void) * the values set or not by the boot ROM code */ mips_clk_setup(0, 0); - /* Setup system PLL at 800 MHz */ - ret = sys_pll_setup(2, 1); + /* Setup system PLL at 700 MHz */ + ret = sys_pll_setup(2, 1, 13, 350); if (ret != CLOCKS_OK) return; /* Setup MIPS PLL at 546 MHz */ @@ -193,9 +193,9 @@ static void bootblock_mainboard_init(void) /* Setup SPIM1 MFIOs */ spim1_mfio_setup(); /* Setup UART1 clock and MFIOs - * System PLL divided by 7 divided by 62 -> 1.8433 Mhz + * System PLL divided by 5 divided by 76 -> 1.8421 Mhz */ - uart1_clk_setup(6, 61); + uart1_clk_setup(4, 75); uart1_mfio_setup(); } @@ -213,23 +213,23 @@ static int init_extra_hardware(void) } /* Setup USB clock - * System clock divided by 8 -> 50 MHz + * System clock divided by 7 -> 50 MHz */ - if (usb_clk_setup(7, 2, 7) != CLOCKS_OK) { + if (usb_clk_setup(6, 2, 7) != CLOCKS_OK) { printk(BIOS_ERR, "%s: Failed to set up USB clock.\n", __func__); return -1; } /* Setup I2C clocks and MFIOs - * System PLL divided by 4 divided by 3 -> 33.33 MHz + * System clock divided by 4 divided by 3 -> 29.1(6) MHz */ i2c_clk_setup(3, 2, hardware->i2c_interface); i2c_mfio_setup(hardware->i2c_interface); /* Ethernet clocks setup: ENET as clock source */ - eth_clk_setup(0, 7); - /* ROM clock setup: system clock divided by 2 -> 200 MHz */ + eth_clk_setup(0, 6); + /* ROM clock setup: system clock divided by 2 -> 175 MHz */ /* Hash accelerator is driven from the ROM clock */ rom_clk_setup(1); diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 40c45b0..43bdc55 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -44,6 +44,13 @@ #define SYS_PLL_STATUS_ADDR 0xB8144038 #define SYS_PLL_STATUS_LOCK_MASK 0x00000001 +#define SYS_PLL_REFDIV_ADDR 0xB814403C +#define SYS_PLL_REFDIV_MASK 0x0000003F +#define SYS_PLL_REFDIV_SHIFT 0 +#define SYS_PLL_FEEDBACK_ADDR 0xB814403C +#define SYS_PLL_FEEDBACK_MASK 0x0003FFC0 +#define SYS_PLL_FEEDBACK_SHIFT 6 + #define MIPS_PLL_POSTDIV_ADDR 0xB8144004 #define MIPS_PLL_POSTDIV1_MASK 0x001C0000 #define MIPS_PLL_POSTDIV1_SHIFT 18 @@ -156,13 +163,13 @@ static struct pll_parameters pll_params[] = { .status_addr = SYS_PLL_STATUS_ADDR, .status_lock_mask = SYS_PLL_STATUS_LOCK_MASK, .refdivider = 0, /* Not defined yet */ - .refdiv_addr = 0, /* Not necessary */ - .refdiv_shift = 0, /* Not necessary */ - .refdiv_mask = 0, /* Not necessary */ - .feedback = 0, /* Not necessary */ - .feedback_addr = 0, /* Not necessary */ - .feedback_shift = 0, /* Not necessary */ - .feedback_mask = 0, /* Not necessary */ + .refdiv_addr = SYS_PLL_REFDIV_ADDR, + .refdiv_shift = SYS_PLL_REFDIV_SHIFT, + .refdiv_mask = SYS_PLL_REFDIV_MASK, + .feedback = 0, /* Not defined yet */ + .feedback_addr = SYS_PLL_FEEDBACK_ADDR, + .feedback_shift = SYS_PLL_FEEDBACK_SHIFT, + .feedback_mask = SYS_PLL_FEEDBACK_MASK }, [MIPS_PLL] = { @@ -263,8 +270,10 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) return CLOCKS_OK; } -int sys_pll_setup(u8 divider1, u8 divider2) +int sys_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) { + pll_params[SYS_PLL].refdivider = refdivider; + pll_params[SYS_PLL].feedback = feedback; return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2); } diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index f351a6f..fc07f0a 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -21,7 +21,7 @@ #include <stdint.h> /* Functions for PLL setting */ -int sys_pll_setup(u8 divider1, u8 divider2); +int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); /* Peripheral divider setting */

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Patch set updated for coreboot: google/veyron: Add commercial board names in Kconfig.name
by Martin Roth 17 Dec '15

17 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12652 -gerrit commit 5fa1157f6a4313c74feb0722396d5e482ac13cbb Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Dec 6 11:54:39 2015 +0100 google/veyron: Add commercial board names in Kconfig.name The correspondence between engineering code names and commercial names can be found on chromium.org website at: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-de… This it to make the names more relevant: towiki (in util/board_status/to-wiki/towiki.sh) will pick such names, which end up in the supported board list at: http://www.coreboot.org/Supported_Motherboards Change-Id: I2d705672d7202964fea3f62a5bd61a231d3f14c0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/google/veyron/Kconfig.name | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/veyron/Kconfig.name b/src/mainboard/google/veyron/Kconfig.name index 1ccffe5..c586293 100644 --- a/src/mainboard/google/veyron/Kconfig.name +++ b/src/mainboard/google/veyron/Kconfig.name @@ -3,22 +3,22 @@ config BOARD_GOOGLE_VEYRON_GUS select BOARD_GOOGLE_VEYRON config BOARD_GOOGLE_VEYRON_JAQ - bool "Veyron_Jaq" + bool "Haier Chromebook 11 (Veyron_Jaq)" select BOARD_GOOGLE_VEYRON select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_JERRY - bool "Veyron_Jerry" + bool "Hisense Chromebook 11 (Veyron_Jerry)" select BOARD_GOOGLE_VEYRON select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_MIGHTY - bool "Veyron_Mighty" + bool "Haier Chromebook 11(edu) (Veyron_Mighty)" select BOARD_GOOGLE_VEYRON select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_MINNIE - bool "Veyron_Minnie" + bool "ASUS Chromebook Flip C100 (Veyron_Minnie)" select BOARD_GOOGLE_VEYRON select SYSTEM_TYPE_LAPTOP @@ -35,7 +35,7 @@ config BOARD_GOOGLE_VEYRON_SHARK select BOARD_GOOGLE_VEYRON config BOARD_GOOGLE_VEYRON_SPEEDY - bool "Veyron_Speedy" + bool "ASUS C201 Chromebook (Veyron_Speedy)" select BOARD_GOOGLE_VEYRON select SYSTEM_TYPE_LAPTOP

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Patch merged into coreboot/master: google/veyron: Indicate which boards are laptops.
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit e87e73edbab113d81f4e38ee5b6b873be4333acb Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Dec 11 00:37:26 2015 +0100 google/veyron: Indicate which boards are laptops. This is to make towiki pick that information, to make these boards end up in the laptop list at: http://www.coreboot.org/Supported_Motherboards Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: https://review.coreboot.org/12716 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12716 for details. -gerrit

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Patch merged into coreboot/master: Drop src/cpu/ indirection for MIPS
by gerrit＠coreboot.org 17 Dec '15

17 Dec '15

the following patch was just integrated into master: commit c32e80d604c4a637c5fe80aa3dfd965df1312dc9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Dec 14 17:39:02 2015 -0800 Drop src/cpu/ indirection for MIPS Change-Id: I406166e650e07851ab1b293450fa29da8af075d9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/12724 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> See https://review.coreboot.org/12724 for details. -gerrit

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coreboot-gerrit December 2015