coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: fsp1_1: pass ROM_SIZE to FSP for cacheable RO region
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 2524be4aff63e01637d28d6866fa23a513a3b8b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 29 10:43:21 2015 -0500 fsp1_1: pass ROM_SIZE to FSP for cacheable RO region As vboot verification works on regions outside of CBFS pass the entire ROM_SIZE to FSP for creating a cacheable RO region. Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't work with non-power of 2 CBFS_SIZE. In practice the entire ROM should be attempted to be cached. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados w/ a 3MiB CBFS_SIZE. Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309770 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12260 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Avoid confusing usb debug output in dwc2 driver
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 102245fbed0b903e107880cb39a43bd8df757180 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Oct 26 19:48:25 2015 +0100 libpayload: Avoid confusing usb debug output in dwc2 driver enqueue_packet already runs start_ep_transfer, which enqueues the next job. It's pretty much guaranteed that the port will look busy. BUG=none BRANCH=none TEST=no spurious ep 0-0 busy messages Change-Id: I9cbfa7b51dd37564262295ddbcdd0755da40c05b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8997dbd78dc363334f4e22eaa61f25de1449ffba Original-Change-Id: I8a39713fc1d6f16b80284e0f21dc95685716a9b7 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308763 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: yunzhi li <lyz(a)rock-chips.com> Reviewed-on: http://review.coreboot.org/12259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12259 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Fix building dwc2 UDC driver with debug enabled
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit b791799d9a9936ab43143e5335f5200fa56db768 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Oct 26 19:48:25 2015 +0100 libpayload: Fix building dwc2 UDC driver with debug enabled hexdump() now takes a pointer instead of an int-containing-an-address. BUG=none BRANCH=none TEST=building with USB_DEBUG works Change-Id: Idd0c43031a212c8f3b6489f533c488805d98d6a9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8660f6091bb124eeabe73302e8c7f1a8e46324f1 Original-Change-Id: I266efcb8b939d6da104ad05a3e79a78065c60beb Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308762 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: yunzhi li <lyz(a)rock-chips.com> Reviewed-on: http://review.coreboot.org/12258 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12258 for details. -gerrit

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Patch merged into coreboot/master: skylake: Set Pkg Power clamping bit in Power Limit MSR
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 0dd72e8b1db78558ef148a5d67a2d12e73c36b94 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Oct 15 21:38:21 2015 +0530 skylake: Set Pkg Power clamping bit in Power Limit MSR Setting the Package Power clamping bits in Power Limit MSR (MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested P or T state for the time window specified for PL1 or PL2. BRANCH=none BUG=chrome-os-partner:47041 TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL, change the power limit value from default (TDP or 15W) to any lower value note that the Pkg power comes down and also the CPU frequency is lowered. Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309556 Original-Tested-by: Charulatha Varadarajan <charuprasanna(a)gmail.com> Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12257 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Allow non-default CBFS media
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit f86d0351051bddf98ed96a5da044b9779e35e9a1 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Oct 23 20:25:03 2015 +0200 libpayload: Allow non-default CBFS media CBFS requests were always fulfilled using the CBFS specified in cbtables. That's a great policy when default requests are sought, but not so great when the user deliberately asked for something else. So check if they want default CBFS media information, otherwise ignore cbtables data. BUG=chromium:445938 BRANCH=none TEST=none Change-Id: I01b63049eebfba6f467808ac84ef77385840c204 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 621c916ab14c0de4bae3dde09c05060c4f3c63c5 Original-Change-Id: Ia4a8848fd7db9d9a2bf9f5c226566fe3936ff543 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308520 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12232 for details. -gerrit

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New patch to review for coreboot: fsp_model_406dx: use external microcode .h files for rangeley
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12335 -gerrit commit 31fb3acca852fb82af7c861bc7aa302b57af90b3 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 09:00:20 2015 -0700 fsp_model_406dx: use external microcode .h files for rangeley The microcode for the Rangeley chip is supplied as .h files in the Rangeley FSP package. Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/fsp_model_406dx/Kconfig | 8 ++++---- src/cpu/intel/fsp_model_406dx/Makefile.inc | 3 --- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 5827c84..03f9a1f 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER + select USES_MICROCODE_HEADER_FILES choice prompt "Rangeley CPU Stepping" @@ -53,9 +54,8 @@ config ENABLE_VMX bool "Enable VMX for virtualization" default n -config CPU_MICROCODE_CBFS_LOC - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0xfff60040 +config CPU_MICROCODE_HEADER_FILES + string + default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d811d.h " endif #CPU_INTEL_FSP_MODEL_406DX diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index 7e18f1b..bb534a4 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -19,6 +19,3 @@ subdirs-y += ../../x86/name ramstage-y += acpi.c CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx -# We don't have microcode for this CPU -# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file -# cpu_microcode_bins += ???

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New patch to review for coreboot: fsp_baytrail: use external microcode .h files
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12334 -gerrit commit 3f3ffda00489049ed9a965e4713aefc6d0c1bdc5 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 08:06:54 2015 -0700 fsp_baytrail: use external microcode .h files The microcode for Bay Trail that's in the blobs repo is for the M and D chip variants only. The fsp_baytrail directory is for Bay Trail I chip variants, and will not boot if the M/D microcode is used. The microcode for the I variant is supplied as part of the Bay Trail FSP package. Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/fsp_baytrail/Kconfig | 5 +++++ src/soc/intel/fsp_baytrail/Makefile.inc | 2 -- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 7e7f217..3b9b3fb 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_INTEL_FIRMWARE select HAVE_SPI_CONSOLE_SUPPORT + select USES_MICROCODE_HEADER_FILES config SOC_INTEL_FSP_BAYTRAIL_MD bool @@ -98,6 +99,10 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS +config CPU_MICROCODE_HEADER_FILES + string + default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" + ## Baytrail Specific FSP Kconfig source src/soc/intel/fsp_baytrail/fsp/Kconfig diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index e52bceb..215f860 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -54,8 +54,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c -cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin - CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp

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New patch to review for coreboot: cpu: Add a way to use microcode .h files back to the build
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12333 -gerrit commit 09c03fb8b8baeb5045ff397df82c6bf223cbf63b Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 08:03:45 2015 -0700 cpu: Add a way to use microcode .h files back to the build The build was changed to remove usage of microcode .h files when all of the .h files were converted to binary. This is still needed for some builds when microcode binaries aren't in the blobs tree. Change-Id: Ia323c90efe8aa0b8799fc5cce6197509e466a105 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/Kconfig | 39 ++++++++++++++++++++++++++++++++++++--- src/cpu/Makefile.inc | 9 +++++++++ 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 578bab2..5509605 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -67,6 +67,13 @@ config SUPPORT_CPU_UCODE_IN_CBFS bool default n +config USES_MICROCODE_HEADER_FILES + def_bool n + select SUPPORT_CPU_UCODE_IN_CBFS + help + This is selected by a board or chipset to set the default for the + microcode source choice to a list of external microcode headers + # This variable is used to determine if we add CPU microcode to CBFS during the # build. Microcode can be added manually afterwards, or removed. As a result, # code should not rely on this to tell if a microcode update is present or not, @@ -80,6 +87,7 @@ config CPU_MICROCODE_ADDED_DURING_BUILD choice prompt "Include CPU microcode in CBFS" if ARCH_X86 + default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS @@ -96,10 +104,28 @@ config CPU_MICROCODE_CBFS_GENERATE If unsure, select this option. config CPU_MICROCODE_CBFS_EXTERNAL - bool "Include external microcode file" + bool "Include external binary microcode file" + help + Select this option if you want to include an external binary file + containing the CPU microcode. This will be included as a separate + file in CBFS. + + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_CBFS_EXTERNAL_HEADER + bool "Include external microcode header files" help - Select this option if you want to include an external file containing - the CPU microcode. This will be included as a separate file in CBFS. + Select this option if you want to include external c header files + containing the CPU microcode. This will be included as a separate + file in CBFS. + A word of caution: only select this option if you are sure the microcode that you have is newer than the microcode shipping with coreboot. @@ -167,3 +193,10 @@ config CPU_MICROCODE_FILE default "cpu_microcode.bin" help The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_HEADER_FILES + string "List of space separated microcode header files with the path" + depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER + help + A list of one or more microcode header files with path from the + coreboot directory. These should be separated by spaces. diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 52b58f7..42d8c68 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -30,6 +30,15 @@ cbfs_include_ucode = y endif endif +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +cpu_ucode_cbfs_file = $(objgenerated)/microcode.bin +cbfs_include_ucode = y + +$(objgenerated)/microcode.bin: + echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" + util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +endif + # We just mash all microcode binaries together into one binary to rule them all. # This approach assumes that the microcode binaries are properly padded, and # their headers specify the correct size. This works fairly well on isolatied

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New patch to review for coreboot: utils/scripts: Add microcode conversion tool
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12332 -gerrit commit e33a629738c755fe6d84b48ba05a514c6da111fe Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 07:51:28 2015 -0700 utils/scripts: Add microcode conversion tool This is an update to the script in the blobs repo that converts individual or multiple files into a microcode binary. Change-Id: I66fb650bbfa334d1f07e8e3914ef6deb8e72bbb4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/scripts/ucode_h_to_bin.sh | 60 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh new file mode 100755 index 0000000..4f51182 --- /dev/null +++ b/util/scripts/ucode_h_to_bin.sh @@ -0,0 +1,60 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Google Inc. +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ -z "$1" ] || [ -z "$2" ]; then + printf "Usage: %s <output file> \"<microcode .h files>\"\n" "$0" +fi + +OUTFILE=$1 +TMPFILE=$(mktemp microcode_XXXX) +cat > "${TMPFILE}.c" << EOF +#include <stdio.h> +unsigned int microcode[] = { +EOF + +for UCODE in ${@:2}; do + echo "#include \"$UCODE\"" >> "${TMPFILE}.c" +done + +cat >> "${TMPFILE}.c" << EOF +}; +int main(void) +{ + FILE *f = fopen("$OUTFILE", "wb"); + fwrite(microcode, sizeof(microcode), 1, f); + fclose(f); + return 0; +} +EOF + +gcc -o "$TMPFILE" "${TMPFILE}.c" +"./$TMPFILE" +rm "$TMPFILE" "${TMPFILE}.c"

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Patch merged into coreboot/master: nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 593e7de5a777db0310da7221f81982b6b3ed4929 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Nov 4 15:46:00 2015 +0100 nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge The touched workaround for Sandy Bridge reserves two memory regions that could cause graphics corruption if mapped by the integrated graphics device. To the best of our knowledge, the workaround is not needed for Ivy Bridge revisions. Tested on kontron/ktqm77 (Ivy Bridge): Booted Linux and checked the memory regions are not reserved. Couldn't test on Sandy Bridge, due to lack of hardware. Change-Id: I4273d1d804b490cf93c23426782eb1ffaf29f7d4 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/12326 Reviewed-by: Duncan Laurie <dlaurie(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12326 for details. -gerrit

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coreboot-gerrit November 2015