coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: fsp_baytrail: use external microcode .h files
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12334 -gerrit commit c8159e7aa971a53488dd6f5eba8410186dfb7725 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 08:06:54 2015 -0700 fsp_baytrail: use external microcode .h files The microcode for Bay Trail that's in the blobs repo is for the M and D chip variants only. The fsp_baytrail directory is for Bay Trail I chip variants, and will not boot if the M/D microcode is used. The microcode for the I variant is supplied as part of the Bay Trail FSP package. Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/fsp_baytrail/Kconfig | 7 +++++++ src/soc/intel/fsp_baytrail/Makefile.inc | 2 -- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 7e7f217..ff23308 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS select HAVE_INTEL_FIRMWARE select HAVE_SPI_CONSOLE_SUPPORT + # Microcode header files are delivered in FSP package + select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN + config SOC_INTEL_FSP_BAYTRAIL_MD bool default n @@ -98,6 +101,10 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS +config CPU_MICROCODE_HEADER_FILES + string + default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" + ## Baytrail Specific FSP Kconfig source src/soc/intel/fsp_baytrail/fsp/Kconfig diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index e52bceb..215f860 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -54,8 +54,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c -cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin - CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp

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Patch set updated for coreboot: fsp_model_406dx: use external microcode .h files for rangeley
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12335 -gerrit commit 49ddc564903bdb2d84a4f5b23b779d8f346320ed Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 09:00:20 2015 -0700 fsp_model_406dx: use external microcode .h files for rangeley The microcode for the Rangeley chip is supplied as .h files in the Rangeley FSP package. Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/fsp_model_406dx/Kconfig | 7 +++++++ src/cpu/intel/fsp_model_406dx/Makefile.inc | 3 --- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 5827c84..87c772a 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -33,6 +33,9 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER + # Microcode header files are delivered in FSP package + select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN + choice prompt "Rangeley CPU Stepping" default FSP_MODEL_406DX_B0 @@ -58,4 +61,8 @@ config CPU_MICROCODE_CBFS_LOC depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff60040 +config CPU_MICROCODE_HEADER_FILES + string + default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d811d.h " + endif #CPU_INTEL_FSP_MODEL_406DX diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index 7e18f1b..bb534a4 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -19,6 +19,3 @@ subdirs-y += ../../x86/name ramstage-y += acpi.c CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx -# We don't have microcode for this CPU -# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file -# cpu_microcode_bins += ???

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Patch set updated for coreboot: utils/scripts: Add microcode conversion tool
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12332 -gerrit commit ef34ae66580642dee4765c95e1a9c63881050790 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 07:51:28 2015 -0700 utils/scripts: Add microcode conversion tool This is an update to the script in the blobs repo that converts individual or multiple files into a microcode binary. Change-Id: I66fb650bbfa334d1f07e8e3914ef6deb8e72bbb4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/scripts/ucode_h_to_bin.sh | 60 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh new file mode 100755 index 0000000..4f51182 --- /dev/null +++ b/util/scripts/ucode_h_to_bin.sh @@ -0,0 +1,60 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Google Inc. +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ -z "$1" ] || [ -z "$2" ]; then + printf "Usage: %s <output file> \"<microcode .h files>\"\n" "$0" +fi + +OUTFILE=$1 +TMPFILE=$(mktemp microcode_XXXX) +cat > "${TMPFILE}.c" << EOF +#include <stdio.h> +unsigned int microcode[] = { +EOF + +for UCODE in ${@:2}; do + echo "#include \"$UCODE\"" >> "${TMPFILE}.c" +done + +cat >> "${TMPFILE}.c" << EOF +}; +int main(void) +{ + FILE *f = fopen("$OUTFILE", "wb"); + fwrite(microcode, sizeof(microcode), 1, f); + fclose(f); + return 0; +} +EOF + +gcc -o "$TMPFILE" "${TMPFILE}.c" +"./$TMPFILE" +rm "$TMPFILE" "${TMPFILE}.c"

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Patch set updated for coreboot: cpu: Add a way to use microcode .h files back to the build
by Martin Roth 05 Nov '15

05 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12333 -gerrit commit 048fbba5647f4d66c58b6b9fc7427e69d63f3c83 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 08:03:45 2015 -0700 cpu: Add a way to use microcode .h files back to the build The build was changed to remove usage of microcode .h files when all of the .h files were converted to binary. This is still needed for some builds when microcode binaries aren't in the blobs tree. Change-Id: Ia323c90efe8aa0b8799fc5cce6197509e466a105 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/Kconfig | 31 +++++++++++++++++++++++++++++++ src/cpu/Makefile.inc | 11 ++++++++++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 9b9413c..a026b28 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -67,8 +67,16 @@ config SUPPORT_CPU_UCODE_IN_CBFS bool default n +config USES_MICROCODE_HEADER_FILES + def_bool n + select SUPPORT_CPU_UCODE_IN_CBFS + help + This is selected by a board or chipset to set the default for the + microcode source choice to a list of external microcode headers + choice prompt "Include CPU microcode in CBFS" if ARCH_X86 + default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS @@ -84,6 +92,22 @@ config CPU_MICROCODE_CBFS_GENERATE If unsure, select this option. +config CPU_MICROCODE_CBFS_EXTERNAL_HEADER + bool "Include external microcode header files" + help + Select this option if you want to include external c header files + containing the CPU microcode. This will be included as a separate + file in CBFS. + + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + config CPU_MICROCODE_CBFS_NONE bool "Do not include microcode updates" help @@ -135,3 +159,10 @@ config CPU_MICROCODE_MULTIPLE_FILES help Select this option to install separate microcode container files into CBFS instead of using the traditional monolithic microcode file format. + +config CPU_MICROCODE_HEADER_FILES + string "List of space separated microcode header files with the path" + depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER + help + A list of one or more microcode header files with path from the + coreboot directory. These should be separated by spaces. diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 517cbfa..046c418 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -21,6 +21,15 @@ ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin endif +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +cbfs-files-y += cpu_microcode_blob.bin +cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin + +$(objgenerated)/microcode.bin: + echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" + util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +endif + # We just mash all microcode binaries together into one binary to rule them all. # This approach assumes that the microcode binaries are properly padded, and # their headers specify the correct size. This works fairly well on isolatied @@ -33,7 +42,7 @@ $(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) @echo $(cpu_microcode_bins) cat /dev/null $+ > $@ -cpu_microcode_blob.bin-file := $(obj)/cpu_microcode_blob.bin +cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)

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New patch to review for coreboot: model_fxx: Check FID&VID Support for the BSP (too)
by Urja Rannikko 05 Nov '15

05 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12336 -gerrit commit 91895108e1f05da82bb41dea950bb8c52a4d8e6b Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 19:24:11 2015 +0200 model_fxx: Check FID&VID Support for the BSP (too) Tested in the direction that now my Sempron 2800+ / K8V-X boots. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/cpu/amd/model_fxx/fidvid.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index a005c46..be66378 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -536,6 +536,10 @@ static void init_fidvid_bsp(unsigned bsp_apicid) unsigned i; #endif + if((cpuid_edx(0x80000007)&0x06)!=0x06) { + return; /* FID/VID change not supported */ + } + msr_t msr; msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */

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Patch merged into coreboot/master: libpayload: xhci: Add delay to get reset working more reliably
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 1528ffa57cdc8bfbea80ce6d23b9acddef68614e Author: Rajmohan Mani <rajmohan.mani(a)intel.com> Date: Fri Oct 30 17:00:24 2015 -0700 libpayload: xhci: Add delay to get reset working more reliably Existing Intel xHCI controllers require a delay of 1 ms, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang in depthcharge. BRANCH=None BUG=None TEST=Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles, without any xHCI reset hang in depthcharge. Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460 Original-Signed-off-by: Rajmohan Mani <rajmohan.mani(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310022 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12325 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/12325 for details. -gerrit

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Patch merged into coreboot/master: google/chell: Fix USB port assignment
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 77d37d21dbb0a52cdf0af17bf20b8ff49ba69256 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 30 17:55:05 2015 -0700 google/chell: Fix USB port assignment The PCH pin names in the schematic were incorrectly labeled. BUG=chrome-os-partner:46289 BRANCH=none TEST=build and boot on chell Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/310061 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12324 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12324 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu, google/glados: Enable Fan control support
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 47657ea1e13885b68485023312adfdf90f615a07 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Oct 19 14:57:43 2015 +0530 intel/kunimitsu, google/glados: Enable Fan control support This patch enables the Fan thermal participant device in the device tree for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. This patch defines the _ART table in dptf ASL file. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307028 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12323 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12323 for details. -gerrit

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Patch merged into coreboot/master: intel/skylake: Add Fan control support
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit 2ca76e688cd74f021c4d0a2e74a83b7baa41f6bd Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Oct 19 14:45:23 2015 +0530 intel/skylake: Add Fan control support This patch adds the ASL file for Fan as cooling device /participant for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: Iacfd9152e300ec47895c29deab2c9d4361230849 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d37a089b5196f02cb95f16083c416456e96d54a4 Original-Change-Id: I8293bfe2a2bf213b69fbb4223bbfcf508a9cf0bf Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307027 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12322 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12322 for details. -gerrit

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Patch merged into coreboot/master: nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit a28e9084bf58dc4094a3383b2887a50b9756f2e1 Author: Joseph Lo <josephl(a)nvidia.com> Date: Wed Oct 28 15:34:22 2015 +0800 nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0 The MC/SMMU should be resumed by the kernel. And the unexpected value in the MC_INTSTATUS should be cleared before that. Or it will cause some noisy MC interrupt once we enable the IRQ in the kernel. BUG=chrome-os-partner:46796 BRANCH=none TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors should not be observed on resume. Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309248 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic(a)chromium.org> Original-Commit-Queue: Joseph Lo <yushun.lo(a)gmail.com> Original-Tested-by: Joseph Lo <yushun.lo(a)gmail.com> Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95) Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309497 Original-Commit-Ready: Andrew Bresticker <abrestic(a)chromium.org> Reviewed-on: http://review.coreboot.org/12321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12321 for details. -gerrit

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coreboot-gerrit November 2015