coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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1544 discussions

Patch set updated for coreboot: amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11975 -gerrit commit 180d12b59409d30cca68c7b40e4f794c7335124e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 4 00:10:03 2015 -0500 amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4371a37..dd01be0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3663,6 +3663,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, u8 devwidth; u16 DimmSlots; u8 byte = 0, bytex; + uint8_t crc_status; /* preload data structure with addrs */ mctGet_DIMMAddr(pDCTstat, pDCTstat->Node_ID); @@ -3683,10 +3684,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, int status; smbaddr = Get_DIMMAddress_D(pDCTstat, i); status = mctRead_SPD(smbaddr, SPD_ByteUse); + if (status >= 0) { + /* Verify result */ + status = mctRead_SPD(smbaddr, SPD_ByteUse); + } if (status >= 0) { /* SPD access is ok */ pDCTstat->DIMMPresent |= 1 << i; read_spd_bytes(pMCTstat, pDCTstat, i); - if (crcCheck(pDCTstat, i)) { /* CRC is OK */ + crc_status = crcCheck(pDCTstat, i); + if (!crc_status) { + /* Try again in case there was a transient glitch */ + read_spd_bytes(pMCTstat, pDCTstat, i); + crc_status = crcCheck(pDCTstat, i); + } + if (crc_status) { /* CRC is OK */ byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/

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Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Add Family 15h microcode file
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11968 -gerrit commit 7eff9c154ad53dd576d44376466f28beb0e1872d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Oct 16 14:08:32 2015 -0500 cpu/amd/family_10h-family_15h: Add Family 15h microcode file Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index 5a81ab8..6cd2513 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -12,3 +12,8 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin microcode_amd.bin-type := microcode + +# Microcode for Family 15h +cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +microcode_amd_fam15h.bin-type := microcode

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Patch set updated for coreboot: amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11969 -gerrit commit a7b6bcb6b83c9ff7ae25c8b5649a43e2b50181c4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 1 20:35:42 2015 -0500 amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 80a85ff..f4bf402 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1848,11 +1848,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, if (nv_DQSTrainCTL) { mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); - /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); + if (!is_fam15h()) { + /* TODO: should be in mctHookBeforeAnyTraining */ + _WRMSR(0x26C, 0x04040404, 0x04040404); + _WRMSR(0x26D, 0x04040404, 0x04040404); + _WRMSR(0x26E, 0x04040404, 0x04040404); + _WRMSR(0x26F, 0x04040404, 0x04040404); + } mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); if (is_fam15h()) {

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Patch set updated for coreboot: cpu/amd/car: Add romstage BSP stack overrun detection
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11970 -gerrit commit 8145913b72f5d5cdc85fbba0ce2ba13dd3e9374a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 1 23:58:59 2015 -0500 cpu/amd/car: Add romstage BSP stack overrun detection Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/car/cache_as_ram.inc | 6 +++++- src/cpu/amd/car/post_cache_as_ram.c | 8 ++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 9874ec4..3295ccc 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -20,7 +20,7 @@ #include <cpu/amd/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) +#define CacheBase CONFIG_DCACHE_RAM_BASE #define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE #define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH @@ -496,6 +496,10 @@ CAR_skip_k8_errata_part2: movl $(CacheBase + CacheSize), %eax movl %eax, %esp + /* Poison the lower stack boundary */ + movl $((CacheBase + CacheSize) - CacheSizeBSPStack), %eax + movl $0xdeadbeef, (%eax) + post_code(0xa3) jmp CAR_FAM10_ap_out diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 49b9ee3..0865b42 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -98,6 +98,14 @@ void post_cache_as_ram(void) void *resume_backup_memory = NULL; uint32_t family = amd_fam1x_cpu_family(); + /* Verify that the BSP didn't overrun the lower stack + * boundary during romstage execution + */ + volatile uint32_t *lower_stack_boundary; + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_STACK_SIZE); + if ((*lower_stack_boundary) != 0xdeadbeef) + printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); + struct romstage_handoff *handoff; handoff = romstage_handoff_find_or_add(); if (handoff != NULL)

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Patch set updated for coreboot: cpu/amd/car: Increase Family 10h CAR size limit to 128k
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11971 -gerrit commit 5c083c691675a40501827136ce8b5bc1465305e0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 13:25:23 2015 -0500 cpu/amd/car: Increase Family 10h CAR size limit to 128k This resolves issues with 4-node (32-core) systems not having sufficient CAR memory to boot. Change-Id: I5378df7fe8c034ba30f7fdf454f81dd10a0c2ae4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/car/post_cache_as_ram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 0865b42..26e611c 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -102,7 +102,7 @@ void post_cache_as_ram(void) * boundary during romstage execution */ volatile uint32_t *lower_stack_boundary; - lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_STACK_SIZE); + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_DCACHE_BSP_STACK_SIZE); if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");

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Patch set updated for coreboot: crossgcc: Update makefile builds
by Martin Roth 06 Nov '15

06 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12300 -gerrit commit a00c52d21b42d624b10166b2fb587fe125d281c0 Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 27 15:03:46 2015 -0600 crossgcc: Update makefile builds - Only build IASL once for the 'all' targets instead of once for each. - Change the control of what gets built from different targets to variables on the build line. - Clean up and correct the list of phony targets - Don't keep the temporary files around while building all. This takes up a lot of space. If it's desired behavior, add BUILDGCC_OPTIONS=-t on the make command line. - Add comments about CPU= and BUILDGCC_OPTIONS= variables - Add KEEP_SOURCES option Change-Id: I7752974e249f25717b42be25a841c69af84d5c69 Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 21 ++++++++++------ util/crossgcc/Makefile | 66 +++++++++++++++++++++----------------------------- 2 files changed, 41 insertions(+), 46 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index de148cb..91d4ff1 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -442,28 +442,33 @@ gitconfig: git config remote.origin.push HEAD:refs/for/master (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) -crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use BUILDGCC_OPTIONS= to set any crossgcc command line options +# Example: BUILDGCC_OPTIONS='-t' will keep temporary files after build +crossgcc: + $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 .PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv crossgcc-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386-without-gdb + $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 crossgcc-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64-without-gdb + $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a-without-gdb + $(MAKE) -C util/crossgcc build-armv7a SKIP_GDB=1 crossgcc-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64-without-gdb + $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 crossgcc-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips-without-gdb + $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 crossgcc-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv-without-gdb + $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 -crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv +crosstools: + $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 .PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-i386: clean-for-update diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 1f1dc1f..152115c 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,38 +1,48 @@ # if no architecture is specified, set a default BUILD_PLATFORM ?= i386-elf -all: - $(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang - $(MAKE) clean_tempfiles +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use KEEP_SOURCES=1 to keep temporary files after the build +# use BUILDGCC_OPTIONS= to set any other crossgcc command line options +# Example: BUILDGCC_OPTIONS=-c to remove temporary files before build + +all all_with_gdb: + $(MAKE) build-i386 + $(MAKE) SKIP_IASL=1 \ + build-x64 build-armv7a build-mips build-riscv build-aarch64 \ + build_clang all_without_gdb: - $(MAKE) BUILDGCC_OPTIONS=-t build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ - build-mips-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang - $(MAKE) clean_tempfiles + $(MAKE) SKIP_GDB=1 build-i386 + $(MAKE) SKIP_IASL=1 SKIP_GDB=1 \ + build-x64 build-armv7a build-mips build-riscv build-aarch64 \ + build_clang build_tools: build_gcc build_iasl build_gdb -build_tools_without_gdb: build_gcc build_iasl - ########################################################### ### targets to do buildgcc builds build_gcc: - bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) \ + bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) \ $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) build_gdb: - bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_GDB),) + bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif build_iasl: - bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_IASL),) + bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif build_clang: - bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_CLANG),) + bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif ########################################################### -### Build with GDB ### build-i386: @$(MAKE) build_tools BUILD_PLATFORM=i386-elf @@ -51,26 +61,6 @@ build-mips: build-riscv: @$(MAKE) build_tools BUILD_PLATFORM=riscv-elf -########################################################### -### Build without GDB -build-i386-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=i386-elf - -build-x64-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=x86_64-elf - -build-armv7a-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=armv7a-eabi - -build-aarch64-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=aarch64-elf - -build-mips-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipsel-elf - -build-riscv-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=riscv-elf - clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -85,7 +75,7 @@ clean: clean_tempfiles distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_gdb build_tools build_tools_without_gdb \ - build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ - build-aarch64-without-gdb build-mips-without-gdb build-riscv-without-gdb \ - all build clean distclean clean_tempfiles all_without_gdb +.PHONY: build_gcc build_iasl build_gdb build_clang \ + all all_with_gdb all_without_gdb build_tools \ + build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv \ + clean distclean clean_tempfiles

1 0

Patch set updated for coreboot: crossgcc: Update makefile builds
by Martin Roth 06 Nov '15

06 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12300 -gerrit commit ade299d4170c22b5ce8c793dc5b97edd13a6e5ea Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 27 15:03:46 2015 -0600 crossgcc: Update makefile builds - Only build IASL once for the 'all' targets instead of once for each. - Change the control of what gets built from different targets to variables on the build line. - Clean up and correct the list of phony targets - Don't keep the temporary files around while building all. This takes up a lot of space. If it's desired behavior, add BUILDGCC_OPTIONS=-t on the make command line. - Add comments about CPU= and BUILDGCC_OPTIONS= variables - Add KEEP_SOURCES option Change-Id: I7752974e249f25717b42be25a841c69af84d5c69 Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 21 ++++++++++------- util/crossgcc/Makefile | 64 +++++++++++++++++++++----------------------------- 2 files changed, 40 insertions(+), 45 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index de148cb..91d4ff1 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -442,28 +442,33 @@ gitconfig: git config remote.origin.push HEAD:refs/for/master (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) -crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use BUILDGCC_OPTIONS= to set any crossgcc command line options +# Example: BUILDGCC_OPTIONS='-t' will keep temporary files after build +crossgcc: + $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 .PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv crossgcc-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386-without-gdb + $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 crossgcc-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64-without-gdb + $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a-without-gdb + $(MAKE) -C util/crossgcc build-armv7a SKIP_GDB=1 crossgcc-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64-without-gdb + $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 crossgcc-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips-without-gdb + $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 crossgcc-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv-without-gdb + $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 -crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv +crosstools: + $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 .PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-i386: clean-for-update diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 1f1dc1f..19d1669 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,20 +1,25 @@ # if no architecture is specified, set a default BUILD_PLATFORM ?= i386-elf -all: - $(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang - $(MAKE) clean_tempfiles +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use KEEP_SOURCES=1 to keep temporary files after the build +# use BUILDGCC_OPTIONS= to set any other crossgcc command line options +# Example: BUILDGCC_OPTIONS=-c to remove temporary files before build + +all all_with_gdb: + $(MAKE) build-i386 + $(MAKE) SKIP_IASL=1 \ + build-x64 build-armv7a build-mips build-riscv build-aarch64 \ + build_clang all_without_gdb: - $(MAKE) BUILDGCC_OPTIONS=-t build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ - build-mips-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang - $(MAKE) clean_tempfiles + $(MAKE) SKIP_GDB=1 build-i386 + $(MAKE) SKIP_IASL=1 SKIP_GDB=1 \ + build-x64 build-armv7a build-mips build-riscv build-aarch64 \ + build_clang build_tools: build_gcc build_iasl build_gdb -build_tools_without_gdb: build_gcc build_iasl - ########################################################### ### targets to do buildgcc builds @@ -23,16 +28,21 @@ build_gcc: $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) build_gdb: - bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_GDB),) + bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif build_iasl: - bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_IASL),) + bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif build_clang: - bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_CLANG),) + bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif ########################################################### -### Build with GDB ### build-i386: @$(MAKE) build_tools BUILD_PLATFORM=i386-elf @@ -51,26 +61,6 @@ build-mips: build-riscv: @$(MAKE) build_tools BUILD_PLATFORM=riscv-elf -########################################################### -### Build without GDB -build-i386-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=i386-elf - -build-x64-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=x86_64-elf - -build-armv7a-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=armv7a-eabi - -build-aarch64-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=aarch64-elf - -build-mips-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipsel-elf - -build-riscv-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=riscv-elf - clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -85,7 +75,7 @@ clean: clean_tempfiles distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_gdb build_tools build_tools_without_gdb \ - build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ - build-aarch64-without-gdb build-mips-without-gdb build-riscv-without-gdb \ - all build clean distclean clean_tempfiles all_without_gdb +.PHONY: build_gcc build_iasl build_gdb build_clang \ + all all_with_gdb all_without_gdb build_tools \ + build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv \ + clean distclean clean_tempfiles

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New patch to review for coreboot: soc/intel/braswell: Drop gfx_read_resources()
by Nico Huber 05 Nov '15

05 Nov '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12338 -gerrit commit 7518a8fdc3dc7e662e981db31f7bd2d9a603f732 Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Nov 5 23:27:06 2015 +0100 soc/intel/braswell: Drop gfx_read_resources() Drop the last remnant of vanished CONFIG_MARK_GRAPHICS_MEM_WRCOMB. Could not build test google/cyan and intel/strago due to lack of UEFI headers, OMG. Change-Id: I0b9eac5c040d24bab2b85e9b63042b6aaa9879d9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/soc/intel/braswell/gfx.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 3cbffc6..4328abb 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -75,28 +75,8 @@ static void gfx_init(device_t dev) gfx_post_vbios_init(dev); } -static void gfx_read_resources(device_t dev) -{ - printk(BIOS_SPEW, "%s/%s ( %s )\n", - __FILE__, __func__, dev_name(dev)); - - pci_dev_read_resources(dev); - -#if IS_ENABLED(CONFIG_MARK_GRAPHICS_MEM_WRCOMB) - struct resource *res; - - /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); - if (res == NULL) { - printk(BIOS_DEBUG, "GFX: memory resource not found.\n"); - return; - } - res->flags |= IORESOURCE_WRCOMB; -#endif -} - static struct device_operations gfx_device_ops = { - .read_resources = gfx_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init,

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Patch set updated for coreboot: mainboard/asus: F2A85-M PRO: switch superIO
by Stefan Reinauer 05 Nov '15

05 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12302 -gerrit commit 0104fa64d6bd5e26c2baceb73354e47975d59b1c Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Jul 30 19:41:57 2015 +0200 mainboard/asus: F2A85-M PRO: switch superIO Change-Id: Ifa799b5e66ef4b93d464bfeccca27165e82b966b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/f2a85-m_pro/Kconfig | 2 +- src/mainboard/asus/f2a85-m_pro/devicetree.cb | 50 ++-------- src/mainboard/asus/f2a85-m_pro/romstage.c | 140 ++++++++++++++++++++++++++- 3 files changed, 147 insertions(+), 45 deletions(-) diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig b/src/mainboard/asus/f2a85-m_pro/Kconfig index b437ed6..4353444 100644 --- a/src/mainboard/asus/f2a85-m_pro/Kconfig +++ b/src/mainboard/asus/f2a85-m_pro/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES - select SUPERIO_ITE_IT8728F + select SUPERIO_NUVOTON_NCT6779D select BOARD_ROMSIZE_KB_8192 select GFXUMA select HUDSON_DISABLE_IMC diff --git a/src/mainboard/asus/f2a85-m_pro/devicetree.cb b/src/mainboard/asus/f2a85-m_pro/devicetree.cb index 4562557..bde400e 100644 --- a/src/mainboard/asus/f2a85-m_pro/devicetree.cb +++ b/src/mainboard/asus/f2a85-m_pro/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2015 Denis 'GNUtoo' Carikli <gnutoo(a)no-log.org> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -56,56 +57,19 @@ chip northbridge/amd/agesa/family15tn/root_complex chip drivers/generic/generic #dimm 1 device i2c 51 on end # 7-bit SPD address end - end # SM + end # SMBUS device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - register hwm_ctl_register = "0xc0" - register hwm_main_ctl_register = "0x33" - register hwm_adc_temp_chan_en_reg = "0x38" - register hwm_fan1_ctl_pwm = "0x00" - register hwm_fan2_ctl_pwm = "0x00" - register hwm_fan3_ctl_pwm = "0x00" - - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 + chip superio/nuvoton/nct6779d + device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 + device pnp 2e.a on # ACPI + irq 0xe7 = 0x10 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 #SMI - io 0x62 = 0x300 #Simple I/O - io 0x64 = 0x238 #Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f + end end #device pci 14.3 # LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 diff --git a/src/mainboard/asus/f2a85-m_pro/romstage.c b/src/mainboard/asus/f2a85-m_pro/romstage.c index 0062c87..feeec61 100644 --- a/src/mainboard/asus/f2a85-m_pro/romstage.c +++ b/src/mainboard/asus/f2a85-m_pro/romstage.c @@ -1 +1,139 @@ -#include "../f2a85-m/romstage.c" +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2015 Denis 'GNUtoo' Carikli <gnutoo(a)no-log.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include <arch/acpi.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/car.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pnp_def.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + u8 byte; + device_t dev; + +#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) + hudson_pci_port80(); +#endif +#if IS_ENABLED(CONFIG_POST_DEVICE_LPC) + hudson_lpc_port80(); +#endif + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + post_code(0x30); + // TODO: SB SuperIO init ? + + post_code(0x31); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + post_code(0x39); + + agesawrapper_amdinitearly(); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + post_code(0x41); + agesawrapper_amdinitenv(); + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

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Patch merged into coreboot/master: intel/i945: Consolidate MADT handling
by gerrit＠coreboot.org 05 Nov '15

05 Nov '15

the following patch was just integrated into master: commit d5d94ea90a9402b480cde91febe1dc7d85f626b5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 18 02:13:11 2014 +0200 intel/i945: Consolidate MADT handling Change-Id: Ic3cdfa6086a45aa231aa817d5ef6998823589818 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7108 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/7108 for details. -gerrit

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coreboot-gerrit November 2015