coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch merged into coreboot/master: AMD Bettong: Enable S4 feature for Windows 7
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit 1897c2c3508f3d5e2d020c6e56f16611c8cfad4a Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 20:25:59 2015 +0800 AMD Bettong: Enable S4 feature for Windows 7 PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise going into hibernation can not be wake up. Change-Id: I692497bad24d745738d670897e725a568c1db114 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/11373 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11373 for details. -gerrit

1 0

Patch merged into coreboot/master: amd/pi/Makefile: Remove cp option '-u'
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit aeb2103ab5184d46dc315f616acbf521f3aa1ab4 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Sep 11 09:11:49 2015 -0400 amd/pi/Makefile: Remove cp option '-u' "-u" is only for GNU cp. Cp of BSD and Solaris don't take this option. It is not necessary to compare the files before copying. Change-Id: I60cf57991275db0e075278f77a95ca5b8b941c7f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/11601 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11601 for details. -gerrit

1 0

Patch merged into coreboot/master: AMD bettong: Fix the interrupt routing.
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit eb90aaf29e5c09612f964f0946a4ced53d88a913 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 19:33:53 2015 +0800 AMD bettong: Fix the interrupt routing. The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. Change-Id: I893e73f2aab3227381e44406fa285613e4ba2904 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/11374 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11374 for details. -gerrit

1 0

New patch to review for coreboot: commonlib: Remove unused static function.
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12339 -gerrit commit 1a9cee8b167191374258077a2af1911bd4572d44 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 14:28:56 2015 +0800 commonlib: Remove unused static function. Building with Clang without option -Wno-unused-function causes building error. I don't know why GCC doesn't have that issue. ------------ coreboot/src/commonlib/fsp1_1_relocate.c:47:23: error: unused function 'le8toh' [-Werror,-Wunused-function] static inline uint8_t le8toh(uint8_t byte) ^ 1 error generated. ------------ Change-Id: Iecd1e84e4321446412ef68d65dc918baf1ab45ce Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/commonlib/fsp1_1_relocate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/commonlib/fsp1_1_relocate.c b/src/commonlib/fsp1_1_relocate.c index c6143eb..7165d86 100644 --- a/src/commonlib/fsp1_1_relocate.c +++ b/src/commonlib/fsp1_1_relocate.c @@ -43,12 +43,6 @@ static int guid_compare(const EFI_GUID *le_guid, const EFI_GUID *native_guid) ARRAY_SIZE(le_guid->Data4)); } -/* Provide this for symmetry when accessing UEFI fields. */ -static inline uint8_t le8toh(uint8_t byte) -{ - return byte; -} - static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID; static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID;

1 0

Patch set updated for coreboot: asus/kgpe-d16: fix DIMMSetVoltages
by Felix Held 06 Nov '15

06 Nov '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12297 -gerrit commit 07accb4ca2c0f374ea01be4418aeb0e36a4cce02 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Tue Nov 3 00:59:49 2015 +0100 asus/kgpe-d16: fix DIMMSetVoltages The RAM voltages can be set per socket, which contains two nodes. Only reset the allowed voltages per socket before processing a new socket and not after every node. Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/mainboard/asus/kgpe-d16/romstage.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 76cbb8e..4e82a11 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -172,7 +172,7 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, uint8_t node; uint8_t socket; uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ - uint8_t node_allowed_voltages; + uint8_t socket_allowed_voltages = allowed_voltages; uint32_t set_voltage = 0; if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { @@ -192,26 +192,31 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, for (node = 0; node < MAX_NODES_SUPPORTED; node++) { socket = node / 2; - node_allowed_voltages = allowed_voltages; struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + node; + + /* reset socket_allowed_voltages before processing each socket */ + if (!(node % 2)) + socket_allowed_voltages = allowed_voltages; + if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { if (pDCTstat->DIMMValid & (1 << dimm)) { - node_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; + socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; } } } + /* set voltage per socket after processing last contained node */ if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ - if (node_allowed_voltages & 0x8) { + if (socket_allowed_voltages & 0x8) { set_voltage = 1150; set_ddr3_voltage(socket, 3); - } else if (node_allowed_voltages & 0x4) { + } else if (socket_allowed_voltages & 0x4) { set_voltage = 1250; set_ddr3_voltage(socket, 2); - } else if (node_allowed_voltages & 0x2) { + } else if (socket_allowed_voltages & 0x2) { set_voltage = 1350; set_ddr3_voltage(socket, 1); } else {

1 0

Patch set updated for coreboot: cpu/x86/lapic: Add stack overrun detection
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11963 -gerrit commit b964374371875c56ea0fd8c9bc401ed016f7b593 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Sep 5 19:31:20 2015 -0500 cpu/x86/lapic: Add stack overrun detection Change-Id: I03e43f38e0d2e51141208ebb169ad8deba77ab78 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e5404e5..ef150a5 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -5,6 +5,7 @@ * Copyright (C) 2001 Ronald G. Minnich * Copyright (C) 2005 Yinghai Lu * Copyright (C) 2008 coresystems GmbH + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -490,6 +491,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } } printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); + checkstack(_estack, 0); for(i = 1; i <= last_cpu_index; i++) checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i); }

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add initial Family 15h CPU support
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11967 -gerrit commit ab41d883d29c54f38e3de534b6f8a6b87955a73c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Sep 5 19:37:57 2015 -0500 mainboard/asus/kgpe-d16: Add initial Family 15h CPU support Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 3 +- src/mainboard/asus/kgpe-d16/cmos.layout | 15 +- src/mainboard/asus/kgpe-d16/devicetree.cb | 4 + src/mainboard/asus/kgpe-d16/resourcemap.c | 276 +++++++++++++++++++++++++++++- src/mainboard/asus/kgpe-d16/romstage.c | 36 ++-- 5 files changed, 309 insertions(+), 25 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index d84c402..e3b3c7b 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -2,13 +2,14 @@ baud_rate = 115200 debug_level = Spew multi_core = Enable slow_cpu = off +compute_unit_siblings = Enable iommu = Disable nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 minimum_memory_voltage = 1.5V ECC_memory = Enable -ECC_redirection = Disable +ECC_redirection = Enable ecc_scrub_rate = 1.28us interleave_chip_selects = Enable interleave_nodes = Disable diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index fbda5e0..264c893 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -26,8 +26,8 @@ entries 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core +404 4 e 8 max_mem_clock +408 1 e 2 multi_core 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi @@ -37,6 +37,7 @@ entries 457 1 e 1 ECC_redirection 458 4 e 11 hypertransport_speed_limit 462 2 e 12 minimum_memory_voltage +464 1 e 2 compute_unit_siblings 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum @@ -74,10 +75,12 @@ enumerations 6 6 Information 6 7 Debug 6 8 Spew -8 0 DDR3-1600 -8 1 DDR3-1333 -8 2 DDR3-1066 -8 3 DDR3-800 +8 0 DDR3-1866 +8 1 DDR3-1600 +8 2 DDR3-1333 +8 3 DDR3-1066 +8 4 DDR3-800 +8 5 DDR3-667 9 0 off 9 1 87.5% 9 2 75.0% diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index e47e256..abe6d16 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -220,21 +220,25 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end + device pci 18.5 on end device pci 19.0 on end # Socket 0 node 1 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end device pci 19.4 on end + device pci 19.5 on end device pci 1a.0 on end # Socket 1 node 0 device pci 1a.1 on end device pci 1a.2 on end device pci 1a.3 on end device pci 1a.4 on end + device pci 1a.5 on end device pci 1b.0 on end # Socket 1 node 1 device pci 1b.1 on end device pci 1b.2 on end device pci 1b.3 on end device pci 1b.4 on end + device pci 1b.5 on end end end end diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c index 6d2c107..8bcb28b 100644 --- a/src/mainboard/asus/kgpe-d16/resourcemap.c +++ b/src/mainboard/asus/kgpe-d16/resourcemap.c @@ -19,7 +19,262 @@ static void setup_mb_resource_map(void) { - static const unsigned int register_values[] = { + static const unsigned int fam15h_register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [31:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Link 3 + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Link 3 + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independent of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Link 3 + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + static const unsigned int fam10h_register_values[] = { /* Careful set limit registers before base registers which contain the enables */ /* DRAM Limit i Registers * F1:0x44 i = 0 @@ -275,6 +530,21 @@ static void setup_mb_resource_map(void) }; int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + if (fam15h) { + max = ARRAY_SIZE(fam15h_register_values); + setup_resource_map(fam15h_register_values, max); + } else { + max = ARRAY_SIZE(fam10h_register_values); + setup_resource_map(fam10h_register_values, max); + } } diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 76cbb8e..a718c14 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -38,6 +38,7 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> #include <cpu/x86/bist.h> +#include <smp/spinlock.h> // #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> @@ -206,20 +207,20 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ if (node_allowed_voltages & 0x8) { - set_voltage = 1150; + set_voltage = 0x8; set_ddr3_voltage(socket, 3); } else if (node_allowed_voltages & 0x4) { - set_voltage = 1250; + set_voltage = 0x4; set_ddr3_voltage(socket, 2); } else if (node_allowed_voltages & 0x2) { - set_voltage = 1350; + set_voltage = 0x2; set_ddr3_voltage(socket, 1); } else { - set_voltage = 1500; + set_voltage = 0x1; set_ddr3_voltage(socket, 0); } - /* Save final DIMM voltages for SMBIOS use */ + /* Save final DIMM voltages for MCT and SMBIOS use */ if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; @@ -233,6 +234,9 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } } } + + /* Allow the DDR supply voltages to settle */ + udelay(100000); } static void set_peripheral_control_lines(void) { @@ -372,7 +376,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); post_code(0x36); - /* wait for all the APs core0 started by finalize_node_setup. */ + /* Wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. * It would be nice to fix up prink spinlocks for ROM XIP mode. * I think it could be done by putting the spinlock flag in the cache @@ -384,6 +388,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr5650_early_setup(); sb7xx_51xx_early_setup(); + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } + if (IS_ENABLED(CONFIG_SET_FIDVID)) { msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -393,11 +405,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); + #if IS_ENABLED(CONFIG_SET_FIDVID) if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } + #endif post_code(0x3A); @@ -406,21 +420,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - } - post_code(0x38); init_timer(); // Need to use TMICT to synconize FID/VID sr5650_htinit(); - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + /* Reset for HT, FIDVID, PLL and errata changes to take effect. */ if (!warm_reset_detect(0)) { printk(BIOS_INFO, "...WARM RESET...\n\n\n"); soft_reset();

1 0

Patch set updated for coreboot: amd/amdmct/mct_ddr3: Use training values from previous boot if possible
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11976 -gerrit commit 2acfb19daf216fa934b51f6e677facd250ab424f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 4 00:11:03 2015 -0500 amd/amdmct/mct_ddr3: Use training values from previous boot if possible DRAM training accounts for most of the romstage startup time, yet if the hardware configuration has not changed from the previous boot the previously discovered training values are still valid. Use them if the DIMM configuration has not changed since the last boot. Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.layout | 1 + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 206 +++++++++++++++++--------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 175 +++++++++++++++++++--- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 10 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 + 6 files changed, 308 insertions(+), 94 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 264c893..b64a85b 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -38,6 +38,7 @@ entries 458 4 e 11 hypertransport_speed_limit 462 2 e 12 minimum_memory_voltage 464 1 e 2 compute_unit_siblings +465 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index dd01be0..ccca91d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -35,7 +35,8 @@ static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); + struct DCTStatStruc *pDCTstatA, + uint8_t allow_config_restore); static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, @@ -361,8 +362,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs else if (drive_strength == 0x3) calibration_code = 0xfff; } - } - else if (ddr_voltage_index & 0x2) { + } else if (ddr_voltage_index & 0x2) { /* 1.35V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 42 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -396,8 +396,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs else if (drive_strength == 0x3) calibration_code = 0xdb6; } - } - else if (ddr_voltage_index & 0x1) { + } else if (ddr_voltage_index & 0x1) { /* 1.5V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 41 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -432,8 +431,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs calibration_code = 0xb6d; } } - } - else if (package_type == PT_C3) { + } else if (package_type == PT_C3) { /* Socket C32 */ if (ddr_voltage_index & 0x4) { /* 1.25V */ @@ -479,8 +477,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs else if (drive_strength == 0x3) calibration_code = 0xfff; } - } - else if (ddr_voltage_index & 0x2) { + } else if (ddr_voltage_index & 0x2) { /* 1.35V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 45 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -524,8 +521,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs else if (drive_strength == 0x3) calibration_code = 0xdb6; } - } - else if (ddr_voltage_index & 0x1) { + } else if (ddr_voltage_index & 0x1) { /* 1.5V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 44 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -625,8 +621,7 @@ static uint32_t fam15h_phy_predriver_cmd_addr_calibration_code(struct DCTStatStr else if (drive_strength == 0x3) calibration_code = 0xb64; } - } - else if (ddr_voltage_index & 0x2) { + } else if (ddr_voltage_index & 0x2) { /* 1.35V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 51 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -660,8 +655,7 @@ static uint32_t fam15h_phy_predriver_cmd_addr_calibration_code(struct DCTStatStr else if (drive_strength == 0x3) calibration_code = 0x924; } - } - else if (ddr_voltage_index & 0x1) { + } else if (ddr_voltage_index & 0x1) { /* 1.5V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 50 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -742,8 +736,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p else if (drive_strength == 0x3) calibration_code = 0xff6; } - } - else if (ddr_voltage_index & 0x2) { + } else if (ddr_voltage_index & 0x2) { /* 1.35V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 54 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -777,8 +770,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p else if (drive_strength == 0x3) calibration_code = 0xdad; } - } - else if (ddr_voltage_index & 0x1) { + } else if (ddr_voltage_index & 0x1) { /* 1.5V */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 53 */ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { @@ -847,16 +839,13 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT else if (MemClkFreq == 0x6) { /* DDR3-800 */ calibration_code = 0x10112222; - } - else if (MemClkFreq == 0xa) { + } else if (MemClkFreq == 0xa) { /* DDR3-1066 */ calibration_code = 0x20112222; - } - else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { + } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { /* DDR3-1333 - DDR3-1600 */ calibration_code = 0x30112222; - } - else if (MemClkFreq == 0x16) { + } else if (MemClkFreq == 0x16) { /* DDR3-1866 */ calibration_code = 0x30332222; } @@ -866,16 +855,13 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT if (MemClkFreq == 0x4) { /* DDR3-667 */ calibration_code = 0x00112222; - } - else if (MemClkFreq == 0x6) { + } else if (MemClkFreq == 0x6) { /* DDR3-800 */ calibration_code = 0x10112222; - } - else if (MemClkFreq == 0xa) { + } else if (MemClkFreq == 0xa) { /* DDR3-1066 */ calibration_code = 0x20112222; - } - else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { + } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { /* DDR3-1333 - DDR3-1600 */ calibration_code = 0x30112222; } @@ -887,20 +873,16 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT if (MemClkFreq == 0x4) { /* DDR3-667 */ calibration_code = 0x10222222; - } - else if (MemClkFreq == 0x6) { + } else if (MemClkFreq == 0x6) { /* DDR3-800 */ calibration_code = 0x20222222; - } - else if (MemClkFreq == 0xa) { + } else if (MemClkFreq == 0xa) { /* DDR3-1066 */ calibration_code = 0x30222222; - } - else if (MemClkFreq == 0xe) { + } else if (MemClkFreq == 0xe) { /* DDR3-1333 */ calibration_code = 0x30222222; - } - else if (MemClkFreq == 0x12) { + } else if (MemClkFreq == 0x12) { /* DDR3-1600 */ if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) calibration_code = 0x30222222; @@ -1087,8 +1069,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { /* DDR3-667 - DDR3-1333 */ slow_access = 0; - } - else if (MemClkFreq == 0x12) { + } else if (MemClkFreq == 0x12) { /* DDR3-1600 */ if (rank_count_dimm0 == 1) slow_access = 0; @@ -1104,8 +1085,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc || (MemClkFreq == 0xa)) { /* DDR3-667 - DDR3-1066 */ slow_access = 0; - } - else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { + } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { /* DDR3-1333 - DDR3-1600 */ slow_access = 1; } @@ -1190,6 +1170,30 @@ static void read_spd_bytes(struct MCTStatStruc *pMCTstat, } } +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +static void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat) +{ + uint8_t dimm; + + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + calculate_spd_hash(pDCTstat->spd_data.spd_bytes[dimm], &pDCTstat->spd_data.spd_hash[dimm]); + } +} + +static void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat) +{ + uint8_t dimm; + + pDCTstat->spd_data.nvram_spd_match = 1; + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + if (pDCTstat->spd_data.spd_hash[dimm] != pDCTstat->spd_data.nvram_spd_hash[dimm]) + pDCTstat->spd_data.nvram_spd_match = 0; + } +} +#endif + static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { @@ -1238,6 +1242,8 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, */ u8 Node, NodesWmem; u32 node_sys_base; + uint8_t nvram; + uint8_t allow_config_restore; uint8_t s3resume = acpi_is_wakeup_s3(); @@ -1254,7 +1260,7 @@ restartinit: #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); - restore_mct_information_from_nvram(); + restore_mct_information_from_nvram(0); #endif printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); @@ -1304,11 +1310,26 @@ restartinit: node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F; } + /* If the boot fails make sure training is attempted after reset */ + nvram = 0; + set_option("allow_spd_nvram_cache_restore", &nvram); + #if IS_ENABLED(DIMM_VOLTAGE_SET_SUPPORT) printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__); DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ #endif + /* If DIMM configuration has not changed since last boot restore training values */ + allow_config_restore = 1; + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (pDCTstat->NodePresent) + if (!pDCTstat->spd_data.nvram_spd_match) + allow_config_restore = 0; + } + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -1342,14 +1363,33 @@ restartinit: CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ mctHookAfterCPU(); /* Setup external northbridge(s) */ + /* FIXME + * Previous training values should only be used if the current desired + * speed is the same as the speed used in the previous boot. + * How to get the desired speed at this point in the code? + */ +#if 0 + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (pDCTstat->NodePresent) { + if (pDCTstat->spd_data.nvram_memclk[0] != pDCTstat->DIMMAutoSpeed) + allow_config_restore = 0; + } + } +#endif + printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); - DQSTiming_D(pMCTstat, pDCTstatA); /* Get Receiver Enable and DQS signal timing*/ + DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n"); - mct_OtherTiming(pMCTstat, pDCTstatA); + if (!allow_config_restore) { + printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n"); + mct_OtherTiming(pMCTstat, pDCTstatA); + } if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/ goto restartinit; @@ -1831,7 +1871,7 @@ static void exit_training_mode_fam15(struct MCTStatStruc *pMCTstat, } static void DQSTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) + struct DCTStatStruc *pDCTstatA, uint8_t allow_config_restore) { u8 nv_DQSTrainCTL; @@ -1839,9 +1879,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, return; } - nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL); - /* FIXME: BOZO- DQS training every time*/ - nv_DQSTrainCTL = 1; + // nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL); + nv_DQSTrainCTL = !allow_config_restore; mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA); phyAssistedMemFnceTraining(pMCTstat, pDCTstatA); @@ -1860,15 +1899,16 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, } } + mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); + if (!is_fam15h()) { + /* TODO: should be in mctHookBeforeAnyTraining */ + _WRMSR(0x26C, 0x04040404, 0x04040404); + _WRMSR(0x26D, 0x04040404, 0x04040404); + _WRMSR(0x26E, 0x04040404, 0x04040404); + _WRMSR(0x26F, 0x04040404, 0x04040404); + } + if (nv_DQSTrainCTL) { - mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); - if (!is_fam15h()) { - /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); - } mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); if (is_fam15h()) { @@ -1898,18 +1938,25 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, exit_training_mode_fam15(pMCTstat, pDCTstatA); else mctSetEccDQSRcvrEn_D(pMCTstat, pDCTstatA); + } else { + mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); - /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ - mctHookAfterAnyTraining(); - mctSaveDQSSigTmg_D(); + mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); - MCTMemClr_D(pMCTstat, pDCTstatA); - } else { - mctGetDQSSigTmg_D(); /* get values into data structure */ - LoadDQSSigTmgRegs_D(pMCTstat, pDCTstatA); /* load values into registers.*/ - /* mctDoWarmResetMemClr_D(); */ - MCTMemClr_D(pMCTstat, pDCTstatA); +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n"); + restore_mct_information_from_nvram(1); +#endif + + if (is_fam15h()) + exit_training_mode_fam15(pMCTstat, pDCTstatA); } + + /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ + mctHookAfterAnyTraining(); + + /* mctDoWarmResetMemClr_D(); */ + MCTMemClr_D(pMCTstat, pDCTstatA); } static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, @@ -3919,6 +3966,8 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 err_code; + uint8_t nvram; + uint8_t allow_config_restore; /* Preconfigure DCT0 */ DCTPreInit_D(pMCTstat, pDCTstat, 0); @@ -3933,6 +3982,27 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, pDCTstat->ErrCode = err_code; /* Using DCT0 Error code to update pDCTstat.ErrCode */ } } + +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + calculate_and_store_spd_hashes(pMCTstat, pDCTstat); + + if (load_spd_hashes_from_nvram(pDCTstat) < 0) { + pDCTstat->spd_data.nvram_spd_match = 0; + } + else { + compare_nvram_spd_hashes(pMCTstat, pDCTstat); + } +#else + pDCTstat->spd_data.nvram_spd_match = 0; +#endif + + /* Check to see if restoration of SPD data from NVRAM is allowed */ + allow_config_restore = 0; + if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) + allow_config_restore = !!nvram; + + if (!allow_config_restore) + pDCTstat->spd_data.nvram_spd_match = 0; } static void mct_initDCT(struct MCTStatStruc *pMCTstat, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index e6b427e..1ac7bbf 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -321,6 +321,10 @@ struct MCTStatStruc { struct amd_spd_node_data { uint8_t spd_bytes[MAX_DIMMS_SUPPORTED][256]; /* [DIMM][byte] */ uint8_t spd_address[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ + uint64_t spd_hash[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ + uint64_t nvram_spd_hash[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ + uint8_t nvram_spd_match; + uint8_t nvram_memclk[2]; /* [channel] */ } __attribute__((packed)); struct DCTStatStruc { /* A per Node structure*/ @@ -780,6 +784,8 @@ struct amd_s3_persistent_mct_channel_data { struct amd_s3_persistent_node_data { uint32_t node_present; + uint64_t spd_hash[MAX_DIMMS_SUPPORTED]; + uint8_t memclk[2]; struct amd_s3_persistent_mct_channel_data channel[2]; } __attribute__((packed)); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 3c2043b..c441044 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -22,8 +22,10 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cbfs.h> +#include <cbmem.h> #include <spi-generic.h> #include <spi_flash.h> +#include <pc80/mc146818rtc.h> #include "s3utils.h" @@ -120,6 +122,68 @@ static uint32_t read_amd_dct_index_register_dct(device_t dev, uint8_t node, uint return read_amd_dct_index_register(dev, index_ctl_reg, index); } +/* Non-cryptographic 64-bit hash function taken from Stack Overflow: + * http://stackoverflow.com/a/13326345 + * Any 64-bit hash with sufficiently low collision potential + * could be used instead. + */ +void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash) +{ + const unsigned long long prime = 2654435789ULL; + uint16_t byte; + *spd_hash = 104395301; + + for (byte = 0; byte < 256; byte++) + *spd_hash += (spd_data[byte] * prime) ^ (*spd_hash >> 23); + + *spd_hash = *spd_hash ^ (*spd_hash << 37); +} + +static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) +{ + ssize_t s3nv_offset; + ssize_t s3nv_file_offset; + void * s3nv_cbfs_file_ptr; + struct amd_s3_persistent_data *persistent_data; + + /* Obtain CBFS file offset */ + s3nv_offset = get_s3nv_file_offset(); + if (s3nv_offset == -1) + return NULL; + + /* Align flash pointer to nearest boundary */ + s3nv_file_offset = s3nv_offset; + s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1); + s3nv_offset += CONFIG_S3_DATA_SIZE; + s3nv_file_offset = s3nv_offset - s3nv_file_offset; + + /* Map data structure in CBFS and restore settings */ + s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL); + if (!s3nv_cbfs_file_ptr) { + printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME); + return NULL; + } + persistent_data = (s3nv_cbfs_file_ptr + s3nv_file_offset); + + return persistent_data; +} + +#ifdef __PRE_RAM__ +int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) +{ + struct amd_s3_persistent_data *persistent_data; + + persistent_data = map_s3nv_in_nvram(); + if (!persistent_data) + return -1; + + memcpy(pDCTstat->spd_data.nvram_spd_hash, persistent_data->node[pDCTstat->Node_ID].spd_hash, sizeof(pDCTstat->spd_data.nvram_spd_hash)); + memcpy(pDCTstat->spd_data.nvram_memclk, persistent_data->node[pDCTstat->Node_ID].memclk, sizeof(pDCTstat->spd_data.nvram_memclk)); + + return 0; +} +#endif + #ifdef __RAMSTAGE__ static uint64_t rdmsr_uint64_t(unsigned long index) { msr_t msr = rdmsr(index); @@ -145,6 +209,31 @@ static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t d return pci_read_config32(dev, reg); } +static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) +{ + uint8_t node; + uint8_t dimm; + uint8_t channel; + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info == NULL) { + /* can't find amdmct information in cbmem */ + for (node = 0; node < MAX_NODES_SUPPORTED; node++) + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) + persistent_data->node[node].spd_hash[dimm] = 0xffffffffffffffffULL; + + return; + } + + for (node = 0; node < MAX_NODES_SUPPORTED; node++) + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) + calculate_spd_hash(mem_info->dct_stat[node].spd_data.spd_bytes[dimm], &persistent_data->node[node].spd_hash[dimm]); + + for (node = 0; node < MAX_NODES_SUPPORTED; node++) + for (channel = 0; channel < 2; channel++) + persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; +} + void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) { uint8_t i; @@ -437,7 +526,7 @@ static void wrmsr_uint64_t(unsigned long index, uint64_t value) { wrmsr(index, msr); } -void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data) +void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only) { uint8_t i; uint8_t j; @@ -447,6 +536,51 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste uint8_t dct_enabled; uint32_t dword; + if (training_only) { + /* Only restore the Receiver Enable and DQS training registers */ + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { + for (channel = 0; channel < 2; channel++) { + struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel]; + if (!persistent_data->node[node].node_present) + continue; + + /* Restore training parameters */ + for (i=0; i<4; i++) + for (j=0; j<3; j++) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); + for (i=0; i<4; i++) + for (j=0; j<3; j++) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); + + for (i=0; i<12; i++) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); + for (i=0; i<12; i++) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); + + if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + for (i=0; i<12; i++) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); + for (i=0; i<12; i++) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); + } + + /* Restore MaxRdLatency */ + if (is_fam15h()) { + for (i=0; i<4; i++) + write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); + } + else { + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78); + } + + /* Other timing control registers */ + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x8c, data->f2x8c); + } + } + + return; + } + /* Load data from data structure into DCTs */ /* Stage 1 */ for (node = 0; node < MAX_NODES_SUPPORTED; node++) { @@ -497,7 +631,8 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste wrmsr_uint64_t(0x00000250, data->msr00000250); wrmsr_uint64_t(0x00000258, data->msr00000258); /* FIXME - * Restoring these MSRs causes a hang on resume + * Restoring these MSRs causes a hang on resume due to + * destroying CAR while still executing from CAR! * For now, skip restoration... */ // for (i=0; i<8; i++) @@ -886,6 +1021,8 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste #ifdef __RAMSTAGE__ int8_t save_mct_information_to_nvram(void) { + uint8_t nvram; + if (acpi_is_wakeup_s3()) return 0; @@ -905,6 +1042,9 @@ int8_t save_mct_information_to_nvram(void) /* Obtain MCT configuration data */ copy_mct_data_to_save_variable(persistent_data); + /* Save RAM SPD data at the same time */ + copy_cbmem_spd_data_to_save_variable(persistent_data); + /* Obtain CBFS file offset */ s3nv_offset = get_s3nv_file_offset(); if (s3nv_offset == -1) @@ -945,36 +1085,23 @@ int8_t save_mct_information_to_nvram(void) /* Restore SPI MMIO address */ pci_write_config32(lpc_dev, 0xa0, spi_mmio_prev); + /* Allow training bypass if DIMM configuration is unchanged on next boot */ + nvram = 1; + set_option("allow_spd_nvram_cache_restore", &nvram); + return 0; } #endif -int8_t restore_mct_information_from_nvram(void) +int8_t restore_mct_information_from_nvram(uint8_t training_only) { - ssize_t s3nv_offset; - ssize_t s3nv_file_offset; - void * s3nv_cbfs_file_ptr; struct amd_s3_persistent_data *persistent_data; - /* Obtain CBFS file offset */ - s3nv_offset = get_s3nv_file_offset(); - if (s3nv_offset == -1) + persistent_data = map_s3nv_in_nvram(); + if (!persistent_data) return -1; - /* Align flash pointer to nearest boundary */ - s3nv_file_offset = s3nv_offset; - s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1); - s3nv_offset += CONFIG_S3_DATA_SIZE; - s3nv_file_offset = s3nv_offset - s3nv_file_offset; - - /* Map data structure in CBFS and restore settings */ - s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL); - if (!s3nv_cbfs_file_ptr) { - printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME); - return -1; - } - persistent_data = (s3nv_cbfs_file_ptr + s3nv_file_offset); - restore_mct_data_from_save_variable(persistent_data); + restore_mct_data_from_save_variable(persistent_data, training_only); return 0; -} \ No newline at end of file +} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 5370496..07502ba 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -16,9 +16,15 @@ #include "../wrappers/mcti.h" #include "mct_d.h" +void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); + +#ifdef __PRE_RAM__ +int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat); +#endif + #ifdef __RAMSTAGE__ int8_t save_mct_information_to_nvram(void); #endif -int8_t restore_mct_information_from_nvram(void); +int8_t restore_mct_information_from_nvram(uint8_t training_only); void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data); -void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data); \ No newline at end of file +void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only); \ No newline at end of file diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 48ab800..a030f71 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -396,14 +396,18 @@ static void mctHookAfterCPU(void) } +#if IS_ENABLED(CONFIG_DIMM_DDR2) static void mctSaveDQSSigTmg_D(void) { } +#endif +#if IS_ENABLED(CONFIG_DIMM_DDR2) static void mctGetDQSSigTmg_D(void) { } +#endif static void mctHookBeforeECC(void)

1 0

Patch set updated for coreboot: cpu/amd/car: Move AP stacks below the BSP stack to free up space
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11972 -gerrit commit 5dee21ad57c8700fd4f406c1080b16c5189a049b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 20:18:44 2015 -0500 cpu/amd/car: Move AP stacks below the BSP stack to free up space Caching SPD data during startup requires additional CAR space. There was a large chunk of free space between the AP stack top and the BSP stack bottom; moving the AP stacks below the BSP stack allows this space to be utilized. Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 7c47e27..81b1d1e 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -33,7 +33,7 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x2000 + default 0x4000 config DCACHE_BSP_STACK_SLUSH hex

1 0

Patch set updated for coreboot: northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time
by Timothy Pearson 06 Nov '15

06 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11973 -gerrit commit 6f1107053727c3bfafb48226f03dd3d033e9178f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 20:51:59 2015 -0500 northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time Change-Id: Ic16a927a3f1fc6f7cb1aea36a8abe8cc1999cb52 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 161 +++++++++++++++------------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 7 ++ 2 files changed, 92 insertions(+), 76 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f4bf402..4371a37 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -176,7 +176,7 @@ static void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat, static u8 Get_Latency_Diff(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void SyncSetting(struct DCTStatStruc *pDCTstat); -static u8 crcCheck(u8 smbaddr); +static uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm); static void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); static void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); @@ -1176,6 +1176,20 @@ static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCT precise_ndelay_fam15(pMCTstat, delay_ns); } +static void read_spd_bytes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dimm) +{ + uint16_t addr; + uint16_t byte; + + addr = Get_DIMMAddress_D(pDCTstat, dimm); + pDCTstat->spd_data.spd_address[dimm] = addr; + + for (byte = 0; byte < 256; byte++) { + pDCTstat->spd_data.spd_bytes[dimm][byte] = mctRead_SPD(addr, byte); + } +} + static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { @@ -1281,7 +1295,7 @@ restartinit: mct_InitialMCT_D(pMCTstat, pDCTstat); printk(BIOS_DEBUG, "%s: mctSMBhub_Init\n", __func__); - mctSMBhub_Init(Node); /* Switch SMBUS crossbar to proper node*/ + mctSMBhub_Init(Node); /* Switch SMBUS crossbar to proper node */ printk(BIOS_DEBUG, "%s: mct_preInitDCT\n", __func__); mct_preInitDCT(pMCTstat, pDCTstat); @@ -2441,7 +2455,6 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, u32 dword; u32 dev; u32 val; - u16 smbaddr; printk(BIOS_DEBUG, "%s: Start\n", __func__); @@ -2461,64 +2474,62 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, (dct + i)); - - val = mctRead_SPD(smbaddr, SPD_MTBDivisor); /* MTB=Dividend/Divisor */ - MTB16x = ((mctRead_SPD(smbaddr, SPD_MTBDividend) & 0xFF)<<4); + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB=Dividend/Divisor */ + MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xff) << 4); MTB16x /= val; /* transfer to MTB*16 */ - byte = mctRead_SPD(smbaddr, SPD_tRPmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRPmin]; val = byte * MTB16x; if (Trp < val) Trp = val; - byte = mctRead_SPD(smbaddr, SPD_tRRDmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRRDmin]; val = byte * MTB16x; if (Trrd < val) Trrd = val; - byte = mctRead_SPD(smbaddr, SPD_tRCDmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCDmin]; val = byte * MTB16x; if (Trcd < val) Trcd = val; - byte = mctRead_SPD(smbaddr, SPD_tRTPmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRTPmin]; val = byte * MTB16x; if (Trtp < val) Trtp = val; - byte = mctRead_SPD(smbaddr, SPD_tWRmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tWRmin]; val = byte * MTB16x; if (Twr < val) Twr = val; - byte = mctRead_SPD(smbaddr, SPD_tWTRmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tWTRmin]; val = byte * MTB16x; if (Twtr < val) Twtr = val; - val = mctRead_SPD(smbaddr, SPD_Upper_tRAS_tRC) & 0xFF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xFF; val >>= 4; val <<= 8; - val |= mctRead_SPD(smbaddr, SPD_tRCmin) & 0xFF; + val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCmin] & 0xFF; val *= MTB16x; if (Trc < val) Trc = val; - byte = mctRead_SPD(smbaddr, SPD_Density) & 0xF; + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Density] & 0xF; if (Trfc[LDIMM] < byte) Trfc[LDIMM] = byte; - val = mctRead_SPD(smbaddr, SPD_Upper_tRAS_tRC) & 0xF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xF; val <<= 8; - val |= (mctRead_SPD(smbaddr, SPD_tRASmin) & 0xFF); + val |= (pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRASmin] & 0xFF); val *= MTB16x; if (Tras < val) Tras = val; - val = mctRead_SPD(smbaddr, SPD_Upper_tFAW) & 0xF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tFAW] & 0xF; val <<= 8; - val |= mctRead_SPD(smbaddr, SPD_tFAWmin) & 0xFF; + val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tFAWmin] & 0xFF; val *= MTB16x; if (Tfaw < val) Tfaw = val; @@ -2934,7 +2945,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, u8 CLactual, CLdesired, CLT_Fail; uint16_t min_frequency_tck16x; - u8 smbaddr, byte = 0, bytex = 0; + u8 byte = 0, bytex = 0; CASLatLow = 0xFF; CASLatHigh = 0xFF; @@ -2955,28 +2966,27 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { if (pDCTstat->DIMMValid & (1 << i)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, (dct + i)); /* Step 1: Determine the common set of supported CAS Latency * values for all modules on the memory channel using the CAS * Latencies Supported in SPD bytes 14 and 15. */ - byte = mctRead_SPD(smbaddr, SPD_CASLow); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_CASLow]; CASLatLow &= byte; - byte = mctRead_SPD(smbaddr, SPD_CASHigh); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_CASHigh]; CASLatHigh &= byte; /* Step 2: Determine tAAmin(all) which is the largest tAAmin value for all modules on the memory channel (SPD byte 16). */ - byte = mctRead_SPD(smbaddr, SPD_MTBDivisor); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; - MTB16x = ((mctRead_SPD(smbaddr, SPD_MTBDividend) & 0xFF)<<4); + MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xFF)<<4); MTB16x /= byte; /* transfer to MTB*16 */ - byte = mctRead_SPD(smbaddr, SPD_tAAmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tAAmin]; if (tAAmin16x < byte * MTB16x) tAAmin16x = byte * MTB16x; /* Step 3: Determine tCKmin(all) which is the largest tCKmin value for all modules on the memory channel (SPD byte 12). */ - byte = mctRead_SPD(smbaddr, SPD_tCKmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tCKmin]; if (tCKmin16x < byte * MTB16x) tCKmin16x = byte * MTB16x; @@ -3347,7 +3357,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, u8 byte; u16 word; u32 dword; - u16 smbaddr; dev = pDCTstat->dev_dct; @@ -3358,16 +3367,14 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, byte -= 3; if (pDCTstat->DIMMValid & (1<<byte)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, (ChipSel + dct)); - - byte = mctRead_SPD(smbaddr, SPD_Addressing); + byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing]; Rows = (byte >> 3) & 0x7; /* Rows:0b=12-bit,... */ Cols = byte & 0x7; /* Cols:0b=9-bit,... */ - byte = mctRead_SPD(smbaddr, SPD_Density); + byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Density]; Banks = (byte >> 4) & 7; /* Banks:0b=3-bit,... */ - byte = mctRead_SPD(smbaddr, SPD_Organization); + byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Organization]; Ranks = ((byte >> 3) & 7) + 1; /* Configure Bank encoding @@ -3462,46 +3469,42 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, * and determine the width mode: 64-bit, 64-bit muxed, 128-bit. */ u8 i; - u8 smbaddr, smbaddr1; u8 byte, byte1; /* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { - smbaddr = Get_DIMMAddress_D(pDCTstat, i); - smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1); - - byte = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7; - byte1 = mctRead_SPD(smbaddr1, SPD_Addressing) & 0x7; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = mctRead_SPD(smbaddr, SPD_Density) & 0x0f; - byte1 = mctRead_SPD(smbaddr1, SPD_Density) & 0x0f; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0x0f; + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Density] & 0x0f; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = mctRead_SPD(smbaddr, SPD_Organization) & 0x7; - byte1 = mctRead_SPD(smbaddr1, SPD_Organization) & 0x7; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7; + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] & 0x7; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = (mctRead_SPD(smbaddr, SPD_Organization) >> 3) & 0x7; - byte1 = (mctRead_SPD(smbaddr1, SPD_Organization) >> 3) & 0x7; + byte = (pDCTstat->spd_data.spd_bytes[i][SPD_Organization] >> 3) & 0x7; + byte1 = (pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] >> 3) & 0x7; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = mctRead_SPD(smbaddr, SPD_DMBANKS) & 7; /* #ranks-1 */ - byte1 = mctRead_SPD(smbaddr1, SPD_DMBANKS) & 7; /* #ranks-1 */ + byte = pDCTstat->spd_data.spd_bytes[i][SPD_DMBANKS] & 7; /* #ranks-1 */ + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_DMBANKS] & 7; /* #ranks-1 */ if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; @@ -3682,8 +3685,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, status = mctRead_SPD(smbaddr, SPD_ByteUse); if (status >= 0) { /* SPD access is ok */ pDCTstat->DIMMPresent |= 1 << i; - if (crcCheck(smbaddr)) { /* CRC is OK */ - byte = mctRead_SPD(smbaddr, SPD_TYPE); + read_spd_bytes(pMCTstat, pDCTstat, i); + if (crcCheck(pDCTstat, i)) { /* CRC is OK */ + byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/ pDCTstat->DIMMValid |= 1 << i; @@ -3696,36 +3700,41 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, } else { /*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/ pDCTstat->ErrStatus |= 1<<SB_DIMMChkSum; - byte = mctRead_SPD(smbaddr, SPD_TYPE); + byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) pDCTstat->DIMMValid |= 1 << i; } } + + /* Zero DIMM SPD data cache if DIMM not present / valid */ + if (!(pDCTstat->DIMMValid & (1 << i))) + memset(pDCTstat->spd_data.spd_bytes[i], 0, 256); + /* Get module information for SMBIOS */ if (pDCTstat->DIMMValid & (1 << i)) { pDCTstat->DimmManufacturerID[i] = 0; for (k = 0; k < 8; k++) - pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)pDCTstat->spd_data.spd_bytes[i][SPD_MANID_START + k]) << (k * 8); for (k = 0; k < SPD_PARTN_LENGTH; k++) - pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmPartNumber[i][k] = pDCTstat->spd_data.spd_bytes[i][SPD_PARTN_START + k]; pDCTstat->DimmPartNumber[i][SPD_PARTN_LENGTH] = 0; pDCTstat->DimmRevisionNumber[i] = 0; for (k = 0; k < 2; k++) - pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)pDCTstat->spd_data.spd_bytes[i][SPD_REVNO_START + k]) << (k * 8); pDCTstat->DimmSerialNumber[i] = 0; for (k = 0; k < 4; k++) - pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); - pDCTstat->DimmRows[i] = (mctRead_SPD(smbaddr, SPD_Addressing) & 0x38) >> 3; - pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7; - pDCTstat->DimmRanks[i] = ((mctRead_SPD(smbaddr, SPD_Organization) & 0x38) >> 3) + 1; - pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3); - pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3); + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)pDCTstat->spd_data.spd_bytes[i][SPD_SERIAL_START + k]) << (k * 8); + pDCTstat->DimmRows[i] = (pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x38) >> 3; + pDCTstat->DimmCols[i] = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; + pDCTstat->DimmRanks[i] = ((pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x38) >> 3) + 1; + pDCTstat->DimmBanks[i] = 1ULL << (((pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0x70) >> 4) + 3); + pDCTstat->DimmWidth[i] = 1ULL << ((pDCTstat->spd_data.spd_bytes[i][SPD_BusWidth] & 0x7) + 3); } /* Check supported voltage(s) */ - pDCTstat->DimmSupportedVoltages[i] = mctRead_SPD(smbaddr, SPD_Voltage) & 0x7; + pDCTstat->DimmSupportedVoltages[i] = pDCTstat->spd_data.spd_bytes[i][SPD_Voltage] & 0x7; pDCTstat->DimmSupportedVoltages[i] ^= 0x1; /* Invert LSB to convert from SPD format to internal bitmap format */ /* Check module type */ - byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE) & 0x7; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_DIMMTYPE] & 0x7; if (byte == JED_RDIMM || byte == JED_MiniRDIMM) { RegDIMMPresent |= 1 << i; pDCTstat->DimmRegistered[i] = 1; @@ -3739,13 +3748,13 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DimmLoadReduced[i] = 0; } /* Check ECC capable */ - byte = mctRead_SPD(smbaddr, SPD_BusWidth); + byte = pDCTstat->spd_data.spd_bytes[i][SPD_BusWidth]; if (byte & JED_ECC) { /* DIMM is ECC capable */ pDCTstat->DimmECCPresent |= 1 << i; } /* Check if x4 device */ - devwidth = mctRead_SPD(smbaddr, SPD_Organization) & 0x7; /* 0:x4,1:x8,2:x16 */ + devwidth = pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7; /* 0:x4,1:x8,2:x16 */ if (devwidth == 0) { /* DIMM is made with x4 or x16 drams */ pDCTstat->Dimmx4Present |= 1 << i; @@ -3755,7 +3764,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->Dimmx16Present |= 1 << i; } - byte = (mctRead_SPD(smbaddr, SPD_Organization) >> 3); + byte = (pDCTstat->spd_data.spd_bytes[i][SPD_Organization] >> 3); byte &= 7; if (byte == 3) { /* 4ranks */ /* if any DIMMs are QR, we have to make two passes through DIMMs*/ @@ -3790,7 +3799,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* check address mirror support for unbuffered dimm */ /* check number of registers on a dimm for registered dimm */ - byte = mctRead_SPD(smbaddr, SPD_AddressMirror); + byte = pDCTstat->spd_data.spd_bytes[i][SPD_AddressMirror]; if (RegDIMMPresent & (1 << i)) { if ((byte & 3) > 1) pDCTstat->MirrPresU_NumRegR |= 1 << i; @@ -3799,20 +3808,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->MirrPresU_NumRegR |= 1 << i; } /* Get byte62: Reference Raw Card information. We dont need it now. */ - /* byte = mctRead_SPD(smbaddr, SPD_RefRawCard); */ + /* byte = pDCTstat->spd_data.spd_bytes[i][SPD_RefRawCard]; */ /* Get Byte65/66 for register manufacture ID code */ - if ((0x97 == mctRead_SPD(smbaddr, SPD_RegManufactureID_H)) && - (0x80 == mctRead_SPD(smbaddr, SPD_RegManufactureID_L))) { - if (0x16 == mctRead_SPD(smbaddr, SPD_RegManRevID)) + if ((0x97 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManufactureID_H]) && + (0x80 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManufactureID_L])) { + if (0x16 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManRevID]) pDCTstat->RegMan2Present |= 1 << i; else pDCTstat->RegMan1Present |= 1 << i; } /* Get Control word values for RC3. We dont need it. */ - byte = mctRead_SPD(smbaddr, 70); + byte = pDCTstat->spd_data.spd_bytes[i][70]; pDCTstat->CtrlWrd3 |= (byte >> 4) << (i << 2); /* C3 = SPD byte 70 [7:4] */ /* Get Control word values for RC4, and RC5 */ - byte = mctRead_SPD(smbaddr, 71); + byte = pDCTstat->spd_data.spd_bytes[i][71]; pDCTstat->CtrlWrd4 |= (byte & 0xFF) << (i << 2); /* RC4 = SPD byte 71 [3:0] */ pDCTstat->CtrlWrd5 |= (byte >> 4) << (i << 2); /* RC5 = SPD byte 71 [7:4] */ } @@ -6190,14 +6199,14 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { * 1010 001111 16 3 10 4GB * 1011 010111 16 3 11 8GB */ -u8 crcCheck(u8 smbaddr) +uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm) { u8 byte_use; u8 Index; u16 CRC; u8 byte, i; - byte_use = mctRead_SPD(smbaddr, SPD_ByteUse); + byte_use = pDCTstat->spd_data.spd_bytes[dimm][SPD_ByteUse]; if (byte_use & 0x80) byte_use = 117; else @@ -6205,7 +6214,7 @@ u8 crcCheck(u8 smbaddr) CRC = 0; for (Index = 0; Index < byte_use; Index ++) { - byte = mctRead_SPD(smbaddr, Index); + byte = pDCTstat->spd_data.spd_bytes[dimm][Index]; CRC ^= byte << 8; for (i=0; i<8; i++) { if (CRC & 0x8000) { @@ -6215,5 +6224,5 @@ u8 crcCheck(u8 smbaddr) CRC <<= 1; } } - return CRC == (mctRead_SPD(smbaddr, SPD_byte_127) << 8 | mctRead_SPD(smbaddr, SPD_byte_126)); + return CRC == (pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_127] << 8 | pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_126]); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 3aeb7ec..e6b427e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -318,6 +318,11 @@ struct MCTStatStruc { ===============================================================================*/ #include "mwlc_d.h" /* I have to */ +struct amd_spd_node_data { + uint8_t spd_bytes[MAX_DIMMS_SUPPORTED][256]; /* [DIMM][byte] */ + uint8_t spd_address[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ +} __attribute__((packed)); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -611,6 +616,8 @@ struct DCTStatStruc { /* A per Node structure*/ char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; + + struct amd_spd_node_data spd_data; } __attribute__((packed)); struct amd_s3_persistent_mct_channel_data {

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015