coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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1544 discussions

Patch set updated for coreboot: AMD/bettong: Add UART support (not tested)
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749 -gerrit commit d3fade4603993bac83978bda5226be8630744071 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 18:34:19 2015 +0800 AMD/bettong: Add UART support (not tested) The function delay in uart8250mem.c is not enough for hudson. Need a seprate patch to fix that. Select HUDSON_UART to enable this feature. (This patch set has been changed much. Not quite confident to work on hardware) Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/romstage.c | 27 ++++++++++++ src/southbridge/amd/pi/hudson/Kconfig | 16 +++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 5 +++ src/southbridge/amd/pi/hudson/acpi/uart.asl | 65 +++++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/uart.c | 47 +++++++++++++++++++++ 5 files changed, 160 insertions(+) diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 9f94d7b..213243c 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/stages.h> +#include <arch/io.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -23,6 +24,10 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> +#include <delay.h> + +#define ACPI_MMIO_BASE ((void *)0xFED80000) +#define AOAC_BASE 0x1E00 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -30,6 +35,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif +#if CONFIG_HUDSON_UART + u8 byte; + msr_t msr; +#endif amd_initmmio(); @@ -39,6 +48,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); +#if CONFIG_HUDSON_UART + msr = rdmsr(0x1B); + msr.lo |= 1 << 11; + wrmsr(0x1B, msr); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x62); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte); + write8(ACPI_MMIO_BASE + 0xD00 + 0x89, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8A, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8E, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8F, 0); + + udelay(2000); + write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */ +#endif console_init(); } diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c720791..94a313d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -227,3 +227,19 @@ config AZ_PIN bit 5,4 - pin 2 bit 7,6 - pin 3 endif + +config HUDSON_UART + bool "UART controller on Kern." + default n + depends on SOUTHBRIDGE_AMD_PI_KERN + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + help + There are two UART controllers in Kern. + The UART registers are memory-mapped. UART + controller 0 registers range from FEDC_6000h + to FEDC_6FFFh. UART controller 1 registers + range from FEDC_8000h to FEDC_8FFFh. + + diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..2c2458c 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -50,6 +50,11 @@ romstage-y += imc.c ramstage-y += imc.c endif +ifeq ($(CONFIG_HUDSON_UART), y) +romstage-y += uart.c +ramstage-y += uart.c +endif + smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c diff --git a/src/southbridge/amd/pi/hudson/acpi/uart.asl b/src/southbridge/amd/pi/hudson/acpi/uart.asl new file mode 100644 index 0000000..ae7baa4 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/acpi/uart.asl @@ -0,0 +1,65 @@ + Scope(\_SB.FUR0) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, Zero) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } +/* + Scope(\_SB.FUR1) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, One) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c new file mode 100644 index 0000000..ba35fbf --- /dev/null +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + + +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> + +#define ACPI_MMIO_BASE 0xFED80000 +#define AOAC_BASE 0x1E00 +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); +} + +unsigned int uart_platform_refclk(void) +{ + return 48000000; +} + +#ifdef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + serial.regwidth = 4; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

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Patch set updated for coreboot: AMD Bettong: Add a special case for SPD address of rev F
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12342 -gerrit commit 906447b6af43500bdcfa1baaf7d9bff323d6ad86 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 17:56:53 2015 +0800 AMD Bettong: Add a special case for SPD address of rev F Rev F's SPD address is different from other revision. 0 1 Channel A A0 A2 Channel B A4 AC Change-Id: I620d1f9c295f9a0e30e3821ea36a05dd9f7d3495 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 12 ++++++++++++ src/northbridge/amd/pi/00660F01/dimmSpd.c | 7 +++++++ src/northbridge/amd/pi/dimmSpd.h | 2 ++ 3 files changed, 21 insertions(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 77d29ce..652bb52 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -27,6 +27,7 @@ #include "hudson.h" #include <stdlib.h> #include "BiosCallOuts.h" +#include "northbridge/amd/pi/dimmSpd.h" #include "northbridge/amd/pi/agesawrapper.h" #include <boardid.h> @@ -96,6 +97,17 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) /* NOTE: Only for Bettong. */ #ifdef __PRE_RAM__ +void mainboard_spdaddress_callback(int *spd_address, int socket, int channel, int dimm) +{ + UINT8 spdAddrLookup_rev_F [2][2][4]= { + { {0xA0, 0xA2}, {0xA4, 0xAC}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }; + if (board_id() == 'F') { + *spd_address = spdAddrLookup_rev_F[socket][channel][dimm]; + } +} + TECHNOLOGY_TYPE get_mainboard_dimmtype(void) { if (board_id() == 'F') { diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 5c81f36..afaea0d 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -24,6 +24,11 @@ #include "chip.h" #include "northbridge/amd/pi/dimmSpd.h" +void __attribute__((weak)) mainboard_spdaddress_callback(int *spd_address, int socket, int channel, int dimm) +{ + /* empty */ +} + AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { int spdAddress; @@ -40,6 +45,8 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA return AGESA_ERROR; spdAddress = config->spdAddrLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + + mainboard_spdaddress_callback(&spdAddress, info->SocketId, info->MemChannelId, info->DimmId); if (spdAddress == 0) return AGESA_ERROR; int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); diff --git a/src/northbridge/amd/pi/dimmSpd.h b/src/northbridge/amd/pi/dimmSpd.h index 8e49b7c..aa5ad62 100644 --- a/src/northbridge/amd/pi/dimmSpd.h +++ b/src/northbridge/amd/pi/dimmSpd.h @@ -23,4 +23,6 @@ int hudson_readSpd(int spdAddress, char *buf, size_t len); int smbus_readSpd(int spdAddress, char *buf, size_t len); +void mainboard_spdaddress_callback(int *spd_address, int socket, int channel, int dimm); + #endif

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Patch set updated for coreboot: AMD/Bettong: Memory configuration for DDR3 and DDR4
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11733 -gerrit commit a7735968d1dcd35e3184b88f761938a25215ae3a Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 17:55:01 2015 +0800 AMD/Bettong: Memory configuration for DDR3 and DDR4 1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4. 2. DDR4 uses different memory configuration in AGESA. Pass memory configuration parameters in agesawrapper_amdinitpost. 3. Tested on Rev C and Rev F. Both of them can boot to Windows 8 and have the correct memory size. Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 16 ++++++++++++++++ src/northbridge/amd/pi/agesawrapper.c | 23 +++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.h | 2 ++ 3 files changed, 41 insertions(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index e14978a..77d29ce 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -27,6 +27,8 @@ #include "hudson.h" #include <stdlib.h> #include "BiosCallOuts.h" +#include "northbridge/amd/pi/agesawrapper.h" +#include <boardid.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); @@ -91,3 +93,17 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +/* NOTE: Only for Bettong. */ +#ifdef __PRE_RAM__ +TECHNOLOGY_TYPE get_mainboard_dimmtype(void) +{ + if (board_id() == 'F') { + return DDR4_TECHNOLOGY; + } else { + return DDR3_TECHNOLOGY; + } + + return UNSUPPORTED_TECHNOLOGY; /* not reached here. */ +} +#endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 5772fb4..dd0a6dc 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -22,6 +22,7 @@ #include <heapManager.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> +#include <PlatformMemoryConfiguration.h> VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -42,6 +43,11 @@ static void *AcpiIvrs = NULL; static void *AcpiCrat = NULL; #endif /* #ifndef __PRE_RAM__ */ +TECHNOLOGY_TYPE __attribute__((weak)) get_mainboard_dimmtype(void) +{ + return DDR3_TECHNOLOGY; +} + AGESA_STATUS agesawrapper_amdinitreset(void) { AGESA_STATUS status; @@ -132,6 +138,23 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; +#if CONFIG_NORTHBRIDGE_AMD_PI_00660F01 + PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MOTHER_BOARD_LAYERS (LAYERS_6), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + PSO_END + }; + + if (get_mainboard_dimmtype() == DDR4_TECHNOLOGY) + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; +#endif + // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index cba7dc6..bd9f71f 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -58,4 +58,6 @@ VOID amd_initcpuio(void); VOID amd_initmmio(void); const void *agesawrapper_locate_module (const CHAR8 name[8]); +TECHNOLOGY_TYPE get_mainboard_dimmtype(void); + #endif /* _AGESAWRAPPER_H_ */

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Patch set updated for coreboot: amd/model_fxx: Check FID&VID Support for the BSP (too)
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12336 -gerrit commit 66781acd7a9496ac597d87cadc875da20c2badcd Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 19:24:11 2015 +0200 amd/model_fxx: Check FID&VID Support for the BSP (too) Tested in the direction that now my Sempron 2800+ / K8V-X boots. Fixed coding style in the check in AP code too to make them identical. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/cpu/amd/model_fxx/fidvid.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index a005c46..03415d1 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -356,9 +356,8 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) u32 fid_max; int loop; - if((cpuid_edx(0x80000007)&0x06)!=0x06) { + if ((cpuid_edx(0x80000007) & 0x06) != 0x06) return; /* FID/VID change not supported */ - } msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ @@ -536,6 +535,9 @@ static void init_fidvid_bsp(unsigned bsp_apicid) unsigned i; #endif + if ((cpuid_edx(0x80000007) & 0x06) != 0x06) + return; /* FID/VID change not supported */ + msr_t msr; msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */

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New patch to review for coreboot: AMD Bettong: Add a special case for SPD address of rev F
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12342 -gerrit commit ff9fa136c8c0281e1467a01b9a00842c74cad7e7 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 17:56:53 2015 +0800 AMD Bettong: Add a special case for SPD address of rev F Rev F's SPD address is different from other revision. 0 1 Channel A A0 A2 Channel B A4 AC Change-Id: I620d1f9c295f9a0e30e3821ea36a05dd9f7d3495 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 12 ++++++++++++ src/northbridge/amd/pi/00660F01/dimmSpd.c | 7 +++++++ src/northbridge/amd/pi/dimmSpd.h | 2 ++ 3 files changed, 21 insertions(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 77d29ce..652bb52 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -27,6 +27,7 @@ #include "hudson.h" #include <stdlib.h> #include "BiosCallOuts.h" +#include "northbridge/amd/pi/dimmSpd.h" #include "northbridge/amd/pi/agesawrapper.h" #include <boardid.h> @@ -96,6 +97,17 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) /* NOTE: Only for Bettong. */ #ifdef __PRE_RAM__ +void mainboard_spdaddress_callback(int *spd_address, int socket, int channel, int dimm) +{ + UINT8 spdAddrLookup_rev_F [2][2][4]= { + { {0xA0, 0xA2}, {0xA4, 0xAC}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }; + if (board_id() == 'F') { + *spd_address = spdAddrLookup_rev_F[socket][channel][dimm]; + } +} + TECHNOLOGY_TYPE get_mainboard_dimmtype(void) { if (board_id() == 'F') { diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 5c81f36..afaea0d 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -24,6 +24,11 @@ #include "chip.h" #include "northbridge/amd/pi/dimmSpd.h" +void __attribute__((weak)) mainboard_spdaddress_callback(int *spd_address, int socket, int channel, int dimm) +{ + /* empty */ +} + AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { int spdAddress; @@ -40,6 +45,8 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA return AGESA_ERROR; spdAddress = config->spdAddrLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + + mainboard_spdaddress_callback(&spdAddress, info->SocketId, info->MemChannelId, info->DimmId); if (spdAddress == 0) return AGESA_ERROR; int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); diff --git a/src/northbridge/amd/pi/dimmSpd.h b/src/northbridge/amd/pi/dimmSpd.h index 8e49b7c..aa5ad62 100644 --- a/src/northbridge/amd/pi/dimmSpd.h +++ b/src/northbridge/amd/pi/dimmSpd.h @@ -23,4 +23,6 @@ int hudson_readSpd(int spdAddress, char *buf, size_t len); int smbus_readSpd(int spdAddress, char *buf, size_t len); +void mainboard_spdaddress_callback(int *spd_address, int socket, int channel, int dimm); + #endif

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Patch set updated for coreboot: AMD/Bettong: Memory configuration for DDR3 and DDR4
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11733 -gerrit commit b22d76311bf32d48663eb22b3045523cacb7bee4 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 17:55:01 2015 +0800 AMD/Bettong: Memory configuration for DDR3 and DDR4 1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4. 2. DDR4 uses different memory configuration in AGESA. Pass memory configuration parameters in agesawrapper_amdinitpost. 3. Tested on Rev C and Rev F. Both of them can boot to Windows 8 and have the correct memory size. Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 16 +++++++++++++++ src/northbridge/amd/pi/agesawrapper.c | 35 ++++++++++++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.h | 2 ++ 3 files changed, 53 insertions(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index e14978a..77d29ce 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -27,6 +27,8 @@ #include "hudson.h" #include <stdlib.h> #include "BiosCallOuts.h" +#include "northbridge/amd/pi/agesawrapper.h" +#include <boardid.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); @@ -91,3 +93,17 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +/* NOTE: Only for Bettong. */ +#ifdef __PRE_RAM__ +TECHNOLOGY_TYPE get_mainboard_dimmtype(void) +{ + if (board_id() == 'F') { + return DDR4_TECHNOLOGY; + } else { + return DDR3_TECHNOLOGY; + } + + return UNSUPPORTED_TECHNOLOGY; /* not reached here. */ +} +#endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 5772fb4..6c2cf12 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -22,6 +22,7 @@ #include <heapManager.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> +#include <PlatformMemoryConfiguration.h> VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -42,6 +43,11 @@ static void *AcpiIvrs = NULL; static void *AcpiCrat = NULL; #endif /* #ifndef __PRE_RAM__ */ +TECHNOLOGY_TYPE __attribute__((weak)) get_mainboard_dimmtype(void) +{ + return DDR3_TECHNOLOGY; +} + AGESA_STATUS agesawrapper_amdinitreset(void) { AGESA_STATUS status; @@ -132,6 +138,35 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MOTHER_BOARD_LAYERS (LAYERS_6), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + PSO_END + }; + + PSO_ENTRY DDR3PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MOTHER_BOARD_LAYERS (LAYERS_6), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + PSO_END + }; + + if (get_mainboard_dimmtype() == DDR4_TECHNOLOGY) + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + else + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR3PlatformMemoryConfiguration; + // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index cba7dc6..bd9f71f 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -58,4 +58,6 @@ VOID amd_initcpuio(void); VOID amd_initmmio(void); const void *agesawrapper_locate_module (const CHAR8 name[8]); +TECHNOLOGY_TYPE get_mainboard_dimmtype(void); + #endif /* _AGESAWRAPPER_H_ */

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Patch set updated for coreboot: AMD/Bettong: add function to read board version
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11732 -gerrit commit e1404e338a49a4bd28a2e428d8a5c9cac7346017 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 16:19:16 2015 +0800 AMD/Bettong: add function to read board version Bettong uses 3 GPIO(5-7) pins to identify board. The GPIO ports are mapped to MMIO space. The GPIO value and board version are mapped as follow: GPIO5 GPIO6 GPIO7 Version 0 0 0 A 0 0 1 B ...... 1 1 1 H Change-Id: I72df28043057d8c4ccc4a2e645011ca5379e9928 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/Makefile.inc | 2 ++ src/mainboard/amd/bettong/boardid.c | 56 ++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc index 0361362..5358d92 100644 --- a/src/mainboard/amd/bettong/Makefile.inc +++ b/src/mainboard/amd/bettong/Makefile.inc @@ -15,9 +15,11 @@ romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c +romstage-y += boardid.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c ifeq ($(CONFIG_HUDSON_IMC_FWM), y) ramstage-y += fchec.c endif +ramstage-y += boardid.c diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c new file mode 100644 index 0000000..3cb40bc --- /dev/null +++ b/src/mainboard/amd/bettong/boardid.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <reset.h> +#include <boardid.h> + +/** + *Bettong uses 3 GPIO(5-7) pins to identify board. + *The GPIO ports are mapped to MMIO space. + *The GPIO value and board version are mapped as follow: + *GPIO5 GPIO6 GPIO7 Version + * 0 0 0 A + * 0 0 1 B + * ...... + * 1 1 1 H + */ + +uint8_t board_id(void) +{ + u32 gpiommioaddr; + u8 value = 0; + u8 boardrev = 0; + char boardid; + + gpiommioaddr = 0xfed80000ul + 0x1500; + value = *(volatile u8 *) (gpiommioaddr + (7 << 2) + 2); //agpio7 //board_id2 + boardrev = value & 1; + value = *(volatile u8 *) (gpiommioaddr + (6 << 2) + 2); //agpio6 //board_id1 + boardrev |= (value & 1) << 1; + value = *(volatile u8 *) (gpiommioaddr + (5 << 2) + 2); //agpio5 //board_id0 + boardrev |= (value & 1) << 2; + + boardid = 'A' + boardrev; + + return boardid; +}

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Patch set updated for coreboot: fsp_baytrail: Add functions to set a GPIO
by Werner Zeh 06 Nov '15

06 Nov '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12341 -gerrit commit 155b1fc6035a067d6b7b73ec792bec22ad5da509 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Nov 6 08:38:38 2015 +0100 fsp_baytrail: Add functions to set a GPIO Add two functions to set a memory mapped GPIO to a given value. TEST=Booted siemens/mc_tcu3 board and confirmed GPIO-value after using this functions. Change-Id: Idc14c5d4049487e60040cc294ba0cea363d998a6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/baytrail/gpio.h | 18 ++++++++++++++++++ src/soc/intel/fsp_baytrail/gpio.c | 24 ++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index 15f65ee..3d30a86 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -336,7 +336,9 @@ void setup_soc_gpios(struct soc_gpio_config *config); /* This function is weak and can be overridden by a mainboard function. */ struct soc_gpio_config* mainboard_get_gpios(void); uint8_t read_score_gpio(uint8_t gpio_num); +void write_score_gpio(uint8_t gpio_num, uint8_t val); uint8_t read_ssus_gpio(uint8_t gpio_num); +void write_ssus_gpio(uint8_t gpio_num, uint8_t val); void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); @@ -398,6 +400,22 @@ static inline int ssus_get_gpio(int pad) return read32(val_addr) & PAD_VAL_HIGH; } +/* These functions require that the output pad is configured as an output */ +/* GPIO and is mapped to memory space and not IO space. */ +static inline void score_set_gpio(int pad, int val) +{ + uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); + + write32(val_addr, ((read32(val_addr) & ~0x1) | val)); +} + +static inline void ssus_set_gpio(int pad, int val) +{ + uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); + + write32(val_addr, ((read32(val_addr) & ~0x1) | val)); +} + static inline void ssus_disable_internal_pull(int pad) { const uint32_t pull_mask = ~(0xf << 7); diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 6313596..3497a63 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -266,6 +266,18 @@ uint8_t read_score_gpio(uint8_t gpio_num) return retval; } +/** \brief sets an output SCORE GPIO to desired value + * + * @param gpio_num The GPIO number being read + * @param val The value this output must be set to (0 or 1) + * @return void + */ +void write_score_gpio(uint8_t gpio_num, uint8_t val) +{ + if (gpio_num < GPSCORE_COUNT) + score_set_gpio(gpscore_gpio_to_pad[gpio_num], val); +} + /** \brief returns the input / output value from an SSUS GPIO * * @param gpio_num The GPIO number being read @@ -280,6 +292,18 @@ uint8_t read_ssus_gpio(uint8_t gpio_num) return retval; } +/** \brief sets an output SSUS GPIO to desired value + * + * @param gpio_num The GPIO number being read + * @param val The value this output must be set to (0 or 1) + * @return void + */ +void write_ssus_gpio(uint8_t gpio_num, uint8_t val) +{ + if (gpio_num < GPSSUS_COUNT) + ssus_set_gpio(gpssus_gpio_to_pad[gpio_num], val); +} + /** \brief Sets up the function, pulls, and Input/Output of a Baytrail * SSUS (S5) or SCORE (S0) GPIO *

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New patch to review for coreboot: fsp_baytrail: Add functions to set a GPIO
by Werner Zeh 06 Nov '15

06 Nov '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12341 -gerrit commit 856d6b3aed589550a3164a1ac0b3459abd2c9a30 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Nov 6 08:38:38 2015 +0100 fsp_baytrail: Add functions to set a GPIO Add two functions to set a memory mapped GPIO to a given value. TEST=siemens/mc_tcu3 booted and GPIO-value confirmed after using this functions. Change-Id: Idc14c5d4049487e60040cc294ba0cea363d998a6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/baytrail/gpio.h | 16 ++++++++++++++++ src/soc/intel/fsp_baytrail/gpio.c | 24 ++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index 15f65ee..70981b4 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -398,6 +398,22 @@ static inline int ssus_get_gpio(int pad) return read32(val_addr) & PAD_VAL_HIGH; } +/* These functions require that the output pad is configured as an output */ +/* GPIO and is mapped to memory space and not IO space. */ +static inline void score_set_gpio(int pad, int val) +{ + uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); + + write32(val_addr, ((read32(val_addr) & ~0x1) | val)); +} + +static inline void ssus_set_gpio(int pad, int val) +{ + uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); + + write32(val_addr, ((read32(val_addr) & ~0x1) | val)); +} + static inline void ssus_disable_internal_pull(int pad) { const uint32_t pull_mask = ~(0xf << 7); diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 6313596..3497a63 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -266,6 +266,18 @@ uint8_t read_score_gpio(uint8_t gpio_num) return retval; } +/** \brief sets an output SCORE GPIO to desired value + * + * @param gpio_num The GPIO number being read + * @param val The value this output must be set to (0 or 1) + * @return void + */ +void write_score_gpio(uint8_t gpio_num, uint8_t val) +{ + if (gpio_num < GPSCORE_COUNT) + score_set_gpio(gpscore_gpio_to_pad[gpio_num], val); +} + /** \brief returns the input / output value from an SSUS GPIO * * @param gpio_num The GPIO number being read @@ -280,6 +292,18 @@ uint8_t read_ssus_gpio(uint8_t gpio_num) return retval; } +/** \brief sets an output SSUS GPIO to desired value + * + * @param gpio_num The GPIO number being read + * @param val The value this output must be set to (0 or 1) + * @return void + */ +void write_ssus_gpio(uint8_t gpio_num, uint8_t val) +{ + if (gpio_num < GPSSUS_COUNT) + ssus_set_gpio(gpssus_gpio_to_pad[gpio_num], val); +} + /** \brief Sets up the function, pulls, and Input/Output of a Baytrail * SSUS (S5) or SCORE (S0) GPIO *

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New patch to review for coreboot: fsp_baytrail: Add macros for legacy GPIO output set up
by Werner Zeh 06 Nov '15

06 Nov '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12340 -gerrit commit 93dd990e9b296b4dd5944f6bb7048406ab4509e3 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Nov 6 08:22:22 2015 +0100 fsp_baytrail: Add macros for legacy GPIO output set up Up to now the GPIO set up macros for input sets up GPIOs to be mapped to memory space while macros for outputs sets up GPIOs to be mapped to legacy io space. This patch adds two additional macros for legacy output definition and changes the old macros to memory space mapping. In addition, the intel/minnowmax mainboard is modified to use the legacy macros for outputs to ensure this mainboard stays unchanged in terms of functionality. TEST=Bootet siemens/mc_tcu3 and ensured GPIO set up in linux. Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/intel/minnowmax/gpio.c | 6 +++--- src/soc/intel/fsp_baytrail/baytrail/gpio.h | 21 +++++++++++++++++++-- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index 12d3aeb..008dbee 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -178,9 +178,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0=1GB 1=2GB or 4GB*/ GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */ GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */ - GPIO_OUT_HIGH, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ - GPIO_OUT_HIGH, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */ - GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ + GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */ + GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */ GPIO_FUNC0, /* GPIO_S5[12] - PMC_SUSCLK0 */ GPIO_FUNC1, /* GPIO_S5[13] - PMC_SLP_S0IX (TP10) */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index 15f65ee..a3fbf5d 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -202,12 +202,29 @@ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } +#define GPIO_OUT_LOW_LEGACY \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_LOW, \ + .is_gpio = 1 } + +#define GPIO_OUT_HIGH_LEGACY \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_HIGH, \ + .is_gpio = 1 } #define GPIO_OUT_LOW \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_LEGACY, \ + .use_sel = GPIO_USE_MMIO, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_LOW, \ .is_gpio = 1 } @@ -216,7 +233,7 @@ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_LEGACY, \ + .use_sel = GPIO_USE_MMIO, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH, \ .is_gpio = 1 }

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coreboot-gerrit November 2015