coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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1544 discussions

New patch to review for coreboot: udc: dwc2: Add handler for add_strings
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12348 -gerrit commit ac4f15484cd76d77c98a156c3269065997d021ed Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Nov 4 16:11:38 2015 -0800 udc: dwc2: Add handler for add_strings BUG=b:24676003 BRANCH=None TEST=Compiles successfully. fastboot devices shows serial number for shark. Change-Id: I61d6c168fa458d1f880bc566db997aa5d6398361 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 45b286b318281aea9a4b0362c9259d748b66fd28 Original-Change-Id: Ib9cc22de9daa6c5ec9cde1e62c6f5f768e946069 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310984 Original-Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/drivers/udc/dwc2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index 2397f8c..521bdc4 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -920,6 +920,7 @@ struct usbdev_ctrl *dwc2_udc_init(device_descriptor_t *dd) ctrl->poll = dwc2_check_irq; ctrl->add_gadget = udc_add_gadget; + ctrl->add_strings = udc_add_strings; ctrl->enqueue_packet = dwc2_enqueue_packet; ctrl->force_shutdown = dwc2_force_shutdown; ctrl->shutdown = dwc2_shutdown;

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New patch to review for coreboot: udc: dwc2: Add timeout for shutdown operation
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12347 -gerrit commit ebe37b249f7f9606de2bfcac20711c7878ce442c Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Nov 4 16:09:08 2015 -0800 udc: dwc2: Add timeout for shutdown operation BUG=b:24676003 BRANCH=None TEST=Verified that udc shutdown returns after the timeout. Change-Id: I5df598c4eddecbecb353343ef5a4e44eae4fc20b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 268913f21adea9969c9f88e3cb759341a60719f0 Original-Change-Id: I3ee059791d6e821f83f9ac41fd7c5385bd60e21e Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310983 Original-Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/drivers/udc/dwc2.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index 32d6a5d..2397f8c 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -695,7 +695,12 @@ static void dwc2_shutdown(struct usbdev_ctrl *this) int i, j; int is_empty = 0; - while (!is_empty) { + uint64_t shutdown_timer_us = timer_us(0); + /* Wait upto 3 seconds for packets to be flushed out. */ + uint64_t shutdown_timeout_us = 3 * 1000 * 1000UL; + + while ((!is_empty) && + (timer_us(shutdown_timer_us) < shutdown_timeout_us)) { is_empty = 1; this->poll(this); for (i = 0; i < 16; i++) @@ -704,6 +709,9 @@ static void dwc2_shutdown(struct usbdev_ctrl *this) is_empty = 0; } + if (timer_us(shutdown_timer_us) >= shutdown_timeout_us) + usb_debug("Error: Failed to empty queues.. timeout\n"); + dwc2_force_shutdown(this); }

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New patch to review for coreboot: rockchip/rk3288: hdmi: configure display output mode with EDID information
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12346 -gerrit commit 9813b23ef2169136b8e9fc1b5e31cc4ee8e6dd87 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Oct 27 16:40:08 2015 +0800 rockchip/rk3288: hdmi: configure display output mode with EDID information 'edid->hdmi_monitor_detected' would indicate whether the monitor interface is HDMI or DVI. BRANCH=none BUG=chrome-os-partner:43789 TEST=Previously, my LG monitor couldn't show dev screen. But now I can see dev screen have been posted normally. Change-Id: Id71f051b2cd792712e52bee7a763db383c1962a8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 88101589a22d06f0bc25e0750b2862cf66b55391 Original-Change-Id: I157861d327926b834e1e8606b0b676f413491c70 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309056 Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/rockchip/rk3288/hdmi.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 104d80f..805b98a 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -488,7 +488,6 @@ static int hdmi_phy_init(u32 mpixelclock) static void hdmi_av_composer(const struct edid *edid) { u8 mdataenablepolarity = 1; - u8 mdvi = 0; u8 inv_val; /* set up hdmi_fc_invidconf */ @@ -506,9 +505,9 @@ static void hdmi_av_composer(const struct edid *edid) HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); - inv_val |= (mdvi ? - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE : - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE); + inv_val |= (edid->hdmi_monitor_detected ? + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE); inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;

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New patch to review for coreboot: edid: add hdmi_monitor_detected in data struct edid
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12345 -gerrit commit e327e3802cde5e00a70f1ca550e69e32b5a0ae51 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Oct 27 16:17:13 2015 +0800 edid: add hdmi_monitor_detected in data struct edid HDMI driver need to know whether the monitor is DVI or HDMI interface, so this commit just introduce a new number 'hdmi_monitor_detected' to struct edid. There were four bits to indicate the monitor interfaces, it's better to take use of that. But those bits only existed in EDID 1.4 version, but didn't persented in the previous EDID version, so I decided to detect the hdmi cea block. BRANCH=none BUG=chrome-os-partner:43789 TEST=When mickey connect with HDMI monitor, see 'hdmi_monitor_detected' is 'true'. When mickey connect with DVI monitor, see 'hdmi_monitor_detected' is 'false'. Change-Id: I1a4f1410e1cce1474ffae858db161a18578cac3a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 409f041805d9fdff2d49faa1a3a262cf4dc609c2 Original-Change-Id: Ife770898b0f2b4f58b8259711101a0cab4a5e4ac Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309055 Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/edid.h | 2 ++ src/lib/edid.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/include/edid.h b/src/include/edid.h index 43e6883..d3cab17 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -87,6 +87,8 @@ struct edid { u32 x_resolution; u32 y_resolution; u32 bytes_per_line; + + int hdmi_monitor_detected; }; /* Defined in src/lib/edid.c */ diff --git a/src/lib/edid.c b/src/lib/edid.c index d005678..0f5643d 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -657,6 +657,8 @@ cea_hdmi_block(struct edid *out, unsigned char *x) { int length = x[0] & 0x1f; + out->hdmi_monitor_detected = 1; + printk(BIOS_SPEW, " (HDMI)\n"); printk(BIOS_SPEW, " Source physical address %d.%d.%d.%d\n",

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New patch to review for coreboot: Lars: Enable Fan control support
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12344 -gerrit commit f3c8ebeb0c3852eb9bd5f9892d6a712fdb2ea370 Author: david <david_wu(a)quantatw.com> Date: Tue Nov 3 18:38:47 2015 +0800 Lars: Enable Fan control support Copy from the CL https://chromium-review.googlesource.com/#/c/307028/ BRANCH=None BUG=None TEST=emerge-lars coreboot Change-Id: I131fb729661f0f3bfd198cdf238c627bf38a46a5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 70d471c507d12924466979c93742944975a03f27 Original-Change-Id: I0128dc65110ba363185db9c2aca5cdb140c344c2 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310394 Original-Commit-Ready: David Wu <david_wu(a)quantatw.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/acpi/dptf.asl | 3 +++ src/mainboard/google/lars/acpi/dptf.asl | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index 15f7275..45783dc 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -40,6 +40,9 @@ /* SKL-Y EC already has a custom charge profile based on temperature. */ #undef DPTF_ENABLE_CHARGER +/* SKL-Y is Fanless design. */ +#undef DPTF_ENABLE_FAN_CONTROL + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl index 73ed77b..2eea804 100644 --- a/src/mainboard/google/lars/acpi/dptf.asl +++ b/src/mainboard/google/lars/acpi/dptf.asl @@ -38,6 +38,7 @@ #define DPTF_TSR2_CRITICAL 70 #define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { @@ -48,6 +49,42 @@ Name (CHPS, Package () { Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ }) +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, + Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, + Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, + Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 3402, 65, 650}, + Package () {40, 0xFFFFFFFF, 2904, 45, 450}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, + 0, 0, 0 + } +}) +#endif + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },

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Patch set updated for coreboot: AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11752 -gerrit commit 00932ad3b738e905d71615dc0481e41256369648 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Thu Aug 13 01:22:33 2015 +0800 AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1 1. This is required the BLOB change Ie86bb0cf AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5) 2. The PSP firmwares' location should be changed or some firmwares can't be added. 3. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 2 +- .../amd/pi/00660F01/Proc/Fch/Common/FchDef.h | 2 ++ src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h | 18 ++++++++++++++---- .../amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h | 2 ++ 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..c50ef2a 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -108,7 +108,7 @@ HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ HUDSON_PSP_DIRECTORY_SIZE=256 else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_PSP_OFFSET=131072 +HUDSON_PSP_OFFSET=196608 else HUDSON_PSP_OFFSET=0 endif diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h index d0063a4..41f103b 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h @@ -340,6 +340,8 @@ VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr); /// VOID FchSpiUnlock (IN VOID *FchDataPtr); VOID FchSpiLock (IN VOID *FchDataPtr); +VOID FchUsb3D3ColdCallback (IN VOID *FchDataPtr); +VOID FchUsb3D0Callback (IN VOID *FchDataPtr); /*--------------------------- Documentation Pages ---------------------------*/ VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h index 7576cad..92201b8 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h @@ -2007,8 +2007,9 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_PMIOxC0_S5ResetStatus 0xFED803C0ul // S5ResetStatus #define FCH_PMIOxC0_S5ResetStatus_ThermalTrip (1 << 0) #define FCH_PMIOxC0_S5ResetStatus_FourSecondPwrBtn (1 << 1) -#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3ff | (1 << 20)) +#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3fe | (1 << 20)) #define FCH_PMIOxC0_S5ResetStatus_All_Status 0x3FFF03FFul +#define FCH_PMIOxC0_S5ResetStatus_Clr_Status 0x3FFF03FEul #define FCH_PMxC8_Misc 0xFED803C8ul // Misc #define FCH_PMxC8_Misc_UseAcpiStraps (1 << 4) @@ -2020,6 +2021,8 @@ FCH_MISC_REGF0 EQU 0F0h // offset : 0x0E00 // #define FCH_MISCx28_ClkDrvStr2 0xFED80E28ul // ClkDrvStr2 +#define FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn (1 << 30) +#define FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn (1 << 31) #define FCH_MISCx40_MiscClkCntl1 0xFED80E40ul // MiscClkCntl1 #define FCH_MISCx40_MiscClkCntl1_CG1PLL_FBDIV_Test (1 << 26) @@ -2038,7 +2041,8 @@ FCH_MISC_REGF0 EQU 0F0h // offset : 0x1C00 // #define FCH_XHC_PMx00_Configure0 0xFED81C00ul // -#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 +#define FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN BIT15 +#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 #define FCH_XHC_PMx10_Xhc_Memory_Configure 0xFED81C10ul // #define FCH_XHC_PMx18_Usb20_Link_Status 0xFED81C18ul // #define FCH_XHC_PMx20_Usb20_Wake_Control 0xFED81C20ul // @@ -2057,9 +2061,12 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_AOACx40_D3_CONTROL 0xFED81E40ul // #define FCH_AOACx41_D3_STATUS 0xFED81E40ul // #define FCH_AOACx5E_SATA_D3_CONTROL 0xFED81E5Eul // +#define FCH_AOACx64_EHCI_D3_CONTROL 0xFED81E64ul // +#define FCH_AOACx65_EHCI_D3_STATE 0xFED81E65ul // #define FCH_AOACx6E_USB3_D3_CONTROL 0xFED81E6Eul // -#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul // -#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul // +#define FCH_AOACx6F_USB3_D3_STATE 0xFED81E6Ful // +#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul // +#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul // #define FCH_AOACx88Shadow_Register_SRAM_Addr 0xFED81E88ul // #define FCH_AOACx8CShadow_Register_SRAM_Data 0xFED81E8Cul // #define FCH_AOACx94S013_CONTROL 0xFED81E94ul // @@ -2070,6 +2077,9 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_AOACx9C_Shadow_Timer_Control_ShadowAcpiTimerEn (1 << 1) // #define FCH_AOACxA0_PwrGood_Control 0xFED81EA0ul // +#define FCH_AOACxA0_PwrGood_Control_XhcPwrGood (1 << 3) // +#define FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown (1 << 29) // +#define FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB (1 << 30) // #define FCH_AOAC_REG00 0x00 // PerfMonControl #define FCH_AOAC_REG04 0x04 // PerfMonTimeLimit diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h index 6108274..6115396 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -63,6 +63,8 @@ #define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr #define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability +#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2 ///< PSP Private Block Base Address (PSP_ADDR) + #define D8F0x44_PmNxtPtrW_MASK 0xff #define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR

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Patch set updated for coreboot: AMD Bettong DSDT table: Declare memory between TOM1 and 0xFED40000 for PCI MMIO
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11747 -gerrit commit ad51c2f198929ed246130d02843494b38d16da52 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Aug 18 06:28:02 2015 +0800 AMD Bettong DSDT table: Declare memory between TOM1 and 0xFED40000 for PCI MMIO In current code, \_SB.PCI0 declare MMIO between TOM1 and 4GB. This is not correct because higher MMIO space is reserved by \_SB rather than \_SB.PCI0. For example: [0xFEDC2000 - 0xFEDC5FFF] reserved for FCH I2C [0xFEDC6000 - 0xFEDC8FFF] reserved for FCH UART Change-Id: I922d8c6a8ff1433582c70f86d5636171394af283 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/southbridge/amd/pi/hudson/acpi/fch.asl | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 02a272d..7551cc5 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -116,16 +116,12 @@ Method(_CRS, 0) { CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* - * Declare memory between TOM1 and 4GB as available + * Declare memory between TOM1 and 0xFED40000 as available * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). + * TODO: change the hardcoded value. */ Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) + Subtract(0xFED40000, TOM1, Local0) Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */

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Patch set updated for coreboot: AMD Bettong: refactor PCI interrupt table
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11746 -gerrit commit 47cf78f0012bb2b2d545986dbb38f168e1bba070 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Aug 18 06:22:22 2015 +0800 AMD Bettong: refactor PCI interrupt table 1. Use write_pci_int_table to write registers 0xC00/0xC01. 2. Add GPIO, I2C and UART interrupt according "BKDG for AMD Family 15h Models 60h-6Fh Processors", 50742 Rev 3.01 - July 17, 2015 3. The interrupt valudes are copied from bettong/mptable.c. All devices work in Windows 10. Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/mainboard/amd/bettong/mainboard.c | 62 +++++++++++++++++++++++ src/mainboard/amd/bettong/mptable.c | 54 +++++--------------- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 8 ++- src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 3 +- 4 files changed, 84 insertions(+), 43 deletions(-) diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index dc5d438..c31f5b7 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -17,6 +17,65 @@ #include <device/device.h> #include <arch/acpi.h> #include <agesawrapper.h> +#include <southbridge/amd/common/amd_pci_util.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F, + [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, + [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, + [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, + [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00, + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00, + [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00, + [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, + [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + + /************************************************* * enable the dedicated function in bettong board. @@ -27,6 +86,9 @@ static void bettong_enable(device_t dev) if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index 77eff8c..d77d7e9 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -24,23 +24,7 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include "southbridge/amd/pi/hudson/hudson.h" /* pm_ioread() */ - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; +#include <southbridge/amd/common/amd_pci_util.h> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) { @@ -64,7 +48,6 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -91,17 +74,6 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ @@ -115,27 +87,27 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 2ace0f0..679f233 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -77,8 +77,14 @@ #endif #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) -#define FCH_INT_TABLE_SIZE 0x75 +#define FCH_INT_TABLE_SIZE 0x76 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#define PIRQ_I2C0 0x70 +#define PIRQ_I2C1 0x71 +#define PIRQ_I2C2 0x72 +#define PIRQ_I2C3 0x73 +#define PIRQ_UART0 0x74 +#define PIRQ_UART1 0x75 #endif #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index 23a7b11..f898907 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -32,7 +32,8 @@ const char * intr_types[] = { #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", - [0x75] = NULL + [0x62] = "GPIO\t", + [0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t", #endif };

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Patch set updated for coreboot: AMD/Bettong: add FCH's GPIO, UART & I2C support
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11750 -gerrit commit 5f3be6e354168956ca1d43cc5cf8e98ffc1c7eb6 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 22:02:36 2015 +0800 AMD/Bettong: add FCH's GPIO, UART & I2C support Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled by registers mapped at MMIO space. This ASL code is used for Windows drivers. TEST: 1. Boot Windows 8 or Windows 10. 2. Install AMD Catalyst driver. 3. AMD FPIO, UART and I2C can be found in device manager. 4. I2C passed Multi Interface Test Tool (MITT) test. Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/dsdt.asl | 1 + src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl | 101 +++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl index 888d5cd..d5390bd 100644 --- a/src/mainboard/amd/bettong/dsdt.asl +++ b/src/mainboard/amd/bettong/dsdt.asl @@ -68,6 +68,7 @@ DefinitionBlock ( /* Describe PCI INT[A-H] for the Southbridge */ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + #include <southbridge/amd/pi/hudson/acpi/carrizo_fch.asl> } /* End \_SB scope */ diff --git a/src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl b/src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl new file mode 100644 index 0000000..5bfb366 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Device(GPIO) { + Name (_HID, "AMD0030") + Name (_CID, "AMD0030") + Name(_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + // + // Interrupt resource. In this example, banks 0 & 1 share the same + // interrupt to the parent controller and similarly banks 2 & 3. + // + // N.B. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform + // + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + + // + // Memory resource. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform. + // + Memory32Fixed(ReadWrite, 0xFED81500, 0x300) + }) + + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(FUR0) { + Name(_HID,"AMD0020") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {10} + Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(FUR1) { + Name(_HID,"AMD0020") + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {11} + Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(I2CA) { + Name(_HID,"AMD0010") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {3} + Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) + }) + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(I2CB) +{ + Name(_HID,"AMD0010") + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {15} + Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +}

1 0

New patch to review for coreboot: uart8250mem: Change the delay for uart (Don't merge)
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12343 -gerrit commit f62b4b4474017e9c151a7881e550f142d3106f3c Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 18:56:56 2015 +0800 uart8250mem: Change the delay for uart (Don't merge) Change-Id: I6131adbe24a0ee6dfd47d00265fd8583ef22ec0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/drivers/uart/uart8250mem.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 278ddb8..9cb29f0 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -32,6 +32,12 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) +static void my_delay(int delay) +{ + while (delay --) + outb(0xaa, 0x80); +} + #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) static uint8_t uart8250_read(void *base, uint8_t reg) { @@ -63,7 +69,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_tx_byte(base)) - udelay(1); + my_delay(1); uart8250_write(base, UART8250_TBR, data); } @@ -71,7 +77,7 @@ static void uart8250_mem_tx_flush(void *base) { unsigned long int i = FIFO_TIMEOUT; while(i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT)) - udelay(1); + my_delay(1); } static int uart8250_mem_can_rx_byte(void *base) @@ -83,7 +89,7 @@ static unsigned char uart8250_mem_rx_byte(void *base) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base)) - udelay(1); + my_delay(1); if (i) return uart8250_read(base, UART8250_RBR); else

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coreboot-gerrit November 2015