coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch merged into coreboot/master: amd/00730F01: Fix MMCONF resource
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit 5d490387045040a02e12592f479e2ab0c40426cf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 27 07:58:22 2015 +0300 amd/00730F01: Fix MMCONF resource Fixed resources have to be declared early. Change-Id: Iedd92e5e7ee43a833bda48e6377da1b78fa4bd81 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12261 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/12261 for details. -gerrit

1 0

Patch set updated for coreboot: AMD/Bettong: Set on-board eMMC as SD 2.0
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11748 -gerrit commit 94e5927b19f566b62bd3c60c9ab51397247b4ff5 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Nov 6 23:24:08 2015 +0800 AMD/Bettong: Set on-board eMMC as SD 2.0 The on-board eMMC is designed as 2.0. If it is set as 3.0, it can not be detected. Change-Id: I9fd913f76535e65c1672924ebdeba3d35dea59cc Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 652bb52..afe20fb 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -89,6 +89,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ /* sata configuration */ + /* SD configuration */ + /* Rev F has an on-board eMMC, which only supports SD 2.0 */ + if (board_id() == 'F') { + FchParams_env->Sd.SdConfig = SdVer2; + } } printk(BIOS_DEBUG, "Done\n");

1 0

Patch set updated for coreboot: libpayload/udc: dwc2: Add handler for add_strings
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12348 -gerrit commit e1d815b2936117015c84dc911fd141c270390066 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Nov 4 16:11:38 2015 -0800 libpayload/udc: dwc2: Add handler for add_strings BUG=b:24676003 BRANCH=None TEST=Compiles successfully. fastboot devices shows serial number for shark. Change-Id: I61d6c168fa458d1f880bc566db997aa5d6398361 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 45b286b318281aea9a4b0362c9259d748b66fd28 Original-Change-Id: Ib9cc22de9daa6c5ec9cde1e62c6f5f768e946069 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310984 Original-Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/drivers/udc/dwc2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index 2397f8c..521bdc4 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -920,6 +920,7 @@ struct usbdev_ctrl *dwc2_udc_init(device_descriptor_t *dd) ctrl->poll = dwc2_check_irq; ctrl->add_gadget = udc_add_gadget; + ctrl->add_strings = udc_add_strings; ctrl->enqueue_packet = dwc2_enqueue_packet; ctrl->force_shutdown = dwc2_force_shutdown; ctrl->shutdown = dwc2_shutdown;

1 0

Patch set updated for coreboot: libpayload/udc: dwc2: Add timeout for shutdown operation
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12347 -gerrit commit a88aeb8fe6a276a119bdef59038da38e52e3a4f6 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Nov 4 16:09:08 2015 -0800 libpayload/udc: dwc2: Add timeout for shutdown operation BUG=b:24676003 BRANCH=None TEST=Verified that udc shutdown returns after the timeout. Change-Id: I5df598c4eddecbecb353343ef5a4e44eae4fc20b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 268913f21adea9969c9f88e3cb759341a60719f0 Original-Change-Id: I3ee059791d6e821f83f9ac41fd7c5385bd60e21e Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310983 Original-Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/drivers/udc/dwc2.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index 32d6a5d..2397f8c 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -695,7 +695,12 @@ static void dwc2_shutdown(struct usbdev_ctrl *this) int i, j; int is_empty = 0; - while (!is_empty) { + uint64_t shutdown_timer_us = timer_us(0); + /* Wait upto 3 seconds for packets to be flushed out. */ + uint64_t shutdown_timeout_us = 3 * 1000 * 1000UL; + + while ((!is_empty) && + (timer_us(shutdown_timer_us) < shutdown_timeout_us)) { is_empty = 1; this->poll(this); for (i = 0; i < 16; i++) @@ -704,6 +709,9 @@ static void dwc2_shutdown(struct usbdev_ctrl *this) is_empty = 0; } + if (timer_us(shutdown_timer_us) >= shutdown_timeout_us) + usb_debug("Error: Failed to empty queues.. timeout\n"); + dwc2_force_shutdown(this); }

1 0

Patch set updated for coreboot: rockchip/rk3288: hdmi: configure display output mode with EDID information
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12346 -gerrit commit df19fb9b4459c029bd489bb4983706f09c209a8c Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Oct 27 16:40:08 2015 +0800 rockchip/rk3288: hdmi: configure display output mode with EDID information 'edid->hdmi_monitor_detected' would indicate whether the monitor interface is HDMI or DVI. BRANCH=none BUG=chrome-os-partner:43789 TEST=Previously, my LG monitor couldn't show dev screen. But now I can see dev screen have been posted normally. Change-Id: Id71f051b2cd792712e52bee7a763db383c1962a8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 88101589a22d06f0bc25e0750b2862cf66b55391 Original-Change-Id: I157861d327926b834e1e8606b0b676f413491c70 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309056 Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/rockchip/rk3288/hdmi.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 104d80f..805b98a 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -488,7 +488,6 @@ static int hdmi_phy_init(u32 mpixelclock) static void hdmi_av_composer(const struct edid *edid) { u8 mdataenablepolarity = 1; - u8 mdvi = 0; u8 inv_val; /* set up hdmi_fc_invidconf */ @@ -506,9 +505,9 @@ static void hdmi_av_composer(const struct edid *edid) HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); - inv_val |= (mdvi ? - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE : - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE); + inv_val |= (edid->hdmi_monitor_detected ? + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE); inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;

1 0

Patch set updated for coreboot: edid: add hdmi_monitor_detected in data struct edid
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12345 -gerrit commit 0e57d940cfe418adff8c3a0fb14ad7b640d571fd Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Oct 27 16:17:13 2015 +0800 edid: add hdmi_monitor_detected in data struct edid HDMI driver need to know whether the monitor is DVI or HDMI interface, so this commit just introduce a new number 'hdmi_monitor_detected' to struct edid. There were four bits to indicate the monitor interfaces, it's better to take use of that. But those bits only existed in EDID 1.4 version, but didn't persented in the previous EDID version, so I decided to detect the hdmi cea block. BRANCH=none BUG=chrome-os-partner:43789 TEST=When mickey connect with HDMI monitor, see 'hdmi_monitor_detected' is 'true'. When mickey connect with DVI monitor, see 'hdmi_monitor_detected' is 'false'. Change-Id: I1a4f1410e1cce1474ffae858db161a18578cac3a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 409f041805d9fdff2d49faa1a3a262cf4dc609c2 Original-Change-Id: Ife770898b0f2b4f58b8259711101a0cab4a5e4ac Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309055 Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/edid.h | 2 ++ src/lib/edid.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/include/edid.h b/src/include/edid.h index 43e6883..d3cab17 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -87,6 +87,8 @@ struct edid { u32 x_resolution; u32 y_resolution; u32 bytes_per_line; + + int hdmi_monitor_detected; }; /* Defined in src/lib/edid.c */ diff --git a/src/lib/edid.c b/src/lib/edid.c index d005678..0f5643d 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -657,6 +657,8 @@ cea_hdmi_block(struct edid *out, unsigned char *x) { int length = x[0] & 0x1f; + out->hdmi_monitor_detected = 1; + printk(BIOS_SPEW, " (HDMI)\n"); printk(BIOS_SPEW, " Source physical address %d.%d.%d.%d\n",

1 0

Patch set updated for coreboot: google/{chell, lars}: Enable Fan control support
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12344 -gerrit commit 51fd31addea777b89143aedc71ab7997660ece25 Author: david <david_wu(a)quantatw.com> Date: Tue Nov 3 18:38:47 2015 +0800 google/{chell,lars}: Enable Fan control support Copy from the CL https://chromium-review.googlesource.com/#/c/307028/ (I40c540dad32beefe249f025b570c347d3ad08c36) BRANCH=None BUG=None TEST=emerge-lars coreboot Change-Id: I131fb729661f0f3bfd198cdf238c627bf38a46a5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 70d471c507d12924466979c93742944975a03f27 Original-Change-Id: I0128dc65110ba363185db9c2aca5cdb140c344c2 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310394 Original-Commit-Ready: David Wu <david_wu(a)quantatw.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/acpi/dptf.asl | 3 +++ src/mainboard/google/lars/acpi/dptf.asl | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index 15f7275..45783dc 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -40,6 +40,9 @@ /* SKL-Y EC already has a custom charge profile based on temperature. */ #undef DPTF_ENABLE_CHARGER +/* SKL-Y is Fanless design. */ +#undef DPTF_ENABLE_FAN_CONTROL + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl index 73ed77b..2eea804 100644 --- a/src/mainboard/google/lars/acpi/dptf.asl +++ b/src/mainboard/google/lars/acpi/dptf.asl @@ -38,6 +38,7 @@ #define DPTF_TSR2_CRITICAL 70 #define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { @@ -48,6 +49,42 @@ Name (CHPS, Package () { Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ }) +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, + Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, + Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, + Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 3402, 65, 650}, + Package () {40, 0xFFFFFFFF, 2904, 45, 450}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, + 0, 0, 0 + } +}) +#endif + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },

1 0

Patch set updated for coreboot: copy mainboard nvidia/l1_2pvv to sunw/ultra40m2 and rename
by Jonathan A. Kollasch 06 Nov '15

06 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12303 -gerrit commit 6f9a811fb502ae3cf62aa1e7b5d0c56e48de45b8 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 30 18:15:55 2015 -0500 copy mainboard nvidia/l1_2pvv to sunw/ultra40m2 and rename Change-Id: Ia275a697caa73168553b5d588d54df651e0539d7 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/sunw/ultra40m2/Kconfig | 75 ++++++++ src/mainboard/sunw/ultra40m2/Kconfig.name | 2 + src/mainboard/sunw/ultra40m2/board_info.txt | 1 + src/mainboard/sunw/ultra40m2/cmos.layout | 77 ++++++++ src/mainboard/sunw/ultra40m2/devicetree.cb | 180 ++++++++++++++++++ src/mainboard/sunw/ultra40m2/get_bus_conf.c | 137 ++++++++++++++ src/mainboard/sunw/ultra40m2/hda_verb.c | 68 +++++++ src/mainboard/sunw/ultra40m2/irq_tables.c | 125 +++++++++++++ src/mainboard/sunw/ultra40m2/mainboard.c | 31 ++++ src/mainboard/sunw/ultra40m2/mb_sysconf.h | 29 +++ src/mainboard/sunw/ultra40m2/mptable.c | 174 +++++++++++++++++ src/mainboard/sunw/ultra40m2/resourcemap.c | 278 ++++++++++++++++++++++++++++ src/mainboard/sunw/ultra40m2/romstage.c | 189 +++++++++++++++++++ 13 files changed, 1366 insertions(+) diff --git a/src/mainboard/sunw/ultra40m2/Kconfig b/src/mainboard/sunw/ultra40m2/Kconfig new file mode 100644 index 0000000..5b19c13 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/Kconfig @@ -0,0 +1,75 @@ +if BOARD_SUNW_ULTRA40M2 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_SOCKET_F + select DIMM_DDR2 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDK8 + select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE + select MCP55_USE_NIC + select MCP55_USE_AZA + select SUPERIO_WINBOND_W83627EHG + select PARALLEL_CPU_INIT + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_512 + select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE + +config MAINBOARD_DIR + string + default sunw/ultra40m2 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config MEM_TRAIN_SEQ + int + default 1 + +config MCP55_NUM + int + default 2 + +config MAINBOARD_PART_NUMBER + string + default "Ultra 40 M2" + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 11 + +config MCP55_PCI_E_X_0 + int + default 2 + +endif # BOARD_SUNW_ULTRA40M2 diff --git a/src/mainboard/sunw/ultra40m2/Kconfig.name b/src/mainboard/sunw/ultra40m2/Kconfig.name new file mode 100644 index 0000000..f6bc551 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUNW_ULTRA40M2 + bool "Ultra 40 M2" diff --git a/src/mainboard/sunw/ultra40m2/board_info.txt b/src/mainboard/sunw/ultra40m2/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/sunw/ultra40m2/cmos.layout b/src/mainboard/sunw/ultra40m2/cmos.layout new file mode 100644 index 0000000..53f259a --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/cmos.layout @@ -0,0 +1,77 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb new file mode 100644 index 0000000..5709db7 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -0,0 +1,180 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/sunw/ultra40m2/get_bus_conf.c b/src/mainboard/sunw/ultra40m2/get_bus_conf.c new file mode 100644 index 0000000..c70cbec --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/get_bus_conf.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/multicore.h> + +#include <cpu/amd/amdk8_sysconf.h> + +#include <stdlib.h> +#include "mb_sysconf.h" + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +struct mb_sysconf_t mb_sysconf; + +unsigned pci1234x[] = +{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, + 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 +}; +unsigned hcdnx[] = +{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, + 0x20202020, + 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +}; + + + + +static unsigned get_bus_conf_done = 0; + +static unsigned get_hcid(unsigned i) +{ + unsigned id = 0; + + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + + unsigned devn = sysconf.hcdn[i] & 0xff; + + device_t dev; + + dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + + switch (dev->device) { + case 0x0369: //IO55 + id = 4; + break; + } + + // we may need more way to find out hcid: subsystem id? GPIO read ? + + // we need use id for 1. bus num, 2. mptable, 3. acpi table + + return id; +} + +void get_bus_conf(void) +{ + unsigned apicid_base; + struct mb_sysconf_t *m; + + int i; + + if (get_bus_conf_done) + return; //do it only once + + get_bus_conf_done = 1; + + sysconf.mb = &mb_sysconf; + + m = sysconf.mb; + memset(m, 0, sizeof(struct mb_sysconf_t)); + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + + m->sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain + + m->bus_mcp55 = (sysconf.pci1234[0] >> 16) & 0xff; + + /* MCP55b */ + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x0f)) + continue; + // check hcid type here + sysconf.hcid[i] = get_hcid(i); + if (!sysconf.hcid[i]) + continue; //unknown co processor + + m->bus_mcp55b = (sysconf.pci1234[1]>>16) & 0xff; + } + +/*I/O APICs: APIC ID Version State Address*/ + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + apicid_base = get_apicid_base(2); + else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + m->apicid_mcp55 = apicid_base+0; + m->apicid_mcp55b = apicid_base+1; +} diff --git a/src/mainboard/sunw/ultra40m2/hda_verb.c b/src/mainboard/sunw/ultra40m2/hda_verb.c new file mode 100644 index 0000000..31052f2 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/hda_verb.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Copyright (C) 2006-2007 AMD + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 + 0x00000000, // Subsystem ID + 0x0000000d, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ + AZALIA_SUBVENDOR(0x0, 0x0000e601), + + /* NID 0x14, FRONT-OUT-L/R */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), + + /* NID 0x15, SURR-OUT-L/R */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), + + /* NID 0x16, CEN/LFE-OUT */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), + + /* NID 0x17, SIDE-SURR-L/R */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01012014), + + /* NID 0x18, MIC1-L/R, VREFO */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19c30), + + /* NID 0x19, MIC2-L/R, VREFO */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c40), + + /* NID 0x1a, LINE1-L/R, VREFO */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x01813431), + + /* NID 0x1b, LINE2-L/R, VREFO */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x0221441f), + + /* NID 0x1c, CD-L/R / GND */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d, PCBEEP */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x9983013e), + + /* NID 0x1e, S/PDIF-OUT */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01454120), + + /* NID 0x1f, S/PDIF-IN */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x01c59150), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sunw/ultra40m2/irq_tables.c b/src/mainboard/sunw/ultra40m2/irq_tables.c new file mode 100644 index 0000000..d643cd4 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/irq_tables.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file was generated by getpir.c, do not modify! + * (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> +#include "mb_sysconf.h" + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + struct mb_sysconf_t *m; + unsigned sbdn; + + uint8_t sum=0; + int i; + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; + m = sysconf.mb; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = m->bus_mcp55; + pirq->rtr_devfn = ((sbdn+6)<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x0370; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; +//pci bridge + write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + + for (i = 1; i < sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff; + + write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + } + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long) pirq_info; + +} diff --git a/src/mainboard/sunw/ultra40m2/mainboard.c b/src/mainboard/sunw/ultra40m2/mainboard.c new file mode 100644 index 0000000..1f26995 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + + +static void mainboard_enable(device_t dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sunw/ultra40m2/mb_sysconf.h b/src/mainboard/sunw/ultra40m2/mb_sysconf.h new file mode 100644 index 0000000..64837f6 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/mb_sysconf.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MB_SYSCONF_H +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_mcp55; + unsigned char bus_mcp55b; + unsigned apicid_mcp55; + unsigned apicid_mcp55b; + unsigned sbdnb; +}; + +#endif diff --git a/src/mainboard/sunw/ultra40m2/mptable.c b/src/mainboard/sunw/ultra40m2/mptable.c new file mode 100644 index 0000000..d000b1a --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/mptable.c @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdk8_sysconf.h> +#include "mb_sysconf.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + struct mb_sysconf_t *m; + unsigned sbdn; + int i, j, bus_isa; + unsigned char apicpin[4]; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + m = sysconf.mb; + + mptable_write_buses(mc, NULL, &bus_isa); + +/*I/O APICs: APIC ID Version State Address*/ + { + device_t dev; + struct resource *res; + uint32_t dword; + + dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) + smp_write_ioapic(mc, m->apicid_mcp55, 0x11, + res2mmio(res, 0, 0)); + + /* Initialize interrupt mapping*/ + dword = pci_read_config32(dev, 0x74); + dword &= ~(1<<15); + dword |= 1<<2; + pci_write_config32(dev, 0x74, dword); + + dword = 0x43c6c643; + pci_write_config32(dev, 0x7c, dword); + + dword = 0x81001a00; + pci_write_config32(dev, 0x80, dword); + + dword = 0xd00012d2; + pci_write_config32(dev, 0x84, dword); + + } + + if (m->bus_mcp55b) { + dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) + smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, + res2mmio(res, 0, 0)); + + dword = 0x43c60000; + pci_write_config32(dev, 0x7c, dword); + + dword = 0x81000000; + pci_write_config32(dev, 0x80, dword); + + dword = 0xd00002d0; + pci_write_config32(dev, 0x84, dword); + + } + + } + + } + + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + +//Slot PCIE + for (j = 2; j < 8; j++) { + device_t dev; + dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); + if (!dev || !dev->enabled) + continue; + for (i = 0; i < 4; i++) + apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4; + smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); + } + +//Slot PCI 32 + { + device_t dev; + dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); + if (dev && dev->enabled) { + for (i = 0; i < 4; i++) + apicpin[i] = 0x10 + (2+i)%4; + smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); + } + } + + if (m->bus_mcp55b) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21 + + + //Slot PCIE + for (j = 2; j < 8; j++) { + device_t dev; + dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0)); + if (!dev || !dev->enabled) + continue; + for (i = 0; i < 4; i++) { + apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4; + } + smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin); + } + + } + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c new file mode 100644 index 0000000..2950687 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/resourcemap.c @@ -0,0 +1,278 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static void setup_mb_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, +// PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, +// PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c new file mode 100644 index 0000000..4186cc7 --- /dev/null +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_fxx_rev.h> +#include "southbridge/nvidia/mcp55/early_smbus.c" +#include <northbridge/amd/amdk8/raminit.h> +#include "lib/delay.c" +#include <cpu/x86/lapic.h> +#include "northbridge/amd/amdk8/reset_test.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <cpu/x86/bist.h> +#include "northbridge/amd/amdk8/debug.c" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/amdk8/f.h> +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "lib/generic_sdram.c" +#include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" + +#define MCP55_MB_SETUP \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ + +#include <southbridge/nvidia/mcp55/early_setup_ss.h> +#include "southbridge/nvidia/mcp55/early_setup_car.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/early_ht.c" + +static void sio_setup(void) +{ + uint32_t dword; + uint8_t byte; + + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + sio_setup(); + } + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x24, 0); + pnp_exit_ext_func_mode(SERIAL_DEV); + + setup_mb_resource_map(); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + setup_coherent_ht_domain(); // routing table and start other core0 + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + +#if CONFIG_SET_FIDVID + { + msr_t msr; + msr=rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } +#endif + + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ + + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x(); + + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } + allow_all_aps_stop(bsp_apicid); + + //It's the time to set ctrl in sysinfo now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + + /* all ap stopped? */ + + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now +}

1 0

Patch set updated for coreboot: ultra40m2: initialize hardware monitor and fan control
by Jonathan A. Kollasch 06 Nov '15

06 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12309 -gerrit commit 350e6f669b459d69654b6139d7ddf7431d89eb8e Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 3 12:19:35 2015 -0600 ultra40m2: initialize hardware monitor and fan control Change-Id: I3fbb897feb68d899e5dec075a09d0dd605eca5ce Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/sunw/ultra40m2/devicetree.cb | 12 +-- src/mainboard/sunw/ultra40m2/mainboard.c | 151 ++++++++++++++++++++++++++++- 2 files changed, 154 insertions(+), 9 deletions(-) diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb index 9928d45..9982459 100644 --- a/src/mainboard/sunw/ultra40m2/devicetree.cb +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -75,12 +75,12 @@ chip northbridge/amd/amdk8/root_complex # Root complex #chip drivers/generic/generic # PCA9556 GPIO on HDD backplanes (address conflict!) # device i2c 18 on end #end - #chip drivers/generic/generic # EMC6D103 HWM (for CPUs) - # device i2c 2d on end - #end - #chip drivers/generic/generic # DME1737 HWM - # device i2c 2e on end - #end + chip drivers/generic/generic # EMC6D103 HWM (for CPUs) + device i2c 2d on end + end + chip drivers/generic/generic # DME1737 HWM + device i2c 2e on end + end #chip drivers/generic/generic # HDD 4-7 backplane FRU 24C64 EEPROM # device i2c 51 on end #end diff --git a/src/mainboard/sunw/ultra40m2/mainboard.c b/src/mainboard/sunw/ultra40m2/mainboard.c index 1f26995..3e2bbf0 100644 --- a/src/mainboard/sunw/ultra40m2/mainboard.c +++ b/src/mainboard/sunw/ultra40m2/mainboard.c @@ -15,15 +15,160 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> +#include <device/pnp_def.h> +#include <device/smbus.h> +#include <stdlib.h> +#include <superio/smsc/dme1737/dme1737.h> +static void emc6d103_init(void) +{ + size_t i; + int reg; + + static const struct { uint8_t idx; uint8_t msk; uint8_t set; } script[] = { + { 0x7f, 0x7f, 0x80 }, // INIT + { 0x4f, 0x00, 0x64 }, // Diode 1 High 100°C + { 0x53, 0x00, 0x64 }, // Diode 2 High 100°C (Sun firmware didn't set this) + { 0x54, 0x00, 0x30 }, // Tach1 Minimum LSB + { 0x55, 0x00, 0x2a }, // Tach1 Minimum MSB + { 0x56, 0x00, 0x30 }, // Tach2 Minimum LSB + { 0x57, 0x00, 0x2a }, // Tach2 Minimum MSB + { 0x5c, 0x00, 0x02 }, // PWM 1 Config + { 0x5d, 0x00, 0x42 }, // PWM 2 Config + { 0x5f, 0x00, 0x8a }, // Zone 1 range, Fan 1 freq + { 0x60, 0x00, 0xca }, // Zone 2 range, Fan 2 freq + { 0x61, 0x00, 0x8a }, // Zone 3 range, Fan 3 freq + { 0x62, 0x00, 0x67 }, // Min/Off, PWM 1 ramp rate + { 0x63, 0x00, 0x70 }, // PWM 2, PWM 3 ramp rate + { 0x64, 0x00, 0x59 }, // PWM1 Minimum Duty Cycle + { 0x65, 0x00, 0x59 }, // PWM2 Minimum Duty Cycle + { 0x67, 0x00, 0x47 }, // Zone 1 Low Temp Limit + { 0x69, 0x00, 0x47 }, // Zone 3 Low Temp Limit + { 0x80, 0x00, 0x07 }, // Interrupt Enable 2 + { 0x40, 0xfe, 0x01 }, // START + }; + + struct device * const dev = dev_find_slot_on_smbus(2, 0x2d); + if (dev == NULL) + printk(BIOS_WARNING, "EMC6D103 not found\n"); + + printk(BIOS_SPEW, "%s EMC6D103 id: %x %x\n", __func__, smbus_read_byte(dev, 0x3e), smbus_read_byte(dev, 0x3f)); + + for (i = 0; i < ARRAY_SIZE(script); i++) { + reg = smbus_read_byte(dev, script[i].idx); + if (reg < 0) + goto fail; + reg &= script[i].msk; + reg |= script[i].set; + reg = smbus_write_byte(dev, script[i].idx, reg & 0xff); + if (reg < 0) + goto fail; + } + + return; + +fail: + printk(BIOS_WARNING, "failed to initialize EMC6D103\n"); +} + +/* set up DME1737 runtime registers for FAN/PWM 5/6 */ +static void dme1737_runtime_init(void) +{ + size_t i; + uint8_t reg; + + static const struct { uint8_t idx; uint8_t msk; uint8_t set; } rttab[] = { + { 0x43, 0xf3, 0x08 }, + { 0x44, 0xf0, 0x08 }, + { 0x45, 0xf3, 0x08 }, + { 0x46, 0xf0, 0x08 }, + }; + + /* find DME1737 runtime device (LDN 10) */ + struct device * const dev = dev_find_slot_pnp(0x2e, DME1737_RT); + if (dev == NULL) + return; + + struct resource * const res = find_resource(dev, PNP_IDX_IO0); + if (res == NULL) + return; + + for (i = 0; i < ARRAY_SIZE(rttab); i++) { + reg = inb(res->base + rttab[i].idx); + reg &= rttab[i].msk; + reg |= rttab[i].set; + outb(reg, res->base + rttab[i].idx); + } +} + +static void dme1737_hwm_init(void) +{ + size_t i; + int reg; + + static const struct { uint8_t idx; uint8_t msk; uint8_t set; } script[] = { + //{ 0x7f, 0x7f, 0x80 }, // INIT + { 0x4f, 0x00, 0x32 }, // High + { 0x54, 0x00, 0x30 }, // Tach0 Minimum LSB + { 0x55, 0x00, 0x2a }, // Tach0 Minimum MSB + { 0x56, 0x00, 0x30 }, // Tach1 Minimum LSB + { 0x57, 0x00, 0x2a }, // Tach1 Minimum MSB + { 0x5a, 0x00, 0x30 }, // Tach3 Minimum LSB + { 0x5b, 0x00, 0x2a }, // Tach3 Minimum MSB + { 0x5d, 0x00, 0x07 }, // PWM 1 Config: Zone 0 + { 0x5f, 0x0f, 0x50 }, // Zone 0 range, PWM freq + { 0x62, 0x00, 0x67 }, // Ramp Rate + { 0x63, 0x00, 0x80 }, // Ramp Rate + { 0x65, 0x00, 0x0d }, // PWM 1 Minimum + { 0x67, 0x00, 0x23 }, // Zone 0 Low + { 0x6a, 0x00, 0x32 }, // Zone 0 High + { 0x6c, 0x00, 0x5a }, // Zone 2 Abs + { 0x80, 0x00, 0x17 }, // Interrupt Enable 2? + { 0xa5, 0x00, 0x40 }, // PMW 4: 25% duty + { 0xa6, 0x00, 0x40 }, // PWM 5: 25% duty + { 0x40, 0xfe, 0x01 }, // START + }; + + struct device * const dev = dev_find_slot_on_smbus(2, 0x2e); + if (dev == NULL) { + printk(BIOS_INFO, "SMBus DME1737 not found\n"); + return; + } + + printk(BIOS_SPEW, "%s DME1737 id: %x %x\n", __func__, smbus_read_byte(dev, 0x3e), smbus_read_byte(dev, 0x3f)); + + for (i = 0; i < ARRAY_SIZE(script); i++) { + reg = smbus_read_byte(dev, script[i].idx); + if (reg < 0) + goto fail; + reg &= script[i].msk; + reg |= script[i].set; + reg = smbus_write_byte(dev, script[i].idx, reg & 0xff); + if (reg < 0) + goto fail; + } + + return; + +fail: + printk(BIOS_WARNING, "failed to initialize EMC6D103\n"); +} + +static void mainboard_init(device_t dev) +{ + emc6d103_init(); + dme1737_runtime_init(); + dme1737_hwm_init(); + + printk(BIOS_DEBUG, "%s done\n", __func__); +} static void mainboard_enable(device_t dev) { + dev->ops->init = mainboard_init; } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: Initial Sun Ultra 40 M2 board port
by Jonathan A. Kollasch 06 Nov '15

06 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12304 -gerrit commit 6e02035e5da4ef9a662a66f0430338804e2bc3d0 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 3 10:06:38 2015 -0600 Initial Sun Ultra 40 M2 board port Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/sunw/ultra40m2/Kconfig | 10 ++- src/mainboard/sunw/ultra40m2/board_info.txt | 7 +- src/mainboard/sunw/ultra40m2/cmos.layout | 2 +- src/mainboard/sunw/ultra40m2/devicetree.cb | 109 ++++++++++------------------ src/mainboard/sunw/ultra40m2/hda_verb.c | 26 +++---- src/mainboard/sunw/ultra40m2/mptable.c | 2 +- src/mainboard/sunw/ultra40m2/resourcemap.c | 4 +- src/mainboard/sunw/ultra40m2/romstage.c | 24 +++--- 8 files changed, 78 insertions(+), 106 deletions(-) diff --git a/src/mainboard/sunw/ultra40m2/Kconfig b/src/mainboard/sunw/ultra40m2/Kconfig index 5b19c13..2913ae8 100644 --- a/src/mainboard/sunw/ultra40m2/Kconfig +++ b/src/mainboard/sunw/ultra40m2/Kconfig @@ -10,13 +10,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA - select SUPERIO_WINBOND_W83627EHG + select SUPERIO_SMSC_DME1737 select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_512 + select BOARD_ROMSIZE_KB_1024 select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE @@ -70,6 +70,10 @@ config IRQ_SLOT_COUNT config MCP55_PCI_E_X_0 int - default 2 + default 1 + +config MCP55_PCI_E_X_1 + int + default 1 endif # BOARD_SUNW_ULTRA40M2 diff --git a/src/mainboard/sunw/ultra40m2/board_info.txt b/src/mainboard/sunw/ultra40m2/board_info.txt index b351b8e..b68555c 100644 --- a/src/mainboard/sunw/ultra40m2/board_info.txt +++ b/src/mainboard/sunw/ultra40m2/board_info.txt @@ -1 +1,6 @@ -Category: eval +Board URL: http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html +Board name: Ultra 40 M2 +Category: desktop +ROM package: PLCC +ROM protocol: LPC +ROM socketed: y diff --git a/src/mainboard/sunw/ultra40m2/cmos.layout b/src/mainboard/sunw/ultra40m2/cmos.layout index 53f259a..3dfdf35 100644 --- a/src/mainboard/sunw/ultra40m2/cmos.layout +++ b/src/mainboard/sunw/ultra40m2/cmos.layout @@ -25,7 +25,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +408 1 e 1 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb index 5709db7..9928d45 100644 --- a/src/mainboard/sunw/ultra40m2/devicetree.cb +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -5,66 +5,45 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x1022 0x2b80 inherit + subsystemid 0x108e 0x6676 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O + chip superio/smsc/dme1737 # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.3 off # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 2 end - device pnp 2e.2 on # Com1 + device pnp 2e.4 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.5 off # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.7 on # PS/2 (connectors not populated) io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 + device pnp 2e.a on # Runtime Registers + io 0x60 = 0x600 end end + # There's an Infineon SLB9635TT12 TPM on this LPC bus. + # There's also an Akom AK2001 7-segment port 0x80 decoder on + # this LPC bus. end device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0 @@ -93,41 +72,36 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end + #chip drivers/generic/generic # PCA9556 GPIO on HDD backplanes (address conflict!) + # device i2c 18 on end + #end + #chip drivers/generic/generic # EMC6D103 HWM (for CPUs) + # device i2c 2d on end + #end + #chip drivers/generic/generic # DME1737 HWM + # device i2c 2e on end + #end + #chip drivers/generic/generic # HDD 4-7 backplane FRU 24C64 EEPROM + # device i2c 51 on end + #end + #chip drivers/generic/generic # front panel module FRU 24C64 EEPROM + # device i2c 52 on end + #end + #chip drivers/generic/generic # HDD 0-3 backplane FRU 24C64 EEPROM + # device i2c 53 on end + #end + # there are more SMbus devices on this bus end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 + device pci 5.2 off end # SATA 2 device pci 6.0 on end # PCI device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC + device pci 8.0 off end # NIC + device pci 9.0 off end # NIC device pci a.0 on end # PCI E 5 device pci b.0 off end # PCI E 4 device pci c.0 off end # PCI E 3 @@ -137,12 +111,8 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT @@ -153,7 +123,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 4.0 off end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 + device pci 5.2 off end # SATA 2 device pci 6.0 off end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC @@ -162,14 +132,11 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci b.0 off end # PCI E 4 device pci c.0 off end # PCI E 3 device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 + device pci e.0 off end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end device pci 18.1 on end diff --git a/src/mainboard/sunw/ultra40m2/hda_verb.c b/src/mainboard/sunw/ultra40m2/hda_verb.c index 31052f2..137196c 100644 --- a/src/mainboard/sunw/ultra40m2/hda_verb.c +++ b/src/mainboard/sunw/ultra40m2/hda_verb.c @@ -19,18 +19,18 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 + 0x10ec0885, // Codec Vendor / Device ID: Realtek ALC889A 0x00000000, // Subsystem ID 0x0000000d, // Number of jacks - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ - AZALIA_SUBVENDOR(0x0, 0x0000e601), + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x108ee601 */ + AZALIA_SUBVENDOR(0x0, 0x108ee601), /* NID 0x14, FRONT-OUT-L/R */ - AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), /* NID 0x15, SURR-OUT-L/R */ - AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), + AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), /* NID 0x16, CEN/LFE-OUT */ AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), @@ -39,28 +39,28 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x17, 0x01012014), /* NID 0x18, MIC1-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840), /* NID 0x19, MIC2-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c40), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19850), /* NID 0x1a, LINE1-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x01813431), + AZALIA_PIN_CFG(0x0, 0x1a, 0x01813041), /* NID 0x1b, LINE2-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x1b, 0x0221441f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214020), /* NID 0x1c, CD-L/R / GND */ - AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1c, 0x9933014f), /* NID 0x1d, PCBEEP */ - AZALIA_PIN_CFG(0x0, 0x1d, 0x9983013e), + AZALIA_PIN_CFG(0x0, 0x1d, 0x99830142), /* NID 0x1e, S/PDIF-OUT */ - AZALIA_PIN_CFG(0x0, 0x1e, 0x01454120), + AZALIA_PIN_CFG(0x0, 0x1e, 0x014b4130), /* NID 0x1f, S/PDIF-IN */ - AZALIA_PIN_CFG(0x0, 0x1f, 0x01c59150), + AZALIA_PIN_CFG(0x0, 0x1f, 0x01cb9160), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/sunw/ultra40m2/mptable.c b/src/mainboard/sunw/ultra40m2/mptable.c index d000b1a..89bb9eb 100644 --- a/src/mainboard/sunw/ultra40m2/mptable.c +++ b/src/mainboard/sunw/ultra40m2/mptable.c @@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); if (dev && dev->enabled) { for (i = 0; i < 4; i++) - apicpin[i] = 0x10 + (2+i)%4; + apicpin[i] = 0x10 + i%4; smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); } } diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c index 2950687..5235b0d 100644 --- a/src/mainboard/sunw/ultra40m2/resourcemap.c +++ b/src/mainboard/sunw/ultra40m2/resourcemap.c @@ -194,7 +194,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007010, // PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -265,7 +265,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of cpu 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 4186cc7..1006f19 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -32,14 +32,13 @@ #include "lib/delay.c" #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <superio/smsc/dme1737/dme1737.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -57,13 +56,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" +#define NMI_SC 0x0061 +#define PCI_SERR_EN 0x04 + #define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0x00, 0x05,/* GPIO62: enable/not-disable on-board TSB43AB22A Firewire */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" @@ -114,13 +111,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); - setup_mb_resource_map(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + dme1737_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ @@ -169,6 +162,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); + /* mask NMI from constantly-asserted-on-this-board SERR# */ + outb((inb(NMI_SC) & 0x0f) | PCI_SERR_EN, NMI_SC); + // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { printk(BIOS_INFO, "ht reset -\n");

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015