coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: asus/k8v-x: Add more subsystem IDs to device tree
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12351 -gerrit commit 427e3bd6a8327f6593fdc95d22f4fb34038470f9 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:36:31 2015 +0200 asus/k8v-x: Add more subsystem IDs to device tree This is an attempt at better compatibility with driver matching etc. Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/devicetree.cb | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 4be4d78..7764413 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x1043 0 inherit + subsystemid 0x1043 0x80ed inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge # Devices on link 0, link 0 == LDT 0 @@ -33,8 +33,18 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "enable_aol_2_smb_slave" = "1" register "enable_gpo5" = "1" register "gpio15_12_dir_output" = "1" - device pci 0.0 on end # HT + device pci 0.0 on # HT + subsystemid 0x1043 0x80a3 + end + device pci a.0 on # GbE + subsystemid 0x1043 0x811a + end + device pci f.0 on end # SATA device pci f.1 on end # IDE + device pci 10.0 on end # USB1 + device pci 10.1 on end # USB1 + device pci 10.2 on end # USB1 + device pci 10.3 on end # USB1 device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 @@ -86,6 +96,10 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end end + device pci 11.5 on # AC97 Audio + subsystemid 0x1043 0x80b0 + end + device pci 11.6 on end # AC97 Modem device pci 12.0 off end # VIA LAN (off, other chip used) end chip southbridge/via/k8t890 # "Southbridge" K8T890

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Patch set updated for coreboot: asus/k8v-x: Add PIRQ tables to init PCI IRQ config
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12350 -gerrit commit c68864f840e26bd11d2932a5cdfdd370710cba9c Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:43:52 2015 +0200 asus/k8v-x: Add PIRQ tables to init PCI IRQ config Pulled getpir from the attic and used data provided by it to create the table a bit more programmatically and added the AGP slot so the video card is given an IRQ Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/Kconfig | 6 ++ src/mainboard/asus/k8v-x/irq_tables.c | 146 ++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 52bf661..4eb1bec 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -9,12 +9,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select SET_FIDVID select K8_FORCE_2T_DRAM_TIMING + select PIRQ_ROUTE config MAINBOARD_DIR string @@ -60,4 +62,8 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 +config IRQ_SLOT_COUNT + int + default 11 + endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/irq_tables.c b/src/mainboard/asus/k8v-x/irq_tables.c new file mode 100644 index 0000000..51b7dd1 --- /dev/null +++ b/src/mainboard/asus/k8v-x/irq_tables.c @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Urja Rannikko <urjaman(a)gmail.com> + * + * Code based on KFSN4-DRE irq_tables.c: + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint8_t link1, uint8_t link2, + uint8_t link3, uint8_t slot, uint8_t rfu) +{ + const uint16_t valid_irqs = 0xccb8; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = link0 ? valid_irqs : 0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = link1 ? valid_irqs : 0; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = link2 ? valid_irqs : 0; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = link3 ? valid_irqs : 0; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + uint8_t *v, sum = 0; + unsigned int slot_num = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr = ALIGN_UP(addr, 16); + + /* This table must be between 0xf0000 & 0x100000. */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + pirq->rtr_bus = 0; + pirq->rtr_devfn = ((0x11) << 3) | 0; + pirq->exclusive_irqs = 0; + pirq->rtr_vendor = PCI_VENDOR_ID_VIA; + pirq->rtr_device = PCI_DEVICE_ID_VIA_VT8237R_LPC; + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + + /* AGP Bridge. */ + write_pirq_info(pirq_info, 0, (0x01 << 3) | 0, 1, 2, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* ISA Bridge + AC97 + MC97 */ + write_pirq_info(pirq_info, 0, (0x11 << 3) | 0, 0, 0, 3, 0, 0, 0); + pirq_info++; + slot_num++; + + /* PATA and SATA. */ + write_pirq_info(pirq_info, 0, (0x0f << 3) | 0, 1, 2, 3, 5, 0, 0); + pirq_info++; + slot_num++; + + /* USB (UHCI and EHCI) */ + write_pirq_info(pirq_info, 0, (0x10 << 3) | 0, 1, 2, 3, 5, 0, 0); + pirq_info++; + slot_num++; + + /* 5 PCI Slots */ + write_pirq_info(pirq_info, 0, (0x0b << 3) | 0, 1, 2, 3, 5, 1, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0c << 3) | 0, 2, 3, 5, 1, 2, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0d << 3) | 0, 3, 5, 1, 2, 3, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0e << 3) | 0, 5, 1, 2, 3, 4, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x09 << 3) | 0, 1, 2, 3, 5, 5, 0); + pirq_info++; + slot_num++; + + /* Ethernet */ + write_pirq_info(pirq_info, 0, (0x0a << 3) | 0, 2, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* AGP Slot. */ + write_pirq_info(pirq_info, 1, (0x00 << 3) | 0, 1, 2, 0, 0, 6, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "done.\n"); + + /* Call copy for side effects: setting PCI IRQ registers. Hack? */ + return copy_pirq_routing_table(addr, pirq); +}

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Patch set updated for coreboot: asus/k8v-x: set superio ROM ctrl reg to enable writes
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12349 -gerrit commit 5721cb36ea28cb110813f4d3d1c374790760a7b9 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Fri Nov 6 16:18:27 2015 +0200 asus/k8v-x: set superio ROM ctrl reg to enable writes This is required for flashrom to work... Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 6bb9bc8..4be4d78 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -82,6 +82,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 irq 0x70 = 0 + irq 0x24 = 0x28 # Global CR24 change bit3: MEMW# Enable end end end

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Patch merged into coreboot/master: amd/00660F01: Fix MMCONF resource
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit 625b944e7584f4b559e2376dce0c35d54fb68aec Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 27 07:58:22 2015 +0300 amd/00660F01: Fix MMCONF resource Fixed resources have to be declared early. Change-Id: I03bb846e0685d47e0befc20bf7bc14c06694cb66 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12262 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/12262 for details. -gerrit

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Patch set updated for coreboot: asus/k8v-x: Add more subsystem IDs to device tree
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12351 -gerrit commit e74d859432ba3bb0bb0fccaf4742bb77d2fd70b7 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:36:31 2015 +0200 asus/k8v-x: Add more subsystem IDs to device tree This is an attempt at better compatibility with driver matching etc. Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/devicetree.cb | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 2ccc8dd..b38edde 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x1043 0 inherit + subsystemid 0x1043 0x80ed inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge # Devices on link 0, link 0 == LDT 0 @@ -33,8 +33,18 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "enable_aol_2_smb_slave" = "1" register "enable_gpo5" = "1" register "gpio15_12_dir_output" = "1" - device pci 0.0 on end # HT + device pci 0.0 on # HT + subsystemid 0x1043 0x80a3 + end + device pci a.0 on # GbE + subsystemid 0x1043 0x811a + end + device pci f.0 on end # SATA device pci f.1 on end # IDE + device pci 10.0 on end # USB1 + device pci 10.1 on end # USB1 + device pci 10.2 on end # USB1 + device pci 10.3 on end # USB1 device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 @@ -86,6 +96,10 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end end + device pci 11.5 on # AC97 Audio + subsystemid 0x1043 0x80b0 + end + device pci 11.6 on end # AC97 Modem device pci 12.0 off end # VIA LAN (off, other chip used) end chip southbridge/via/k8t890 # "Southbridge" K8T890

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Patch set updated for coreboot: asus/k8v-x: Add PIRQ tables to init PCI IRQ config
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12350 -gerrit commit 5509d3bb2639f8146a1bb9d2a81caab719c959a3 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:43:52 2015 +0200 asus/k8v-x: Add PIRQ tables to init PCI IRQ config Pulled getpir from the attic and used data provided by it to create the table a bit more programmatically and added the AGP slot so the video card is given an IRQ Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/Kconfig | 6 ++ src/mainboard/asus/k8v-x/irq_tables.c | 146 ++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 52bf661..4eb1bec 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -9,12 +9,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select SET_FIDVID select K8_FORCE_2T_DRAM_TIMING + select PIRQ_ROUTE config MAINBOARD_DIR string @@ -60,4 +62,8 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 +config IRQ_SLOT_COUNT + int + default 11 + endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/irq_tables.c b/src/mainboard/asus/k8v-x/irq_tables.c new file mode 100644 index 0000000..51b7dd1 --- /dev/null +++ b/src/mainboard/asus/k8v-x/irq_tables.c @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Urja Rannikko <urjaman(a)gmail.com> + * + * Code based on KFSN4-DRE irq_tables.c: + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint8_t link1, uint8_t link2, + uint8_t link3, uint8_t slot, uint8_t rfu) +{ + const uint16_t valid_irqs = 0xccb8; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = link0 ? valid_irqs : 0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = link1 ? valid_irqs : 0; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = link2 ? valid_irqs : 0; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = link3 ? valid_irqs : 0; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + uint8_t *v, sum = 0; + unsigned int slot_num = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr = ALIGN_UP(addr, 16); + + /* This table must be between 0xf0000 & 0x100000. */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + pirq->rtr_bus = 0; + pirq->rtr_devfn = ((0x11) << 3) | 0; + pirq->exclusive_irqs = 0; + pirq->rtr_vendor = PCI_VENDOR_ID_VIA; + pirq->rtr_device = PCI_DEVICE_ID_VIA_VT8237R_LPC; + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + + /* AGP Bridge. */ + write_pirq_info(pirq_info, 0, (0x01 << 3) | 0, 1, 2, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* ISA Bridge + AC97 + MC97 */ + write_pirq_info(pirq_info, 0, (0x11 << 3) | 0, 0, 0, 3, 0, 0, 0); + pirq_info++; + slot_num++; + + /* PATA and SATA. */ + write_pirq_info(pirq_info, 0, (0x0f << 3) | 0, 1, 2, 3, 5, 0, 0); + pirq_info++; + slot_num++; + + /* USB (UHCI and EHCI) */ + write_pirq_info(pirq_info, 0, (0x10 << 3) | 0, 1, 2, 3, 5, 0, 0); + pirq_info++; + slot_num++; + + /* 5 PCI Slots */ + write_pirq_info(pirq_info, 0, (0x0b << 3) | 0, 1, 2, 3, 5, 1, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0c << 3) | 0, 2, 3, 5, 1, 2, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0d << 3) | 0, 3, 5, 1, 2, 3, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0e << 3) | 0, 5, 1, 2, 3, 4, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x09 << 3) | 0, 1, 2, 3, 5, 5, 0); + pirq_info++; + slot_num++; + + /* Ethernet */ + write_pirq_info(pirq_info, 0, (0x0a << 3) | 0, 2, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* AGP Slot. */ + write_pirq_info(pirq_info, 1, (0x00 << 3) | 0, 1, 2, 0, 0, 6, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "done.\n"); + + /* Call copy for side effects: setting PCI IRQ registers. Hack? */ + return copy_pirq_routing_table(addr, pirq); +}

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Patch set updated for coreboot: asus/k8v-x: set superio ROM size control reg to 4Mbit
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12349 -gerrit commit 812b6fe2e81da2158a77ede6a0e504b0dc09ae39 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Fri Nov 6 16:18:27 2015 +0200 asus/k8v-x: set superio ROM size control reg to 4Mbit This is required for flashrom to work (writes), but not for booting (apparently). Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 6bb9bc8..2ccc8dd 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -82,6 +82,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 irq 0x70 = 0 + irq 0x24 = 0x28 # Global CR24 Flash ROM size = 4Mbit (needed for writes) end end end

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New patch to review for coreboot: asus/k8v-x: Add more subsystem IDs to device tree
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12351 -gerrit commit 03fb6c7e7ad1f9a9ca34d0a99866d4c8cd4b9169 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:36:31 2015 +0200 asus/k8v-x: Add more subsystem IDs to device tree This is an attempt at better compatibility with driver matching etc. Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/devicetree.cb | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 2ccc8dd..b38edde 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x1043 0 inherit + subsystemid 0x1043 0x80ed inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge # Devices on link 0, link 0 == LDT 0 @@ -33,8 +33,18 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "enable_aol_2_smb_slave" = "1" register "enable_gpo5" = "1" register "gpio15_12_dir_output" = "1" - device pci 0.0 on end # HT + device pci 0.0 on # HT + subsystemid 0x1043 0x80a3 + end + device pci a.0 on # GbE + subsystemid 0x1043 0x811a + end + device pci f.0 on end # SATA device pci f.1 on end # IDE + device pci 10.0 on end # USB1 + device pci 10.1 on end # USB1 + device pci 10.2 on end # USB1 + device pci 10.3 on end # USB1 device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 @@ -86,6 +96,10 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end end + device pci 11.5 on # AC97 Audio + subsystemid 0x1043 0x80b0 + end + device pci 11.6 on end # AC97 Modem device pci 12.0 off end # VIA LAN (off, other chip used) end chip southbridge/via/k8t890 # "Southbridge" K8T890

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New patch to review for coreboot: asus/k8v-x: Add PIRQ tables to init PCI IRQ config
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12350 -gerrit commit b144a99c115a3ffe037275d0928d8a12858b63d0 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:43:52 2015 +0200 asus/k8v-x: Add PIRQ tables to init PCI IRQ config Pulled getpir from the attic and used data provided by it to create the table a bit more programmatically and added the AGP slot so the video card is given an IRQ Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/Kconfig | 6 ++ src/mainboard/asus/k8v-x/irq_tables.c | 146 ++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 52bf661..4eb1bec 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -9,12 +9,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select SET_FIDVID select K8_FORCE_2T_DRAM_TIMING + select PIRQ_ROUTE config MAINBOARD_DIR string @@ -60,4 +62,8 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 +config IRQ_SLOT_COUNT + int + default 11 + endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/irq_tables.c b/src/mainboard/asus/k8v-x/irq_tables.c new file mode 100644 index 0000000..51b7dd1 --- /dev/null +++ b/src/mainboard/asus/k8v-x/irq_tables.c @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Urja Rannikko <urjaman(a)gmail.com> + * + * Code based on KFSN4-DRE irq_tables.c: + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint8_t link1, uint8_t link2, + uint8_t link3, uint8_t slot, uint8_t rfu) +{ + const uint16_t valid_irqs = 0xccb8; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = link0 ? valid_irqs : 0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = link1 ? valid_irqs : 0; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = link2 ? valid_irqs : 0; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = link3 ? valid_irqs : 0; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + uint8_t *v, sum = 0; + unsigned int slot_num = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr = ALIGN_UP(addr, 16); + + /* This table must be between 0xf0000 & 0x100000. */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + pirq->rtr_bus = 0; + pirq->rtr_devfn = ((0x11) << 3) | 0; + pirq->exclusive_irqs = 0; + pirq->rtr_vendor = PCI_VENDOR_ID_VIA; + pirq->rtr_device = PCI_DEVICE_ID_VIA_VT8237R_LPC; + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + + /* AGP Bridge. */ + write_pirq_info(pirq_info, 0, (0x01 << 3) | 0, 1, 2, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* ISA Bridge + AC97 + MC97 */ + write_pirq_info(pirq_info, 0, (0x11 << 3) | 0, 0, 0, 3, 0, 0, 0); + pirq_info++; + slot_num++; + + /* PATA and SATA. */ + write_pirq_info(pirq_info, 0, (0x0f << 3) | 0, 1, 2, 3, 5, 0, 0); + pirq_info++; + slot_num++; + + /* USB (UHCI and EHCI) */ + write_pirq_info(pirq_info, 0, (0x10 << 3) | 0, 1, 2, 3, 5, 0, 0); + pirq_info++; + slot_num++; + + /* 5 PCI Slots */ + write_pirq_info(pirq_info, 0, (0x0b << 3) | 0, 1, 2, 3, 5, 1, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0c << 3) | 0, 2, 3, 5, 1, 2, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0d << 3) | 0, 3, 5, 1, 2, 3, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x0e << 3) | 0, 5, 1, 2, 3, 4, 0); + pirq_info++; + slot_num++; + + write_pirq_info(pirq_info, 0, (0x09 << 3) | 0, 1, 2, 3, 5, 5, 0); + pirq_info++; + slot_num++; + + /* Ethernet */ + write_pirq_info(pirq_info, 0, (0x0a << 3) | 0, 2, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* AGP Slot. */ + write_pirq_info(pirq_info, 1, (0x00 << 3) | 0, 1, 2, 0, 0, 6, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "done.\n"); + + /* Call copy for side effects: setting PCI IRQ registers. Hack? */ + return copy_pirq_routing_table(addr, pirq); +}

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New patch to review for coreboot: asus/k8v-x: change global superio register to support flash writes
by Urja Rannikko 06 Nov '15

06 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12349 -gerrit commit b8fa0d9d78a7d2dab07b73563f861a9ac1c43c5a Author: Urja Rannikko <urjaman(a)gmail.com> Date: Fri Nov 6 16:18:27 2015 +0200 asus/k8v-x: change global superio register to support flash writes Sets 4Mbit ROM size. Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/mainboard/asus/k8v-x/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 6bb9bc8..2ccc8dd 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -82,6 +82,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 irq 0x70 = 0 + irq 0x24 = 0x28 # Global CR24 Flash ROM size = 4Mbit (needed for writes) end end end

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coreboot-gerrit November 2015