coreboot-gerrit November 2015

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Patch merged into coreboot/master: amd/00730F01: Add missing headerfile
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit a62191b827411e0e42ac64cf42a861f649b874f9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 27 07:58:22 2015 +0300 amd/00730F01: Add missing headerfile Change-Id: Id69b339bbed03d7a1f64aa5935721e7e8aab62fa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12265 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/12265 for details. -gerrit

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Patch merged into coreboot/master: amd binaryPI: Fix usbdebug
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit 55ed6728b17669bdd7abe747327e58a2864a88e1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 8 16:39:52 2015 +0300 amd binaryPI: Fix usbdebug EHCI functions have moved. Change-Id: I47e79d3790b272b0fc322d534de733889679622b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12264 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/12264 for details. -gerrit

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Patch merged into coreboot/master: amd/00730F01: Add correct CPU model
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit ed98e945c0c6938a26bff6d5b38932b2851d348a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 27 07:58:22 2015 +0300 amd/00730F01: Add correct CPU model Change-Id: I887f9eb890f1f1c6f88b7984f0520bd17be8b88b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12284 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12284 for details. -gerrit

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Patch merged into coreboot/master: AMD binaryPI: Fix include paths
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit 740edf4f958873ec8ff648ca5bd9e23d94903337 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 31 18:31:36 2015 +0200 AMD binaryPI: Fix include paths Do not mix open-source AGESA and binaryPI includes. Change-Id: I1e43334ba8d5a17d3580f81e023ca2c8caf86f7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12283 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/12283 for details. -gerrit

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Patch merged into coreboot/master: AMD binaryPI BiosCallouts: Remove cast
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit a58c0b02ba97a770076b261914dbbd497766ce5d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 30 23:38:40 2015 +0200 AMD binaryPI BiosCallouts: Remove cast This cast only hides errors in matching the API properly. Change-Id: I9b878ab997b8ff087a7209f94522646b10b94bf6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12271 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12271 for details. -gerrit

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Patch merged into coreboot/master: AGESA BiosCallouts: Remove cast
by gerrit＠coreboot.org 06 Nov '15

06 Nov '15

the following patch was just integrated into master: commit 82860f854901d79f1392226364345fdc3fd0c03d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 30 23:38:40 2015 +0200 AGESA BiosCallouts: Remove cast This cast only hides errors in matching the API properly. Change-Id: Ic396dfb572a50ac5ce5c1c83424e1f17f15bad1d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12270 for details. -gerrit

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New patch to review for coreboot: pcengines/apu1: enable use of clkreq pins
by Felix Held 06 Nov '15

06 Nov '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12353 -gerrit commit 488ce6d347c78e42ab0c7a7d5dd20efafb47a29e Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Fri Nov 6 18:32:43 2015 +0100 pcengines/apu1: enable use of clkreq pins only enable pcie gpp clocks when the corresponding clkreq pin is asserted Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/mainboard/pcengines/apu1/mainboard.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 82cf992..f91e879 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -187,10 +187,10 @@ static void mainboard_enable(device_t dev) u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); /* GPP CLK0-2 are connected to the 3 ethernet chips * GPP CLK3-4 are connected to the miniPCIe slots */ - write8(misc_mem_clk_cntrl + 0, 0xFF); - write8(misc_mem_clk_cntrl + 1, 0xFF); + write8(misc_mem_clk_cntrl + 0, 0x21); + write8(misc_mem_clk_cntrl + 1, 0x43); /* GPP CLK5 is only connected to test pads -> disable */ - write8(misc_mem_clk_cntrl + 2, 0x0F); + write8(misc_mem_clk_cntrl + 2, 0x05); /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ write8(misc_mem_clk_cntrl + 3, 0x00); write8(misc_mem_clk_cntrl + 4, 0x00);

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Patch set updated for coreboot: pcengines/apu1: disable unused clock outputs
by Felix Held 06 Nov '15

06 Nov '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12082 -gerrit commit 9d473fab9967f4d95bcabd612349513b9988207a Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Fri Nov 6 18:31:01 2015 +0100 pcengines/apu1: disable unused clock outputs disable unconnected FCH clock outputs to save some power Change-Id: Ib3efebb8656392d58d762c23827168017d273de8 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/mainboard/pcengines/apu1/mainboard.c | 12 ++++++++++++ src/mainboard/pcengines/apu1/platform_cfg.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index f80f24e..82cf992 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -183,6 +183,18 @@ static void mainboard_enable(device_t dev) config_gpio_mux(); + /* Power off unused clock pins of GPP PCIe devices */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + /* GPP CLK0-2 are connected to the 3 ethernet chips + * GPP CLK3-4 are connected to the miniPCIe slots */ + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0xFF); + /* GPP CLK5 is only connected to test pads -> disable */ + write8(misc_mem_clk_cntrl + 2, 0x0F); + /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 946f238..7172e82 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -69,12 +69,12 @@ * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 + * PCI SLOT 1 define at BIT1 -> connected to LPC devices * PCI SLOT 2 define at BIT2 * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x1F +#define PCI_CLOCK_CTRL 0x02 /** * @def SATA_CONTROLLER

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New patch to review for coreboot: AMD/hudson: Add tail size of each CBFS modules
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12352 -gerrit commit 783ca4fea252eef98dfb08f2ceb96ec8b71fbabf Author: zbao <fishbaozi(a)gmail.com> Date: Sat Nov 7 01:09:05 2015 +0800 AMD/hudson: Add tail size of each CBFS modules When we calculate the offset of each module, we need to add the tail size of last one. Change-Id: I2ec01ffd36b2708b72968b7742849da83339c3a6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..37046be 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -67,6 +67,7 @@ HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) CBFS_HEADER_SIZE=0x60 +CBFS_TAIL_SIZE=0x40 #assume the cbfs header is less than $(CBFS_HEADER_SIZE) bytes. ROMSIG_SIZE=4096 @@ -205,7 +206,7 @@ endif #5 CONFIG_PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key PUBSIGNEDKEY_POS=$(call int-align, \ - $(call int-add,$(AMDPUBKEY_POS) $(AMDPUBKEY_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(AMDPUBKEY_POS) $(AMDPUBKEY_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) PUBSIGNEDKEY_SIZE=$(call file-size,$(CONFIG_PUBSIGNEDKEY_FILE)) @@ -216,7 +217,7 @@ else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin endif PSPBTLDR_POS=$(call int-align, \ - $(call int-add,$(PUBSIGNEDKEY_POS) $(PUBSIGNEDKEY_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(PUBSIGNEDKEY_POS) $(PUBSIGNEDKEY_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPBTLDR_SIZE=$(call file-size,$(CONFIG_PSPBTLDR_FILE)) @@ -227,7 +228,7 @@ else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin endif PSPRCVR_POS=$(call int-align, \ - $(call int-add,$(PSPBTLDR_POS) $(PSPBTLDR_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(PSPBTLDR_POS) $(PSPBTLDR_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPRCVR_SIZE=$(call file-size,$(CONFIG_PSPRCVR_FILE)) @@ -238,35 +239,35 @@ else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin endif PSPSECUREOS_POS=$(call int-align, \ - $(call int-add,$(PSPRCVR_POS) $(PSPRCVR_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(PSPRCVR_POS) $(PSPRCVR_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPSECUREOS_SIZE=$(call file-size,$(CONFIG_PSPSCUREOS_FILE)) #4 CONFIG_PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin PSPNVRAM_POS=$(call int-align, \ - $(call int-add,$(PSPSECUREOS_POS) $(PSPSECUREOS_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(PSPSECUREOS_POS) $(PSPSECUREOS_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPNVRAM_SIZE=$(call file-size,$(CONFIG_PSPNVRAM_FILE)) #8 CONFIG_SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_POS=$(call int-align, \ - $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) #95 CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin SMUSCS_POS=$(call int-align, \ - $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) #9 CONFIG_PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key PSPSECUREDEBUG_POS=$(call int-align, \ - $(call int-add,$(SMUSCS_POS) $(SMUSCS_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(SMUSCS_POS) $(SMUSCS_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPSECUREDEBUG_SIZE=$(call file-size,$(CONFIG_PSPSECUREDEBUG_FILE)) @@ -277,7 +278,7 @@ else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin endif PSPTRUSTLETS_POS=$(call int-align, \ - $(call int-add,$(PSPSECUREDEBUG_POS) $(PSPSECUREDEBUG_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(PSPSECUREDEBUG_POS) $(PSPSECUREDEBUG_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPTRUSTLETS_SIZE=$(call file-size,$(CONFIG_PSPTRUSTLETS_FILE)) @@ -288,7 +289,7 @@ else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin endif TRUSTLETKEY_POS=$(call int-align, \ - $(call int-add,$(PSPTRUSTLETS_POS) $(PSPTRUSTLETS_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(PSPTRUSTLETS_POS) $(PSPTRUSTLETS_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) TRUSTLETKEY_SIZE=$(call file-size,$(CONFIG_TRUSTLETKEY_FILE)) @@ -296,7 +297,7 @@ TRUSTLETKEY_SIZE=$(call file-size,$(CONFIG_TRUSTLETKEY_FILE)) ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin SMUFIRMWARE2_POS=$(call int-align, \ - $(call int-add,$(TRUSTLETKEY_POS) $(TRUSTLETKEY_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(TRUSTLETKEY_POS) $(TRUSTLETKEY_SIZE) $(CBFS_HEADER_SIZE) $(CBFS_TAIL_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUFIRMWARE2_SIZE=$(call file-size,$(CONFIG_SMUFIRMWARE2_FILE)) endif

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Patch set updated for coreboot: AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1
by Zheng Bao 06 Nov '15

06 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11752 -gerrit commit 9a7de74e4a5cab4d6dc64a272620b012d6670fb9 Author: zbao <fishbaozi(a)gmail.com> Date: Sat Nov 7 01:12:20 2015 +0800 AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1 1. This is required the BLOB change Ie86bb0cf AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5) 2. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- .../amd/pi/00660F01/Proc/Fch/Common/FchDef.h | 2 ++ src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h | 18 ++++++++++++++---- .../amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h | 2 ++ 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h index d0063a4..41f103b 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h @@ -340,6 +340,8 @@ VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr); /// VOID FchSpiUnlock (IN VOID *FchDataPtr); VOID FchSpiLock (IN VOID *FchDataPtr); +VOID FchUsb3D3ColdCallback (IN VOID *FchDataPtr); +VOID FchUsb3D0Callback (IN VOID *FchDataPtr); /*--------------------------- Documentation Pages ---------------------------*/ VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h index 7576cad..92201b8 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h @@ -2007,8 +2007,9 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_PMIOxC0_S5ResetStatus 0xFED803C0ul // S5ResetStatus #define FCH_PMIOxC0_S5ResetStatus_ThermalTrip (1 << 0) #define FCH_PMIOxC0_S5ResetStatus_FourSecondPwrBtn (1 << 1) -#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3ff | (1 << 20)) +#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3fe | (1 << 20)) #define FCH_PMIOxC0_S5ResetStatus_All_Status 0x3FFF03FFul +#define FCH_PMIOxC0_S5ResetStatus_Clr_Status 0x3FFF03FEul #define FCH_PMxC8_Misc 0xFED803C8ul // Misc #define FCH_PMxC8_Misc_UseAcpiStraps (1 << 4) @@ -2020,6 +2021,8 @@ FCH_MISC_REGF0 EQU 0F0h // offset : 0x0E00 // #define FCH_MISCx28_ClkDrvStr2 0xFED80E28ul // ClkDrvStr2 +#define FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn (1 << 30) +#define FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn (1 << 31) #define FCH_MISCx40_MiscClkCntl1 0xFED80E40ul // MiscClkCntl1 #define FCH_MISCx40_MiscClkCntl1_CG1PLL_FBDIV_Test (1 << 26) @@ -2038,7 +2041,8 @@ FCH_MISC_REGF0 EQU 0F0h // offset : 0x1C00 // #define FCH_XHC_PMx00_Configure0 0xFED81C00ul // -#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 +#define FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN BIT15 +#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 #define FCH_XHC_PMx10_Xhc_Memory_Configure 0xFED81C10ul // #define FCH_XHC_PMx18_Usb20_Link_Status 0xFED81C18ul // #define FCH_XHC_PMx20_Usb20_Wake_Control 0xFED81C20ul // @@ -2057,9 +2061,12 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_AOACx40_D3_CONTROL 0xFED81E40ul // #define FCH_AOACx41_D3_STATUS 0xFED81E40ul // #define FCH_AOACx5E_SATA_D3_CONTROL 0xFED81E5Eul // +#define FCH_AOACx64_EHCI_D3_CONTROL 0xFED81E64ul // +#define FCH_AOACx65_EHCI_D3_STATE 0xFED81E65ul // #define FCH_AOACx6E_USB3_D3_CONTROL 0xFED81E6Eul // -#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul // -#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul // +#define FCH_AOACx6F_USB3_D3_STATE 0xFED81E6Ful // +#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul // +#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul // #define FCH_AOACx88Shadow_Register_SRAM_Addr 0xFED81E88ul // #define FCH_AOACx8CShadow_Register_SRAM_Data 0xFED81E8Cul // #define FCH_AOACx94S013_CONTROL 0xFED81E94ul // @@ -2070,6 +2077,9 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_AOACx9C_Shadow_Timer_Control_ShadowAcpiTimerEn (1 << 1) // #define FCH_AOACxA0_PwrGood_Control 0xFED81EA0ul // +#define FCH_AOACxA0_PwrGood_Control_XhcPwrGood (1 << 3) // +#define FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown (1 << 29) // +#define FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB (1 << 30) // #define FCH_AOAC_REG00 0x00 // PerfMonControl #define FCH_AOAC_REG04 0x04 // PerfMonTimeLimit diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h index 6108274..6115396 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -63,6 +63,8 @@ #define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr #define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability +#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2 ///< PSP Private Block Base Address (PSP_ADDR) + #define D8F0x44_PmNxtPtrW_MASK 0xff #define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR

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coreboot-gerrit November 2015