coreboot-gerrit November 2015

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Patch set updated for coreboot: arm64: Remove cpu intialization through device-tree
by Julius Werner 07 Nov '15

07 Nov '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11913 -gerrit commit d76c1e2f0e80cc4e6318584e07d8dcdff124ba75 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 15 15:50:30 2015 -0700 arm64: Remove cpu intialization through device-tree Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/arch/arm64/Makefile.inc | 1 - src/arch/arm64/c_entry.c | 75 ++++++++++ src/arch/arm64/cpu_ramstage.c | 204 ---------------------------- src/arch/arm64/include/armv8/arch/cpu.h | 34 +---- src/drivers/gic/gic.c | 1 + src/mainboard/google/rush/devicetree.cb | 1 - src/mainboard/google/rush_ryu/devicetree.cb | 2 - src/mainboard/google/smaug/devicetree.cb | 1 - src/soc/nvidia/tegra132/ramstage.c | 15 ++ src/soc/nvidia/tegra132/soc.c | 56 ++------ src/soc/nvidia/tegra210/ramstage.c | 6 + src/soc/nvidia/tegra210/soc.c | 54 ++------ 12 files changed, 121 insertions(+), 329 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index b4ee3a5..8bcad75 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -131,7 +131,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) ramstage-y += c_entry.c ramstage-y += stages.c ramstage-y += div0.c -ramstage-y += cpu_ramstage.c ramstage-y += eabi_compat.c ramstage-y += boot.c ramstage-y += tables.c diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index deef83d..f26ed92 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -15,8 +15,11 @@ #include <arch/cache.h> #include <arch/cpu.h> +#include <arch/lib_helpers.h> #include <arch/mmu.h> #include <arch/stages.h> +#include <gic.h> + #include "cpu-internal.h" void __attribute__((weak)) arm64_soc_init(void) @@ -42,10 +45,82 @@ static void seed_stack(void) *slot++ = 0xdeadbeefdeadbeefULL; } +/* Set up default SCR values. */ +static void el3_init(void) +{ + uint32_t scr; + + if (get_current_el() != EL3) + return; + + scr = raw_read_scr_el3(); + /* Default to non-secure EL1 and EL0. */ + scr &= ~(SCR_NS_MASK); + scr |= SCR_NS_ENABLE; + /* Disable IRQ, FIQ, and external abort interrupt routing. */ + scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK); + scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE; + /* Enable HVC */ + scr &= ~(SCR_HVC_MASK); + scr |= SCR_HVC_ENABLE; + /* Disable SMC */ + scr &= ~(SCR_SMC_MASK); + scr |= SCR_SMC_DISABLE; + /* Disable secure instruction fetches. */ + scr &= ~(SCR_SIF_MASK); + scr |= SCR_SIF_DISABLE; + /* All lower exception levels 64-bit by default. */ + scr &= ~(SCR_RW_MASK); + scr |= SCR_LOWER_AARCH64; + /* Disable secure EL1 access to secure timer. */ + scr &= ~(SCR_ST_MASK); + scr |= SCR_ST_DISABLE; + /* Don't trap on WFE or WFI instructions. */ + scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK); + scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE; + raw_write_scr_el3(scr); + isb(); +} + +void __attribute__((weak)) arm64_arch_timer_init(void) +{ + /* Default weak implementation does nothing. */ +} + static void arm64_init(void) { seed_stack(); + + /* Set up default SCR values. */ + el3_init(); + + /* Initialize the GIC. */ + gic_init(); + + /* + * Disable coprocessor traps to EL3: + * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR + * and EL2/EL1 access to CPACR_EL1. + * TTA [20] = 0, disable traps for trace register access from any EL. + * TFP [10] = 0, disable traps for floating-point instructions from any + * EL. + */ + raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | + CPTR_EL3_TFP_DISABLE); + + /* + * Allow FPU accesses: + * FPEN [21:20] = 3, disable traps for floating-point instructions from + * EL0/EL1. + * TTA [28] = 0, disable traps for trace register access from EL0/EL1. + */ + raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE); + + /* Arch Timer init: setup cntfrq per CPU */ + arm64_arch_timer_init(); + arm64_soc_init(); + main(); } diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c deleted file mode 100644 index c94c26f..0000000 --- a/src/arch/arm64/cpu_ramstage.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <arch/cache.h> -#include <arch/cpu.h> -#include <arch/lib_helpers.h> -#include <cpu/cpu.h> -#include <console/console.h> -#include <gic.h> -#include <timer.h> -#include "cpu-internal.h" - -static struct cpu_info cpu_info; - -void __attribute__((weak)) arm64_arch_timer_init(void) -{ - /* Default weak implementation does nothing. */ -} - -static inline void cpu_disable_dev(device_t dev) -{ - dev->enabled = 0; -} - -static struct cpu_driver *locate_cpu_driver(uint32_t midr) -{ - struct cpu_driver *cur; - - for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) { - const struct cpu_device_id *id_table = cur->id_table; - - for (; id_table->midr != CPU_ID_END; id_table++) { - if (id_table->midr == midr) - return cur; - } - } - return NULL; -} - -static int cpu_set_device_operations(device_t dev) -{ - uint32_t midr; - struct cpu_driver *driver; - - midr = raw_read_midr_el1(); - driver = locate_cpu_driver(midr); - - if (driver == NULL) { - printk(BIOS_WARNING, "No CPU driver for MIDR %08x\n", midr); - return -1; - } - dev->ops = driver->ops; - return 0; -} - -/* Set up default SCR values. */ -static void el3_init(void) -{ - uint32_t scr; - - if (get_current_el() != EL3) - return; - - scr = raw_read_scr_el3(); - /* Default to non-secure EL1 and EL0. */ - scr &= ~(SCR_NS_MASK); - scr |= SCR_NS_ENABLE; - /* Disable IRQ, FIQ, and external abort interrupt routing. */ - scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK); - scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE; - /* Enable HVC */ - scr &= ~(SCR_HVC_MASK); - scr |= SCR_HVC_ENABLE; - /* Disable SMC */ - scr &= ~(SCR_SMC_MASK); - scr |= SCR_SMC_DISABLE; - /* Disable secure instruction fetches. */ - scr &= ~(SCR_SIF_MASK); - scr |= SCR_SIF_DISABLE; - /* All lower exception levels 64-bit by default. */ - scr &= ~(SCR_RW_MASK); - scr |= SCR_LOWER_AARCH64; - /* Disable secure EL1 access to secure timer. */ - scr &= ~(SCR_ST_MASK); - scr |= SCR_ST_DISABLE; - /* Don't trap on WFE or WFI instructions. */ - scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK); - scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE; - raw_write_scr_el3(scr); - isb(); -} - -static void init_this_cpu(void) -{ - struct cpu_info *ci = &cpu_info; - device_t dev = ci->cpu; - - cpu_set_device_operations(dev); - - printk(BIOS_DEBUG, "CPU%x: MPIDR: %llx\n", ci->id, ci->mpidr); - - /* Initialize the GIC. */ - gic_init(); - - /* - * Disable coprocessor traps to EL3: - * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR - * and EL2/EL1 access to CPACR_EL1. - * TTA [20] = 0, disable traps for trace register access from any EL. - * TFP [10] = 0, disable traps for floating-point instructions from any - * EL. - */ - raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | - CPTR_EL3_TFP_DISABLE); - - /* - * Allow FPU accesses: - * FPEN [21:20] = 3, disable traps for floating-point instructions from - * EL0/EL1. - * TTA [28] = 0, disable traps for trace register access from EL0/EL1. - */ - raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE); - - /* Arch Timer init: setup cntfrq per CPU */ - arm64_arch_timer_init(); - - if (dev->ops != NULL && dev->ops->init != NULL) { - dev->initialized = 1; - printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); - dev->ops->init(dev); - } -} - -/* Fill in cpu_info structures according to device tree. */ -static void init_cpu_info(struct bus *bus) -{ - device_t cur; - - for (cur = bus->children; cur != NULL; cur = cur->sibling) { - struct cpu_info *ci; - unsigned int id = cur->path.cpu.id; - - if (cur->path.type != DEVICE_PATH_CPU) - continue; - - /* IDs are currently mapped 1:1 with logical CPU numbers. */ - if (id != 0) { - printk(BIOS_WARNING, - "CPU id %x too large. Disabling.\n", id); - cpu_disable_dev(cur); - continue; - } - - ci = &cpu_info; - if (ci->cpu != NULL) { - printk(BIOS_WARNING, - "Duplicate ID %x in device tree.\n", id); - cpu_disable_dev(cur); - } - - ci->cpu = cur; - ci->id = cur->path.cpu.id; - } -} - -void arch_initialize_cpu(device_t cluster) -{ - struct bus *bus; - - if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) { - printk(BIOS_ERR, - "CPU init failed. Device is not a CPU_CLUSTER: %s\n", - dev_path(cluster)); - return; - } - - bus = cluster->link_list; - - /* Check if no children under this device. */ - if (bus == NULL) - return; - - el3_init(); - - /* Initialize the cpu_info structures. */ - init_cpu_info(bus); - - /* Send it the init action. */ - init_this_cpu(); -} diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 778909d..fdc34e5 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -18,36 +18,6 @@ #define asmlinkage -#if !defined(__PRE_RAM__) -#include <arch/barrier.h> -#include <arch/mpidr.h> -#include <device/device.h> - -enum { - CPU_ID_END = 0x00000000, -}; - -struct cpu_device_id { - uint32_t midr; -}; - -struct cpu_driver { - /* This is excessive as init() is the only one called. */ - struct device_operations *ops; - const struct cpu_device_id *id_table; -}; - -struct cpu_info { - device_t cpu; - unsigned int id; - uint64_t mpidr; -}; - -/* Initialize CPU0 under the DEVICE_PATH_CPU_CLUSTER cluster. */ -void arch_initialize_cpu(device_t cluster); - -#endif /* !__PRE_RAM__ */ - static inline unsigned int smp_processor_id(void) { return 0; } /* @@ -63,4 +33,8 @@ void arm64_cpu_startup(void); */ void arm64_arch_timer_init(void); +#if !defined(__PRE_RAM__) +struct cpu_driver { }; +#endif + #endif /* __ARCH_CPU_H__ */ diff --git a/src/drivers/gic/gic.c b/src/drivers/gic/gic.c index 622aaff..80e98eb 100644 --- a/src/drivers/gic/gic.c +++ b/src/drivers/gic/gic.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <console/console.h> #include <gic.h> +#include <stddef.h> #include "gic.h" enum { diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb index 40c4ec3..6b3e148 100644 --- a/src/mainboard/google/rush/devicetree.cb +++ b/src/mainboard/google/rush/devicetree.cb @@ -15,7 +15,6 @@ chip soc/nvidia/tegra132 device cpu_cluster 0 on - device cpu 0 on end end register "display_controller" = "TEGRA_ARM_DISPLAYA" diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb index 5caa6f6..4245444 100644 --- a/src/mainboard/google/rush_ryu/devicetree.cb +++ b/src/mainboard/google/rush_ryu/devicetree.cb @@ -15,8 +15,6 @@ chip soc/nvidia/tegra132 device cpu_cluster 0 on - device cpu 0 on end - device cpu 1 on end end register "display_controller" = "TEGRA_ARM_DISPLAYA" diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb index e7f8647..5d7bf86 100644 --- a/src/mainboard/google/smaug/devicetree.cb +++ b/src/mainboard/google/smaug/devicetree.cb @@ -15,7 +15,6 @@ chip soc/nvidia/tegra210 device cpu_cluster 0 on - device cpu 0 on end end register "display_controller" = "TEGRA_ARM_DISPLAYA" diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index 64b61e9..ca9cec4 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -16,8 +16,18 @@ #include <arch/stages.h> #include <soc/addressmap.h> #include <soc/clock.h> +#include <soc/mc.h> #include <soc/mmu_operations.h> +static void lock_down_vpr(void) +{ + struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; + + write32(&regs->video_protect_bom, 0); + write32(&regs->video_protect_size_mb, 0); + write32(&regs->video_protect_reg_ctrl, 1); +} + void arm64_soc_init(void) { trustzone_region_init(); @@ -25,4 +35,9 @@ void arm64_soc_init(void) tegra132_mmu_init(); clock_cpu0_config(); + + clock_init_arm_generic_timer(); + + /* Lock down VPR */ + lock_down_vpr(); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 8eabd39..40889a7 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -26,7 +26,6 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/cpu.h> -#include <soc/mc.h> #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> @@ -55,38 +54,11 @@ static void soc_read_resources(device_t dev) ram_resource(dev, index++, begin * KiB, size * KiB); } -static void lock_down_vpr(void) -{ - struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; - - write32(&regs->video_protect_bom, 0); - write32(&regs->video_protect_size_mb, 0); - write32(&regs->video_protect_reg_ctrl, 1); -} - -static void soc_init(device_t dev) -{ - clock_init_arm_generic_timer(); - - arch_initialize_cpu(dev); - - /* Lock down VPR */ - lock_down_vpr(); - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - return; - - if (display_init_required()) - display_startup(dev); - else - printk(BIOS_INFO, "Skipping display init.\n"); -} - static struct device_operations soc_ops = { .read_resources = soc_read_resources, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = soc_init, + .init = DEVICE_NOOP, .scan_bus = NULL, }; @@ -94,6 +66,14 @@ static void enable_tegra132_dev(device_t dev) { if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; + + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) + display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static void tegra132_init(void *chip_info) @@ -114,24 +94,6 @@ struct chip_operations soc_nvidia_tegra132_ops = { .enable_dev = enable_tegra132_dev, }; -static void tegra132_cpu_init(device_t cpu) -{ -} - -static const struct cpu_device_id ids[] = { - { 0x4e0f0000 }, - { CPU_ID_END }, -}; - -static struct device_operations cpu_dev_ops = { - .init = tegra132_cpu_init, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = ids, -}; - static void enable_plld(void *unused) { /* diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index f55c256..5c37510 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -19,6 +19,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> +#include <soc/mtc.h> void arm64_arch_timer_init(void) { @@ -54,4 +55,9 @@ void arm64_soc_init(void) trustzone_region_init(); tegra210_mmu_init(); + + clock_init_arm_generic_timer(); + + if (tegra210_run_mtc() != 0) + printk(BIOS_ERR, "MTC: No training data.\n"); } diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index bcbef49..1071d68 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -27,7 +27,6 @@ #include <soc/clock.h> #include <soc/cpu.h> #include <soc/mc.h> -#include <soc/mtc.h> #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> @@ -58,30 +57,11 @@ static void soc_read_resources(device_t dev) ram_resource(dev, index++, begin * KiB, size * KiB); } -static void soc_init(device_t dev) -{ - clock_init_arm_generic_timer(); - - arch_initialize_cpu(dev); - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - return; - - if (display_init_required()) - display_startup(dev); - else - printk(BIOS_INFO, "Skipping display init.\n"); -} - -static void soc_noop(device_t dev) -{ -} - static struct device_operations soc_ops = { .read_resources = soc_read_resources, - .set_resources = soc_noop, - .enable_resources = soc_noop, - .init = soc_init, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = DEVICE_NOOP, .scan_bus = NULL, }; @@ -89,6 +69,14 @@ static void enable_tegra210_dev(device_t dev) { if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; + + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) + display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static void tegra210_init(void *chip_info) @@ -111,26 +99,6 @@ struct chip_operations soc_nvidia_tegra210_ops = { .enable_dev = enable_tegra210_dev, }; -static void tegra210_cpu_init(device_t cpu) -{ - if (tegra210_run_mtc() != 0) - printk(BIOS_ERR, "MTC: No training data.\n"); -} - -static const struct cpu_device_id ids[] = { - { 0x411fd071 }, - { CPU_ID_END }, -}; - -static struct device_operations cpu_dev_ops = { - .init = tegra210_cpu_init, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = ids, -}; - static void enable_plld(void *unused) { /*

1 0

Patch set updated for coreboot: arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
by Julius Werner 07 Nov '15

07 Nov '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11898 -gerrit commit 8d8682474d9ed6a5443807b1928a66ebd8faef5d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 14 10:20:18 2015 -0500 arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT With the removal of secmon from coreboot there are no power down operations required. As such remove the A57 power down support. Change-Id: I8eebb0ecd87b5e8bb3eaac335d652689d7f57796 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/cpu-stubs.c | 6 --- src/arch/arm64/cpu/Kconfig | 5 -- src/arch/arm64/cpu/cortex_a57.S | 95 --------------------------------- src/arch/arm64/include/armv8/arch/cpu.h | 14 ----- src/soc/nvidia/tegra210/Kconfig | 1 - 5 files changed, 121 deletions(-) diff --git a/src/arch/arm64/cpu-stubs.c b/src/arch/arm64/cpu-stubs.c index 119ff44..1a61872 100644 --- a/src/arch/arm64/cpu-stubs.c +++ b/src/arch/arm64/cpu-stubs.c @@ -14,14 +14,8 @@ */ void arm64_cpu_early_setup(void); -void cortex_a57_cpu_power_down(int l2_flush); void __attribute__((weak)) arm64_cpu_early_setup(void) { /* Default empty implementation */ } - -void __attribute__((weak)) cortex_a57_cpu_power_down(int l2_flush) -{ - /* Default empty implementation */ -} diff --git a/src/arch/arm64/cpu/Kconfig b/src/arch/arm64/cpu/Kconfig index 91773ae..21526e6 100644 --- a/src/arch/arm64/cpu/Kconfig +++ b/src/arch/arm64/cpu/Kconfig @@ -17,8 +17,3 @@ config ARCH_ARM64_CPU_CORTEX_A57 bool default n depends on ARCH_ARM64 - -config ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT - bool - default n - depends on ARCH_ARM64 && ARCH_ARM64_CPU_CORTEX_A57 diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S index 08c22a8..80707ca 100644 --- a/src/arch/arm64/cpu/cortex_a57.S +++ b/src/arch/arm64/cpu/cortex_a57.S @@ -14,7 +14,6 @@ */ #include <arch/asm.h> -#include <arch/cache_helpers.h> #include <cpu/cortex_a57.h> ENTRY(arm64_cpu_early_setup) @@ -24,97 +23,3 @@ ENTRY(arm64_cpu_early_setup) isb ret ENDPROC(arm64_cpu_early_setup) - -/* - * CPU power down sequence as per A57/A53/A72 TRM - * - * x0 - L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported - * - */ -#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) -ENTRY(cortex_a57_cpu_power_down) - /* Store L2 cache flush request */ - mov x13, x0 - - /* 1. Stop allocations to our data cache */ - mrs x0, sctlr_el1 - bic x0, x0, #1 << 2 // clear SCTLR.C - msr sctlr_el1, x0 - isb - - mrs x0, sctlr_el3 - bic x0, x0, #1 << 2 // clear SCTLR.C - msr sctlr_el3, x0 - isb - - mrs x0, midr_el1 - ubfx x0, x0, #4, #12 - cmp x0, #CORTEX_A53_PN - b.eq a53 - - /* 2. Disable L2 prefetch */ - mrs x0, CPUECTLR_EL1 // CPUECTLR_EL1 - /* CPUECTLR[38], disable table walk descriptor access L2 prefetch */ - orr x0, x0, #1 << 38 - /* - * CPUECTLR[36:35] L2 instruction fetch prefetch distance - * 0 => disable instruction prefetch - */ - bic x0, x0, #3 << 35 - /* - * CPUECTLR[33:32] L2 load/store prefetch distance - * 0 => disable instruction prefetch - */ - bic x0, x0, #3 << 32 - msr CPUECTLR_EL1, x0 - - /* 3. ISB to ensure ectlr write is complete */ - isb - - /* 4. DSB to ensure prior prefetches are complete */ - dsb sy - -a53: - /* 5. Clean and invalidate L1 and L2 if X13 == 1 */ - mov x0, #DCCISW - cmp x13, #1 - bne 1f - bl flush_dcache_all - b 2f -1: - bl flush_dcache_louis -2: - - /* 6. Leave coherency, clear SMPEN */ - mrs x0, CPUECTLR_EL1 - bic x0, x0, #(1 << SMPEN_SHIFT) - msr CPUECTLR_EL1, x0 - - /* 7. Set the DBGOSDLR.DLK, Double lock control bit */ - mrs x0, osdlr_el1 - orr x0, x0, #OSDLR_DBL_LOCK_BIT - msr osdlr_el1, x0 - - /* - * 9. Execute an ISB instruction to ensure that all of the - * System register changes from the previous steps have - * been committed. - */ - isb - - /* - * 10. Execute a DSB instruction to ensure that all - * instruction cache, TLB, and branch predictor - * maintenance operations issued by any processor in the - * multiprocessor before the SMPEN bit was cleared have - * completed. - */ - dsb sy - - /* 11. wfi */ -3: wfi - - /* we never return here */ - b 3b -ENDPROC(cortex_a57_cpu_power_down) -#endif diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 03e9cf9..d1056c5 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -183,18 +183,4 @@ void arm64_cpu_startup_resume(void); */ void arm64_arch_timer_init(void); -/* - * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM. - * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported. - */ -#define NO_L2_FLUSH 0 -#define L2_FLUSH_HW 0 -#define L2_FLUSH_SW 1 - -#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) -void cortex_a57_cpu_power_down(int l2_flush); -#else -static inline void cortex_a57_cpu_power_down(int l2_flush) {} -#endif - #endif /* __ARCH_CPU_H__ */ diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 37d3360..2d910be 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210 select ARCH_ROMSTAGE_ARMV4 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ARM64_CPU_CORTEX_A57 - select ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT select BOOTBLOCK_CONSOLE select GIC select HAVE_MONOTONIC_TIMER

1 0

Patch set updated for coreboot: arm64: remove spin table support
by Julius Werner 07 Nov '15

07 Nov '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11908 -gerrit commit 8d4676f040d810cd692e2727e3a5565e11d6b222 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 15 12:22:27 2015 -0500 arm64: remove spin table support As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/Kconfig | 5 -- src/arch/arm64/Makefile.inc | 1 - src/arch/arm64/boot.c | 5 -- src/arch/arm64/include/arch/spintable.h | 45 -------------- src/arch/arm64/spintable.c | 96 ----------------------------- src/arch/arm64/spintable_asm.S | 34 ---------- src/commonlib/include/commonlib/cbmem_id.h | 2 - src/mainboard/google/foster/devicetree.cb | 2 - src/mainboard/google/rush/Kconfig | 1 - src/mainboard/google/rush/devicetree.cb | 2 - src/mainboard/google/rush_ryu/Kconfig | 1 - src/mainboard/google/rush_ryu/devicetree.cb | 2 - src/mainboard/google/smaug/devicetree.cb | 2 - src/soc/nvidia/tegra132/chip.h | 3 - src/soc/nvidia/tegra132/soc.c | 5 -- src/soc/nvidia/tegra210/chip.h | 3 - src/soc/nvidia/tegra210/soc.c | 5 -- 17 files changed, 214 deletions(-) diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 2f019a3..2c87132 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -28,11 +28,6 @@ config ARM64_BOOTBLOCK_CUSTOM bool default n -config ARM64_USE_SPINTABLE - bool - default n - depends on ARCH_RAMSTAGE_ARM64 - config ARM64_USE_ARM_TRUSTED_FIRMWARE bool default n diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index e82e872..fabe7b3 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -142,7 +142,6 @@ ramstage-y += memcpy.S ramstage-y += memmove.S ramstage-y += stage_entry.S ramstage-y += cpu-stubs.c -ramstage-$(CONFIG_ARM64_USE_SPINTABLE) += spintable.c spintable_asm.S ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c ramstage-y += transition.c transition_asm.S diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 6076e67..10d7257 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -16,7 +16,6 @@ #include <arch/cache.h> #include <arch/lib_helpers.h> #include <arch/stages.h> -#include <arch/spintable.h> #include <arch/transition.h> #include <arm_tf.h> #include <cbmem.h> @@ -39,10 +38,6 @@ static void run_payload(struct prog *prog) else { uint8_t current_el = get_current_el(); - /* Start the other CPUs spinning. */ - if (IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE)) - spintable_start(); - cache_sync_instructions(); printk(BIOS_SPEW, "entry = %p\n", doit); diff --git a/src/arch/arm64/include/arch/spintable.h b/src/arch/arm64/include/arch/spintable.h deleted file mode 100644 index 598090a..0000000 --- a/src/arch/arm64/include/arch/spintable.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_SPINTABLE_H__ -#define __ARCH_SPINTABLE_H__ - -struct spintable_attributes { - void (*entry)(void *); - void *addr; -}; - -#if IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) - -/* Initialize spintable with provided monitor address. */ -void spintable_init(void *monitor_address); - -/* Return NULL on failure, otherwise the spintable info. */ -const struct spintable_attributes *spintable_get_attributes(void); - -#else /* IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) */ - -static inline void spintable_init(void *monitor_address) {} -static inline const struct spintable_attributes *spintable_get_attributes(void) -{ - return NULL; -} - -#endif /* IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) */ - -/* Start spinning on the non-boot CPUs. */ -void spintable_start(void); - -#endif /* __ARCH_SPINTABLE_H__ */ diff --git a/src/arch/arm64/spintable.c b/src/arch/arm64/spintable.c deleted file mode 100644 index 83b2207..0000000 --- a/src/arch/arm64/spintable.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> -#include <arch/spintable.h> -#include <arch/transition.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <cbmem.h> -#include <string.h> - -static struct spintable_attributes spin_attrs; - -void spintable_init(void *monitor_address) -{ - extern void __wait_for_spin_table_request(void); - const size_t code_size = 4096; - - if (monitor_address == NULL) { - printk(BIOS_ERR, "spintable: NULL address to monitor.\n"); - return; - } - - spin_attrs.entry = cbmem_add(CBMEM_ID_SPINTABLE, code_size); - - if (spin_attrs.entry == NULL) - return; - - spin_attrs.addr = monitor_address; - - printk(BIOS_INFO, "spintable @ %p will monitor %p\n", - spin_attrs.entry, spin_attrs.addr); - - /* Ensure the memory location is zero'd out. */ - *(uint64_t *)monitor_address = 0; - - memcpy(spin_attrs.entry, __wait_for_spin_table_request, code_size); - - dcache_clean_invalidate_by_mva(monitor_address, sizeof(uint64_t)); - dcache_clean_invalidate_by_mva(spin_attrs.entry, code_size); -} - -static void spintable_enter(void *unused) -{ - struct exc_state state; - const struct spintable_attributes *attrs; - int current_el; - - attrs = spintable_get_attributes(); - - current_el = get_current_el(); - - if (current_el != EL3) - attrs->entry(attrs->addr); - - memset(&state, 0, sizeof(state)); - state.elx.spsr = get_eret_el(EL2, SPSR_USE_L); - - transition_with_entry(attrs->entry, attrs->addr, &state); -} - -const struct spintable_attributes *spintable_get_attributes(void) -{ - if (spin_attrs.entry == NULL) { - printk(BIOS_ERR, "spintable: monitor code not present.\n"); - return NULL; - } - - return &spin_attrs; -} - -void spintable_start(void) -{ - struct cpu_action action = { - .run = spintable_enter, - }; - - if (spintable_get_attributes() == NULL) - return; - - printk(BIOS_INFO, "All non-boot CPUs to enter spintable.\n"); - - arch_run_on_all_cpus_but_self_async(&action); -} diff --git a/src/arch/arm64/spintable_asm.S b/src/arch/arm64/spintable_asm.S deleted file mode 100644 index 470a9bb..0000000 --- a/src/arch/arm64/spintable_asm.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/asm.h> - -ENTRY(__wait_for_spin_table_request) - /* Entry here is in EL2 with the magic address in x0. */ - mov x28, x0 -1: - ldr x27, [x28] - cmp x27, xzr - b.ne 2f - wfe - b 1b -2: - /* Entry into the kernel. */ - mov x0, xzr - mov x1, xzr - mov x2, xzr - mov x3, xzr - br x27 -ENDPROC(__wait_for_spin_table_request) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index f267a32..580d5ea 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -55,7 +55,6 @@ #define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee -#define CBMEM_ID_SPINTABLE 0x59175917 #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 #define CBMEM_ID_TCPA_LOG 0x54435041 @@ -101,7 +100,6 @@ { CBMEM_ID_ROOT, "CBMEM ROOT " }, \ { CBMEM_ID_SMBIOS, "SMBIOS " }, \ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ - { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ diff --git a/src/mainboard/google/foster/devicetree.cb b/src/mainboard/google/foster/devicetree.cb index e800139..0255b53 100644 --- a/src/mainboard/google/foster/devicetree.cb +++ b/src/mainboard/google/foster/devicetree.cb @@ -14,8 +14,6 @@ ## chip soc/nvidia/tegra210 - register "spintable_addr" = "0x80000008" - device cpu_cluster 0 on device cpu 0 on end device cpu 1 on end diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index 7a411b3..fcf755a 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_SOR_INIT select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_4096 - select ARM64_USE_SPINTABLE config CHROMEOS select CHROMEOS_VBNV_EC diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb index f34bdc1..fa25e1f 100644 --- a/src/mainboard/google/rush/devicetree.cb +++ b/src/mainboard/google/rush/devicetree.cb @@ -14,8 +14,6 @@ ## chip soc/nvidia/tegra132 - register "spintable_addr" = "0x80000008" - device cpu_cluster 0 on device cpu 0 on end device cpu 1 on end diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 657d88a..47e432f 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_DSI_INIT select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_8192 - select ARM64_USE_SPINTABLE config CHROMEOS select CHROMEOS_VBNV_EC diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb index 7bd8950..5caa6f6 100644 --- a/src/mainboard/google/rush_ryu/devicetree.cb +++ b/src/mainboard/google/rush_ryu/devicetree.cb @@ -14,8 +14,6 @@ ## chip soc/nvidia/tegra132 - register "spintable_addr" = "0x80000008" - device cpu_cluster 0 on device cpu 0 on end device cpu 1 on end diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb index 863647a..e7f8647 100644 --- a/src/mainboard/google/smaug/devicetree.cb +++ b/src/mainboard/google/smaug/devicetree.cb @@ -14,8 +14,6 @@ ## chip soc/nvidia/tegra210 - register "spintable_addr" = "0x80000008" - device cpu_cluster 0 on device cpu 0 on end end diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h index bdbad1b..ae08636 100644 --- a/src/soc/nvidia/tegra132/chip.h +++ b/src/soc/nvidia/tegra132/chip.h @@ -20,9 +20,6 @@ #include <soc/nvidia/tegra/dc.h> struct soc_nvidia_tegra132_config { - /* Address to monitor if spintable employed. */ - uintptr_t spintable_addr; - /* * panel resolution * The two parameters below provides dc about panel spec. diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 07a2f10..99896be 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <arch/cache.h> -#include <arch/spintable.h> #include <cpu/cpu.h> #include <bootmode.h> #include <bootstate.h> @@ -86,12 +85,8 @@ static void lock_down_vpr(void) static void soc_init(device_t dev) { - struct soc_nvidia_tegra132_config *cfg; - clock_init_arm_generic_timer(); - cfg = dev->chip_info; - spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); /* Lock down VPR */ diff --git a/src/soc/nvidia/tegra210/chip.h b/src/soc/nvidia/tegra210/chip.h index b221130..6a2aa84 100644 --- a/src/soc/nvidia/tegra210/chip.h +++ b/src/soc/nvidia/tegra210/chip.h @@ -20,9 +20,6 @@ #include <soc/nvidia/tegra/dc.h> struct soc_nvidia_tegra210_config { - /* Address to monitor if spintable employed. */ - uintptr_t spintable_addr; - /* * panel resolution * The two parameters below provides dc about panel spec. diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index ce71eb4..871c148 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <arch/cache.h> -#include <arch/spintable.h> #include <cpu/cpu.h> #include <bootmode.h> #include <bootstate.h> @@ -80,12 +79,8 @@ static struct cpu_control_ops cntrl_ops = { static void soc_init(device_t dev) { - struct soc_nvidia_tegra210_config *cfg; - clock_init_arm_generic_timer(); - cfg = dev->chip_info; - spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))

1 0

Patch set updated for coreboot: arm64: Remove SMP support
by Julius Werner 07 Nov '15

07 Nov '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11909 -gerrit commit 3d828f35e0fb9213f6136a6f94db41776474604c Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 15 12:15:31 2015 -0700 arm64: Remove SMP support As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove SMP support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/arch/arm64/Makefile.inc | 2 - src/arch/arm64/c_entry.c | 18 +- src/arch/arm64/cpu-internal.h | 20 +- src/arch/arm64/cpu.c | 224 ----------------------- src/arch/arm64/cpu_ramstage.c | 92 +--------- src/arch/arm64/include/arch/startup.h | 44 ----- src/arch/arm64/include/armv8/arch/cpu.h | 134 +------------- src/arch/arm64/include/armv8/arch/smp/spinlock.h | 29 --- src/arch/arm64/stage_entry.S | 122 ++---------- src/arch/arm64/startup.c | 53 ------ src/mainboard/google/rush/devicetree.cb | 1 - src/soc/nvidia/tegra132/Kconfig | 1 - src/soc/nvidia/tegra132/Makefile.inc | 1 - src/soc/nvidia/tegra132/cpu_lib.S | 23 --- src/soc/nvidia/tegra132/soc.c | 21 +-- src/soc/nvidia/tegra210/Makefile.inc | 1 - src/soc/nvidia/tegra210/cpu_lib.S | 23 --- src/soc/nvidia/tegra210/soc.c | 26 +-- 18 files changed, 38 insertions(+), 797 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index fabe7b3..b4ee3a5 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -130,9 +130,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) ramstage-y += c_entry.c ramstage-y += stages.c -ramstage-y += startup.c ramstage-y += div0.c -ramstage-y += cpu.c ramstage-y += cpu_ramstage.c ramstage-y += eabi_compat.c ramstage-y += boot.c diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index 0a5541c..deef83d 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -17,7 +17,6 @@ #include <arch/cpu.h> #include <arch/mmu.h> #include <arch/stages.h> -#include <arch/startup.h> #include "cpu-internal.h" void __attribute__((weak)) arm64_soc_init(void) @@ -32,7 +31,7 @@ static void seed_stack(void) int i; int size; - stack_begin = cpu_get_stack(smp_processor_id()); + stack_begin = cpu_get_stack(); stack_begin -= CONFIG_STACK_SIZE; slot = (void *)stack_begin; @@ -45,21 +44,10 @@ static void seed_stack(void) static void arm64_init(void) { - cpu_set_bsp(); seed_stack(); arm64_soc_init(); main(); } -/* - * This variable holds entry point for CPUs starting up. The first - * element is the BSP path, and the second is the non-BSP path. - */ -void (*c_entry[2])(void) = { &arm64_init, &arch_secondary_cpu_init }; - -void *prepare_secondary_cpu_startup(void) -{ - startup_save_cpu_data(); - - return secondary_entry_point(&arm64_cpu_startup_resume); -} +/* This variable holds entry point for CPU starting up. */ +void (*c_entry)(void) = &arm64_init; diff --git a/src/arch/arm64/cpu-internal.h b/src/arch/arm64/cpu-internal.h index fb5d13f..75d2d4d 100644 --- a/src/arch/arm64/cpu-internal.h +++ b/src/arch/arm64/cpu-internal.h @@ -16,22 +16,10 @@ #ifndef ARCH_CPU_INTERNAL_H #define ARCH_CPU_INTERNAL_H -/* - * Do the necessary work to prepare for secondary CPUs coming up. The - * SoC will call this function before bringing up the other CPUs. The - * entry point for the seoncdary CPUs is returned. - */ -void *prepare_secondary_cpu_startup(void); - -/* - * Code path for the non-BSP CPUs. This is an internal function used. - */ -void arch_secondary_cpu_init(void); - -/* Return the top of the stack for the specified cpu. */ -void *cpu_get_stack(unsigned int cpu); +/* Return the top of the stack for the cpu. */ +void *cpu_get_stack(void); -/* Return the top of the exception stack for the specified cpu. */ -void *cpu_get_exception_stack(unsigned int cpu); +/* Return the top of the exception stack for the cpu. */ +void *cpu_get_exception_stack(void); #endif /* ARCH_CPU_INTERNAL_H */ diff --git a/src/arch/arm64/cpu.c b/src/arch/arm64/cpu.c deleted file mode 100644 index 1501181..0000000 --- a/src/arch/arm64/cpu.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <arch/lib_helpers.h> -#include <cpu/cpu.h> -#include <console/console.h> -#include <smp/node.h> -#include "cpu-internal.h" - -struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; -struct cpu_info *bsp_cpu_info; - -struct cpu_info *cpu_info(void) -{ - return cpu_info_for_cpu(smp_processor_id()); -} - -size_t cpus_online(void) -{ - int i; - size_t num = 0; - - for (i = 0; i < ARRAY_SIZE(cpu_infos); i++) { - if (cpu_online(cpu_info_for_cpu(i))) - num++; - } - - return num; -} - -static inline int action_queue_empty(struct cpu_action_queue *q) -{ - return load_acquire_exclusive(&q->todo) == NULL; -} - -static inline int action_completed(struct cpu_action_queue *q, - struct cpu_action *action) -{ - return load_acquire(&q->completed) == action; -} - -static inline void wait_for_action_queue_slot(struct cpu_action_queue *q) -{ - while (!action_queue_empty(q)) - wfe(); -} - -static void wait_for_action_complete(struct cpu_action_queue *q, - struct cpu_action *a) -{ - while (!action_completed(q, a)) - wfe(); -} - -static struct cpu_action *wait_for_action(struct cpu_action_queue *q, - struct cpu_action *local) -{ - struct cpu_action *action; - - while (action_queue_empty(q)) - wfe(); - - /* - * Keep original address, but use a local copy for async processing. - */ - do { - action = load_acquire_exclusive(&q->todo); - *local = *action; - } while (!store_release_exclusive(&q->todo, NULL)); - - return action; -} - -static void queue_action(struct cpu_action_queue *q, struct cpu_action *action) -{ - do { - wait_for_action_queue_slot(q); - if (load_acquire_exclusive(&q->todo) != NULL) - continue; - } while (!store_release_exclusive(&q->todo, action)); -} - -static void action_queue_complete(struct cpu_action_queue *q, - struct cpu_action *action) -{ - /* Mark completion and send events to waiters. */ - store_release(&q->completed, action); - sev(); -} - -static void action_run(struct cpu_action *action) -{ - action->run(action->arg); -} - -static void action_run_on_cpu(struct cpu_info *ci, struct cpu_action *action, - int sync) -{ - struct cpu_action_queue *q = &ci->action_queue; - - /* Don't run actions on non-online cpus. */ - if (!cpu_online(ci)) - return; - - if (ci->id == smp_processor_id()) { - action->run(action->arg); - return; - } - - queue_action(q, action); - /* Wait for CPU to pick it up. Empty slot means it was picked up. */ - wait_for_action_queue_slot(q); - /* Wait for completion if requested. */ - if (sync) - wait_for_action_complete(q, action); -} - -static int __arch_run_on_cpu(unsigned int cpu, struct cpu_action *action, - int sync) -{ - struct cpu_info *ci; - - if (cpu >= CONFIG_MAX_CPUS) - return -1; - - ci = cpu_info_for_cpu(cpu); - - action_run_on_cpu(ci, action, sync); - - return 0; -} - -int arch_run_on_cpu(unsigned int cpu, struct cpu_action *action) -{ - return __arch_run_on_cpu(cpu, action, 1); -} - -int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action) -{ - return __arch_run_on_cpu(cpu, action, 0); -} - -static int __arch_run_on_all_cpus(struct cpu_action *action, int sync) -{ - int i; - - for (i = 0; i < CONFIG_MAX_CPUS; i++) - action_run_on_cpu(cpu_info_for_cpu(i), action, sync); - - return 0; -} - -static int __arch_run_on_all_cpus_but_self(struct cpu_action *action, int sync) -{ - int i; - struct cpu_info *me = cpu_info(); - - for (i = 0; i < CONFIG_MAX_CPUS; i++) { - struct cpu_info *ci = cpu_info_for_cpu(i); - if (ci == me) - continue; - action_run_on_cpu(ci, action, sync); - } - - return 0; -} - -int arch_run_on_all_cpus(struct cpu_action *action) -{ - return __arch_run_on_all_cpus(action, 1); -} - -int arch_run_on_all_cpus_async(struct cpu_action *action) -{ - return __arch_run_on_all_cpus(action, 0); -} - -int arch_run_on_all_cpus_but_self(struct cpu_action *action) -{ - return __arch_run_on_all_cpus_but_self(action, 1); -} - -int arch_run_on_all_cpus_but_self_async(struct cpu_action *action) -{ - return __arch_run_on_all_cpus_but_self(action, 0); -} - - -void arch_cpu_wait_for_action(void) -{ - struct cpu_info *ci = cpu_info(); - struct cpu_action_queue *q = &ci->action_queue; - - while (1) { - struct cpu_action *orig; - struct cpu_action action; - - orig = wait_for_action(q, &action); - - action_run(&action); - action_queue_complete(q, orig); - } -} - -#if IS_ENABLED(CONFIG_SMP) -int boot_cpu(void) -{ - return cpu_is_bsp(); -} -#endif diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c index 81df98c..c94c26f 100644 --- a/src/arch/arm64/cpu_ramstage.c +++ b/src/arch/arm64/cpu_ramstage.c @@ -24,6 +24,8 @@ #include <timer.h> #include "cpu-internal.h" +static struct cpu_info cpu_info; + void __attribute__((weak)) arm64_arch_timer_init(void) { /* Default weak implementation does nothing. */ @@ -102,9 +104,9 @@ static void el3_init(void) isb(); } -static void init_this_cpu(void *arg) +static void init_this_cpu(void) { - struct cpu_info *ci = arg; + struct cpu_info *ci = &cpu_info; device_t dev = ci->cpu; cpu_set_device_operations(dev); @@ -156,14 +158,14 @@ static void init_cpu_info(struct bus *bus) continue; /* IDs are currently mapped 1:1 with logical CPU numbers. */ - if (id >= CONFIG_MAX_CPUS) { + if (id != 0) { printk(BIOS_WARNING, "CPU id %x too large. Disabling.\n", id); cpu_disable_dev(cur); continue; } - ci = cpu_info_for_cpu(id); + ci = &cpu_info; if (ci->cpu != NULL) { printk(BIOS_WARNING, "Duplicate ID %x in device tree.\n", id); @@ -175,12 +177,8 @@ static void init_cpu_info(struct bus *bus) } } -void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops) +void arch_initialize_cpu(device_t cluster) { - size_t max_cpus; - size_t i; - struct cpu_info *ci; - void (*entry)(void); struct bus *bus; if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) { @@ -196,83 +194,11 @@ void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops) if (bus == NULL) return; - /* - * el3_init must be performed prior to prepare_secondary_cpu_startup. - * This is important since el3_init initializes SCR values on BSP CPU - * and then prepare_secondary_cpu_startup reads the initialized SCR - * value and saves it for use by non-BSP CPUs. - */ el3_init(); - /* Mark current cpu online. */ - cpu_mark_online(cpu_info()); - entry = prepare_secondary_cpu_startup(); /* Initialize the cpu_info structures. */ init_cpu_info(bus); - max_cpus = cntrl_ops->total_cpus(); - - if (max_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_WARNING, - "max_cpus (%zu) exceeds CONFIG_MAX_CPUS (%zu).\n", - max_cpus, (size_t)CONFIG_MAX_CPUS); - max_cpus = CONFIG_MAX_CPUS; - } - - for (i = 0; i < max_cpus; i++) { - device_t dev; - struct cpu_action action; - struct stopwatch sw; - - ci = cpu_info_for_cpu(i); - dev = ci->cpu; - - /* Disregard CPUs not in device tree. */ - if (dev == NULL) - continue; - - /* Skip disabled CPUs. */ - if (!dev->enabled) - continue; - - if (!cpu_online(ci)) { - /* Start the CPU. */ - printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id); - - if (cntrl_ops->start_cpu(ci->id, entry)) { - printk(BIOS_ERR, - "Failed to start CPU%x\n", ci->id); - continue; - } - stopwatch_init_msecs_expire(&sw, 1000); - /* Wait for CPU to come online. */ - while (!stopwatch_expired(&sw)) { - if (!cpu_online(ci)) - continue; - printk(BIOS_DEBUG, - "CPU%x online in %ld usecs.\n", - ci->id, stopwatch_duration_usecs(&sw)); - break; - } - } - - if (!cpu_online(ci)) { - printk(BIOS_DEBUG, - "CPU%x failed to come online in %ld usecs.\n", - ci->id, stopwatch_duration_usecs(&sw)); - continue; - } - - /* Send it the init action. */ - action.run = init_this_cpu; - action.arg = ci; - arch_run_on_cpu(ci->id, &action); - } -} - -void arch_secondary_cpu_init(void) -{ - /* Mark this CPU online. */ - cpu_mark_online(cpu_info()); - arch_cpu_wait_for_action(); + /* Send it the init action. */ + init_this_cpu(); } diff --git a/src/arch/arm64/include/arch/startup.h b/src/arch/arm64/include/arch/startup.h deleted file mode 100644 index def0b37..0000000 --- a/src/arch/arm64/include/arch/startup.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM64_INCLUDE_ARCH_STARTUP_H__ -#define __ARCH_ARM64_INCLUDE_ARCH_STARTUP_H__ - -/* Every element occupies 8 bytes (64-bit entries) */ -#define PER_ELEMENT_SIZE_BYTES 8 -#define MAIR_INDEX 0 -#define TCR_INDEX 1 -#define TTBR0_INDEX 2 -#define SCR_INDEX 3 -#define VBAR_INDEX 4 -#define CNTFRQ_INDEX 5 -#define CPTR_INDEX 6 -#define CPACR_INDEX 7 -/* IMPORTANT!!! If any new element is added please update NUM_ELEMENTS */ -#define NUM_ELEMENTS 8 - -#ifndef __ASSEMBLY__ - -/* - * startup_save_cpu_data is used to save register values that need to be setup - * when a CPU starts booting. This is used by secondary CPUs as well as resume - * path to directly setup MMU and other related registers. - */ -void startup_save_cpu_data(void); - -#endif - -#endif /* __ARCH_ARM64_INCLUDE_ARCH_STARTUP_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index d1056c5..778909d 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -37,148 +37,28 @@ struct cpu_driver { const struct cpu_device_id *id_table; }; -/* Action to run. */ -struct cpu_action { - void (*run)(void *arg); - void *arg; -}; - -/* - * Actions are queued to 'todo'. When picked up 'todo' is cleared. The - * 'completed' field is set to the original 'todo' value when the action - * is complete. - */ -struct cpu_action_queue { - struct cpu_action *todo; - struct cpu_action *completed; -}; - struct cpu_info { device_t cpu; - struct cpu_action_queue action_queue; - unsigned int online; - /* Current assumption is that id matches smp_processor_id(). */ unsigned int id; uint64_t mpidr; }; -/* Obtain cpu_info for current executing CPU. */ -struct cpu_info *cpu_info(void); - -extern struct cpu_info *bsp_cpu_info; -extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; - -static inline struct cpu_info *cpu_info_for_cpu(unsigned int id) -{ - return &cpu_infos[id]; -} - -/* Ran only by BSP at initial boot strapping. */ -static inline void cpu_set_bsp(void) -{ - bsp_cpu_info = cpu_info(); -} - -static inline int cpu_is_bsp(void) -{ - return cpu_info() == bsp_cpu_info; -} - -static inline int cpu_online(struct cpu_info *ci) -{ - return load_acquire(&ci->online) != 0; -} - -static inline void cpu_mark_online(struct cpu_info *ci) -{ - ci->mpidr = read_affinity_mpidr(); - store_release(&ci->online, 1); -} - -/* Provide number of CPUs online. */ -size_t cpus_online(void); - -/* Control routines for starting CPUs. */ -struct cpu_control_ops { - /* Return the maximum number of CPUs supported. */ - size_t (*total_cpus)(void); - /* - * Start the requested CPU and have it start running entry(). - * Returns 0 on success, < 0 on error. - */ - int (*start_cpu)(unsigned int id, void (*entry)(void)); -}; - -/* - * Initialize all DEVICE_PATH_CPUS under the DEVICE_PATH_CPU_CLUSTER cluster. - * type DEVICE_PATH_CPUS. Start up is controlled by cntrl_ops. - */ -void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops); - -/* - * Run cpu_action returning < 0 on error, 0 on success. There are synchronous - * and asynchronous methods. Both cases ensure the action has been picked up - * by the target cpu. The synchronous variants will wait for the action to - * be completed before returning. - * - * Though the current implementation allows queuing actions on the main cpu, - * the main cpu doesn't process its own queue. - */ -int arch_run_on_cpu(unsigned int cpu, struct cpu_action *action); -int arch_run_on_all_cpus(struct cpu_action *action); -int arch_run_on_all_cpus_but_self(struct cpu_action *action); -int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action); -int arch_run_on_all_cpus_async(struct cpu_action *action); -int arch_run_on_all_cpus_but_self_async(struct cpu_action *action); - -/* Wait for actions to be perfomed. */ -void arch_cpu_wait_for_action(void); +/* Initialize CPU0 under the DEVICE_PATH_CPU_CLUSTER cluster. */ +void arch_initialize_cpu(device_t cluster); #endif /* !__PRE_RAM__ */ -/* - * Returns logical cpu in range [0:MAX_CPUS). SoC should define this. - * Additionally, this is needed early in arm64 init so it should not - * rely on a stack. Standard clobber list is fair game: x0-x7 and x0 - * returns the logical cpu number. - */ -unsigned int smp_processor_id(void); - -/* - * Stages and rmodules have 2 entry points: BSP and non-BSP. Provided - * a pointer the correct non-BSP entry point will be returned. The - * first instruction is for BSP and the 2nd is for non-BSP. Instructions - * are all 32-bit on arm64. - */ -static inline void *secondary_entry_point(void *e) -{ - uintptr_t nonbsp = (uintptr_t)e; - - return (void *)(nonbsp + sizeof(uint32_t)); -} +static inline unsigned int smp_processor_id(void) { return 0; } /* - * The arm64_cpu_startup() initializes a CPU's exception stack and regular - * stack as well initializing the C environment for the processor. It - * calls into the array of function pointers at symbol c_entry depending - * on BSP state. Note that arm64_cpu_startup contains secondary entry - * point which can be obtained by secondary_entry_point(). + * The arm64_cpu_startup() initializes CPU's exception stack and regular + * stack as well initializing the C environment for the processor. Finally it + * calls into c_entry. */ void arm64_cpu_startup(void); /* - * The arm64_cpu_startup_resume() initializes a CPU's exception stack and - * regular stack as well initializing the C environment for the processor. It - * calls into the array of function pointers at symbol c_entry depending - * on BSP state. Note that arm64_cpu_startup contains secondary entry - * point which can be obtained by secondary_entry_point(). - * Additionally, it also restores saved register data and enables MMU, caches - * and exceptions before jumping to C environment for both BSP and non-BSP CPUs. - */ -void arm64_cpu_startup_resume(void); - -/* - * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of + * The arm64_arch_timer_init() initializes the CPU's cntfrq register of * ARM arch timer. */ void arm64_arch_timer_init(void); diff --git a/src/arch/arm64/include/armv8/arch/smp/spinlock.h b/src/arch/arm64/include/armv8/arch/smp/spinlock.h deleted file mode 100644 index 10278e7..0000000 --- a/src/arch/arm64/include/armv8/arch/smp/spinlock.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef ARCH_SMP_SPINLOCK_H -#define ARCH_SMP_SPINLOCK_H - -#include <arch/barrier.h> -#include <stdint.h> - -typedef struct { - volatile uint32_t lock; -} spinlock_t; - -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } -#define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; - -static inline void spin_lock(spinlock_t *spin) -{ - while (1) { - if (load_acquire_exclusive(&spin->lock) != 0) - continue; - if (store_release_exclusive(&spin->lock, 1)) - break; - } -} - -static inline void spin_unlock(spinlock_t *spin) -{ - store_release(&spin->lock, 0); -} - -#endif diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 79db9dd..7f113fb 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -15,51 +15,41 @@ /* * ======================== stage_entry.S ===================================== - * This file acts as an entry point to the different stages of arm64 as well as - * for the secure monitor. They share the same process of setting up stacks and - * jumping to c code. It is important to save x25 from corruption as it contains - * the argument for secure monitor. + * This file acts as an entry point to the different stages of arm64. They share + * the same process of setting up stacks and jumping to c code. It is important + * to save x25 from corruption as it contains the argument for rmodule. * ============================================================================= */ #include <arch/asm.h> #define __ASSEMBLY__ #include <arch/lib_helpers.h> -#include <arch/startup.h> #define STACK_SZ CONFIG_STACK_SIZE #define EXCEPTION_STACK_SZ CONFIG_STACK_SIZE /* - * The stacks for each of the armv8 cores grows down from _estack. It is sized - * according to MAX_CPUS. Additionally provide exception stacks for each CPU. + * Stack for armv8 CPU grows down from _estack. Additionally, provide exception + * stack for the CPU. */ .section .bss, "aw", @nobits -.global _arm64_startup_data -.balign 8 -_arm64_startup_data: -.space NUM_ELEMENTS*PER_ELEMENT_SIZE_BYTES - .global _stack .global _estack .balign STACK_SZ _stack: -.space CONFIG_MAX_CPUS*STACK_SZ +.space STACK_SZ _estack: .global _stack_exceptions .global _estack_exceptions .balign EXCEPTION_STACK_SZ _stack_exceptions: -.space CONFIG_MAX_CPUS*EXCEPTION_STACK_SZ +.space EXCEPTION_STACK_SZ _estack_exceptions: ENTRY(cpu_get_stack) - mov x1, #STACK_SZ - mul x0, x0, x1 - ldr x1, 1f - sub x0, x1, x0 + ldr x0, 1f ret .align 3 1: @@ -67,10 +57,7 @@ ENTRY(cpu_get_stack) ENDPROC(cpu_get_stack) ENTRY(cpu_get_exception_stack) - mov x1, #EXCEPTION_STACK_SZ - mul x0, x0, x1 - ldr x1, 1f - sub x0, x1, x0 + ldr x0, 1f ret .align 3 1: @@ -87,11 +74,7 @@ ENDPROC(cpu_get_exception_stack) * any rmodules. */ ENTRY(arm64_c_environment) - bl smp_processor_id /* x0 = cpu */ - mov x24, x0 - - - /* Set the exception stack for this cpu. */ + /* Set the exception stack for the cpu. */ bl cpu_get_exception_stack msr SPSel, #1 isb @@ -101,16 +84,12 @@ ENTRY(arm64_c_environment) msr SPSel, #0 isb - /* Set stack for this cpu. */ - mov x0, x24 /* x0 = cpu */ + /* Set the non-exception stack for the cpu. */ bl cpu_get_stack mov sp, x0 /* Get entry point by dereferencing c_entry. */ ldr x1, 1f - /* Retrieve entry in c_entry array using x26 as the index. */ - adds x1, x1, x26, lsl #3 - ldr x1, [x1] /* Move back the arguments from x25 to x0 */ mov x0, x25 br x1 @@ -119,21 +98,7 @@ ENTRY(arm64_c_environment) .quad c_entry ENDPROC(arm64_c_environment) -/* The first 2 instructions are for BSP and secondary CPUs, - * respectively. x26 holds the index into c_entry array. */ -.macro split_bsp_path - b 2000f - b 2001f - 2000: - mov x26, #0 - b 2002f - 2001: - mov x26, #1 - 2002: -.endm - ENTRY(_start) - split_bsp_path /* Save any arguments to current rmodule in x25 */ mov x25, x0 b arm64_c_environment @@ -153,77 +118,12 @@ ENDPROC(_start) write_current sctlr, x0, x1 .endm -/* - * This macro assumes x2 has base address and returns value read in x0 - * x1 is used as temporary register. - */ -.macro get_element_addr index - add x1, x2, #(\index * PER_ELEMENT_SIZE_BYTES) - ldr x0, [x1] -.endm - -/* - * Uses following registers: - * x0 = reading stored value - * x1 = temp reg - * x2 = base address of saved data region - */ -.macro startup_restore - adr x2, _arm64_startup_data - - get_element_addr MAIR_INDEX - write_current mair, x0, x1 - - get_element_addr TCR_INDEX - write_current tcr, x0, x1 - - get_element_addr TTBR0_INDEX - write_current ttbr0, x0, x1 - - get_element_addr SCR_INDEX - write_el3 scr, x0, x1 - - get_element_addr VBAR_INDEX - write_current vbar, x0, x1 - - get_element_addr CNTFRQ_INDEX - write_el0 cntfrq, x0, x1 - - get_element_addr CPTR_INDEX - write_el3 cptr, x0, x1 - - get_element_addr CPACR_INDEX - write_el1 cpacr, x0, x1 - - dsb sy - isb - - tlbiall_current x1 - read_current x0, sctlr - orr x0, x0, #(1 << 12) /* Enable Instruction Cache */ - orr x0, x0, #(1 << 2) /* Enable Data/Unified Cache */ - orr x0, x0, #(1 << 0) /* Enable MMU */ - write_current sctlr, x0, x1 - - dsb sy - isb -.endm - CPU_RESET_ENTRY(arm64_cpu_startup) - split_bsp_path bl arm64_cpu_early_setup setup_sctlr b arm64_c_environment ENDPROC(arm64_cpu_startup) -CPU_RESET_ENTRY(arm64_cpu_startup_resume) - split_bsp_path - bl arm64_cpu_early_setup - setup_sctlr - startup_restore - b arm64_c_environment -ENDPROC(arm64_cpu_startup_resume) - /* * stage_entry is defined as a weak symbol to allow SoCs/CPUs to define a custom * entry point to perform any fixups that need to be done immediately after diff --git a/src/arch/arm64/startup.c b/src/arch/arm64/startup.c deleted file mode 100644 index 6ffe3f9..0000000 --- a/src/arch/arm64/startup.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> -#include <arch/lib_helpers.h> -#include <arch/startup.h> -#include <console/console.h> - -/* This space is defined in stage_entry.S. */ -extern u8 _arm64_startup_data[]; - -static inline void save_element(size_t index, uint64_t val) -{ - uint64_t *ptr = (uint64_t *)_arm64_startup_data; - - ptr[index] = val; -} - -/* - * startup_save_cpu_data is used to save register values that need to be setup - * when a CPU starts booting. This is used by secondary CPUs as well as resume - * path to directly setup MMU and other related registers. - */ -void startup_save_cpu_data(void) -{ - save_element(MAIR_INDEX, raw_read_mair_current()); - save_element(TCR_INDEX, raw_read_tcr_current()); - save_element(TTBR0_INDEX, raw_read_ttbr0_current()); - save_element(VBAR_INDEX, raw_read_vbar_current()); - save_element(CNTFRQ_INDEX, raw_read_cntfrq_el0()); - save_element(CPACR_INDEX, raw_read_cpacr_el1()); - - if (get_current_el() == EL3) { - save_element(SCR_INDEX, raw_read_scr_el3()); - save_element(CPTR_INDEX, raw_read_cptr_el3()); - } - - dcache_clean_by_mva(_arm64_startup_data, - NUM_ELEMENTS * PER_ELEMENT_SIZE_BYTES); -} diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb index fa25e1f..40c4ec3 100644 --- a/src/mainboard/google/rush/devicetree.cb +++ b/src/mainboard/google/rush/devicetree.cb @@ -16,7 +16,6 @@ chip soc/nvidia/tegra132 device cpu_cluster 0 on device cpu 0 on end - device cpu 1 on end end register "display_controller" = "TEGRA_ARM_DISPLAYA" diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 4420e52..cb6798c 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -12,7 +12,6 @@ config SOC_NVIDIA_TEGRA132 select HAVE_HARD_RESET select HAVE_UART_SPECIAL select ARM_BOOTBLOCK_CUSTOM - select SMP select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 592c34f..22ccba5 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -61,7 +61,6 @@ ramstage-y += 32bit_reset.S ramstage-y += addressmap.c ramstage-y += cbmem.c ramstage-y += cpu.c -ramstage-y += cpu_lib.S ramstage-y += clock.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c diff --git a/src/soc/nvidia/tegra132/cpu_lib.S b/src/soc/nvidia/tegra132/cpu_lib.S deleted file mode 100644 index 9040643..0000000 --- a/src/soc/nvidia/tegra132/cpu_lib.S +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -.text -.global smp_processor_id -smp_processor_id: - /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */ - mrs x0, mpidr_el1 - uxtb w0, w0 - ret diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 99896be..8eabd39 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -55,25 +55,6 @@ static void soc_read_resources(device_t dev) ram_resource(dev, index++, begin * KiB, size * KiB); } -static size_t cntrl_total_cpus(void) -{ - return CONFIG_MAX_CPUS; -} - -static int cntrl_start_cpu(unsigned int id, void (*entry)(void)) -{ - if (id != 1) - return -1; - start_cpu(1, entry); - return 0; -} - -static struct cpu_control_ops cntrl_ops = { - .total_cpus = cntrl_total_cpus, - .start_cpu = cntrl_start_cpu, -}; - - static void lock_down_vpr(void) { struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; @@ -87,7 +68,7 @@ static void soc_init(device_t dev) { clock_init_arm_generic_timer(); - arch_initialize_cpus(dev, &cntrl_ops); + arch_initialize_cpu(dev); /* Lock down VPR */ lock_down_vpr(); diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 2898cec..84d59d7 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -64,7 +64,6 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += addressmap.c ramstage-y += cbmem.c ramstage-y += cpu.c -ramstage-y += cpu_lib.S ramstage-y += clock.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c diff --git a/src/soc/nvidia/tegra210/cpu_lib.S b/src/soc/nvidia/tegra210/cpu_lib.S deleted file mode 100644 index 9040643..0000000 --- a/src/soc/nvidia/tegra210/cpu_lib.S +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -.text -.global smp_processor_id -smp_processor_id: - /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */ - mrs x0, mpidr_el1 - uxtb w0, w0 - ret diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 871c148..bcbef49 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -58,30 +58,11 @@ static void soc_read_resources(device_t dev) ram_resource(dev, index++, begin * KiB, size * KiB); } -static size_t cntrl_total_cpus(void) -{ - return CONFIG_MAX_CPUS; -} - -static int cntrl_start_cpu(unsigned int id, void (*entry)(void)) -{ - if (id >= CONFIG_MAX_CPUS) - return -1; - start_cpu(id, entry); - return 0; -} - -static struct cpu_control_ops cntrl_ops = { - .total_cpus = cntrl_total_cpus, - .start_cpu = cntrl_start_cpu, -}; - - static void soc_init(device_t dev) { clock_init_arm_generic_timer(); - arch_initialize_cpus(dev, &cntrl_ops); + arch_initialize_cpu(dev); if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) return; @@ -132,9 +113,8 @@ struct chip_operations soc_nvidia_tegra210_ops = { static void tegra210_cpu_init(device_t cpu) { - if (cpu_is_bsp()) - if (tegra210_run_mtc() != 0) - printk(BIOS_ERR, "MTC: No training data.\n"); + if (tegra210_run_mtc() != 0) + printk(BIOS_ERR, "MTC: No training data.\n"); } static const struct cpu_device_id ids[] = {

1 0

Patch set updated for coreboot: arm64: remove secmon
by Julius Werner 07 Nov '15

07 Nov '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11897 -gerrit commit f11d002656ba0770b2ea76858b31324d54f76c66 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 14 10:08:10 2015 -0500 arm64: remove secmon It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 2 +- src/arch/arm64/Kconfig | 7 - src/arch/arm64/Makefile.inc | 8 - src/arch/arm64/armv8/Makefile.inc | 4 - src/arch/arm64/armv8/lib/Makefile.inc | 4 - src/arch/arm64/armv8/secmon/Makefile.inc | 53 --- src/arch/arm64/armv8/secmon/psci.c | 705 ----------------------------- src/arch/arm64/armv8/secmon/secmon.h | 29 -- src/arch/arm64/armv8/secmon/secmon_init.c | 132 ------ src/arch/arm64/armv8/secmon/smc.c | 163 ------- src/arch/arm64/armv8/secmon/trampoline.S | 47 -- src/arch/arm64/armv8/secmon_loader.c | 157 ------- src/arch/arm64/boot.c | 3 - src/arch/arm64/cpu/Makefile.inc | 1 - src/arch/arm64/include/arch/header.ld | 1 - src/arch/arm64/include/arch/psci.h | 263 ----------- src/arch/arm64/include/arch/smc.h | 118 ----- src/arch/arm64/include/armv8/arch/secmon.h | 30 -- src/arch/arm64/stage_entry.S | 4 +- src/console/Makefile.inc | 4 - src/console/init.c | 2 - src/drivers/uart/Makefile.inc | 1 - src/include/console/console.h | 4 +- src/include/console/uart.h | 2 +- src/include/rules.h | 16 - src/lib/Makefile.inc | 3 - src/soc/nvidia/tegra132/Kconfig | 1 - src/soc/nvidia/tegra132/Makefile.inc | 10 - src/soc/nvidia/tegra132/psci.c | 141 ------ src/soc/nvidia/tegra132/secmon.c | 46 -- src/soc/nvidia/tegra210/Makefile.inc | 10 - src/soc/nvidia/tegra210/ccplex.c | 5 - src/soc/nvidia/tegra210/psci.c | 190 -------- src/soc/nvidia/tegra210/secmon.c | 46 -- 34 files changed, 6 insertions(+), 2206 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index de148cb..5b8e4dc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -63,7 +63,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage verstage secmon +classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage verstage # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index f2adf5c..2f019a3 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -28,13 +28,6 @@ config ARM64_BOOTBLOCK_CUSTOM bool default n -config ARM64_USE_SECURE_MONITOR - bool - default n - select RELOCATABLE_MODULES - depends on ARCH_RAMSTAGE_ARM64 - depends on !ARM64_USE_ARM_TRUSTED_FIRMWARE - config ARM64_USE_SPINTABLE bool default n diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c320c93..e82e872 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -151,14 +151,6 @@ rmodules_arm64-y += memcpy.S rmodules_arm64-y += memmove.S rmodules_arm64-y += eabi_compat.c -secmon-y += stage_entry.S -secmon-y += cpu-stubs.c -secmon-y += startup.c -secmon-y += ../../lib/malloc.c -secmon-y += memset.S -secmon-y += memmove.S -secmon-y += memcpy.S - ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) # Build the ramstage diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 48358ad..357159d 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -17,8 +17,6 @@ subdirs-y += lib/ -subdirs-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon/ - armv8_flags = -march=armv8-a -I$(src)/arch/arm64/include/armv8/ -D__COREBOOT_ARM_ARCH__=8 armv8_asm_flags = $(armv8_flags) @@ -88,8 +86,6 @@ ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += mmu.c -ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon_loader.c - ramstage-c-ccopts += $(armv8_flags) ramstage-S-ccopts += $(armv8_asm_flags) diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc index c3de597..2bf1a37 100644 --- a/src/arch/arm64/armv8/lib/Makefile.inc +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -32,8 +32,4 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += $(lib_access) -ifeq ($(CONFIG_ARM64_USE_SECURE_MONITOR),y) -secmon-y += $(lib_access) -endif - endif diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc deleted file mode 100644 index 7d66adf..0000000 --- a/src/arch/arm64/armv8/secmon/Makefile.inc +++ /dev/null @@ -1,53 +0,0 @@ -################################################################################ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -################################################################################ - -$(eval $(call create_class_compiler,secmon,arm64)) - -SECMON_DIR=$(obj)/arch/arm64/armv8/secmon -SECMON_BIN=$(SECMON_DIR)/secmon -SECMON_OBJ=$(SECMON_BIN).o -SECMON_ELF=$(SECMON_BIN).elf -SECMON_RMOD=$(SECMON_ELF).rmod -SECMON_RAMSTAGE=$(SECMON_DIR)/secmon.manual - -secmon-generic-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__ - -secmon-y += secmon_init.c -secmon-y += psci.c -secmon-y += smc.c -secmon-y += trampoline.S -secmon-y += ../cache.c -secmon-y += ../cache_helpers.S -secmon-y += ../cpu.S -secmon-y += ../exception.c -secmon-y += ../../cpu.c -secmon-y += ../../transition_asm.S ../../transition.c -secmon-y += ../../../../drivers/gic/gic.c - -ramstage-srcs += $(SECMON_RAMSTAGE) - -$(SECMON_OBJ): $$(secmon-objs) - $(CC_secmon) $(LDFLAGS) -nostdlib -r -o $@ $^ - -$(eval $(call rmodule_link,$(SECMON_ELF), $(SECMON_OBJ), 8192,arm64)) - -$(SECMON_BIN): $(SECMON_RMOD) - $(OBJCOPY_secmon) -O binary $< $@ - -$(SECMON_BIN).ramstage.manual: $(SECMON_BIN) - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY_secmon) -I binary $(notdir $<) -O elf64-littleaarch64 -B aarch64 $(notdir $@) diff --git a/src/arch/arm64/armv8/secmon/psci.c b/src/arch/arm64/armv8/secmon/psci.c deleted file mode 100644 index 9ae8cc5..0000000 --- a/src/arch/arm64/armv8/secmon/psci.c +++ /dev/null @@ -1,705 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <gic.h> -#include <string.h> -#include <stdlib.h> -#include <smp/spinlock.h> -#include <arch/cpu.h> -#include <arch/psci.h> -#include <arch/smc.h> -#include <arch/transition.h> -#include <arch/lib_helpers.h> -#include <console/console.h> -#include "secmon.h" - -DECLARE_SPIN_LOCK(psci_spinlock); - -/* Root of PSCI node tree. */ -static struct psci_node psci_root; - -/* Array of all the psci_nodes in system. */ -static size_t psci_num_nodes; -static struct psci_node **psci_nodes; - -static inline void psci_lock(void) -{ - spin_lock(&psci_spinlock); -} - -static inline void psci_unlock(void) -{ - spin_unlock(&psci_spinlock); -} - -static inline int psci_state_locked(const struct psci_node *e) -{ - return e->state; -} - -static inline void psci_set_state_locked(struct psci_node *e, int s) -{ - e->state = s; -} - -static struct psci_node *psci_node_lookup(uint64_t mpidr, int level) -{ - size_t i; - - /* The array of node pointers are in depth-first order of the tree. */ - for (i = 0; i < psci_num_nodes; i++) { - struct psci_node *current = psci_nodes[i]; - - if (current->mpidr > mpidr) - break; - if (current->mpidr < mpidr) - continue; - if (current->level == level) - return current; - } - return NULL; -} - -static inline struct psci_node *node_self(void) -{ - return psci_node_lookup(cpu_info()->mpidr, PSCI_AFFINITY_LEVEL_0); -} - -/* Find the ancestor of node affected by a state transition limited by level. */ -static struct psci_node *psci_find_ancestor(struct psci_node *e, int level, - int state) -{ - struct psci_node *p; - - /* If all siblings of the node are already off then parent can be - * set to off as well. */ - if (state == PSCI_STATE_OFF) { - while (1) { - size_t i; - struct psci_node *s; - - if (psci_root_node(e)) - return e; - - p = psci_node_parent(e); - - if (p->level > level) - return e; - - for (i = 0; i < p->children.num; i++) { - s = &p->children.nodes[i]; - /* Don't check target. */ - if (s == e) - continue; - if (psci_state_locked(s) != PSCI_STATE_OFF) - return e; - } - - e = p; - } - } - - /* All ancestors in state OFF are affected. */ - if (state == PSCI_STATE_ON_PENDING) { - while (1) { - /* At the root. Return last affected node. */ - if (psci_root_node(e)) - return e; - - p = psci_node_parent(e); - - if (p->level > level) - return e; - - /* This parent is already ON. */ - if (psci_state_locked(p) != PSCI_STATE_OFF) - return e; - - e = p; - } - } - - /* Default to returning node passed in. */ - return e; -} - -static void psci_set_hierarchy_state(struct psci_node *from, - struct psci_node *to, - int state) -{ - struct psci_node *end; - - end = psci_node_parent(to); - - while (from != end) { - /* Raced with another CPU as state is already set. */ - if (psci_state_locked(from) == state) - break; - psci_set_state_locked(from, state); - from = psci_node_parent(from); - } -} - -static void psci_cpu_on_callback(void *arg) -{ - struct exc_state state; - int target_el; - struct psci_node *e = arg; - - psci_lock(); - psci_set_hierarchy_state(e, e->cpu_state.ancestor, PSCI_STATE_ON); - psci_unlock(); - - /* Target EL is determined if HVC is enabled or not. */ - target_el = (raw_read_scr_el3() & SCR_HVC_ENABLE) ? EL2 : EL1; - - memset(&state, 0, sizeof(state)); - state.elx.spsr = get_eret_el(target_el, SPSR_USE_H); - transition_with_entry(e->cpu_state.startup.run, - e->cpu_state.startup.arg, &state); -} - -static void psci_cpu_on_prepare(struct psci_cmd *cmd, - const struct cpu_action *a) -{ - struct psci_node *ancestor; - struct psci_node *e; - int state = PSCI_STATE_ON_PENDING; - - e = cmd->target; - e->cpu_state.startup = *a; - ancestor = psci_find_ancestor(e, PSCI_AFFINITY_LEVEL_HIGHEST, state); - e->cpu_state.ancestor = ancestor; - cmd->ancestor = ancestor; -} - -static int psci_schedule_cpu_on(struct psci_node *e) -{ - struct cpu_info *ci; - struct cpu_action action = { - .run = &psci_cpu_on_callback, - .arg = e, - }; - - ci = e->cpu_state.ci; - if (ci == NULL || arch_run_on_cpu_async(ci->id, &action)) { - psci_set_hierarchy_state(e, e->cpu_state.ancestor, - PSCI_STATE_OFF); - return PSCI_RET_INTERNAL_FAILURE; - } - - return PSCI_RET_SUCCESS; -} - -static void psci_cpu_resume_prepare(struct psci_cmd *cmd, - const struct cpu_action *a) -{ - struct psci_node *ancestor; - struct psci_node *e; - int state = PSCI_STATE_ON_PENDING; - - e = cmd->target; - e->cpu_state.resume = *a; - ancestor = psci_find_ancestor(e, PSCI_AFFINITY_LEVEL_HIGHEST, state); - e->cpu_state.ancestor = ancestor; - cmd->ancestor = ancestor; -} - -static void psci_schedule_cpu_resume(struct psci_node *e) -{ - struct cpu_info *ci; - struct cpu_action *action; - - if (e->cpu_state.resume.run == NULL) - return; - - ci = e->cpu_state.ci; - action = &e->cpu_state.resume; - - arch_run_on_cpu(ci->id, action); -} - -void psci_turn_on_self(const struct cpu_action *action) -{ - struct psci_node *e = node_self(); - struct psci_cmd cmd = { - .type = PSCI_CMD_ON, - }; - - if (e == NULL) { - printk(BIOS_ERR, "Couldn't turn on self: mpidr %llx\n", - cpu_info()->mpidr); - return; - } - - cmd.target = e; - - psci_lock(); - psci_cpu_on_prepare(&cmd, action); - psci_set_hierarchy_state(e, cmd.ancestor, PSCI_STATE_ON_PENDING); - psci_unlock(); - - psci_schedule_cpu_on(e); -} - -void psci_cpu_entry(void) -{ - gic_enable(); - - /* - * Just wait for an action to be performed. - */ - psci_schedule_cpu_resume(node_self()); - secmon_wait_for_action(); -} - -static void psci_cpu_resume(void *arg) -{ - uint64_t power_state = (uint64_t)arg; - struct psci_node *e; - struct psci_power_state state; - struct psci_cmd cmd = { - .type = PSCI_CMD_RESUME, - }; - - psci_power_state_unpack(power_state, &state); - - psci_lock(); - - e = node_self(); - /* clear the resume action after resume */ - e->cpu_state.resume.run = NULL; - e->cpu_state.resume.arg = NULL; - - cmd.target = e; - cmd.state = &state; - soc_psci_ops.cmd_prepare(&cmd); - - psci_unlock(); - - soc_psci_ops.cmd_commit(&cmd); - - psci_lock(); - psci_set_hierarchy_state(e, e->cpu_state.ancestor, PSCI_STATE_ON); - psci_unlock(); - - psci_schedule_cpu_on(node_self()); -} - -static void psci_cpu_suspend(struct psci_func *pf) -{ - uint64_t power_state; - uint64_t entry; - uint64_t context_id; - struct psci_node *e; - struct psci_power_state state; - struct cpu_action action; - struct cpu_action resume_action; - struct psci_cmd cmd = { - .type = PSCI_CMD_SUSPEND, - }; - int ret; - - power_state = psci64_arg(pf, PSCI_PARAM_0); - entry = psci64_arg(pf, PSCI_PARAM_1); - context_id = psci64_arg(pf, PSCI_PARAM_2); - psci_power_state_unpack(power_state, &state); - - psci_lock(); - - e = node_self(); - cmd.target = e; - cmd.state = &state; - action.run = (void *)entry; - action.arg = (void *)context_id; - resume_action.run = &psci_cpu_resume; - resume_action.arg = (void*)power_state; - - psci_cpu_on_prepare(&cmd, &action); - psci_cpu_resume_prepare(&cmd, &resume_action); - - ret = soc_psci_ops.cmd_prepare(&cmd); - - if (ret == PSCI_RET_SUCCESS) - psci_set_hierarchy_state(e, cmd.ancestor, PSCI_STATE_OFF); - - psci_unlock(); - - if (ret != PSCI_RET_SUCCESS) - return psci32_return(pf, ret); - - gic_disable(); - - ret = soc_psci_ops.cmd_commit(&cmd); - - /* PSCI_POWER_STATE_TYPE_STANDBY mode only */ - - psci_lock(); - resume_action.run = NULL; - resume_action.arg = NULL; - psci_cpu_resume_prepare(&cmd, &resume_action); - psci_unlock(); - - if (ret != PSCI_RET_SUCCESS) - return psci32_return(pf, ret); - - psci_lock(); - psci_set_hierarchy_state(e, e->cpu_state.ancestor, PSCI_STATE_ON); - psci_unlock(); - - psci32_return(pf, PSCI_RET_SUCCESS); -} - -static void psci_cpu_on(struct psci_func *pf) -{ - uint64_t entry; - uint64_t target_mpidr; - uint64_t context_id; - int cpu_state; - int ret; - struct psci_node *e; - struct cpu_action action; - struct psci_cmd cmd = { - .type = PSCI_CMD_ON, - }; - - target_mpidr = psci64_arg(pf, PSCI_PARAM_0); - entry = psci64_arg(pf, PSCI_PARAM_1); - context_id = psci64_arg(pf, PSCI_PARAM_2); - - e = psci_node_lookup(target_mpidr, PSCI_AFFINITY_LEVEL_0); - - if (e == NULL) { - psci32_return(pf, PSCI_RET_INVALID_PARAMETERS); - return; - } - - psci_lock(); - cpu_state = psci_state_locked(e); - - if (cpu_state == PSCI_STATE_ON_PENDING) { - psci32_return(pf, PSCI_RET_ON_PENDING); - psci_unlock(); - return; - } else if (cpu_state == PSCI_STATE_ON) { - psci32_return(pf, PSCI_RET_ALREADY_ON); - psci_unlock(); - return; - } - - cmd.target = e; - action.run = (void *)entry; - action.arg = (void *)context_id; - psci_cpu_on_prepare(&cmd, &action); - - ret = soc_psci_ops.cmd_prepare(&cmd); - - if (ret == PSCI_RET_SUCCESS) - psci_set_hierarchy_state(e, cmd.ancestor, - PSCI_STATE_ON_PENDING); - - psci_unlock(); - - if (ret != PSCI_RET_SUCCESS) - return psci32_return(pf, ret); - - ret = soc_psci_ops.cmd_commit(&cmd); - - if (ret != PSCI_RET_SUCCESS) { - psci_lock(); - psci_set_hierarchy_state(e, cmd.ancestor, PSCI_STATE_OFF); - psci_unlock(); - return psci32_return(pf, ret); - } - - psci32_return(pf, psci_schedule_cpu_on(e)); -} - -static int psci_turn_off_node(struct psci_node *e, int level, - int state_id) -{ - int ret; - struct psci_cmd cmd = { - .type = PSCI_CMD_OFF, - .state_id = state_id, - .target = e, - }; - - psci_lock(); - - cmd.ancestor = psci_find_ancestor(e, level, PSCI_STATE_OFF); - - ret = soc_psci_ops.cmd_prepare(&cmd); - - if (ret == PSCI_RET_SUCCESS) - psci_set_hierarchy_state(e, cmd.ancestor, PSCI_STATE_OFF); - - psci_unlock(); - - if (ret != PSCI_RET_SUCCESS) - return ret; - - gic_disable(); - - /* Should never return. */ - ret = soc_psci_ops.cmd_commit(&cmd); - - /* Adjust ret to be an error. */ - if (ret == PSCI_RET_SUCCESS) - ret = PSCI_RET_INTERNAL_FAILURE; - - /* Turn things back on. */ - psci_lock(); - psci_set_hierarchy_state(e, cmd.ancestor, PSCI_STATE_ON); - psci_unlock(); - - return ret; -} - -int psci_turn_off_self(void) -{ - struct psci_node *e = node_self(); - - if (e == NULL) { - printk(BIOS_ERR, "No PSCI node for MPIDR %llx.\n", - cpu_info()->mpidr); - return PSCI_RET_INTERNAL_FAILURE; - } - - /* -1 state id indicates to SoC to make its own decision for - * internal state when powering off the node. */ - return psci_turn_off_node(e, PSCI_AFFINITY_LEVEL_HIGHEST, -1); -} - -static int psci_handler(struct smc_call *smc) -{ - struct psci_func pf_storage; - struct psci_func *pf = &pf_storage; - - psci_func_init(pf, smc); - - switch (pf->id) { - case PSCI_CPU_SUSPEND64: - psci_cpu_suspend(pf); - break; - case PSCI_CPU_ON64: - psci_cpu_on(pf); - break; - case PSCI_CPU_OFF32: - psci32_return(pf, psci_turn_off_self()); - break; - default: - psci32_return(pf, PSCI_RET_NOT_SUPPORTED); - break; - } - - return 0; -} - -static void psci_link_cpu_info(void *arg) -{ - struct psci_node *e = node_self(); - - if (e == NULL) { - printk(BIOS_ERR, "No PSCI node for MPIDR %llx.\n", - cpu_info()->mpidr); - return; - } - - e->cpu_state.ci = cpu_info(); -} - -static int psci_init_node(struct psci_node *e, - struct psci_node *parent, - int level, uint64_t mpidr) -{ - size_t i; - uint64_t mpidr_inc; - struct psci_node_group *ng; - size_t num_children; - - memset(e, 0, sizeof(*e)); - e->mpidr = mpidr; - psci_set_state_locked(e, PSCI_STATE_OFF); - e->parent = parent; - e->level = level; - - if (level == PSCI_AFFINITY_LEVEL_0) - return 0; - - num_children = soc_psci_ops.children_at_level(level, mpidr); - - if (num_children == 0) - return 0; - - ng = &e->children; - ng->num = num_children; - ng->nodes = malloc(ng->num * sizeof(struct psci_node)); - if (ng->nodes == NULL) { - printk(BIOS_DEBUG, "PSCI: Allocation failure at level %d\n", - level); - return -1; - } - - /* Switch to next level below. */ - level = psci_level_below(level); - mpidr_inc = mpidr_mask(!!(level == PSCI_AFFINITY_LEVEL_3), - !!(level == PSCI_AFFINITY_LEVEL_2), - !!(level == PSCI_AFFINITY_LEVEL_1), - !!(level == PSCI_AFFINITY_LEVEL_0)); - - for (i = 0; i < ng->num; i++) { - struct psci_node *c = &ng->nodes[i]; - - /* Recursively initialize the nodes. */ - if (psci_init_node(c, e, level, mpidr)) - return -1; - mpidr += mpidr_inc; - } - - return 0; -} - -static size_t psci_count_children(struct psci_node *e) -{ - size_t i; - size_t count; - - if (e->level == PSCI_AFFINITY_LEVEL_0) - return 0; - - count = e->children.num; - for (i = 0; i < e->children.num; i++) - count += psci_count_children(&e->children.nodes[i]); - - return count; -} - -static size_t psci_write_nodes(struct psci_node *e, size_t index) -{ - size_t i; - - /* - * Recursively save node pointers in array. Node pointers are - * ordered in ascending mpidr and descending level within same mpidr. - * i.e. each node is saved in depth-first order of the tree. - */ - if (e->level != PSCI_AFFINITY_ROOT) { - psci_nodes[index] = e; - index++; - } - - if (e->level == PSCI_AFFINITY_LEVEL_0) - return index; - - for (i = 0; i < e->children.num; i++) - index = psci_write_nodes(&e->children.nodes[i], index); - - return index; -} - -static int psci_allocate_nodes(void) -{ - int level; - size_t num_children; - uint64_t mpidr; - struct psci_node *e; - - mpidr = 0; - level = PSCI_AFFINITY_ROOT; - - /* Find where the root should start. */ - while (psci_level_below(level) >= PSCI_AFFINITY_LEVEL_0) { - num_children = soc_psci_ops.children_at_level(level, mpidr); - - if (num_children == 0) { - printk(BIOS_ERR, "PSCI: No children at level %d!\n", - level); - return -1; - } - - /* The root starts where the affinity levels branch. */ - if (num_children > 1) - break; - - level = psci_level_below(level); - } - - if (psci_init_node(&psci_root, NULL, level, mpidr)) { - printk(BIOS_ERR, "PSCI init node failure.\n"); - return -1; - } - - num_children = psci_count_children(&psci_root); - /* Count the root node if isn't a fake node. */ - if (psci_root.level != PSCI_AFFINITY_ROOT) - num_children++; - - psci_nodes = malloc(num_children * sizeof(void *)); - psci_num_nodes = num_children; - - if (psci_nodes == NULL) { - printk(BIOS_ERR, "PSCI node pointer array failure.\n"); - return -1; - } - - num_children = psci_write_nodes(&psci_root, 0); - if (num_children != psci_num_nodes) { - printk(BIOS_ERR, "Wrong nodes written: %zd vs %zd.\n", - num_children, psci_num_nodes); - return -1; - } - - /* - * By default all nodes are set to PSCI_STATE_OFF. In order not - * to race with other CPUs turning themselves off set the BSPs - * affinity node to ON. - */ - e = node_self(); - if (e == NULL) { - printk(BIOS_ERR, "No PSCI node for BSP.\n"); - return -1; - } - psci_set_state_locked(e, PSCI_STATE_ON); - - return 0; -} - -void psci_init(uintptr_t cpu_on_entry) -{ - struct cpu_action action = { - .run = &psci_link_cpu_info, - }; - - if (psci_allocate_nodes()) { - printk(BIOS_ERR, "PSCI support not enabled.\n"); - return; - } - - if (arch_run_on_all_cpus_async(&action)) - printk(BIOS_ERR, "Error linking cpu_info to PSCI nodes.\n"); - - /* Register PSCI handlers. */ - if (smc_register_range(PSCI_CPU_SUSPEND32, PSCI_CPU_ON32, - &psci_handler)) - printk(BIOS_ERR, "Couldn't register PSCI handler.\n"); - - if (smc_register_range(PSCI_CPU_SUSPEND64, PSCI_CPU_ON64, - &psci_handler)) - printk(BIOS_ERR, "Couldn't register PSCI handler.\n"); - - /* Inform SoC layer of CPU_ON entry point. */ - psci_soc_init(cpu_on_entry); -} diff --git a/src/arch/arm64/armv8/secmon/secmon.h b/src/arch/arm64/armv8/secmon/secmon.h deleted file mode 100644 index 26ce9fc..0000000 --- a/src/arch/arm64/armv8/secmon/secmon.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SECMON_SECMON_H__ -#define __SECMON_SECMON_H__ - -/* - * The secmon_trampoline() switches mode to EL3t, reinitializing both - * EL3t and EL3h stacks. - */ -void secmon_trampoline(void *entry, void *arg); - -/* Wait for action to take place. */ -void secmon_wait_for_action(void); - -#endif /* __SECMON_SECMON_H__ */ diff --git a/src/arch/arm64/armv8/secmon/secmon_init.c b/src/arch/arm64/armv8/secmon/secmon_init.c deleted file mode 100644 index 2ac59fb..0000000 --- a/src/arch/arm64/armv8/secmon/secmon_init.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/barrier.h> -#include <arch/cache.h> -#include <arch/io.h> -#include <arch/exception.h> -#include <arch/lib_helpers.h> -#include <arch/psci.h> -#include <arch/secmon.h> -#include <arch/smc.h> -#include <arch/startup.h> -#include <console/console.h> -#include <stddef.h> -#include "secmon.h" - -static void secmon_init(struct secmon_params *params, int bsp); - -static void secmon_init_bsp(void *arg) -{ - secmon_init(arg, 1); -} - -static void secmon_init_nonbsp(void *arg) -{ - secmon_init(arg, 0); -} - -/* - * This variable holds entry point for secmon init code. Once the stacks are - * setup by the stage_entry.S, it jumps to c_entry. - */ -void (*c_entry[2])(void *) = { &secmon_init_bsp, &secmon_init_nonbsp }; - -static void cpu_resume(void *unused) -{ - psci_cpu_entry(); -} - -static void cpu_resume_init(void) -{ - /* Change entry points into secmon. */ - c_entry[0] = c_entry[1] = cpu_resume; - dcache_clean_by_mva(&c_entry, sizeof(c_entry)); - - /* Back up state. */ - startup_save_cpu_data(); -} - -static void start_up_cpu(void *arg) -{ - struct secmon_params *params = arg; - struct cpu_action *action; - - if (cpu_is_bsp()) - action = &params->bsp; - else - action = &params->secondary; - - - if (action->run == NULL) - psci_turn_off_self(); - - psci_turn_on_self(action); -} - -static void cpu_init(int bsp) -{ - struct cpu_info *ci = cpu_info(); - - ci->id = smp_processor_id(); - cpu_mark_online(ci); - - if (bsp) - cpu_set_bsp(); -} - -static void wait_for_all_cpus(size_t expected) -{ - while (cpus_online() != expected) - ; -} - -static void secmon_init(struct secmon_params *params, int bsp) -{ - struct cpu_action action = { - .run = start_up_cpu, - .arg = params, - }; - - exception_hwinit(); - cpu_init(bsp); - - if (!cpu_is_bsp()) - secmon_wait_for_action(); - - /* Wait for all CPUs to enter secmon. */ - wait_for_all_cpus(params->online_cpus); - - smc_init(); - psci_init((uintptr_t)arm64_cpu_startup_resume); - - /* Initialize the resume path. */ - cpu_resume_init(); - - /* Make sure all non-BSP CPUs take action before the BSP. */ - arch_run_on_all_cpus_but_self_async(&action); - /* Turn on BSP. */ - start_up_cpu(params); - - printk(BIOS_ERR, "CPU turn on failed for BSP.\n"); - - secmon_wait_for_action(); -} - -void secmon_wait_for_action(void) -{ - arch_cpu_wait_for_action(); -} diff --git a/src/arch/arm64/armv8/secmon/smc.c b/src/arch/arm64/armv8/secmon/smc.c deleted file mode 100644 index 6fa6294..0000000 --- a/src/arch/arm64/armv8/secmon/smc.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <stdlib.h> -#include <arch/cpu.h> -#include <arch/smc.h> -#include <arch/exception.h> -#include <arch/lib_helpers.h> -#include <console/console.h> - -enum { - /* SMC called from AARCH32 */ - EC_SMC_AARCH32 = 0x13, - /* SMC called from AARCH64 */ - EC_SMC_AARCH64 = 0x17, - - SMC_NUM_RANGES = 8, -}; - -struct smc_range { - uint32_t func_begin; - uint32_t func_end; - int (*handler)(struct smc_call *); -}; - -struct smc_ranges { - size_t used; - struct smc_range handlers[SMC_NUM_RANGES]; -}; - -static struct smc_ranges smc_functions; - -static struct smc_range *smc_handler_by_function(uint32_t fid) -{ - int i; - - for (i = 0; i < smc_functions.used; i++) { - struct smc_range *r = &smc_functions.handlers[i]; - - if (fid >= r->func_begin && fid <= r->func_end) - return r; - } - - return NULL; -} - -int smc_register_range(uint32_t min, uint32_t max, int (*h)(struct smc_call *)) -{ - struct smc_range *r; - - if (smc_functions.used == SMC_NUM_RANGES) - return -1; - - if (min > max) - return -1; - - /* This check isn't exhaustive but it's fairly quick. */ - if (smc_handler_by_function(min) || smc_handler_by_function(max)) - return -1; - - r = &smc_functions.handlers[smc_functions.used]; - r->func_begin = min; - r->func_end = max; - r->handler = h; - smc_functions.used++; - - return 0; -} - -static int smc_cleanup(struct exc_state *state, struct smc_call *smc, int ret) -{ - memcpy(&state->regs.x, &smc->results, sizeof(smc->results)); - - return ret; -} - -static int smc_return_with_error(struct exc_state *state, struct smc_call *smc) -{ - smc32_return(smc, SMC_UNKNOWN_FUNC); - return smc_cleanup(state, smc, EXC_RET_HANDLED); -} - -static int smc_handler(struct exc_state *state, uint64_t vector_id) -{ - struct smc_call smc_storage; - struct smc_call *smc = &smc_storage; - uint32_t exception_class; - uint32_t esr; - struct smc_range *r; - - memcpy(&smc->args, &state->regs.x, sizeof(smc->args)); - memcpy(&smc->results, &state->regs.x, sizeof(smc->results)); - - esr = raw_read_esr_el3(); - exception_class = (esr >> 26) & 0x3f; - - /* No support for SMC calls from AARCH32 */ - if (exception_class == EC_SMC_AARCH32) - return smc_return_with_error(state, smc); - - /* Check to ensure this is an SMC from AARCH64. */ - if (exception_class != EC_SMC_AARCH64) - return EXC_RET_IGNORED; - - /* Ensure immediate value is 0. */ - if ((esr & 0xffff) != 0) - return smc_return_with_error(state, smc); - - r = smc_handler_by_function(smc_function_id(smc)); - - if (r != NULL) { - if (!r->handler(smc)) - return smc_cleanup(state, smc, EXC_RET_HANDLED); - } - - return smc_return_with_error(state, smc); -} - -/* SMC calls can be generated by 32-bit or 64-bit code. */ -static struct exception_handler smc_handler64 = { - .handler = &smc_handler, -}; - -static struct exception_handler smc_handler32 = { - .handler = &smc_handler, -}; - -static void enable_smc(void *arg) -{ - uint32_t scr; - - /* Enable SMC */ - scr = raw_read_scr_el3(); - scr &= ~(SCR_SMC_MASK); - scr |= SCR_SMC_ENABLE; - raw_write_scr_el3(scr); -} - -void smc_init(void) -{ - struct cpu_action action = { - .run = enable_smc, - }; - - arch_run_on_all_cpus_async(&action); - - /* Register SMC handlers. */ - exception_handler_register(EXC_VID_LOW64_SYNC, &smc_handler64); - exception_handler_register(EXC_VID_LOW32_SYNC, &smc_handler32); -} diff --git a/src/arch/arm64/armv8/secmon/trampoline.S b/src/arch/arm64/armv8/secmon/trampoline.S deleted file mode 100644 index 5db904a..0000000 --- a/src/arch/arm64/armv8/secmon/trampoline.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/asm.h> - -/* - * Call entry(arg) after reinitializing stack state. - * void secmon_trampoline(void *entry, void *arg); - */ -ENTRY(secmon_trampoline) - mov x22, x0 /* x22 = function pointer */ - mov x23, x1 /* x23 = argument */ - bl smp_processor_id /* x0 = cpu */ - mov x24, x0 - - /* Set the exception stack for this cpu. */ - bl cpu_get_exception_stack - msr SPSel, #1 - isb - mov sp, x0 - - /* Have stack pointer use SP_EL0. */ - msr SPSel, #0 - isb - - /* Set stack for this cpu. */ - mov x0, x24 /* x0 = cpu */ - bl cpu_get_stack - mov sp, x0 - - /* Call the function with specified argument. */ - mov x1, x22 - mov x0, x23 - br x1 -ENDPROC(secmon_trampoline) diff --git a/src/arch/arm64/armv8/secmon_loader.c b/src/arch/arm64/armv8/secmon_loader.c deleted file mode 100644 index 946ca0f..0000000 --- a/src/arch/arm64/armv8/secmon_loader.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * secmon_loader.c: Responsible for loading the rmodule, providing entry point - * and parameter location for the rmodule. - */ - -#include <arch/cache.h> -#include <arch/lib_helpers.h> -#include <arch/secmon.h> -#include <arch/spintable.h> -#include <arch/stages.h> -#include <console/console.h> -#include <rmodule.h> -#include <string.h> - -/* SECMON entry point encoded as an rmodule */ -extern unsigned char _binary_secmon_start[]; - -typedef void (*secmon_entry_t)(struct secmon_params *); - -void __attribute__((weak)) soc_get_secmon_base_size(uint64_t *secmon_base, size_t *secmon_size) -{ - /* Default weak implementation initializes to 0 */ - *secmon_base = 0; - *secmon_size = 0; -} - -static secmon_entry_t secmon_load_rmodule(void) -{ - struct rmodule secmon_mod; - uint64_t secmon_base; - size_t secmon_size; - - /* Get base address and size of the area available for secure monitor - * rmodule. - */ - soc_get_secmon_base_size(&secmon_base, &secmon_size); - - if ((secmon_base == 0) || (secmon_size == 0)) { - printk(BIOS_ERR, "ARM64: secmon_base / secmon_size invalid\n"); - return NULL; - } - - printk(BIOS_DEBUG,"secmon_base:%lx,secmon_size:%lx\n", - (unsigned long)secmon_base, (unsigned long)secmon_size); - - /* Fail if can't parse secmon module */ - if (rmodule_parse(&_binary_secmon_start, &secmon_mod)) { - printk(BIOS_ERR, "ARM64: secmon_mod not found\n"); - return NULL; - } - - /* Load rmodule at secmon_base */ - if (rmodule_load((void *)secmon_base, &secmon_mod)) { - printk(BIOS_ERR, "ARM64:secmon_mod cannot load\n"); - return NULL; - } - - /* Identify the entry point for secure monitor */ - return rmodule_entry(&secmon_mod); -} - -struct secmon_runit { - secmon_entry_t entry; - struct secmon_params params; -}; - -static void secmon_start(void *arg) -{ - uint32_t scr; - secmon_entry_t entry; - struct secmon_params *p; - struct secmon_runit *r = arg; - - entry = r->entry; - p = &r->params; - - /* Obtain secondary entry point for non-BSP CPUs. */ - if (!cpu_is_bsp()) - entry = secondary_entry_point(entry); - - printk(BIOS_DEBUG, "CPU%x entering secure monitor %p.\n", - cpu_info()->id, entry); - - /* We want to enforce the following policies: - * NS bit is set for lower EL - */ - scr = raw_read_scr_el3(); - scr |= SCR_NS; - raw_write_scr_el3(scr); - - /* Invalidate instruction cache. Necessary for non-BSP. */ - icache_invalidate_all(); - entry(p); -} - -static void fill_secmon_params(struct secmon_params *p, - void (*bsp_entry)(void *), void *bsp_arg) -{ - const struct spintable_attributes *spin_attrs; - - memset(p, 0, sizeof(*p)); - - p->online_cpus = cpus_online(); - - spin_attrs = spintable_get_attributes(); - - if (spin_attrs != NULL) { - p->secondary.run = spin_attrs->entry; - p->secondary.arg = spin_attrs->addr; - } - - p->bsp.run = bsp_entry; - p->bsp.arg = bsp_arg; -} - -void secmon_run(void (*entry)(void *), void *cb_tables) -{ - static struct secmon_runit runit; - struct cpu_action action = { - .run = secmon_start, - .arg = &runit, - }; - - printk(BIOS_SPEW, "payload jump @ %p\n", entry); - - if (get_current_el() != EL3) { - printk(BIOS_DEBUG, "Secmon Error: Can only be loaded in EL3\n"); - return; - } - - runit.entry = secmon_load_rmodule(); - - if (runit.entry == NULL) - die("ARM64 Error: secmon load error"); - - printk(BIOS_DEBUG, "ARM64: Loaded the el3 monitor...jumping to %p\n", - runit.entry); - - fill_secmon_params(&runit.params, entry, cb_tables); - - arch_run_on_all_cpus_but_self_async(&action); - secmon_start(&runit); -} diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index ba60260..6076e67 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -15,7 +15,6 @@ #include <arch/cache.h> #include <arch/lib_helpers.h> -#include <arch/secmon.h> #include <arch/stages.h> #include <arch/spintable.h> #include <arch/transition.h> @@ -37,8 +36,6 @@ static void run_payload(struct prog *prog) if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr); - else if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_MONITOR)) - secmon_run(doit, arg); else { uint8_t current_el = get_current_el(); diff --git a/src/arch/arm64/cpu/Makefile.inc b/src/arch/arm64/cpu/Makefile.inc index 644aef3..4b249c7 100644 --- a/src/arch/arm64/cpu/Makefile.inc +++ b/src/arch/arm64/cpu/Makefile.inc @@ -17,5 +17,4 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) ramstage-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S -secmon-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S endif diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index 318f998..2ea0a19 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -28,7 +28,6 @@ PHDRS TARGET(binary) #endif -/* secmon uses rmodules */ #if ENV_RMODULE ENTRY(_start) #else diff --git a/src/arch/arm64/include/arch/psci.h b/src/arch/arm64/include/arch/psci.h deleted file mode 100644 index 4d9f051..0000000 --- a/src/arch/arm64/include/arch/psci.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_PSCI_H__ -#define __ARCH_PSCI_H__ - -#include <stdint.h> -#include <arch/cpu.h> -#include <arch/smc.h> - -/* PSCI v0.2 power state encoding for CPU_SUSPEND function */ -#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff -#define PSCI_0_2_POWER_STATE_ID_SHIFT 0 -#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 -#define PSCI_0_2_POWER_STATE_TYPE_MASK \ - (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) -#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 -#define PSCI_0_2_POWER_STATE_AFFL_MASK \ - (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) - -#define PSCI_POWER_STATE_TYPE_STANDBY 0 -#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1 - -struct psci_power_state { - u16 id; - u8 type; - u8 affinity_level; -}; - -/* Return Values */ -enum { - PSCI_RET_SUCCESS = 0, - PSCI_RET_NOT_SUPPORTED = -1, - PSCI_RET_INVALID_PARAMETERS = -2, - PSCI_RET_DENIED = -3, - PSCI_RET_ALREADY_ON = -4, - PSCI_RET_ON_PENDING = -5, - PSCI_RET_INTERNAL_FAILURE = -6, - PSCI_RET_NOT_PRESENT = -7, - PSCI_RET_DISABLED = -8, -}; - -/* Generic PSCI state. */ -enum { - PSCI_STATE_OFF = 0, - PSCI_STATE_ON_PENDING, - PSCI_STATE_ON, -}; - -/* Affinity level support. */ -enum { - PSCI_AFFINITY_LEVEL_0, - PSCI_AFFINITY_LEVEL_1, - PSCI_AFFINITY_LEVEL_2, - PSCI_AFFINITY_LEVEL_3, - PSCI_AFFINITY_ROOT, - PSCI_AFFINITY_LEVEL_HIGHEST = PSCI_AFFINITY_ROOT, -}; - -static inline int psci_level_below(int level) -{ - return level - 1; -} - -struct psci_node; - -struct psci_cpu_state { - struct cpu_info *ci; - struct cpu_action startup; - struct cpu_action resume; - /* Ancestor of target to update state in CPU_ON case. */ - struct psci_node *ancestor; -}; - -struct psci_node_group { - size_t num; - struct psci_node *nodes; -}; - -struct psci_node { - uint64_t mpidr; - /* Affinity level of node. */ - int level; - /* Generic power state of this entity. */ - int state; - /* The SoC can stash its own state accounting in here. */ - int soc_state; - /* Parent of curernt entity. */ - struct psci_node *parent; - /* - * CPUs are leaves in the tree. They don't have children. The - * CPU-specific bits of storage can be shared with the children - * storage. - */ - union { - struct psci_node_group children; - struct psci_cpu_state cpu_state; - }; -}; - -static inline struct psci_node *psci_node_parent(const struct psci_node *n) -{ - return n->parent; -} - -static inline int psci_root_node(const struct psci_node *n) -{ - return psci_node_parent(n) == NULL; -} - -enum { - PSCI_CMD_ON, - PSCI_CMD_OFF, - PSCI_CMD_SUSPEND, - PSCI_CMD_RESUME, -}; - -/* - * PSCI actions are serialized into a command for the SoC to process. There are - * 2 phases of a command being processed: prepare and commit. The prepare() is - * called with the PSCI locks held for the state of the PSCI nodes. If - * successful, the appropriate locks will be dropped and commit() will be - * called with the same structure. It is permissible for the SoC support code - * to modify the struture passed in (e.g. to update the requested state_id to - * reflect dynamic constraints on how deep of a state to enter). - */ -struct psci_cmd { - /* Command type. */ - int type; - /* - * PSCI state id for PSCI_CMD_OFF and PSCI_CMD_STANDBY commands. - * A value of -1 indicates a CPU_OFF request. - */ - int state_id; - struct psci_power_state *state; - /* - * target is the command's target, but it can affect up to the - * ancestor entity. If target == ancestor then it only affects - * target, otherwise all entites up the hierarchy including ancestor. - */ - struct psci_node *target; - struct psci_node *ancestor; -}; - -struct psci_soc_ops { - /* - * Return number of entities one level below given parent affinitly - * level and mpidr. - */ - size_t (*children_at_level)(int parent_level, uint64_t mpidr); - - int (*cmd_prepare)(struct psci_cmd *cmd); - int (*cmd_commit)(struct psci_cmd *cmd); -}; - -/* Each SoC needs to provide the functions in the psci_soc_ops structure. */ -extern struct psci_soc_ops soc_psci_ops; - -/* PSCI Functions. */ -enum { - /* 32-bit System level functions. */ - PSCI_VERSION = SMC_FUNC_FAST32(0x4, 0x0), - PSCI_SYSTEM_OFF = SMC_FUNC_FAST32(0x4, 0x8), - PSCI_SYSTEM_RESET = SMC_FUNC_FAST32(0x4, 0x9), - - /* 32-bit CPU support functions. */ - PSCI_CPU_SUSPEND32 = SMC_FUNC_FAST32(0x4, 0x1), - PSCI_CPU_OFF32 = SMC_FUNC_FAST32(0x4, 0x2), - PSCI_CPU_ON32 = SMC_FUNC_FAST32(0x4, 0x3), - - /* 64-bit CPU support functions. */ - PSCI_CPU_SUSPEND64 = SMC_FUNC_FAST64(0x4, 0x1), - PSCI_CPU_ON64 = SMC_FUNC_FAST64(0x4, 0x3), -}; - -/* Parameter arguments. */ -enum { - PSCI_PARAM_0 = 1, - PSCI_PARAM_1, - PSCI_PARAM_2, - PSCI_PARAM_3, - PSCI_RETURN_0 = 1, - PSCI_RETURN_1, - PSCI_RETURN_2, - PSCI_RETURN_3, -}; - -struct psci_func { - uint32_t id; - struct smc_call *smc; -}; - -static inline void psci_power_state_unpack(uint32_t power_state, - struct psci_power_state *state) -{ - state->id = (power_state & PSCI_0_2_POWER_STATE_ID_MASK) >> - PSCI_0_2_POWER_STATE_ID_SHIFT; - state->type = (power_state & PSCI_0_2_POWER_STATE_TYPE_MASK) >> - PSCI_0_2_POWER_STATE_TYPE_SHIFT; - state->affinity_level = - (power_state & PSCI_0_2_POWER_STATE_AFFL_MASK) >> - PSCI_0_2_POWER_STATE_AFFL_SHIFT; -} - -static inline void psci_func_init(struct psci_func *pf, struct smc_call *smc) -{ - pf->id = smc_function_id(smc); - pf->smc = smc; -} - -static inline uint64_t psci64_arg(struct psci_func *pf, unsigned i) -{ - return smc64_arg(pf->smc, i); -} - -static inline uint32_t psci32_arg(struct psci_func *pf, unsigned i) -{ - return psci64_arg(pf, i); -} - -static inline void psci64_result(struct psci_func *pf, unsigned i, uint64_t v) -{ - smc64_result(pf->smc, i, v); -} - -static inline void psci32_result(struct psci_func *pf, unsigned i, uint32_t v) -{ - uint64_t v64 = v; - psci64_result(pf, i, v64); -} - -static inline void psci32_return(struct psci_func *pf, int32_t val) -{ - psci32_result(pf, 0, val); -} - -static inline void psci64_return(struct psci_func *pf, int64_t val) -{ - psci64_result(pf, 0, val); -} - -void psci_init(uintptr_t cpu_on_entry); -void psci_soc_init(uintptr_t cpu_on_entry); - -/* Turn on the current CPU within the PSCI subsystem. */ -void psci_turn_on_self(const struct cpu_action *action); -int psci_turn_off_self(void); -/* Entry point for CPUs just turning on or waking up. */ -void psci_cpu_entry(void); - -#endif /* __ARCH_PSCI_H__ */ diff --git a/src/arch/arm64/include/arch/smc.h b/src/arch/arm64/include/arch/smc.h deleted file mode 100644 index 90cbdcd..0000000 --- a/src/arch/arm64/include/arch/smc.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_SMC_H__ -#define __ARCH_SMC_H__ - -#include <stdint.h> - -enum { - FUNC_ID_CALL_TYPE_SHIFT = 31, - FUNC_ID_CALL_TYPE_MASK = (1 << FUNC_ID_CALL_TYPE_SHIFT), - FUNC_ID_FASTCALL = (1 << FUNC_ID_CALL_TYPE_SHIFT), - FUNC_ID_STDCALL = (0 << FUNC_ID_CALL_TYPE_SHIFT), - - FUNC_ID_CALL_CONVENTION_SHIFT = 30, - FUNC_ID_CALL_CONVENTION_MASK = (1 << FUNC_ID_CALL_CONVENTION_SHIFT), - FUNC_ID_SMC32 = (0 << FUNC_ID_CALL_CONVENTION_SHIFT), - FUNC_ID_SMC64 = (1 << FUNC_ID_CALL_CONVENTION_SHIFT), - - FUNC_ID_ENTITY_SHIFT = 24, - FUNC_ID_ENTITY_MASK = (0x3f << FUNC_ID_ENTITY_SHIFT), - - FUNC_ID_FUNC_NUMBER_SHIFT = 0, - FUNC_ID_FUNC_NUMBER_MASK = (0xffff << FUNC_ID_FUNC_NUMBER_SHIFT), - - FUNC_ID_MASK = FUNC_ID_CALL_TYPE_MASK | FUNC_ID_CALL_CONVENTION_MASK | - FUNC_ID_ENTITY_MASK | FUNC_ID_FUNC_NUMBER_MASK, - - SMC_NUM_ARGS = 8, /* The last is optional hypervisor id. */ - SMC_NUM_RESULTS = 4, - - SMC_UNKNOWN_FUNC = 0xffffffff, -}; - -#define SMC_FUNC(entity, number, call_convention, call_type) \ - ((call_type) | (call_convention) | \ - ((entity) << FUNC_ID_ENTITY_SHIFT) | (number)) - -#define SMC_FUNC_FAST(entity, number, call_convention) \ - SMC_FUNC((entity), (number), (call_convention), FUNC_ID_FASTCALL) - -#define SMC_FUNC_FAST32(entity, number) \ - SMC_FUNC_FAST((entity), (number), FUNC_ID_SMC32) - -#define SMC_FUNC_FAST64(entity, number) \ - SMC_FUNC_FAST((entity), (number), FUNC_ID_SMC64) - -struct smc_call { - uint64_t args[SMC_NUM_ARGS]; - uint64_t results[SMC_NUM_RESULTS]; -}; - -/* SMC immediate value needs to be 0. */ -/* Check mod AARCHx mode against calling convention. */ - -static inline uint64_t smc64_arg(const struct smc_call *smc, unsigned i) -{ - return smc->args[i]; -} - -static inline uint32_t smc32_arg(const struct smc_call *smc, unsigned i) -{ - return smc64_arg(smc, i); -} - -static inline void smc64_result(struct smc_call *smc, unsigned i, uint64_t v) -{ - smc->results[i] = v; -} - -static inline void smc32_result(struct smc_call *smc, unsigned i, uint32_t v) -{ - uint64_t v64 = v; - smc64_result(smc, i, v64); -} - -static inline void smc32_return(struct smc_call *smc, int32_t v) -{ - smc32_result(smc, 0, v); -} - -static inline uint32_t smc_hypervisor_id(const struct smc_call *smc) -{ - /* Set in W7 */ - return smc32_arg(smc, 7); -} - -static inline uint32_t smc_session_id(const struct smc_call *smc) -{ - /* Set in W6 */ - return smc32_arg(smc, 6); -} - -static inline uint32_t smc_function_id(const struct smc_call *smc) -{ - /* Function ID in W0. */ - return smc32_arg(smc, 0) & FUNC_ID_MASK; -} - -/* Initialize the SMC layer. */ -void smc_init(void); - -/* Register a handler for a given function range, inclusive. */ -int smc_register_range(uint32_t min, uint32_t max, int (*)(struct smc_call *)); - -#endif /* __ARCH_SMC_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/secmon.h b/src/arch/arm64/include/armv8/arch/secmon.h deleted file mode 100644 index c100de5..0000000 --- a/src/arch/arm64/include/armv8/arch/secmon.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM64_ARMV8_SECMON__ -#define __ARCH_ARM64_ARMV8_SECMON__ - -#include <arch/cpu.h> - -struct secmon_params { - size_t online_cpus; - struct cpu_action bsp; - struct cpu_action secondary; -}; - -void secmon_run(void (*entry)(void *), void *arg); -void soc_get_secmon_base_size(uint64_t *secmon_base, size_t *secmon_size); - -#endif /*__ARCH_ARM64_ARMV8_SECMON__ */ diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 35d1278..79db9dd 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -84,7 +84,7 @@ ENDPROC(cpu_get_exception_stack) */ /* * IMPORTANT: Ensure x25 is not corrupted because it saves the argument to - * secmon + * any rmodules. */ ENTRY(arm64_c_environment) bl smp_processor_id /* x0 = cpu */ @@ -134,7 +134,7 @@ ENDPROC(arm64_c_environment) ENTRY(_start) split_bsp_path - /* Save the arguments to secmon in x25 */ + /* Save any arguments to current rmodule in x25 */ mov x25, x0 b arm64_c_environment ENDPROC(_start) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a5f4318..b236578 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -21,7 +21,3 @@ romstage-y += die.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += die.c - -secmon-y += vtxprintf.c printk.c -secmon-y += init.c console.c -secmon-y += die.c diff --git a/src/console/init.c b/src/console/init.c index ed1f056..7e7c5ac 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -53,8 +53,6 @@ void console_init(void) "ramstage" #elif ENV_VERSTAGE "verstage" -#elif ENV_SECMON - "secmon" #else "UNKNOWN" #endif diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 91cc190..fc33ee9 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_DRIVERS_UART),y) romstage-y += util.c ramstage-y += util.c bootblock-y += util.c -secmon-y += util.c verstage-y += util.c smm-$(CONFIG_DEBUG_SMI) += util.c diff --git a/src/include/console/console.h b/src/include/console/console.h index c304206..7704899 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -47,8 +47,8 @@ void __attribute__ ((noreturn)) die(const char *msg); #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \ - ENV_SECMON || ENV_VERSTAGE || \ - ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) + ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || \ + (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_ENABLE__ void console_init(void); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 7da0e87..8458086 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -53,7 +53,7 @@ void oxford_remap(unsigned int new_base); #define __CONSOLE_SERIAL_ENABLE__ CONFIG_CONSOLE_SERIAL && \ (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \ - ENV_SECMON || (ENV_SMM && CONFIG_DEBUG_SMI)) + (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } diff --git a/src/include/rules.h b/src/include/rules.h index a18f2f3..315a65e 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -24,7 +24,6 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_SECMON 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 @@ -33,7 +32,6 @@ #define ENV_ROMSTAGE 1 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_SECMON 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 @@ -42,16 +40,6 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 1 -#define ENV_SECMON 0 -#define ENV_VERSTAGE 0 -#define ENV_RMODULE 0 - -#elif defined(__SECMON__) -#define ENV_BOOTBLOCK 0 -#define ENV_ROMSTAGE 0 -#define ENV_RAMSTAGE 0 -#define ENV_SMM 0 -#define ENV_SECMON 1 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 @@ -60,7 +48,6 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_SECMON 0 #define ENV_VERSTAGE 1 #define ENV_RMODULE 0 @@ -69,7 +56,6 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 -#define ENV_SECMON 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 @@ -78,7 +64,6 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_SECMON 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 1 @@ -93,7 +78,6 @@ #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 0 #define ENV_SMM 0 -#define ENV_SECMON 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e9f36f6..7b90819 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -164,14 +164,12 @@ bootblock-y += version.c romstage-y += version.c ramstage-y += version.c smm-y += version.c -secmon-y += version.c verstage-y += version.c $(obj)/lib/version.bootblock.o : $(obj)/build.h $(obj)/lib/version.romstage.o : $(obj)/build.h $(obj)/lib/version.ramstage.o : $(obj)/build.h $(obj)/lib/version.smm.o : $(obj)/build.h -$(obj)/lib/version.secmon.o : $(obj)/build.h $(obj)/lib/version.verstage.o : $(obj)/build.h romstage-y += bootmode.c @@ -181,7 +179,6 @@ bootblock-y += halt.c romstage-y += halt.c ramstage-y += halt.c smm-y += halt.c -secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) # X86 bootblock uses custom ldscripts that are all glued together, diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index ee3b80e..4420e52 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -13,7 +13,6 @@ config SOC_NVIDIA_TEGRA132 select HAVE_UART_SPECIAL select ARM_BOOTBLOCK_CUSTOM select SMP - select ARM64_USE_SECURE_MONITOR select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 491b18b..592c34f 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -91,16 +91,6 @@ ramstage-y += ramstage.c ramstage-y += mmu_operations.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c -ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c - -secmon-y += 32bit_reset.S -secmon-y += cpu.c -secmon-y += cpu_lib.S -secmon-y += flow_ctrl.c -secmon-y += power.c -secmon-y += psci.c -secmon-y += uart.c -secmon-y += gic.c modules_arm-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra132/psci.c b/src/soc/nvidia/tegra132/psci.c deleted file mode 100644 index 3d6c210..0000000 --- a/src/soc/nvidia/tegra132/psci.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/psci.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/cpu.h> -#include <soc/flow_ctrl.h> -#include <soc/power.h> - -#include <console/console.h> - -static void *cpu_on_entry_point; - -void psci_soc_init(uintptr_t cpu_on_entry) -{ - /* - * Stash secmon entry point for CPUs starting up. The 32-bit reset - * vector register is accessible in < EL3 so one has to attempt to - * plug the potential race for that register being changed out from - * under us. Therefore, we set the appropriate registers here, but - * it is also done on each CPU_ON request. - */ - cpu_on_entry_point = (void *)cpu_on_entry; - cpu_prepare_startup(cpu_on_entry_point); -} - -static size_t children_at_level(int parent_level, uint64_t mpidr) -{ - if (mpidr != 0) - return 0; - - /* T132 just has 2 cores. 0. Level 1 has 2 children at level 0. */ - switch (parent_level) { - case PSCI_AFFINITY_ROOT: - return 1; - case PSCI_AFFINITY_LEVEL_3: - return 1; - case PSCI_AFFINITY_LEVEL_2: - return 1; - case PSCI_AFFINITY_LEVEL_1: - return 2; - case PSCI_AFFINITY_LEVEL_0: - return 0; - default: - return 0; - } -} - -#define TEGRA132_PM_CORE_C7 0x3 - -static inline void tegra132_enter_sleep(unsigned long pmstate) -{ - asm volatile( - " isb\n" - " msr actlr_el1, %0\n" - " wfi\n" - : - : "r" (pmstate)); -} - -static void prepare_cpu_on(int cpu) -{ - uint32_t partid; - - partid = cpu ? POWER_PARTID_CE1 : POWER_PARTID_CE0; - - power_ungate_partition(partid); - flowctrl_write_cpu_halt(cpu, 0); -} - -static int cmd_prepare(struct psci_cmd *cmd) -{ - int ret; - - switch (cmd->type) { - case PSCI_CMD_ON: - prepare_cpu_on(cmd->target->cpu_state.ci->id); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_OFF: - if (cmd->state_id != -1) { - ret = PSCI_RET_INVALID_PARAMETERS; - break; - } - cmd->state_id = TEGRA132_PM_CORE_C7; - ret = PSCI_RET_SUCCESS; - break; - default: - ret = PSCI_RET_NOT_SUPPORTED; - break; - } - return ret; -} - -static int cmd_commit(struct psci_cmd *cmd) -{ - int ret; - struct cpu_info *ci; - - ci = cmd->target->cpu_state.ci; - - switch (cmd->type) { - case PSCI_CMD_ON: - /* Take CPU out of reset */ - start_cpu_silent(ci->id, cpu_on_entry_point); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_OFF: - flowctrl_cpu_off(ci->id); - tegra132_enter_sleep(cmd->state_id); - /* Never reach here */ - ret = PSCI_RET_NOT_SUPPORTED; - printk(BIOS_ERR, "t132 CPU%d PSCI_CMD_OFF fail\n", ci->id); - break; - default: - ret = PSCI_RET_NOT_SUPPORTED; - break; - } - return ret; -} - -struct psci_soc_ops soc_psci_ops = { - .children_at_level = &children_at_level, - .cmd_prepare = &cmd_prepare, - .cmd_commit = &cmd_commit, -}; diff --git a/src/soc/nvidia/tegra132/secmon.c b/src/soc/nvidia/tegra132/secmon.c deleted file mode 100644 index ea5467d..0000000 --- a/src/soc/nvidia/tegra132/secmon.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/secmon.h> -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/mmu_operations.h> - -static void soc_get_secure_mem(uint64_t *base, size_t *size) -{ - uintptr_t tz_base_mib; - size_t tz_size_mib; - - carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); - - tz_base_mib *= MiB; - tz_size_mib *= MiB; - - *base = tz_base_mib; - *size = tz_size_mib; -} - -void soc_get_secmon_base_size(uint64_t *base, size_t *size) -{ - uintptr_t tz_base; - size_t ttb_size, tz_size; - - soc_get_secure_mem(&tz_base, &tz_size); - - ttb_size = TTB_SIZE * MiB; - - *base = tz_base + ttb_size; - *size = tz_size - ttb_size; -} diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 66df6b4..2898cec 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -98,19 +98,9 @@ ramstage-y += ramstage.c ramstage-y += mmu_operations.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c -ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c ramstage-$(CONFIG_HAVE_MTC) += mtc.c ramstage-y += stage_entry.S -secmon-y += cpu.c -secmon-y += cpu_lib.S -secmon-y += flow_ctrl.c -secmon-y += power.c -secmon-y += psci.c -secmon-y += stage_entry.S -secmon-y += uart.c -secmon-y += gic.c - rmodules_arm-y += monotonic_timer.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra210/include/ diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index 5e03623..a652b76 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -43,11 +43,6 @@ static void enable_cpu_power_partitions(void) power_ungate_partition(POWER_PARTID_CRAIL); power_ungate_partition(POWER_PARTID_C0NC); power_ungate_partition(POWER_PARTID_CE0); - if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_MONITOR)) { - power_ungate_partition(POWER_PARTID_CE1); - power_ungate_partition(POWER_PARTID_CE2); - power_ungate_partition(POWER_PARTID_CE3); - } if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) { /* diff --git a/src/soc/nvidia/tegra210/psci.c b/src/soc/nvidia/tegra210/psci.c deleted file mode 100644 index c3a1a7d..0000000 --- a/src/soc/nvidia/tegra210/psci.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <assert.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/psci.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/cpu.h> -#include <soc/flow_ctrl.h> -#include <soc/power.h> -#include <stdlib.h> - -#include <console/console.h> - -extern void tegra210_reset_handler(void); - -#define TEGRA210_PM_STATE_C7 7 - -static void *cpu_on_entry_point; - -void psci_soc_init(uintptr_t cpu_on_entry) -{ - /* - * Stash secmon entry point for CPUs starting up. The 32-bit reset - * vector register is accessible in < EL3 so one has to attempt to - * plug the potential race for that register being changed out from - * under us. Therefore, we set the appropriate registers here, but - * it is also done on each CPU_ON request. - */ - cpu_on_entry_point = tegra210_reset_handler; - cpu_prepare_startup(cpu_on_entry_point); -} - -static size_t children_at_level(int parent_level, uint64_t mpidr) -{ - if (mpidr != 0) - return 0; - - /* - * T210 has 2 clusters. Each cluster has 4 cores. Currently we are - * concentrating only on one of the clusters i.e. A57 cluster. For A53 - * bringup, correct the cluster details for A53 cluster as well. - * Since, A57 cluster has 4 cores, level 1 has 4 children at level 0. - * TODO(furquan): Update for A53. - */ - switch (parent_level) { - case PSCI_AFFINITY_ROOT: - return 1; - case PSCI_AFFINITY_LEVEL_3: - return 1; - case PSCI_AFFINITY_LEVEL_2: - return 1; - case PSCI_AFFINITY_LEVEL_1: - return 4; - case PSCI_AFFINITY_LEVEL_0: - return 0; - default: - return 0; - } -} - -static void prepare_cpu_on(int cpu) -{ - cpu_prepare_startup(cpu_on_entry_point); -} - -static void prepare_cpu_suspend(int cpu, uint32_t state_id) -{ - flowctrl_write_cc4_ctrl(cpu, 0xffffffff); - switch (state_id) { - case TEGRA210_PM_STATE_C7: - flowctrl_cpu_suspend(cpu); - break; - default: - return; - } -} - -static void prepare_cpu_resume(int cpu) -{ - flowctrl_write_cpu_csr(cpu, 0); - flowctrl_write_cpu_halt(cpu, 0); - flowctrl_write_cc4_ctrl(cpu, 0); -} - -static void cpu_suspend_commit(int cpu, uint32_t state_id) -{ - int l2_flush; - - switch (state_id) { - case TEGRA210_PM_STATE_C7: - l2_flush = NO_L2_FLUSH; - break; - default: - return; - } - - cortex_a57_cpu_power_down(l2_flush); - /* should never be here */ -} - -static int cmd_prepare(struct psci_cmd *cmd) -{ - int ret; - struct cpu_info *ci; - - ci = cmd->target->cpu_state.ci; - - switch (cmd->type) { - case PSCI_CMD_SUSPEND: - cmd->state_id = cmd->state->id; - prepare_cpu_on(ci->id); - prepare_cpu_suspend(ci->id, cmd->state_id); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_RESUME: - prepare_cpu_resume(ci->id); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_ON: - prepare_cpu_on(ci->id); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_OFF: - if (cmd->state_id != -1) { - ret = PSCI_RET_INVALID_PARAMETERS; - break; - } - ret = PSCI_RET_SUCCESS; - break; - default: - ret = PSCI_RET_NOT_SUPPORTED; - break; - } - return ret; -} - -static int cmd_commit(struct psci_cmd *cmd) -{ - int ret; - struct cpu_info *ci; - - ci = cmd->target->cpu_state.ci; - - switch (cmd->type) { - case PSCI_CMD_SUSPEND: - cpu_suspend_commit(ci->id, cmd->state_id); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_RESUME: - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_ON: - /* Take CPU out of reset */ - flowctrl_cpu_on(ci->id); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_OFF: - flowctrl_cpu_off(ci->id); - cortex_a57_cpu_power_down(NO_L2_FLUSH); - /* Never reach here */ - ret = PSCI_RET_NOT_SUPPORTED; - printk(BIOS_ERR, "t210 CPU%d PSCI_CMD_OFF fail\n", ci->id); - break; - default: - ret = PSCI_RET_NOT_SUPPORTED; - break; - } - return ret; -} - -struct psci_soc_ops soc_psci_ops = { - .children_at_level = &children_at_level, - .cmd_prepare = &cmd_prepare, - .cmd_commit = &cmd_commit, -}; diff --git a/src/soc/nvidia/tegra210/secmon.c b/src/soc/nvidia/tegra210/secmon.c deleted file mode 100644 index 392e06c..0000000 --- a/src/soc/nvidia/tegra210/secmon.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/secmon.h> -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/mmu_operations.h> - -static void soc_get_secure_mem(uint64_t *base, size_t *size) -{ - uintptr_t tz_base_mib; - size_t tz_size_mib; - - carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); - - tz_base_mib *= MiB; - tz_size_mib *= MiB; - - *base = tz_base_mib; - *size = tz_size_mib; -} - -void soc_get_secmon_base_size(uint64_t *base, size_t *size) -{ - uintptr_t tz_base; - size_t ttb_size, tz_size; - - soc_get_secure_mem(&tz_base, &tz_size); - - ttb_size = CONFIG_TTB_SIZE_MB * MiB; - - *base = tz_base + ttb_size; - *size = tz_size - ttb_size; -}

1 0

New patch to review for coreboot: src/console: Link die.c in bootblock without BOOTBLOCK_CONSOLE
by Alexandru Gagniuc 07 Nov '15

07 Nov '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12356 -gerrit commit 359b34e286bce47abcfa30bae95b3ef849bf50a7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Nov 6 15:55:46 2015 -0800 src/console: Link die.c in bootblock without BOOTBLOCK_CONSOLE Without BOOTBLOCK_CONSOLE any call to die() fails due to die() symbol not being defined at link time. die() is not is dependent on the console backend, and can function without it (the prink gets no-oped). Change-Id: I6cecafb576c3b1e901f3927c777f6282174fb259 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/console/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a5f4318..0c61123 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -20,7 +20,7 @@ romstage-y += die.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += die.c +bootblock-y += die.c secmon-y += vtxprintf.c printk.c secmon-y += init.c console.c

1 0

New patch to review for coreboot: [RFC] mainboard: Remove empty mainboard.c files
by Paul Menzel 07 Nov '15

07 Nov '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12355 -gerrit commit d62fed549d2b28ebbbb57eec8314efeabfa3c224 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Nov 7 00:07:05 2015 +0100 [RFC] mainboard: Remove empty mainboard.c files Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/aaeon/pfm-540i_revb/mainboard.c | 32 ----------------------- src/mainboard/amd/db800/mainboard.c | 32 ----------------------- src/mainboard/amd/norwich/mainboard.c | 32 ----------------------- src/mainboard/asus/dsbf/mainboard.c | 31 ---------------------- src/mainboard/asus/m2n-e/mainboard.c | 26 ------------------- src/mainboard/digitallogic/msm800sev/mainboard.c | 32 ----------------------- src/mainboard/dmp/vortex86ex/mainboard.c | 31 ---------------------- src/mainboard/emulation/qemu-armv7/mainboard.c | 26 ------------------- src/mainboard/gigabyte/m57sli/mainboard.c | 31 ---------------------- src/mainboard/intel/mohonpeak/mainboard.c | 30 --------------------- src/mainboard/intel/sklrvp/mainboard.c | 21 --------------- src/mainboard/iwave/iWRainbowG6/mainboard.c | 27 ------------------- src/mainboard/msi/ms7260/mainboard.c | 29 --------------------- src/mainboard/msi/ms9282/mainboard.c | 31 ---------------------- src/mainboard/msi/ms9652_fam10/mainboard.c | 31 ---------------------- src/mainboard/nvidia/l1_2pvv/mainboard.c | 31 ---------------------- src/mainboard/pcengines/alix1c/mainboard.c | 32 ----------------------- src/mainboard/pcengines/alix2d/mainboard.c | 32 ----------------------- src/mainboard/rca/rm4100/mainboard.c | 32 ----------------------- src/mainboard/supermicro/x7db8/mainboard.c | 31 ---------------------- src/mainboard/traverse/geos/mainboard.c | 32 ----------------------- src/mainboard/winent/pl6064/mainboard.c | 32 ----------------------- src/mainboard/wyse/s50/mainboard.c | 33 ------------------------ 23 files changed, 697 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c b/src/mainboard/aaeon/pfm-540i_revb/mainboard.c deleted file mode 100644 index 6f253dd..0000000 --- a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Mark Norman <mpnorman(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "AAEON PFM-540I_REVB ENTER %s\n", __func__); - printk(BIOS_DEBUG, "AAEON PFM-540I_REVB EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/db800/mainboard.c b/src/mainboard/amd/db800/mainboard.c deleted file mode 100644 index 8445b06..0000000 --- a/src/mainboard/amd/db800/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "AMD DB800 ENTER %s\n", __func__); - printk(BIOS_DEBUG, "AMD DB800 EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/norwich/mainboard.c b/src/mainboard/amd/norwich/mainboard.c deleted file mode 100644 index 59257a0..0000000 --- a/src/mainboard/amd/norwich/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "Norwich ENTER %s\n", __func__); - printk(BIOS_DEBUG, "Norwich EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c deleted file mode 100644 index a243940..0000000 --- a/src/mainboard/asus/dsbf/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <arch/io.h> -#include <delay.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <arch/io.h> - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c deleted file mode 100644 index 48bf006..0000000 --- a/src/mainboard/asus/m2n-e/mainboard.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> - - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/digitallogic/msm800sev/mainboard.c b/src/mainboard/digitallogic/msm800sev/mainboard.c deleted file mode 100644 index 1b0cf8f..0000000 --- a/src/mainboard/digitallogic/msm800sev/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "MSM800SEV ENTER %s\n", __func__); - printk(BIOS_DEBUG, "MSM800SEV EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c deleted file mode 100644 index 485b467..0000000 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/io.h> -#include <boot/tables.h> -#include <device/pci_def.h> - - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - CHIP_NAME("DMP VORTEX86EX Mainboard") - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c deleted file mode 100644 index 83a55e3..0000000 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void mainboard_enable(device_t dev) -{ - printk(BIOS_INFO, "Enable qemu/armv7 device...\n"); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c deleted file mode 100644 index 1f26995..0000000 --- a/src/mainboard/gigabyte/m57sli/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * Copyright (C) 2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c deleted file mode 100644 index 4ad16ec..0000000 --- a/src/mainboard/intel/mohonpeak/mainboard.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(device_t dev) -{ - -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/sklrvp/mainboard.c b/src/mainboard/intel/sklrvp/mainboard.c deleted file mode 100644 index 0437b11..0000000 --- a/src/mainboard/intel/sklrvp/mainboard.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> - -struct chip_operations mainboard_ops = { -}; diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c deleted file mode 100644 index 1645343..0000000 --- a/src/mainboard/iwave/iWRainbowG6/mainboard.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009-2010 iWave Systems - * Copyright (C) 2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <console/console.h> - - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c deleted file mode 100644 index df669c2..0000000 --- a/src/mainboard/msi/ms7260/mainboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> - -#if 0 - - -static void mainboard_enable(device_t dev) -{ -} -#endif - -struct chip_operations mainboard_ops = { - // .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c deleted file mode 100644 index 6e4631d..0000000 --- a/src/mainboard/msi/ms9282/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 MSI - * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c deleted file mode 100644 index 5557014..0000000 --- a/src/mainboard/msi/ms9652_fam10/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c deleted file mode 100644 index 1f26995..0000000 --- a/src/mainboard/nvidia/l1_2pvv/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. - * Copyright (C) 2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/pcengines/alix1c/mainboard.c b/src/mainboard/pcengines/alix1c/mainboard.c deleted file mode 100644 index e94c3cc..0000000 --- a/src/mainboard/pcengines/alix1c/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "ALIX1.C ENTER %s\n", __func__); - printk(BIOS_DEBUG, "ALIX1.C EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/pcengines/alix2d/mainboard.c b/src/mainboard/pcengines/alix2d/mainboard.c deleted file mode 100644 index 11cc385..0000000 --- a/src/mainboard/pcengines/alix2d/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "ALIX.2D ENTER %s\n", __func__); - printk(BIOS_DEBUG, "ALIX.2D EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c deleted file mode 100644 index ad0e5f8..0000000 --- a/src/mainboard/rca/rm4100/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2010 Joseph Smith <joe(a)settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> - -static void mainboard_init(device_t dev) -{ - // TODO Switch parport LEDs again -} - -static void mainboard_enable(device_t dev) -{ - // TODO Switch parport LEDs - dev->ops->init = mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c deleted file mode 100644 index a243940..0000000 --- a/src/mainboard/supermicro/x7db8/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <arch/io.h> -#include <delay.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <arch/io.h> - -static void mainboard_enable(device_t dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/traverse/geos/mainboard.c b/src/mainboard/traverse/geos/mainboard.c deleted file mode 100644 index 115d911..0000000 --- a/src/mainboard/traverse/geos/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "Geos ENTER %s\n", __func__); - printk(BIOS_DEBUG, "Geos EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/winent/pl6064/mainboard.c b/src/mainboard/winent/pl6064/mainboard.c deleted file mode 100644 index f959f2a..0000000 --- a/src/mainboard/winent/pl6064/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Win Enterprises, Inc. (anishp(a)win-ent.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the license. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 ENTER %s\n", __func__); - printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/wyse/s50/mainboard.c b/src/mainboard/wyse/s50/mainboard.c deleted file mode 100644 index 7b746e3..0000000 --- a/src/mainboard/wyse/s50/mainboard.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Nils Jacobs - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -static void init(struct device *dev) -{ - printk(BIOS_DEBUG, "S50 ENTER %s\n", __func__); - printk(BIOS_DEBUG, "S50 EXIT %s\n", __func__); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -};

1 0

Patch set updated for coreboot: Provide coreboot coding style formalisation file for clang-format
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8036 -gerrit commit 8d4017991f18aa54b68db7e02bcdb721e7d3a39b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jan 3 01:55:22 2015 +1100 Provide coreboot coding style formalisation file for clang-format The Clang project has a powerful code rewrite engine in the form of LibFormat. A auxiliary tool is provided called `clang-format' that can take a coding style formalisation file and rewrite your code to conform to this style. Further, a wrapper script called `git-clang-format' is also provided that can hook pre-commits potentially replacing our slow and poor coverage regexp scripts on pre-commits. Herein we provide essentially the Linux Style Guide formalism. Change-Id: Ica2207fdb8a4702793fa73eba6293b7b36ea9050 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .clang-format | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..a3ef233 --- /dev/null +++ b/.clang-format @@ -0,0 +1,6 @@ +BasedOnStyle: LLVM +IndentWidth: 8 +UseTab: Always +BreakBeforeBraces: Linux +AllowShortIfStatementsOnASingleLine: false +IndentCaseLabels: false

1 0

Patch set updated for coreboot: util/gitconfig/pre-commit: Use clang-format to sanitise commits
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8037 -gerrit commit f22c29e0eb305e79ec0dc09772c668f9dd37fe76 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jan 3 02:08:33 2015 +1100 util/gitconfig/pre-commit: Use clang-format to sanitise commits Use the `git-format' tool to sanitise coreboot commits such that they conform to coreboot's coding style. This fancy piece of machinary allows one to have LibFormat from Clang to automatically check your commit conforms to coreboot's coding style, fix any issues automatically and provides you a diff you may review and apply at your convenience. N.B. When the `clang-format' binary is not found we issue a warning that the test was skipped and carry on as usual. Hence, this is strictly non-enforcing at this current time. You may use it at your leisure. Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 8 ++- util/gitconfig/pre-commit | 2 +- util/lint/check-style | 143 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index de148cb..7b107fe 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -46,7 +46,7 @@ coreboot: build-dirs $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool ####################################################################### # our phony targets -PHONY+= clean-abuild coreboot lint lint-stable build-dirs +PHONY+= clean-abuild coreboot check-style lint lint-stable build-dirs ####################################################################### # root source directories of coreboot @@ -418,6 +418,12 @@ printcrt0s: update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF +check-style: + @grep "^# DESCR:" util/lint/check-style | sed "s,.*DESCR: *,," + @echo "========" + @util/lint/check-style + @echo "========" + lint lint-stable: util/lint/lint $@ diff --git a/util/gitconfig/pre-commit b/util/gitconfig/pre-commit index 70cd6ea..45a3d1e 100755 --- a/util/gitconfig/pre-commit +++ b/util/gitconfig/pre-commit @@ -1,3 +1,3 @@ #!/bin/sh -%MAKE% lint-stable +%MAKE% check-style lint-stable git diff --cached | util/lint/checkpatch.pl --no-signoff -q - diff --git a/util/lint/check-style b/util/lint/check-style new file mode 100755 index 0000000..1ac51b4 --- /dev/null +++ b/util/lint/check-style @@ -0,0 +1,143 @@ +#!/bin/bash +# git pre-commit hook that runs an clang-format stylecheck. +# Features: +# - abort commit when commit does not comply with the style guidelines +# - create a patch of the proposed style changes +# +# modifications for clang-format by rene.milk(a)wwu.de +# This file is part of a set of unofficial pre-commit hooks available +# at github. +# Link: https://github.com/githubbrowser/Pre-commit-hooks +# Contact: David Martin, david.martin.mailbox(a)googlemail.com + +# DESCR: Checking that VCS 'staged' source conforms to coding style + +################################################################## +# SETTINGS +# set path to clang-format binary +CLANG_FORMAT="/usr/bin/clang-format" + +# remove any older patches from previous commits. Set to true or false. +# DELETE_OLD_PATCHES=false +DELETE_OLD_PATCHES=false + +# only parse files with the extensions in FILE_EXTS. Set to true or false. +# if false every changed file in the commit will be parsed with clang-format. +# if true only files matching one of the extensions are parsed with clang-format. +# PARSE_EXTS=true +PARSE_EXTS=true + +# file types to parse. Only effective when PARSE_EXTS is true. +# FILE_EXTS=".c .h .cpp .hpp" +FILE_EXTS=".c .h .cpp .hpp .cc .hh .cxx" + +################################################################## +# There should be no need to change anything below this line. + +# Reference: http://stackoverflow.com/questions/1055671/how-can-i-get-the-behavior-of-gn… +canonicalize_filename () { + local target_file=$1 + local physical_directory="" + local result="" + + # Need to restore the working directory after work. + pushd `pwd` > /dev/null + + cd "$(dirname "$target_file")" + target_file=`basename $target_file` + + # Iterate down a (possible) chain of symlinks + while [ -L "$target_file" ] + do + target_file=$(readlink "$target_file") + cd "$(dirname "$target_file")" + target_file=$(basename "$target_file") + done + + # Compute the canonicalized name by finding the physical path + # for the directory we're in and appending the target file. + physical_directory=`pwd -P` + result="$physical_directory"/"$target_file" + + # restore the working directory after work. + popd > /dev/null + + echo "$result" +} + +# exit on error +set -e + +# check whether the given file matches any of the set extensions +matches_extension() { + local filename=$(basename "$1") + local extension=".${filename##*.}" + local ext + + for ext in $FILE_EXTS; do [[ "$ext" == "$extension" ]] && return 0; done + + return 1 +} + +# necessary check for initial commit +if git rev-parse --verify HEAD >/dev/null 2>&1 ; then + against=HEAD +else + # Initial commit: diff against an empty tree object + against=4b825dc642cb6eb9a060e54bf8d69288fbee4904 +fi + +if [ ! -x "$CLANG_FORMAT" ] ; then + printf "Warning: clang-format executable not found.\n" + printf "Set the correct path in $(canonicalize_filename "$0").\n" + printf "Skipping clang-format style check test.\n" +# exit 1 + exit 0 +fi + +# create a random filename to store our generated patch +prefix="pre-commit-clang-format" +suffix="$(date +%s)" +patch="/tmp/$prefix-$suffix.patch" + +# clean up any older clang-format patches +$DELETE_OLD_PATCHES && rm -f /tmp/$prefix*.patch + +# create one patch containing all changes to the files +git diff-index --cached --diff-filter=ACMR --name-only $against -- | while read file; +do + # ignore file if we do check for file extensions and the file + # does not match any of the extensions specified in $FILE_EXTS + if $PARSE_EXTS && ! matches_extension "$file"; then + continue; + fi + + # clang-format our sourcefile, create a patch with diff and append it to our $patch + # The sed call is necessary to transform the patch from + # --- $file timestamp + # +++ - timestamp + # to both lines working on the same file and having a a/ and b/ prefix. + # Else it can not be applied with 'git apply'. + "$CLANG_FORMAT" -style=file "$file" | \ + diff -u "$file" - | \ + sed -e "1s|--- |--- a/|" -e "2s|+++ -|+++ b/$file|" >> "$patch" +done + +# if no patch has been generated all is ok, clean up the file stub and exit +if [ ! -s "$patch" ] ; then + printf "Files in this commit comply with the clang-format rules.\n" + rm -f "$patch" + exit 0 +fi + +# a patch has been created, notify the user and exit +printf "\nThe following differences were found between the code to commit " +printf "and the clang-format rules:\n\n" +cat "$patch" + +printf "\nYou can apply these changes with:\n git apply $patch\n" +printf "(may need to be called from the root directory of your repository)\n" +printf "Aborting commit. Apply changes and commit again or skip checking with" +printf " --no-verify (not recommended).\n" + +exit 1

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New patch to review for coreboot: mainboard/**/irq_tables.c: Remove reference to getpir
by Patrick Georgi 06 Nov '15

06 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12354 -gerrit commit 21bc68b86124305466fd9bdbb7bcfb629bb6613f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Nov 6 22:40:57 2015 +0100 mainboard/**/irq_tables.c: Remove reference to getpir The obsolete and removed getpir utility remarked in its output that the data is autogenerated. The tool was removed because it wasn't very reliable, so there's no need to point that anymore. Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/amd/dbm690t/irq_tables.c | 6 ------ src/mainboard/amd/mahogany/irq_tables.c | 6 ------ src/mainboard/amd/pistachio/irq_tables.c | 6 ------ src/mainboard/amd/rumba/irq_tables.c | 7 ------- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 6 ------ src/mainboard/asrock/939a785gmh/irq_tables.c | 6 ------ src/mainboard/asus/mew-vm/irq_tables.c | 7 ------- src/mainboard/broadcom/blast/irq_tables.c | 6 ------ src/mainboard/digitallogic/adl855pc/irq_tables.c | 7 ------- src/mainboard/emulation/qemu-i440fx/irq_tables.c | 7 ------- src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c | 6 ------ src/mainboard/gigabyte/m57sli/irq_tables.c | 6 ------ src/mainboard/hp/dl145_g1/irq_tables.c | 6 ------ src/mainboard/hp/dl145_g3/irq_tables.c | 9 --------- src/mainboard/hp/dl165_g6_fam10/irq_tables.c | 9 --------- src/mainboard/iwill/dk8_htx/irq_tables.c | 6 ------ src/mainboard/iwill/dk8s2/irq_tables.c | 7 ------- src/mainboard/kontron/kt690/irq_tables.c | 6 ------ src/mainboard/lippert/frontrunner/irq_tables.c | 7 ------- src/mainboard/msi/ms9185/irq_tables.c | 6 ------ src/mainboard/msi/ms9282/irq_tables.c | 6 ------ src/mainboard/msi/ms9652_fam10/irq_tables.c | 6 ------ src/mainboard/nvidia/l1_2pvv/irq_tables.c | 6 ------ src/mainboard/siemens/sitemp_g1p1/irq_tables.c | 6 ------ src/mainboard/sunw/ultra40/irq_tables.c | 6 ------ src/mainboard/sunw/ultra40m2/irq_tables.c | 6 ------ src/mainboard/supermicro/h8dme/irq_tables.c | 6 ------ src/mainboard/supermicro/h8dmr/irq_tables.c | 6 ------ src/mainboard/supermicro/h8dmr_fam10/irq_tables.c | 6 ------ src/mainboard/supermicro/h8qme_fam10/irq_tables.c | 6 ------ src/mainboard/technexion/tim5690/irq_tables.c | 6 ------ src/mainboard/technexion/tim8690/irq_tables.c | 6 ------ src/mainboard/tyan/s2735/irq_tables.c | 7 ------- src/mainboard/tyan/s2850/irq_tables.c | 7 ------- src/mainboard/tyan/s2875/irq_tables.c | 7 ------- src/mainboard/tyan/s2880/irq_tables.c | 7 ------- src/mainboard/tyan/s2881/irq_tables.c | 6 ------ src/mainboard/tyan/s2882/irq_tables.c | 6 ------ src/mainboard/tyan/s2885/irq_tables.c | 6 ------ src/mainboard/tyan/s2891/irq_tables.c | 6 ------ src/mainboard/tyan/s2892/irq_tables.c | 6 ------ src/mainboard/tyan/s2895/irq_tables.c | 6 ------ src/mainboard/tyan/s2912/irq_tables.c | 6 ------ src/mainboard/tyan/s2912_fam10/irq_tables.c | 6 ------ src/mainboard/tyan/s4880/irq_tables.c | 7 ------- src/mainboard/tyan/s4882/irq_tables.c | 7 ------- src/mainboard/winent/mb6047/irq_tables.c | 6 ------ 47 files changed, 300 deletions(-) diff --git a/src/mainboard/amd/dbm690t/irq_tables.c b/src/mainboard/amd/dbm690t/irq_tables.c index 2019547..f2be994 100644 --- a/src/mainboard/amd/dbm690t/irq_tables.c +++ b/src/mainboard/amd/dbm690t/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/amd/mahogany/irq_tables.c b/src/mainboard/amd/mahogany/irq_tables.c index 564b7d0..80bfbb4 100644 --- a/src/mainboard/amd/mahogany/irq_tables.c +++ b/src/mainboard/amd/mahogany/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/amd/pistachio/irq_tables.c b/src/mainboard/amd/pistachio/irq_tables.c index 4d26cf7..940b1aa 100644 --- a/src/mainboard/amd/pistachio/irq_tables.c +++ b/src/mainboard/amd/pistachio/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c index 5c045cc..2e0d9d6 100644 --- a/src/mainboard/amd/rumba/irq_tables.c +++ b/src/mainboard/amd/rumba/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> /* Platform IRQs */ diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 4d42f47..9a359e3 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/asrock/939a785gmh/irq_tables.c b/src/mainboard/asrock/939a785gmh/irq_tables.c index 564b7d0..80bfbb4 100644 --- a/src/mainboard/asrock/939a785gmh/irq_tables.c +++ b/src/mainboard/asrock/939a785gmh/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c index 4fbf122..3d8bebe 100644 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ b/src/mainboard/asus/mew-vm/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c index 1f39adf..d5b7352 100644 --- a/src/mainboard/broadcom/blast/irq_tables.c +++ b/src/mainboard/broadcom/blast/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/digitallogic/adl855pc/irq_tables.c b/src/mainboard/digitallogic/adl855pc/irq_tables.c index 94adba1..5cbee86 100644 --- a/src/mainboard/digitallogic/adl855pc/irq_tables.c +++ b/src/mainboard/digitallogic/adl855pc/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/emulation/qemu-i440fx/irq_tables.c b/src/mainboard/emulation/qemu-i440fx/irq_tables.c index 21eeabf..daa6782 100644 --- a/src/mainboard/emulation/qemu-i440fx/irq_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c index 2d282ae..d724a51 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c @@ -17,12 +17,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c index 1037153..7c717f1 100644 --- a/src/mainboard/gigabyte/m57sli/irq_tables.c +++ b/src/mainboard/gigabyte/m57sli/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index f5e19cd..1cb5fa9 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c index b5ea725..3e256b7 100644 --- a/src/mainboard/hp/dl145_g3/irq_tables.c +++ b/src/mainboard/hp/dl145_g3/irq_tables.c @@ -1,12 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * - * Contains the IRQ Routing Table dumped directly from your - * memory, which BIOS sets up. - * - * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx - */ - #ifdef GETPIR #include "pirq_routing.h" #else diff --git a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c index 1784aec..d589c9e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c +++ b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c @@ -1,12 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * - * Contains the IRQ Routing Table dumped directly from your - * memory, which BIOS sets up. - * - * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx - */ - #ifdef GETPIR #include "pirq_routing.h" #else diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c index 4d42f47..9a359e3 100644 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ b/src/mainboard/iwill/dk8_htx/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/iwill/dk8s2/irq_tables.c b/src/mainboard/iwill/dk8s2/irq_tables.c index 3e1424c..b86e602 100644 --- a/src/mainboard/iwill/dk8s2/irq_tables.c +++ b/src/mainboard/iwill/dk8s2/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/kontron/kt690/irq_tables.c b/src/mainboard/kontron/kt690/irq_tables.c index 2019547..f2be994 100644 --- a/src/mainboard/kontron/kt690/irq_tables.c +++ b/src/mainboard/kontron/kt690/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c index 5c045cc..2e0d9d6 100644 --- a/src/mainboard/lippert/frontrunner/irq_tables.c +++ b/src/mainboard/lippert/frontrunner/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> /* Platform IRQs */ diff --git a/src/mainboard/msi/ms9185/irq_tables.c b/src/mainboard/msi/ms9185/irq_tables.c index 4901495..992dc5a 100644 --- a/src/mainboard/msi/ms9185/irq_tables.c +++ b/src/mainboard/msi/ms9185/irq_tables.c @@ -18,12 +18,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/msi/ms9282/irq_tables.c b/src/mainboard/msi/ms9282/irq_tables.c index 6713272..5891512 100644 --- a/src/mainboard/msi/ms9282/irq_tables.c +++ b/src/mainboard/msi/ms9282/irq_tables.c @@ -18,12 +18,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c index 2c37beb..c11707d 100644 --- a/src/mainboard/msi/ms9652_fam10/irq_tables.c +++ b/src/mainboard/msi/ms9652_fam10/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/nvidia/l1_2pvv/irq_tables.c b/src/mainboard/nvidia/l1_2pvv/irq_tables.c index d643cd4..0396812 100644 --- a/src/mainboard/nvidia/l1_2pvv/irq_tables.c +++ b/src/mainboard/nvidia/l1_2pvv/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c index 299a370..721e73e 100644 --- a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c index a0e21e4..aa4fa10 100644 --- a/src/mainboard/sunw/ultra40/irq_tables.c +++ b/src/mainboard/sunw/ultra40/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/sunw/ultra40m2/irq_tables.c b/src/mainboard/sunw/ultra40m2/irq_tables.c index d643cd4..0396812 100644 --- a/src/mainboard/sunw/ultra40m2/irq_tables.c +++ b/src/mainboard/sunw/ultra40m2/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c index 3b4fbf3..b8319b5 100644 --- a/src/mainboard/supermicro/h8dme/irq_tables.c +++ b/src/mainboard/supermicro/h8dme/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/supermicro/h8dmr/irq_tables.c b/src/mainboard/supermicro/h8dmr/irq_tables.c index 3b4fbf3..b8319b5 100644 --- a/src/mainboard/supermicro/h8dmr/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c index 2c37beb..c11707d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index 6596cc2..459a8b1 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/technexion/tim5690/irq_tables.c b/src/mainboard/technexion/tim5690/irq_tables.c index 2019547..f2be994 100644 --- a/src/mainboard/technexion/tim5690/irq_tables.c +++ b/src/mainboard/technexion/tim5690/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/technexion/tim8690/irq_tables.c b/src/mainboard/technexion/tim8690/irq_tables.c index 2019547..f2be994 100644 --- a/src/mainboard/technexion/tim8690/irq_tables.c +++ b/src/mainboard/technexion/tim8690/irq_tables.c @@ -13,12 +13,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2735/irq_tables.c b/src/mainboard/tyan/s2735/irq_tables.c index 3d69b49..ba1c7b3 100644 --- a/src/mainboard/tyan/s2735/irq_tables.c +++ b/src/mainboard/tyan/s2735/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/tyan/s2850/irq_tables.c b/src/mainboard/tyan/s2850/irq_tables.c index 187981c..77bd67a 100644 --- a/src/mainboard/tyan/s2850/irq_tables.c +++ b/src/mainboard/tyan/s2850/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/tyan/s2875/irq_tables.c b/src/mainboard/tyan/s2875/irq_tables.c index af8c385..b52ba6b 100644 --- a/src/mainboard/tyan/s2875/irq_tables.c +++ b/src/mainboard/tyan/s2875/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c index d0c0d18..be08105 100644 --- a/src/mainboard/tyan/s2880/irq_tables.c +++ b/src/mainboard/tyan/s2880/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/tyan/s2881/irq_tables.c b/src/mainboard/tyan/s2881/irq_tables.c index 53e761d..6a45658 100644 --- a/src/mainboard/tyan/s2881/irq_tables.c +++ b/src/mainboard/tyan/s2881/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index e78ebf1..2b24363 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c index f217365..dc74776 100644 --- a/src/mainboard/tyan/s2885/irq_tables.c +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2891/irq_tables.c b/src/mainboard/tyan/s2891/irq_tables.c index ea180db..536456c 100644 --- a/src/mainboard/tyan/s2891/irq_tables.c +++ b/src/mainboard/tyan/s2891/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2892/irq_tables.c b/src/mainboard/tyan/s2892/irq_tables.c index b3f54a4..878a070 100644 --- a/src/mainboard/tyan/s2892/irq_tables.c +++ b/src/mainboard/tyan/s2892/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2895/irq_tables.c b/src/mainboard/tyan/s2895/irq_tables.c index a247c3e..797220e 100644 --- a/src/mainboard/tyan/s2895/irq_tables.c +++ b/src/mainboard/tyan/s2895/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2912/irq_tables.c b/src/mainboard/tyan/s2912/irq_tables.c index 4744d7f..117aabc 100644 --- a/src/mainboard/tyan/s2912/irq_tables.c +++ b/src/mainboard/tyan/s2912/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index 2c37beb..c11707d 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -15,12 +15,6 @@ * GNU General Public License for more details. */ -/* This file was generated by getpir.c, do not modify! - * (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h> diff --git a/src/mainboard/tyan/s4880/irq_tables.c b/src/mainboard/tyan/s4880/irq_tables.c index defe03b..848d2d9 100644 --- a/src/mainboard/tyan/s4880/irq_tables.c +++ b/src/mainboard/tyan/s4880/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/tyan/s4882/irq_tables.c b/src/mainboard/tyan/s4882/irq_tables.c index d89c034..e7d6b1a 100644 --- a/src/mainboard/tyan/s4882/irq_tables.c +++ b/src/mainboard/tyan/s4882/irq_tables.c @@ -1,10 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c index 6fe7349..d03f2c4 100644 --- a/src/mainboard/winent/mb6047/irq_tables.c +++ b/src/mainboard/winent/mb6047/irq_tables.c @@ -1,9 +1,3 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ #include <console/console.h> #include <device/pci.h> #include <string.h>

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coreboot-gerrit November 2015