coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch set updated for coreboot: amd/model_fxx: Check FID&VID Support for the BSP (too)
by Urja Rannikko 07 Nov '15

07 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12336 -gerrit commit 3d67a449879047f7530221e94a3b3aecf64b4efb Author: Urja Rannikko <urjaman(a)gmail.com> Date: Sat Nov 7 15:43:06 2015 +0200 amd/model_fxx: Check FID&VID Support for the BSP (too) Tested in the direction that now my Sempron 2800+ / K8V-X boots. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/cpu/amd/model_fxx/fidvid.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 9851e65..03415d1 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -535,6 +535,9 @@ static void init_fidvid_bsp(unsigned bsp_apicid) unsigned i; #endif + if ((cpuid_edx(0x80000007) & 0x06) != 0x06) + return; /* FID/VID change not supported */ + msr_t msr; msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */

1 0

New patch to review for coreboot: AMD binaryPI: Allow fine-tuning platform memory configuration
by Kyösti Mälkki 07 Nov '15

07 Nov '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12358 -gerrit commit 24ba64ea3d45aed307be539937bcd08f15b0024b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 30 16:45:21 2015 +0200 AMD binaryPI: Allow fine-tuning platform memory configuration The RDK amd/db-ft3b-lc board will use this for on-board DDR3. Change-Id: I2ffd38e7e949d3a60487e91188ddaab04b03d4b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/pi/agesawrapper.c | 4 ++++ src/northbridge/amd/pi/agesawrapper.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index ec43539..b1e514a 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -26,6 +26,8 @@ VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); +void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} + #define FILECODE UNASSIGNED_FILE_FILECODE #ifndef __PRE_RAM__ @@ -132,6 +134,8 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + OemPostParams(PostParams); + // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index cba7dc6..811d904 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -58,4 +58,6 @@ VOID amd_initcpuio(void); VOID amd_initmmio(void); const void *agesawrapper_locate_module (const CHAR8 name[8]); +void OemPostParams(AMD_POST_PARAMS *PostParams); + #endif /* _AGESAWRAPPER_H_ */

1 0

Patch set updated for coreboot: Revert "AMD OemS3Save: refactor for Merlin Falcon"
by Kyösti Mälkki 07 Nov '15

07 Nov '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12282 -gerrit commit 3f7006426943ed61d4cab50f4a1e70cb871b6db7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 31 18:06:52 2015 +0200 Revert "AMD OemS3Save: refactor for Merlin Falcon" This reverts commit d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93. Do not mix open-source AGESA and binary PI trees. Once you have working S3 support for binaryPI platforms, add the adapted oem_s3.c file as northbridge/amd/pi/oem_s3.c instead. Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/agesawrapper.h | 2 +- src/northbridge/amd/agesa/oem_s3.c | 8 +------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index d9938ac..f5d52d6 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -70,6 +70,6 @@ extern const struct OEM_HOOK OemCustomize; /* For suspend-to-ram support. */ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(void *vS3SaveParams); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index b71aff5..8cce0e7 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -113,15 +113,9 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) static u8 MTRRStorage[S3_DATA_MTRR_SIZE]; -AGESA_STATUS OemS3Save(void *vS3SaveParams) +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) { -#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01) - AMD_RTB_PARAMS *S3SaveParams = (AMD_RTB_PARAMS *)vS3SaveParams; - S3_DATA_BLOCK *dataBlock = &S3SaveParams->S3DataBlock; -#else - AMD_S3SAVE_PARAMS *S3SaveParams = (AMD_S3SAVE_PARAMS *)vS3SaveParams; AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; -#endif u32 MTRRStorageSize = 0; uintptr_t pos, size;

1 0

Patch set updated for coreboot: Makefile.inc: Build test intelvbttool
by Paul Menzel 07 Nov '15

07 Nov '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12085 -gerrit commit 9ee40ef4f3d8bc2f9c8fe1cf75f3d288a6ff9e6c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Oct 18 11:47:45 2015 +0200 Makefile.inc: Build test intelvbttool Add intelvbttool to list of utilities to be build tested by the build servers. Change-Id: Id75724726778fd939fb7497f5b33a3d5d58124fd Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile.inc b/Makefile.inc index 5b8e4dc..b85a2cb 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -703,6 +703,7 @@ TOOLLIST= \ cbmem \ ectool \ inteltool \ + intelvbttool \ nvramtool \ superiotool \ viatool

1 0

New patch to review for coreboot: cpu/amd/car/post_cache_as_ram: Avoid trailing spaces
by Paul Menzel 07 Nov '15

07 Nov '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12357 -gerrit commit ad60be0507c485c0ab90cc619665401f7402f3d7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Nov 7 09:15:06 2015 +0100 cpu/amd/car/post_cache_as_ram: Avoid trailing spaces Looking at the coreboot console logs there are sometimes trailing whitespaces in the output, for example, if writing `Done` was not possible. Adapt the code, that spaces are only added when needed. Change-Id: Ia0af493ab62b6fab24e8a2629cf5fd67329e0af7 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/car/post_cache_as_ram.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 49b9ee3..ae73b24 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -32,20 +32,20 @@ static size_t backup_size(void) static void memcpy_(void *d, const void *s, size_t len) { - print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ... ", + print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", (uint32_t) s, (uint32_t) (s + len - 1), (uint32_t) d, (uint32_t) (d + len - 1)); memcpy(d, s, len); } static void memset_(void *d, int val, size_t len) { - print_car_debug(" Fill [%08x-%08x] ... ", (uint32_t) d, (uint32_t) (d + len - 1)); + print_car_debug(" Fill [%08x-%08x] ...", (uint32_t) d, (uint32_t) (d + len - 1)); memset(d, val, len); } static int memcmp_(void *d, const void *s, size_t len) { - print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ... ", + print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", (uint32_t) s, (uint32_t) (s + len - 1), (uint32_t) d, (uint32_t) (d + len - 1)); return memcmp(d, s, len); } @@ -61,13 +61,13 @@ static void prepare_romstage_ramstack(void *resume_backup_memory) } memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); - print_car_debug("Done\n"); + print_car_debug(" Done\n"); } static void prepare_ramstage_region(void *resume_backup_memory) { size_t backup_top = backup_size(); - print_car_debug("Prepare ramstage memory region... "); + print_car_debug("Prepare ramstage memory region..."); if (resume_backup_memory) { memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); @@ -76,7 +76,7 @@ static void prepare_ramstage_region(void *resume_backup_memory) memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); } - print_car_debug("Done\n"); + print_car_debug(" Done\n"); } /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */ @@ -121,18 +121,18 @@ void post_cache_as_ram(void) size_t car_size = car_data_size(); void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); - print_car_debug("Copying data from cache to RAM... "); + print_car_debug("Copying data from cache to RAM..."); memcpy_(migrated_car, &_car_data_start[0], car_size); - print_car_debug("Done\n"); + print_car_debug(" Done\n"); - print_car_debug("Verifying data integrity in RAM... "); + print_car_debug("Verifying data integrity in RAM..."); if (memcmp_(migrated_car, &_car_data_start[0], car_size) == 0) - print_car_debug("Done\n"); + print_car_debug(" Done\n"); else - print_car_debug("FAILED\n"); + print_car_debug(" FAILED\n"); /* New stack grows right below migrated_car. */ - print_car_debug("Switching to use RAM as stack... "); + print_car_debug("Switching to use RAM as stack..."); cache_as_ram_switch_stack(migrated_car); /* We do not come back. */

1 0

Patch merged into coreboot/master: arm64: Remove cpu intialization through device-tree
by gerrit＠coreboot.org 07 Nov '15

07 Nov '15

the following patch was just integrated into master: commit fdb3a8d07d46c0011555029e041890dc668ec7f0 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 15 15:50:30 2015 -0700 arm64: Remove cpu intialization through device-tree Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See http://review.coreboot.org/11913 for details. -gerrit

1 0

Patch merged into coreboot/master: arm64: Remove SMP support
by gerrit＠coreboot.org 07 Nov '15

07 Nov '15

the following patch was just integrated into master: commit b3f6ad35221984419ee0998f47b778d669d1636e Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 15 12:15:31 2015 -0700 arm64: Remove SMP support As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove SMP support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: http://review.coreboot.org/11909 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See http://review.coreboot.org/11909 for details. -gerrit

1 0

Patch merged into coreboot/master: arm64: remove spin table support
by gerrit＠coreboot.org 07 Nov '15

07 Nov '15

the following patch was just integrated into master: commit 1148786c05d97b4c646c11e770b275809b562953 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 15 12:22:27 2015 -0500 arm64: remove spin table support As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See http://review.coreboot.org/11908 for details. -gerrit

1 0

Patch merged into coreboot/master: arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
by gerrit＠coreboot.org 07 Nov '15

07 Nov '15

the following patch was just integrated into master: commit 0325a45fd03eb33818c7ac32208ea6568236ec14 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 14 10:20:18 2015 -0500 arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT With the removal of secmon from coreboot there are no power down operations required. As such remove the A57 power down support. Change-Id: I8eebb0ecd87b5e8bb3eaac335d652689d7f57796 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11898 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11898 for details. -gerrit

1 0

Patch merged into coreboot/master: arm64: remove secmon
by gerrit＠coreboot.org 07 Nov '15

07 Nov '15

the following patch was just integrated into master: commit 8c8e2b7e4c5f1e6a543ce67cf8b47e9feb1bac50 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 14 10:08:10 2015 -0500 arm64: remove secmon It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See http://review.coreboot.org/11897 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015