coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Increase BSP stack size
by Timothy Pearson 07 Nov '15

07 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11972 -gerrit commit b0f077d87170eea2d2010b82dc225069b59aeaca Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 20:18:44 2015 -0500 cpu/amd/family_10h-family_15h: Increase BSP stack size The additional local data storage requirements of the full DDR3 DRAM training algorithm make a BSP stack overrun a distint possibility. Increase the BSP stack size to compensate. Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 7c47e27..81b1d1e 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -33,7 +33,7 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x2000 + default 0x4000 config DCACHE_BSP_STACK_SLUSH hex

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Patch set updated for coreboot: northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time
by Timothy Pearson 07 Nov '15

07 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11973 -gerrit commit b45659a0d2607295b321d7d6ae4031b96cae17ac Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 20:51:59 2015 -0500 northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time Change-Id: Ic16a927a3f1fc6f7cb1aea36a8abe8cc1999cb52 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 161 +++++++++++++++------------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 7 ++ 2 files changed, 92 insertions(+), 76 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f4bf402..4371a37 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -176,7 +176,7 @@ static void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat, static u8 Get_Latency_Diff(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void SyncSetting(struct DCTStatStruc *pDCTstat); -static u8 crcCheck(u8 smbaddr); +static uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm); static void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); static void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); @@ -1176,6 +1176,20 @@ static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCT precise_ndelay_fam15(pMCTstat, delay_ns); } +static void read_spd_bytes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dimm) +{ + uint16_t addr; + uint16_t byte; + + addr = Get_DIMMAddress_D(pDCTstat, dimm); + pDCTstat->spd_data.spd_address[dimm] = addr; + + for (byte = 0; byte < 256; byte++) { + pDCTstat->spd_data.spd_bytes[dimm][byte] = mctRead_SPD(addr, byte); + } +} + static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { @@ -1281,7 +1295,7 @@ restartinit: mct_InitialMCT_D(pMCTstat, pDCTstat); printk(BIOS_DEBUG, "%s: mctSMBhub_Init\n", __func__); - mctSMBhub_Init(Node); /* Switch SMBUS crossbar to proper node*/ + mctSMBhub_Init(Node); /* Switch SMBUS crossbar to proper node */ printk(BIOS_DEBUG, "%s: mct_preInitDCT\n", __func__); mct_preInitDCT(pMCTstat, pDCTstat); @@ -2441,7 +2455,6 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, u32 dword; u32 dev; u32 val; - u16 smbaddr; printk(BIOS_DEBUG, "%s: Start\n", __func__); @@ -2461,64 +2474,62 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, (dct + i)); - - val = mctRead_SPD(smbaddr, SPD_MTBDivisor); /* MTB=Dividend/Divisor */ - MTB16x = ((mctRead_SPD(smbaddr, SPD_MTBDividend) & 0xFF)<<4); + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB=Dividend/Divisor */ + MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xff) << 4); MTB16x /= val; /* transfer to MTB*16 */ - byte = mctRead_SPD(smbaddr, SPD_tRPmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRPmin]; val = byte * MTB16x; if (Trp < val) Trp = val; - byte = mctRead_SPD(smbaddr, SPD_tRRDmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRRDmin]; val = byte * MTB16x; if (Trrd < val) Trrd = val; - byte = mctRead_SPD(smbaddr, SPD_tRCDmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCDmin]; val = byte * MTB16x; if (Trcd < val) Trcd = val; - byte = mctRead_SPD(smbaddr, SPD_tRTPmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRTPmin]; val = byte * MTB16x; if (Trtp < val) Trtp = val; - byte = mctRead_SPD(smbaddr, SPD_tWRmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tWRmin]; val = byte * MTB16x; if (Twr < val) Twr = val; - byte = mctRead_SPD(smbaddr, SPD_tWTRmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tWTRmin]; val = byte * MTB16x; if (Twtr < val) Twtr = val; - val = mctRead_SPD(smbaddr, SPD_Upper_tRAS_tRC) & 0xFF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xFF; val >>= 4; val <<= 8; - val |= mctRead_SPD(smbaddr, SPD_tRCmin) & 0xFF; + val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCmin] & 0xFF; val *= MTB16x; if (Trc < val) Trc = val; - byte = mctRead_SPD(smbaddr, SPD_Density) & 0xF; + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Density] & 0xF; if (Trfc[LDIMM] < byte) Trfc[LDIMM] = byte; - val = mctRead_SPD(smbaddr, SPD_Upper_tRAS_tRC) & 0xF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xF; val <<= 8; - val |= (mctRead_SPD(smbaddr, SPD_tRASmin) & 0xFF); + val |= (pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRASmin] & 0xFF); val *= MTB16x; if (Tras < val) Tras = val; - val = mctRead_SPD(smbaddr, SPD_Upper_tFAW) & 0xF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tFAW] & 0xF; val <<= 8; - val |= mctRead_SPD(smbaddr, SPD_tFAWmin) & 0xFF; + val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tFAWmin] & 0xFF; val *= MTB16x; if (Tfaw < val) Tfaw = val; @@ -2934,7 +2945,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, u8 CLactual, CLdesired, CLT_Fail; uint16_t min_frequency_tck16x; - u8 smbaddr, byte = 0, bytex = 0; + u8 byte = 0, bytex = 0; CASLatLow = 0xFF; CASLatHigh = 0xFF; @@ -2955,28 +2966,27 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { if (pDCTstat->DIMMValid & (1 << i)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, (dct + i)); /* Step 1: Determine the common set of supported CAS Latency * values for all modules on the memory channel using the CAS * Latencies Supported in SPD bytes 14 and 15. */ - byte = mctRead_SPD(smbaddr, SPD_CASLow); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_CASLow]; CASLatLow &= byte; - byte = mctRead_SPD(smbaddr, SPD_CASHigh); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_CASHigh]; CASLatHigh &= byte; /* Step 2: Determine tAAmin(all) which is the largest tAAmin value for all modules on the memory channel (SPD byte 16). */ - byte = mctRead_SPD(smbaddr, SPD_MTBDivisor); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; - MTB16x = ((mctRead_SPD(smbaddr, SPD_MTBDividend) & 0xFF)<<4); + MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xFF)<<4); MTB16x /= byte; /* transfer to MTB*16 */ - byte = mctRead_SPD(smbaddr, SPD_tAAmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tAAmin]; if (tAAmin16x < byte * MTB16x) tAAmin16x = byte * MTB16x; /* Step 3: Determine tCKmin(all) which is the largest tCKmin value for all modules on the memory channel (SPD byte 12). */ - byte = mctRead_SPD(smbaddr, SPD_tCKmin); + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tCKmin]; if (tCKmin16x < byte * MTB16x) tCKmin16x = byte * MTB16x; @@ -3347,7 +3357,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, u8 byte; u16 word; u32 dword; - u16 smbaddr; dev = pDCTstat->dev_dct; @@ -3358,16 +3367,14 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, byte -= 3; if (pDCTstat->DIMMValid & (1<<byte)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, (ChipSel + dct)); - - byte = mctRead_SPD(smbaddr, SPD_Addressing); + byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing]; Rows = (byte >> 3) & 0x7; /* Rows:0b=12-bit,... */ Cols = byte & 0x7; /* Cols:0b=9-bit,... */ - byte = mctRead_SPD(smbaddr, SPD_Density); + byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Density]; Banks = (byte >> 4) & 7; /* Banks:0b=3-bit,... */ - byte = mctRead_SPD(smbaddr, SPD_Organization); + byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Organization]; Ranks = ((byte >> 3) & 7) + 1; /* Configure Bank encoding @@ -3462,46 +3469,42 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, * and determine the width mode: 64-bit, 64-bit muxed, 128-bit. */ u8 i; - u8 smbaddr, smbaddr1; u8 byte, byte1; /* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { - smbaddr = Get_DIMMAddress_D(pDCTstat, i); - smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1); - - byte = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7; - byte1 = mctRead_SPD(smbaddr1, SPD_Addressing) & 0x7; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = mctRead_SPD(smbaddr, SPD_Density) & 0x0f; - byte1 = mctRead_SPD(smbaddr1, SPD_Density) & 0x0f; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0x0f; + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Density] & 0x0f; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = mctRead_SPD(smbaddr, SPD_Organization) & 0x7; - byte1 = mctRead_SPD(smbaddr1, SPD_Organization) & 0x7; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7; + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] & 0x7; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = (mctRead_SPD(smbaddr, SPD_Organization) >> 3) & 0x7; - byte1 = (mctRead_SPD(smbaddr1, SPD_Organization) >> 3) & 0x7; + byte = (pDCTstat->spd_data.spd_bytes[i][SPD_Organization] >> 3) & 0x7; + byte1 = (pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] >> 3) & 0x7; if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; } - byte = mctRead_SPD(smbaddr, SPD_DMBANKS) & 7; /* #ranks-1 */ - byte1 = mctRead_SPD(smbaddr1, SPD_DMBANKS) & 7; /* #ranks-1 */ + byte = pDCTstat->spd_data.spd_bytes[i][SPD_DMBANKS] & 7; /* #ranks-1 */ + byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_DMBANKS] & 7; /* #ranks-1 */ if (byte != byte1) { pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); break; @@ -3682,8 +3685,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, status = mctRead_SPD(smbaddr, SPD_ByteUse); if (status >= 0) { /* SPD access is ok */ pDCTstat->DIMMPresent |= 1 << i; - if (crcCheck(smbaddr)) { /* CRC is OK */ - byte = mctRead_SPD(smbaddr, SPD_TYPE); + read_spd_bytes(pMCTstat, pDCTstat, i); + if (crcCheck(pDCTstat, i)) { /* CRC is OK */ + byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/ pDCTstat->DIMMValid |= 1 << i; @@ -3696,36 +3700,41 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, } else { /*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/ pDCTstat->ErrStatus |= 1<<SB_DIMMChkSum; - byte = mctRead_SPD(smbaddr, SPD_TYPE); + byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) pDCTstat->DIMMValid |= 1 << i; } } + + /* Zero DIMM SPD data cache if DIMM not present / valid */ + if (!(pDCTstat->DIMMValid & (1 << i))) + memset(pDCTstat->spd_data.spd_bytes[i], 0, 256); + /* Get module information for SMBIOS */ if (pDCTstat->DIMMValid & (1 << i)) { pDCTstat->DimmManufacturerID[i] = 0; for (k = 0; k < 8; k++) - pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)pDCTstat->spd_data.spd_bytes[i][SPD_MANID_START + k]) << (k * 8); for (k = 0; k < SPD_PARTN_LENGTH; k++) - pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmPartNumber[i][k] = pDCTstat->spd_data.spd_bytes[i][SPD_PARTN_START + k]; pDCTstat->DimmPartNumber[i][SPD_PARTN_LENGTH] = 0; pDCTstat->DimmRevisionNumber[i] = 0; for (k = 0; k < 2; k++) - pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)pDCTstat->spd_data.spd_bytes[i][SPD_REVNO_START + k]) << (k * 8); pDCTstat->DimmSerialNumber[i] = 0; for (k = 0; k < 4; k++) - pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); - pDCTstat->DimmRows[i] = (mctRead_SPD(smbaddr, SPD_Addressing) & 0x38) >> 3; - pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7; - pDCTstat->DimmRanks[i] = ((mctRead_SPD(smbaddr, SPD_Organization) & 0x38) >> 3) + 1; - pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3); - pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3); + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)pDCTstat->spd_data.spd_bytes[i][SPD_SERIAL_START + k]) << (k * 8); + pDCTstat->DimmRows[i] = (pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x38) >> 3; + pDCTstat->DimmCols[i] = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; + pDCTstat->DimmRanks[i] = ((pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x38) >> 3) + 1; + pDCTstat->DimmBanks[i] = 1ULL << (((pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0x70) >> 4) + 3); + pDCTstat->DimmWidth[i] = 1ULL << ((pDCTstat->spd_data.spd_bytes[i][SPD_BusWidth] & 0x7) + 3); } /* Check supported voltage(s) */ - pDCTstat->DimmSupportedVoltages[i] = mctRead_SPD(smbaddr, SPD_Voltage) & 0x7; + pDCTstat->DimmSupportedVoltages[i] = pDCTstat->spd_data.spd_bytes[i][SPD_Voltage] & 0x7; pDCTstat->DimmSupportedVoltages[i] ^= 0x1; /* Invert LSB to convert from SPD format to internal bitmap format */ /* Check module type */ - byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE) & 0x7; + byte = pDCTstat->spd_data.spd_bytes[i][SPD_DIMMTYPE] & 0x7; if (byte == JED_RDIMM || byte == JED_MiniRDIMM) { RegDIMMPresent |= 1 << i; pDCTstat->DimmRegistered[i] = 1; @@ -3739,13 +3748,13 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DimmLoadReduced[i] = 0; } /* Check ECC capable */ - byte = mctRead_SPD(smbaddr, SPD_BusWidth); + byte = pDCTstat->spd_data.spd_bytes[i][SPD_BusWidth]; if (byte & JED_ECC) { /* DIMM is ECC capable */ pDCTstat->DimmECCPresent |= 1 << i; } /* Check if x4 device */ - devwidth = mctRead_SPD(smbaddr, SPD_Organization) & 0x7; /* 0:x4,1:x8,2:x16 */ + devwidth = pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7; /* 0:x4,1:x8,2:x16 */ if (devwidth == 0) { /* DIMM is made with x4 or x16 drams */ pDCTstat->Dimmx4Present |= 1 << i; @@ -3755,7 +3764,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->Dimmx16Present |= 1 << i; } - byte = (mctRead_SPD(smbaddr, SPD_Organization) >> 3); + byte = (pDCTstat->spd_data.spd_bytes[i][SPD_Organization] >> 3); byte &= 7; if (byte == 3) { /* 4ranks */ /* if any DIMMs are QR, we have to make two passes through DIMMs*/ @@ -3790,7 +3799,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* check address mirror support for unbuffered dimm */ /* check number of registers on a dimm for registered dimm */ - byte = mctRead_SPD(smbaddr, SPD_AddressMirror); + byte = pDCTstat->spd_data.spd_bytes[i][SPD_AddressMirror]; if (RegDIMMPresent & (1 << i)) { if ((byte & 3) > 1) pDCTstat->MirrPresU_NumRegR |= 1 << i; @@ -3799,20 +3808,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->MirrPresU_NumRegR |= 1 << i; } /* Get byte62: Reference Raw Card information. We dont need it now. */ - /* byte = mctRead_SPD(smbaddr, SPD_RefRawCard); */ + /* byte = pDCTstat->spd_data.spd_bytes[i][SPD_RefRawCard]; */ /* Get Byte65/66 for register manufacture ID code */ - if ((0x97 == mctRead_SPD(smbaddr, SPD_RegManufactureID_H)) && - (0x80 == mctRead_SPD(smbaddr, SPD_RegManufactureID_L))) { - if (0x16 == mctRead_SPD(smbaddr, SPD_RegManRevID)) + if ((0x97 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManufactureID_H]) && + (0x80 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManufactureID_L])) { + if (0x16 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManRevID]) pDCTstat->RegMan2Present |= 1 << i; else pDCTstat->RegMan1Present |= 1 << i; } /* Get Control word values for RC3. We dont need it. */ - byte = mctRead_SPD(smbaddr, 70); + byte = pDCTstat->spd_data.spd_bytes[i][70]; pDCTstat->CtrlWrd3 |= (byte >> 4) << (i << 2); /* C3 = SPD byte 70 [7:4] */ /* Get Control word values for RC4, and RC5 */ - byte = mctRead_SPD(smbaddr, 71); + byte = pDCTstat->spd_data.spd_bytes[i][71]; pDCTstat->CtrlWrd4 |= (byte & 0xFF) << (i << 2); /* RC4 = SPD byte 71 [3:0] */ pDCTstat->CtrlWrd5 |= (byte >> 4) << (i << 2); /* RC5 = SPD byte 71 [7:4] */ } @@ -6190,14 +6199,14 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { * 1010 001111 16 3 10 4GB * 1011 010111 16 3 11 8GB */ -u8 crcCheck(u8 smbaddr) +uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm) { u8 byte_use; u8 Index; u16 CRC; u8 byte, i; - byte_use = mctRead_SPD(smbaddr, SPD_ByteUse); + byte_use = pDCTstat->spd_data.spd_bytes[dimm][SPD_ByteUse]; if (byte_use & 0x80) byte_use = 117; else @@ -6205,7 +6214,7 @@ u8 crcCheck(u8 smbaddr) CRC = 0; for (Index = 0; Index < byte_use; Index ++) { - byte = mctRead_SPD(smbaddr, Index); + byte = pDCTstat->spd_data.spd_bytes[dimm][Index]; CRC ^= byte << 8; for (i=0; i<8; i++) { if (CRC & 0x8000) { @@ -6215,5 +6224,5 @@ u8 crcCheck(u8 smbaddr) CRC <<= 1; } } - return CRC == (mctRead_SPD(smbaddr, SPD_byte_127) << 8 | mctRead_SPD(smbaddr, SPD_byte_126)); + return CRC == (pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_127] << 8 | pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_126]); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 3aeb7ec..e6b427e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -318,6 +318,11 @@ struct MCTStatStruc { ===============================================================================*/ #include "mwlc_d.h" /* I have to */ +struct amd_spd_node_data { + uint8_t spd_bytes[MAX_DIMMS_SUPPORTED][256]; /* [DIMM][byte] */ + uint8_t spd_address[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ +} __attribute__((packed)); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -611,6 +616,8 @@ struct DCTStatStruc { /* A per Node structure*/ char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; + + struct amd_spd_node_data spd_data; } __attribute__((packed)); struct amd_s3_persistent_mct_channel_data {

1 0

Patch set updated for coreboot: amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability
by Timothy Pearson 07 Nov '15

07 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11975 -gerrit commit 843e33038f976125585814943b6e27d6238b9441 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 4 00:10:03 2015 -0500 amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4371a37..dd01be0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3663,6 +3663,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, u8 devwidth; u16 DimmSlots; u8 byte = 0, bytex; + uint8_t crc_status; /* preload data structure with addrs */ mctGet_DIMMAddr(pDCTstat, pDCTstat->Node_ID); @@ -3683,10 +3684,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, int status; smbaddr = Get_DIMMAddress_D(pDCTstat, i); status = mctRead_SPD(smbaddr, SPD_ByteUse); + if (status >= 0) { + /* Verify result */ + status = mctRead_SPD(smbaddr, SPD_ByteUse); + } if (status >= 0) { /* SPD access is ok */ pDCTstat->DIMMPresent |= 1 << i; read_spd_bytes(pMCTstat, pDCTstat, i); - if (crcCheck(pDCTstat, i)) { /* CRC is OK */ + crc_status = crcCheck(pDCTstat, i); + if (!crc_status) { + /* Try again in case there was a transient glitch */ + read_spd_bytes(pMCTstat, pDCTstat, i); + crc_status = crcCheck(pDCTstat, i); + } + if (crc_status) { /* CRC is OK */ byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/

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Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Add Family 15h microcode file
by Timothy Pearson 07 Nov '15

07 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11968 -gerrit commit 70820e5746a46585d0a05492a2e5ae6ec040c7bc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Oct 16 14:08:32 2015 -0500 cpu/amd/family_10h-family_15h: Add Family 15h microcode file Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index 5a81ab8..6cd2513 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -12,3 +12,8 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin microcode_amd.bin-type := microcode + +# Microcode for Family 15h +cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +microcode_amd_fam15h.bin-type := microcode

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Patch set updated for coreboot: amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h
by Timothy Pearson 07 Nov '15

07 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11969 -gerrit commit e361ea808e7d9718838b5669f2dc82cb9c2cb1c5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 1 20:35:42 2015 -0500 amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 80a85ff..f4bf402 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1848,11 +1848,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, if (nv_DQSTrainCTL) { mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); - /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); + if (!is_fam15h()) { + /* TODO: should be in mctHookBeforeAnyTraining */ + _WRMSR(0x26C, 0x04040404, 0x04040404); + _WRMSR(0x26D, 0x04040404, 0x04040404); + _WRMSR(0x26E, 0x04040404, 0x04040404); + _WRMSR(0x26F, 0x04040404, 0x04040404); + } mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); if (is_fam15h()) {

1 0

Patch set updated for coreboot: cpu/amd/car: Add romstage BSP stack overrun detection
by Timothy Pearson 07 Nov '15

07 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11970 -gerrit commit a7ebd386710d8fd822283b73c0b49cfb189d1742 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 1 23:58:59 2015 -0500 cpu/amd/car: Add romstage BSP stack overrun detection Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/car/cache_as_ram.inc | 6 +++++- src/cpu/amd/car/post_cache_as_ram.c | 8 ++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 9874ec4..3295ccc 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -20,7 +20,7 @@ #include <cpu/amd/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) +#define CacheBase CONFIG_DCACHE_RAM_BASE #define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE #define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH @@ -496,6 +496,10 @@ CAR_skip_k8_errata_part2: movl $(CacheBase + CacheSize), %eax movl %eax, %esp + /* Poison the lower stack boundary */ + movl $((CacheBase + CacheSize) - CacheSizeBSPStack), %eax + movl $0xdeadbeef, (%eax) + post_code(0xa3) jmp CAR_FAM10_ap_out diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 49b9ee3..26e611c 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -98,6 +98,14 @@ void post_cache_as_ram(void) void *resume_backup_memory = NULL; uint32_t family = amd_fam1x_cpu_family(); + /* Verify that the BSP didn't overrun the lower stack + * boundary during romstage execution + */ + volatile uint32_t *lower_stack_boundary; + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_DCACHE_BSP_STACK_SIZE); + if ((*lower_stack_boundary) != 0xdeadbeef) + printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); + struct romstage_handoff *handoff; handoff = romstage_handoff_find_or_add(); if (handoff != NULL)

1 0

Patch set updated for coreboot: amd/model_fxx: fix code style in FID&VID support check
by Urja Rannikko 07 Nov '15

07 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12359 -gerrit commit dc5558631c582e87f1652a74eb4779f35bbc83e1 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Sat Nov 7 15:40:56 2015 +0200 amd/model_fxx: fix code style in FID&VID support check This is in AP code, fixed in preparation for copying the same check to BSP. Change-Id: I0750919d9fdb3d4e6666221ad82097e0c479cf14 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/cpu/amd/model_fxx/fidvid.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index a005c46..9851e65 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -356,9 +356,8 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) u32 fid_max; int loop; - if((cpuid_edx(0x80000007)&0x06)!=0x06) { + if ((cpuid_edx(0x80000007) & 0x06) != 0x06) return; /* FID/VID change not supported */ - } msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */

1 0

Patch set updated for coreboot: amd/model_fxx: Check FID&VID Support for the BSP (too)
by Urja Rannikko 07 Nov '15

07 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12336 -gerrit commit 2dda80b5ab5e71b9c814bdd95f85dc38b78c5fa0 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Sat Nov 7 15:43:06 2015 +0200 amd/model_fxx: Check FID&VID Support for the BSP (too) Tested in the direction that now my Sempron 2800+ / K8V-X boots. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/cpu/amd/model_fxx/fidvid.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 9851e65..03415d1 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -535,6 +535,9 @@ static void init_fidvid_bsp(unsigned bsp_apicid) unsigned i; #endif + if ((cpuid_edx(0x80000007) & 0x06) != 0x06) + return; /* FID/VID change not supported */ + msr_t msr; msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */

1 0

Patch set updated for coreboot: amdfam10/northbridge: fix amdfam10_scan_chain()
by Jonathan A. Kollasch 07 Nov '15

07 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10983 -gerrit commit d197418240de5ba8075b9100e25ac557e2e82789 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 20 07:43:32 2015 -0500 amdfam10/northbridge: fix amdfam10_scan_chain() Fixes two issues introduced recently: - The subordinate bus limit was reduced from essentially unlimited (0xfc) to 0 additional busses. This caused config space of subordinate busses of a non-primary HT IO chain to become unrouted (and thus invisible) during initial scan. Introduced in I41aeb80121f120641b65759c8502150ce89caa30 and I297de09dcf93511acece4441593ef958a390fddb and reinforced in subsequent related changes. - The HTcap+0x14 register is *not* the same on K8 and 10h. 10h has isochronous HT link buffer controls where K8 had bus numbers. Introduced in I41aeb80121f120641b65759c8502150ce89caa30 These two issues resulted in the non-primary IO chain not having resources allocated to subordinate busses due to the devices being invisible during initial scan, and for MMIO accesses to devices on the base bus of the non-primary chain to stall the whole machine, presumably due to invalid HT buffer allocations. Change-Id: I7a1f51bd91ab3dae6ed1c447209b36003830f3dc Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/northbridge/amd/amdfam10/northbridge.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index d1803ae..1a7bc08 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -157,7 +157,6 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } typedef enum { - HT_ROUTE_CLOSE, HT_ROUTE_SCAN, HT_ROUTE_FINAL, } scan_state; @@ -181,17 +180,8 @@ static void ht_route_link(struct bus *link, scan_state mode) * not correctly configured */ busses = pci_read_config32(link->dev, link->cap + 0x14); - busses &= 0xff000000; - busses |= parent->secondary & 0xff; - if (mode == HT_ROUTE_CLOSE) { - busses |= 0xfeff << 8; - } else if (mode == HT_ROUTE_SCAN) { - busses |= ((u32) link->secondary & 0xff) << 8; - busses |= 0xfc << 16; - } else if (mode == HT_ROUTE_FINAL) { - busses |= ((u32) link->secondary & 0xff) << 8; - busses |= ((u32) link->subordinate & 0xff) << 16; - } + busses &= 0xffff00ff; + busses |= ((u32) link->secondary & 0xff) << 8; pci_write_config32(link->dev, link->cap + 0x14, busses); if (mode == HT_ROUTE_FINAL) { @@ -251,6 +241,7 @@ static void amd_g34_fixup(struct bus *link, device_t dev) static void amdfam10_scan_chain(struct bus *link) { unsigned int next_unitid; + uint16_t sub; /* See if there is an available configuration space mapping * register in function 1. @@ -266,7 +257,10 @@ static void amdfam10_scan_chain(struct bus *link) ht_route_link(link, HT_ROUTE_SCAN); /* set the config map space */ + sub = link->subordinate; + link->subordinate = 0xfc; set_config_map_reg(link); + link->subordinate = sub; /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link

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New patch to review for coreboot: amd/model_fxx: fix code style in FID&VID support check
by Urja Rannikko 07 Nov '15

07 Nov '15

Urja Rannikko (urjaman(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12359 -gerrit commit adfc9d17e6910ceb657ccf2a7a26d85331928850 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Sat Nov 7 15:40:56 2015 +0200 amd/model_fxx: fix code style in FID&VID support check This was in AP code, fixed in preparation for adding the same check for BSP. Change-Id: I0750919d9fdb3d4e6666221ad82097e0c479cf14 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- src/cpu/amd/model_fxx/fidvid.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index a005c46..9851e65 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -356,9 +356,8 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) u32 fid_max; int loop; - if((cpuid_edx(0x80000007)&0x06)!=0x06) { + if ((cpuid_edx(0x80000007) & 0x06) != 0x06) return; /* FID/VID change not supported */ - } msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */

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coreboot-gerrit November 2015