coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: bed345d northbridge/amd/amdmct: Remove superfluous parenthesis in if-statements
by Edward O'Callaghan 22 May '14

22 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5817 -gerrit commit bed345d2daf6b9c37a3ae11e9c3cb375eae09259 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 05:58:27 2014 +1000 northbridge/amd/amdmct: Remove superfluous parenthesis in if-statements Spotted by Clang Change-Id: I98d2bf6b408caf320c5bcc8adb23d621b182976b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 10 +++++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 47b89b4..66eb88a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1532,27 +1532,27 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigLo |= 1 << 4; /* 75 Ohms ODT */ if (mctGet_NVbits(NV_MAX_DIMMS) == 8) { if (pDCTstat->Speed == 3) { - if ((pDCTstat->MAdimms[dct] == 4)) + if (pDCTstat->MAdimms[dct] == 4) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } else if (pDCTstat->Speed == 4){ - if ((pDCTstat->MAdimms[dct] != 1)) + if (pDCTstat->MAdimms[dct] != 1) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } else { // FIXME: Skip for Ax versions - if ((pDCTstat->MAdimms[dct] == 4)) { + if (pDCTstat->MAdimms[dct] == 4) { if ( pDCTstat->DimmQRPresent != 0) { if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 4)) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } - } else if ((pDCTstat->MAdimms[dct] == 4)) { + } else if (pDCTstat->MAdimms[dct] == 4) { if (pDCTstat->Speed == 4) { if ( pDCTstat->DimmQRPresent != 0) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } } - } else if ((pDCTstat->MAdimms[dct] == 2)) { + } else if (pDCTstat->MAdimms[dct] == 2) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 7db13d2..90b7ed3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3380,7 +3380,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, u32 dev = pDCTstat->dev_dct; if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { - if ((pDCTstat->Speed == 3)) + if (pDCTstat->Speed == 3) dword = 0x00000800; else dword = 0x00000000; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index aba558f..1446f4f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -502,7 +502,7 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl) } } else { /* 1 or 4 Dimms per channel */ - if ((pDCTData->MaxDimmsInstalled == 4)) + if (pDCTData->MaxDimmsInstalled == 4) { tempW1 = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ }

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Patch merged into coreboot/master: de6c3c8 southbridge/amd/cimx/sb700: Unused func smbus_delay()
by gerrit＠coreboot.org 22 May '14

22 May '14

the following patch was just integrated into master: commit de6c3c846a448e1bdb6b9335510e0aa819371402 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 06:18:10 2014 +1000 southbridge/amd/cimx/sb700: Unused func smbus_delay() Spotted by Clang. Change-Id: Ie4bed914ab694f4e96155140b8b54b6eb96d70d7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5819 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5819 for details. -gerrit

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Patch merged into coreboot/master: 3a5ea48 vendorcode/amd/agesa/f*: Fix typo in header guards
by gerrit＠coreboot.org 22 May '14

22 May '14

the following patch was just integrated into master: commit 3a5ea48c0c7c2385b51b781f86147742844900ac Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 06:15:53 2014 +1000 vendorcode/amd/agesa/f*: Fix typo in header guards _CPU_L3_FEATIRES_H -> _CPU_L3_FEATURES_H Spotted by Clang Change-Id: I1eabebffc7fd5e4f37b28dabcd28984bed64acd8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5818 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5818 for details. -gerrit

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Patch merged into coreboot/master: 72ae4a3 northbridge/amd/amdmct/mct: Initialize variables at the eol
by gerrit＠coreboot.org 22 May '14

22 May '14

the following patch was just integrated into master: commit 72ae4a3091046db366e7831b7361ea16a77672a0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 05:55:04 2014 +1000 northbridge/amd/amdmct/mct: Initialize variables at the eol Spotted by Clang Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5816 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5816 for details. -gerrit

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Patch merged into coreboot/master: f67395e southbridge/amd/sb700/smbus.c: Unused func smbus_delay()
by gerrit＠coreboot.org 22 May '14

22 May '14

the following patch was just integrated into master: commit f67395ee5b28f4d0a0694050089805d1b3395b63 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 05:51:21 2014 +1000 southbridge/amd/sb700/smbus.c: Unused func smbus_delay() Spotted by Clang Change-Id: I0f04c380b5ada28fb900710facc293edd65ac177 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5815 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5815 for details. -gerrit

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New patch to review for coreboot: 5c7d6f7 southbridge/amd/cimx/sb700: Unused func smbus_delay()
by Edward O'Callaghan 22 May '14

22 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5819 -gerrit commit 5c7d6f7bb2b1a434351c5ded14ba29bf530c298a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 06:18:10 2014 +1000 southbridge/amd/cimx/sb700: Unused func smbus_delay() Spotted by Clang. Change-Id: Ie4bed914ab694f4e96155140b8b54b6eb96d70d7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/cimx/sb700/smbus.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c index 12a0815..418adf5 100644 --- a/src/southbridge/amd/cimx/sb700/smbus.c +++ b/src/southbridge/amd/cimx/sb700/smbus.c @@ -22,11 +22,6 @@ #include "smbus.h" #include <console/console.h> /* printk */ -static inline void smbus_delay(void) -{ - outb(inb(0x80), 0x80); -} - static int smbus_wait_until_ready(u32 smbus_io_base) { u32 loops;

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New patch to review for coreboot: 7aa3a3a vendorcode/amd/agesa/f*: Fix typo in header guards
by Edward O'Callaghan 22 May '14

22 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5818 -gerrit commit 7aa3a3a6afb49e6a72fd2629ab586373a2baa3aa Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 06:15:53 2014 +1000 vendorcode/amd/agesa/f*: Fix typo in header guards _CPU_L3_FEATIRES_H -> _CPU_L3_FEATURES_H Spotted by Clang Change-Id: I1eabebffc7fd5e4f37b28dabcd28984bed64acd8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h | 2 +- src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h index d9ed4a9..ef5b23b 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h @@ -43,7 +43,7 @@ */ #ifndef _CPU_L3_FEATURES_H_ -#define _CPU_L3_FEATIRES_H_ +#define _CPU_L3_FEATURES_H_ #include "Filecode.h" /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h index 8042286..ff75b19 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h @@ -44,7 +44,7 @@ */ #ifndef _CPU_L3_FEATURES_H_ -#define _CPU_L3_FEATIRES_H_ +#define _CPU_L3_FEATURES_H_ #include "Filecode.h" /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h index 5223900..3c28bb6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h @@ -43,7 +43,7 @@ */ #ifndef _CPU_L3_FEATURES_H_ -#define _CPU_L3_FEATIRES_H_ +#define _CPU_L3_FEATURES_H_ #include "Filecode.h" /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h index d2c1424..aad05ce 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h @@ -43,7 +43,7 @@ */ #ifndef _CPU_L3_FEATURES_H_ -#define _CPU_L3_FEATIRES_H_ +#define _CPU_L3_FEATURES_H_ #include "Filecode.h" /*----------------------------------------------------------------------------------------

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New patch to review for coreboot: 63dfd7d northbridge/amd/amdmct: Remove superfluous brace in if-statements
by Edward O'Callaghan 22 May '14

22 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5817 -gerrit commit 63dfd7dd9611410c9bf3c50152f7640684433a1d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 05:58:27 2014 +1000 northbridge/amd/amdmct: Remove superfluous brace in if-statements Spotted by Clang Change-Id: I98d2bf6b408caf320c5bcc8adb23d621b182976b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 10 +++++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 47b89b4..66eb88a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1532,27 +1532,27 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigLo |= 1 << 4; /* 75 Ohms ODT */ if (mctGet_NVbits(NV_MAX_DIMMS) == 8) { if (pDCTstat->Speed == 3) { - if ((pDCTstat->MAdimms[dct] == 4)) + if (pDCTstat->MAdimms[dct] == 4) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } else if (pDCTstat->Speed == 4){ - if ((pDCTstat->MAdimms[dct] != 1)) + if (pDCTstat->MAdimms[dct] != 1) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } else { // FIXME: Skip for Ax versions - if ((pDCTstat->MAdimms[dct] == 4)) { + if (pDCTstat->MAdimms[dct] == 4) { if ( pDCTstat->DimmQRPresent != 0) { if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 4)) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } - } else if ((pDCTstat->MAdimms[dct] == 4)) { + } else if (pDCTstat->MAdimms[dct] == 4) { if (pDCTstat->Speed == 4) { if ( pDCTstat->DimmQRPresent != 0) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } } - } else if ((pDCTstat->MAdimms[dct] == 2)) { + } else if (pDCTstat->MAdimms[dct] == 2) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 7db13d2..90b7ed3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3380,7 +3380,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, u32 dev = pDCTstat->dev_dct; if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { - if ((pDCTstat->Speed == 3)) + if (pDCTstat->Speed == 3) dword = 0x00000800; else dword = 0x00000000; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index aba558f..1446f4f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -502,7 +502,7 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl) } } else { /* 1 or 4 Dimms per channel */ - if ((pDCTData->MaxDimmsInstalled == 4)) + if (pDCTData->MaxDimmsInstalled == 4) { tempW1 = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ }

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New patch to review for coreboot: b60faa0 northbridge/amd/amdmct/mct: Initialize variables at the eol
by Edward O'Callaghan 22 May '14

22 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5816 -gerrit commit b60faa019bfec01185b2de4ae3e826232ebce23a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 05:55:04 2014 +1000 northbridge/amd/amdmct/mct: Initialize variables at the eol Spotted by Clang Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/amdmct/mct/mctndi_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 1404355..a408d47 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -27,7 +27,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, u8 Node; u32 Base; u32 MemSize, MemSize0 = 0; - u32 Dct0MemSize = 0, DctSelBase, DctSelBaseOffset; + u32 Dct0MemSize, DctSelBase, DctSelBaseOffset = 0; u8 Nodes; u8 NodesWmem; u8 DoIntlv; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c index d3b2aad..520a178 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c @@ -24,7 +24,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, u8 Node; u32 Base; u32 MemSize, MemSize0 = 0; - u32 Dct0MemSize = 0, DctSelBase, DctSelBaseOffset; + u32 Dct0MemSize, DctSelBase, DctSelBaseOffset = 0; u8 Nodes; u8 NodesWmem; u8 DoIntlv;

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New patch to review for coreboot: 05b8200 southbridge/amd/sb700/smbus.c: Unused func smbus_delay()
by Edward O'Callaghan 22 May '14

22 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5815 -gerrit commit 05b82007de9350e191c0717774b9cc311b4c48d4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 05:51:21 2014 +1000 southbridge/amd/sb700/smbus.c: Unused func smbus_delay() Spotted by Clang Change-Id: I0f04c380b5ada28fb900710facc293edd65ac177 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/sb700/smbus.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c index 5b22502..46dad41 100644 --- a/src/southbridge/amd/sb700/smbus.c +++ b/src/southbridge/amd/sb700/smbus.c @@ -66,12 +66,6 @@ void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) outl(tmp, AB_DATA); } - -static inline void smbus_delay(void) -{ - outb(inb(0x80), 0x80); -} - static int smbus_wait_until_ready(u32 smbus_io_base) { u32 loops;

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coreboot-gerrit May 2014