coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 11c098e Print segment clean up information only when required.
by Marc Jones 27 Dec '14

27 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7937 -gerrit commit 11c098e407d91ddfd5b23c0b7929b834a8f40756 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 13 15:43:58 2014 -0700 Print segment clean up information only when required. Eliminate duplicated printout and if needed, print only changed information. BUG=none TEST=verified that the 'New segment dstaddr...' message is not duplicated anymore Original-Change-Id: Ia13593394fccbb225f2bd9ab2b9228bac29d50fb Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199672 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit aadf018821ebfa63d6ac9d2429ae1fb483dd6cb3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7544bddc4026191395cfe3b8ac66256ec223391e --- src/lib/selfboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8e9e0de..de059b0 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -252,9 +252,10 @@ static int build_self_segment_list( /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; + printk(BIOS_DEBUG, + " cleaned up filesize 0x%lx\n", + new->s_filesz); } - printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS:

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New patch to review for coreboot: dc46d6a vboot: Add a new post code for TPM failure
by Marc Jones 27 Dec '14

27 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7936 -gerrit commit dc46d6aeb0454860323912862f5e32dd2f5cd535 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 12 10:22:01 2014 -0700 vboot: Add a new post code for TPM failure If the kernel does not properly handle the TPM and send it a TPM_SaveState command before suspend then it will not be in the correct state on resume. In order to easily detect this case add a new post code for TPM failure and use it in the vboot resume path. BUG=chromium:371105 TEST=Build and boot on wtm2. Original-Change-Id: I412520b521387a8e18ad1c6f5a64b39cdd5c88ec Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199371 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit ff2f0dc56c1a783295710f81567af02729fe1da2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5baf894fd72922acd79d191e5485ae8ef7e0d559 --- src/include/console/post_codes.h | 7 +++++++ src/vendorcode/google/chromeos/vboot.c | 1 + 2 files changed, 8 insertions(+) diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 0310db3..9f9b788 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -220,6 +220,13 @@ #define POST_JUMPING_TO_PAYLOAD 0xf3 /** + * \brief TPM failure + * + * An error with the TPM, either unexepcted state or communications failure. + */ +#define POST_TPM_FAILURE 0xed + +/** * \brief Not supposed to get here * * A function that should not have returned, returned diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index e42961f..44fe9e3 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -233,6 +233,7 @@ static void init_vboot(int bootmode) #if !MOCK_TPM printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); + post_code(POST_TPM_FAILURE); hard_reset(); #endif }

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New patch to review for coreboot: 5887876 SPI: Add Eon EN25S64 support.
by Marc Jones 27 Dec '14

27 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7935 -gerrit commit 588787684c620dacc2037e05a83718a823b4ca37 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu May 1 14:54:11 2014 -0600 SPI: Add Eon EN25S64 support. BUG=chrome-os-partner:25907 BRANCH=baytrail(rambi) TEST=Read and write MRC and ELOG on Glimmer with Eon device. Original-Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d Original-Reviewed-on: https://chromium-review.googlesource.com/198324 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: Marc Jones <marc.jones(a)se-eng.com> Original-Tested-by: Marc Jones <marc.jones(a)se-eng.com> (cherry picked from commit 536c34c2d92178f4e62b8ca7cfffceaf80a305f6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I199451ed2b29c55bfb5e1487afa8cf3b9978e63e --- src/drivers/spi/eon.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 2e5fa8c..684fb2e 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -26,6 +26,7 @@ #define EON_ID_EN25Q128 0x3018 #define EON_ID_EN25Q64 0x3017 +#define EON_ID_EN25S64 0x3817 struct eon_spi_flash_params { u16 id; @@ -64,6 +65,14 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = { .nr_sectors = 2048, .name = "EN25Q64", }, + { + .id = EON_ID_EN25S64, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 2048, + .name = "EN25S64", + }, }; static int eon_write(struct spi_flash *flash,

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New patch to review for coreboot: e40b480 SPI: Fix Eon support
by Marc Jones 27 Dec '14

27 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7934 -gerrit commit e40b4809a2779416e6b58ebcfe6a378657845245 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu May 1 14:53:24 2014 -0600 SPI: Fix Eon support The Eon SPI25 code had a number of issues: - fix page write calculation - fix erase segment - fix id check - fix sector size - make commands EN25 generic This make the code similar to other SPI25 devices used in coreboot. BUG=chrome-os-partner:25907 BRANCH=baytrail(rambi) TEST=Read and write MRC and ELOG on Glimmer with Eon device. Original-Change-Id: I7667eab28b850790d92a591c869788d51c26a56c Original-Reviewed-on: https://chromium-review.googlesource.com/198323 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: Marc Jones <marc.jones(a)se-eng.com> Original-Tested-by: Marc Jones <marc.jones(a)se-eng.com> (cherry picked from commit 2ee0da695bf6a6c6aedc0dd2b3a3b7c9c3165bca) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8917e778cd62f3745189336d23c0c6118887d893 --- src/drivers/spi/eon.c | 90 +++++++++++++++++++++++++++------------------------ 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 69869e9..2e5fa8c 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -1,5 +1,7 @@ /* * (C) Copyright 2010, ucRobotics Inc. + * Copyright (c) 2014, Sage Electronic Engineering, LLC + * . * Author: Chong Huang <chuang(a)ucrobotics.com> * Licensed under the GPL-2 or later. */ @@ -9,24 +11,24 @@ #include "spi_flash_internal.h" -/* EN25Q128-specific commands */ -#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ -#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ -#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ -#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ -#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ -#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_EN25Q128_PP 0x02 /* Page Program */ -#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ -#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ -#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ -#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ - -#define EON_ID_EN25Q64 0x17 -#define EON_ID_EN25Q128 0x18 +/* EN25*-specific commands */ +#define CMD_EN25_WREN 0x06 /* Write Enable */ +#define CMD_EN25_WRDI 0x04 /* Write Disable */ +#define CMD_EN25_RDSR 0x05 /* Read Status Register */ +#define CMD_EN25_WRSR 0x01 /* Write Status Register */ +#define CMD_EN25_READ 0x03 /* Read Data Bytes */ +#define CMD_EN25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_EN25_PP 0x02 /* Page Program */ +#define CMD_EN25_SE 0x20 /* Sector Erase */ +#define CMD_EN25_BE 0xd8 /* Block Erase */ +#define CMD_EN25_DP 0xb9 /* Deep Power-down */ +#define CMD_EN25_RES 0xab /* Release from DP, and Read Signature */ + +#define EON_ID_EN25Q128 0x3018 +#define EON_ID_EN25Q64 0x3017 struct eon_spi_flash_params { - u8 idcode1; + u16 id; u16 page_size; u16 pages_per_sector; u16 sectors_per_block; @@ -47,7 +49,7 @@ static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash) static const struct eon_spi_flash_params eon_spi_flash_table[] = { { - .idcode1 = EON_ID_EN25Q128, + .id = EON_ID_EN25Q128, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, @@ -55,7 +57,7 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = { .name = "EN25Q128", }, { - .idcode1 = EON_ID_EN25Q64, + .id = EON_ID_EN25Q64, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, @@ -68,7 +70,6 @@ static int eon_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { struct eon_spi_flash *eon = to_eon_spi_flash(flash); - unsigned long page_addr; unsigned long byte_addr; unsigned long page_size; size_t chunk_len; @@ -76,19 +77,25 @@ static int eon_write(struct spi_flash *flash, int ret = 0; u8 cmd[4]; - page_size = eon->params->page_size; - page_addr = offset / page_size; + page_size = 1 << eon->params->page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); - cmd[0] = CMD_EN25Q128_PP; - cmd[1] = page_addr >> 8; - cmd[2] = page_addr; - cmd[3] = byte_addr; + ret = spi_flash_cmd(flash->spi, CMD_EN25_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + cmd[0] = CMD_EN25_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, @@ -96,38 +103,35 @@ static int eon_write(struct spi_flash *flash, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); - if (ret < 0) { - printk(BIOS_WARNING, "SF: Enabling Write failed\n"); - break; - } - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: EON Page Program failed\n"); - break; + goto out; } ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - break; + if (ret) { + printk(BIOS_WARNING, "SF: EON Page Program timeout\n"); + goto out; + } - page_addr++; + offset += chunk_len; byte_addr = 0; } #if CONFIG_DEBUG_SPI_FLASH - printk(BIOS_SPEW, "SF: EON: Successfully programmed %zu bytes @ 0x%x\n", - len, offset); + printk(BIOS_SPEW, "SF: EON: Successfully programmed %zu bytes @ %#x\n", + len, (unsigned int)(offset - len)); #endif +out: return ret; } static int eon_erase(struct spi_flash *flash, u32 offset, size_t len) { - return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len); + return spi_flash_cmd_erase(flash, CMD_EN25_SE, offset, len); } struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) @@ -138,12 +142,13 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { params = &eon_spi_flash_table[i]; - if (params->idcode1 == idcode[2]) + if (params->id == ((idcode[1] << 8) | idcode[2])) break; } if (i == ARRAY_SIZE(eon_spi_flash_table)) { - printk(BIOS_WARNING, "SF: Unsupported EON ID %02x\n", idcode[1]); + printk(BIOS_WARNING, "SF: Unsupported EON ID %#02x%02x\n", + idcode[1], idcode[2]); return NULL; } @@ -160,8 +165,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) eon->flash.write = eon_write; eon->flash.erase = eon_erase; eon->flash.read = spi_flash_cmd_read_fast; - eon->flash.sector_size = params->page_size * params->pages_per_sector - * params->sectors_per_block; + eon->flash.sector_size = params->page_size * params->pages_per_sector; eon->flash.size = params->page_size * params->pages_per_sector * params->nr_sectors;

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New patch to review for coreboot: 1282e28 Prepare Spansion driver for use in CBFS wrapper
by Marc Jones 27 Dec '14

27 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7933 -gerrit commit 1282e28becdf933c3b6284b534c628a99781e64f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 19:30:46 2014 -0700 Prepare Spansion driver for use in CBFS wrapper Since the same driver is going to be used at all coreboot stages, it can not use malloc() anymore. Replace it with static allocation of the driver container structure. The read interface is changed to spi_flash_cmd_read_slow(), because of the problems with spi_flash_cmd_read_fast() implementation. In fact there is no performance difference in the way the two interface functions are implemented. BUG=chrome-os-partner:27784 TEST=manual . with all patches applied coreboot proceeds to attempting to load the payload. Original-Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197931 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 57ee2fd875c689706c70338e073acefb806787e7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9d9e7e343148519580ed4986800dc6c6b9a5f5d2 --- src/drivers/spi/spansion.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index e17f890..c7e31fe 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -208,6 +208,8 @@ static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len); } +static struct spansion_spi_flash spsn_flash; + struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) { const struct spansion_spi_flash_params *params; @@ -231,11 +233,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) return NULL; } - spsn = malloc(sizeof(struct spansion_spi_flash)); - if (!spsn) { - printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); - return NULL; - } + spsn = &spsn_flash; spsn->params = params; spsn->flash.spi = spi; @@ -243,7 +241,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) spsn->flash.write = spansion_write; spsn->flash.erase = spansion_erase; - spsn->flash.read = spi_flash_cmd_read_fast; + spsn->flash.read = spi_flash_cmd_read_slow; spsn->flash.sector_size = params->page_size * params->pages_per_sector; spsn->flash.size = spsn->flash.sector_size * params->nr_sectors;

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New patch to review for coreboot: bb18e42 Provide a common CBFS wrapper for SPI storage
by Marc Jones 27 Dec '14

27 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7932 -gerrit commit bb18e42518058d3a5ecaee762938f522e9407e07 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 12:23:09 2014 -0700 Provide a common CBFS wrapper for SPI storage Coreboot has all necessary infrastructure to use the proper SPI flash interface in bootblock for CBFS. This patch creates a common CBFS wrapper which can be enabled on different platforms as required. COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the common CBFS interface and prevents default inclusion of all SPI chip drivers, only explicitly configured ones will be included when the new feature is enabled. Since the wrapper uses the same driver at all stages, enabling the new feature will also make it necessary to include the SPI chip drivers in bootblock and romstage images. init_default_cbfs_media() can now be common for different platforms, and as such is defined in the library. BUG=none TEST=manual . with this change and the rest of the patches coreboot on AP148 comes up all the way to attempting to boot the payload (reading earlier stages from the SPI flash along the way). Original-Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197800 Original-Tested-by: Vadim Bendebury <vbendeb(a)google.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 60eb16ebe624f9420c6191afa6ba239b8e83a6e6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7b0bf3dda915c227659ab62743e405312dedaf41 --- src/Kconfig | 8 ++++ src/drivers/spi/Kconfig | 20 ++++----- src/drivers/spi/Makefile.inc | 24 +++++++++++ src/lib/Makefile.inc | 4 ++ src/lib/cbfs_spi.c | 96 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 142 insertions(+), 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7b52589..1aff981 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,6 +47,14 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. +config COMMON_CBFS_SPI_WRAPPER + bool + default n + depends on SPI_FLASH + depends on !ARCH_X86 + help + Use common wrapper to interface CBFS to SPI bootprom. + choice prompt "Compiler to use" default COMPILER_GCC diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index cc8703f..3a1950f 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -59,70 +59,70 @@ config SPI_FLASH_NO_FAST_READ config SPI_FLASH_ADESTO bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Adesto Technologies. config SPI_FLASH_AMIC bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by AMIC. config SPI_FLASH_ATMEL bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Atmel. config SPI_FLASH_EON bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON. config SPI_FLASH_GIGADEVICE bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice. config SPI_FLASH_MACRONIX bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Macronix. config SPI_FLASH_SPANSION bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Spansion. config SPI_FLASH_SST bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST. config SPI_FLASH_STMICRO bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by ST MICRO. config SPI_FLASH_WINBOND bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 934743e..1cb789a 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -1,4 +1,28 @@ # SPI flash driver interface + +ifeq ($(CONFIG_COMMON_CBFS_SPI_WRAPPER),y) +bootblock-y += spi_flash.c +bootblock-$(CONFIG_SPI_FLASH_EON) += eon.c +bootblock-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c +bootblock-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +bootblock-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +bootblock-$(CONFIG_SPI_FLASH_SST) += sst.c +bootblock-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +bootblock-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +bootblock-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c + +romstage-$(CONFIG_SPI_FLASH) += spi_flash.c +romstage-$(CONFIG_SPI_FLASH_EON) += eon.c +romstage-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c +romstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +romstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +romstage-$(CONFIG_SPI_FLASH_SST) += sst.c +romstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +romstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +romstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c + +endif + ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b7daea1..5c50ad1 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,8 @@ subdirs-y += loaders bootblock-y += cbfs.c cbfs_core.c +bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c + bootblock-y += memchr.c bootblock-y += memcmp.c @@ -29,6 +31,7 @@ $(foreach arch,$(ARCH_SUPPORTED),\ romstage-$(CONFIG_I2C_TPM) += delay.c romstage-y += cbfs.c cbfs_core.c +romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c @@ -55,6 +58,7 @@ ramstage-y += delay.c ramstage-y += fallback_boot.c ramstage-y += compute_ip_checksum.c ramstage-y += cbfs.c cbfs_core.c +ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c ramstage-y += clog2.c diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c new file mode 100644 index 0000000..717a4a3 --- /dev/null +++ b/src/lib/cbfs_spi.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This file provides a common CBFS wrapper for SPI storage. SPI driver + * context is expanded with the buffer descriptor used to store data read from + * SPI. + */ + +#include <cbfs.h> +#include <spi_flash.h> + +/* SPI flash as CBFS media. */ +struct cbfs_spi_context { + struct spi_flash *spi_flash_info; + struct cbfs_simple_buffer buffer; +}; + +static struct cbfs_spi_context spi_context; + +static int cbfs_media_open(struct cbfs_media *media) +{ + return 0; +} + +static int cbfs_media_close(struct cbfs_media *media) +{ + return 0; +} + +static size_t cbfs_media_read(struct cbfs_media *media, + void *dest, size_t offset, + size_t count) +{ + struct cbfs_spi_context *context = media->context; + + return context->spi_flash_info->read + (context->spi_flash_info, offset, count, dest) ? 0 : count; +} + +static void *cbfs_media_map(struct cbfs_media *media, + size_t offset, size_t count) +{ + struct cbfs_spi_context *context = media->context; + + return cbfs_simple_buffer_map(&context->buffer, media, offset, count); +} + +static void *cbfs_media_unmap(struct cbfs_media *media, + const void *address) +{ + struct cbfs_spi_context *context = media->context; + + return cbfs_simple_buffer_unmap(&context->buffer, address); +} + +int init_default_cbfs_media(struct cbfs_media *media) +{ + if (spi_context.buffer.buffer) + return 0; /* It has been already initialized. */ + + spi_context.spi_flash_info = spi_flash_probe + (CONFIG_BOOT_MEDIA_SPI_BUS, 0); + if (!spi_context.spi_flash_info) + return -1; + + spi_context.buffer.buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS; + spi_context.buffer.size = CONFIG_CBFS_CACHE_SIZE; + + media->context = &spi_context; + + media->open = cbfs_media_open; + media->close = cbfs_media_close; + media->read = cbfs_media_read; + media->map = cbfs_media_map; + media->unmap = cbfs_media_unmap; + + return 0; +} +

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New patch to review for coreboot: c87f9e2 storm: add support for another Spansion chip
by Marc Jones 27 Dec '14

27 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7931 -gerrit commit c87f9e29cc6eb9032c06339668fa606132d74734 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 15:50:43 2014 -0700 storm: add support for another Spansion chip Add the device ID definitions and properties for the SPI chip used on the AP148 board. BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to read the payload. Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197895 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b --- src/drivers/spi/spansion.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fba816a..e17f890 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -48,10 +48,12 @@ #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 #define SPSN_ID_S25FL064A 0x0216 +#define SPSN_ID_S25FL128S 0x0219 #define SPSN_ID_S25FL128P 0x2018 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 #define SPSN_EXT_ID_S25FL032P 0x4d00 +#define SPSN_EXT_ID_S25FLXXS_64KB 0x4d01 struct spansion_spi_flash_params { u16 idcode1; @@ -123,6 +125,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .name = "S25FL128P_256K", }, { + .idcode1 = SPSN_ID_S25FL128S, + .idcode2 = SPSN_EXT_ID_S25FLXXS_64KB, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 512, + .name = "S25FL128S_256K", + }, + { .idcode1 = SPSN_ID_S25FL032A, .idcode2 = SPSN_EXT_ID_S25FL032P, .page_size = 256,

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Patch merged into coreboot/master: c7aa64b blaze: change ramcode 0001/0010 to use 792MHz bct
by gerrit＠coreboot.org 26 Dec '14

26 Dec '14

the following patch was just integrated into master: commit c7aa64bdff08399f43d58b615c0153a0001008c6 Author: Jerry Wang <jerryw(a)nvidia.com> Date: Mon May 12 10:52:43 2014 +0800 blaze: change ramcode 0001/0010 to use 792MHz bct This change updates the cfg file for Micron/Samsung 2GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad Original-Signed-off-by: Jerry Wang <jerryw(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/199296 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit cb70674c6551c8c36d2fd2d220e0f677ed2c6b24) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I11222bc1453a76cc27c2be169be5d3481ed7cfe7 Reviewed-on: http://review.coreboot.org/7902 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7902 for details. -gerrit

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Patch merged into coreboot/master: c852206 nyan*: Detect watchdog resets and reset the whole machine.
by gerrit＠coreboot.org 26 Dec '14

26 Dec '14

the following patch was just integrated into master: commit c85220654f03e1c0815627c36fb3928aef4e6850 Author: Gabe Black <gabeblack(a)google.com> Date: Tue May 6 15:44:14 2014 -0700 nyan*: Detect watchdog resets and reset the whole machine. When a watchdog reset happens, the SOC will reset but other parts of the system might not. That puts the machine in a funny state and may prevent it from booting properly. BUG=chrome-os-partner:28559 TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/198582 Reviewed-by: Tom Warren <twarren(a)nvidia.com> Reviewed-by: Andrew Bresticker <abrestic(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7900 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7900 for details. -gerrit

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Patch merged into coreboot/master: 4dc3e28 tegra124: Add a utility function to read the cause of the most recent reset.
by gerrit＠coreboot.org 26 Dec '14

26 Dec '14

the following patch was just integrated into master: commit 4dc3e28c741cd0b5ce6effeaec58eeda45b12303 Author: Gabe Black <gabeblack(a)google.com> Date: Tue May 6 15:33:37 2014 -0700 tegra124: Add a utility function to read the cause of the most recent reset. When a watchdog reset happens, the SOC will reset but other parts of the system might not. In order to detect those situations we can check the rst_status register in the PMC. BUG=chrome-os-partner:28559 TEST=With this and a change which uses the new function in the nyan boards, built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/198581 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72 Reviewed-on: http://review.coreboot.org/7899 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7899 for details. -gerrit

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coreboot-gerrit December 2014