coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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1346 discussions

New patch to review for coreboot: 299dea9 3rdparty: Update to latest commit in blobs repository
by Paul Menzel 28 Dec '14

28 Dec '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7963 -gerrit commit 299dea93920ea1b66444d3347ed88a33e6cfb536 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Dec 28 12:09:23 2014 +0100 3rdparty: Update to latest commit in blobs repository Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error occurs) unintentionally reverted commit 16472743 (3dparty: Update to latest commit in blobs repository). Apply that commit again: 'blobs' now contains updates which allow binary AGESA to build with Clang. Pull those in, in anticipation of re-enabling -Werror on Clang builds. Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- 3rdparty | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index 9f68e20..a8b0c52 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 9f68e20e5ef4b6681fb18bdb4022471bc6810788 +Subproject commit a8b0c52850495c30dfa1cd8cc2c679a6ba4e18ac

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New patch to review for coreboot: 599b728 haswell: Fix MRC cache to use CBFS
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7962 -gerrit commit 599b7284489e1fcb53646f9a217b1c85676e4803 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 21:04:53 2014 +0200 haswell: Fix MRC cache to use CBFS Place the mrc.cache file at top of CBFS. There is no real requirement for it to have a fixed location though. Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/haswell/Kconfig | 10 ---------- src/northbridge/intel/haswell/Makefile.inc | 12 ++++++++++++ src/northbridge/intel/haswell/mrccache.c | 12 +++++------- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index cac5c46..0845a3f 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -42,16 +42,6 @@ config CACHE_MRC_SIZE_KB int default 512 -# FIXME: build from rom size -config MRC_CACHE_BASE - hex - default 0xff800000 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x370000 - config MRC_CACHE_SIZE hex depends on !CHROMEOS diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index f2577c7..c8ebcdb 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -40,3 +40,15 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := 0xab +ifneq ($(CONFIG_CHROMEOS),y) +$(obj)/mrc.cache: $(obj)/config.h + dd if=/dev/zero count=1 \ + bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ + tr '\000' '\377' > $@ + +cbfs-files-y += mrc.cache +mrc.cache-file := $(obj)/mrc.cache +mrc.cache-position := 0xfffe0000 +mrc.cache-type := 0xac +endif + diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..540bbf6 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -66,16 +66,14 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; #if CONFIG_CHROMEOS - region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else - region_size = CONFIG_MRC_CACHE_SIZE; - *mrc_region_ptr = (struct mrc_data_container *) - (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); -#endif - + size_t region_size; + *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + "mrc.cache", 0xac, &region_size); return region_size; +#endif } /*

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Patch set updated for coreboot: e9cee35 x86 SMM: Replace weak prototypes with weak function stub
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7961 -gerrit commit e9cee350d53bc35d401b4667c9a85f853e3718eb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 10:21:26 2014 +0200 x86 SMM: Replace weak prototypes with weak function stub Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/smm/smihandler.c | 21 +++++++++++++++------ src/include/cpu/x86/smm.h | 16 ++++++---------- src/southbridge/amd/agesa/hudson/smihandler.c | 6 ++---- src/southbridge/amd/pi/avalon/smihandler.c | 6 ++---- src/southbridge/intel/bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/i82801dx/smihandler.c | 10 ++++------ src/southbridge/intel/i82801gx/smihandler.c | 12 +++++------- src/southbridge/intel/i82801ix/smihandler.c | 12 +++++------- src/southbridge/intel/ibexpeak/smihandler.c | 16 ++++++---------- 10 files changed, 57 insertions(+), 74 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index c864df2..9d21015 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -185,12 +185,9 @@ void smi_handler(u32 smm_revision) } /* Call chipset specific SMI handlers. */ - if (cpu_smi_handler) - cpu_smi_handler(node, &state_save); - if (northbridge_smi_handler) - northbridge_smi_handler(node, &state_save); - if (southbridge_smi_handler) - southbridge_smi_handler(node, &state_save); + cpu_smi_handler(node, &state_save); + northbridge_smi_handler(node, &state_save); + southbridge_smi_handler(node, &state_save); smi_restore_pci_address(); @@ -201,3 +198,15 @@ void smi_handler(u32 smm_revision) /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); } + +/* Provide a default implementation for all weak handlers so that relocation + * entries in the modules make sense. Without default implementations the + * weak relocations w/o a symbol have a 0 address which is where the modules + * are linked at. */ +int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } +void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} +int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } +void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7b529e0..c16a6c5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -467,7 +467,7 @@ void smi_handler(u32 smm_revision); void io_trap_handler(int smif); int southbridge_io_trap_handler(int smif); -int __attribute__((weak)) mainboard_io_trap_handler(int smif); +int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); @@ -475,18 +475,14 @@ void southbridge_smi_set_eos(void); void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); +#else +void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +#endif /* CONFIG_SMM_MODULES */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#else -void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); - -void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts); -int __attribute__((weak)) mainboard_smi_apmc(u8 data); -void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); -#endif /* CONFIG_SMM_MODULES */ #if !CONFIG_SMM_TSEG void smi_release_lock(void); diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index d1b661b..af8c215 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occurred */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/amd/pi/avalon/smihandler.c b/src/southbridge/amd/pi/avalon/smihandler.c index e762d0b..6f2504b 100644 --- a/src/southbridge/amd/pi/avalon/smihandler.c +++ b/src/southbridge/amd/pi/avalon/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occured */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 1b8810f..e1773a9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 493a98e..ae9e9c6 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -353,8 +353,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -541,8 +540,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -584,12 +582,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 9b0c235..eafb605 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -441,12 +441,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 4959c4d..998bacb 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -369,7 +369,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -454,12 +454,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 6d17621..604e85f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -235,7 +235,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -322,12 +322,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index b6ca523..9f1d35c 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); }

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New patch to review for coreboot: 210c0e1 x86 SMM: Replace weak prototypes with weak function stub
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7961 -gerrit commit 210c0e1cfad8a74fe33c83980b26f37259df268d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 10:21:26 2014 +0200 x86 SMM: Replace weak prototypes with weak function stub Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/smm/smihandler.c | 21 +++++++++++++++------ src/include/cpu/x86/smm.h | 16 ++++++---------- src/southbridge/amd/agesa/hudson/smihandler.c | 6 ++---- src/southbridge/amd/pi/avalon/smihandler.c | 6 ++---- src/southbridge/intel/bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/i82801dx/smihandler.c | 10 ++++------ src/southbridge/intel/i82801gx/smihandler.c | 12 +++++------- src/southbridge/intel/i82801ix/smihandler.c | 12 +++++------- src/southbridge/intel/ibexpeak/smihandler.c | 16 ++++++---------- 10 files changed, 57 insertions(+), 74 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index c864df2..9d21015 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -185,12 +185,9 @@ void smi_handler(u32 smm_revision) } /* Call chipset specific SMI handlers. */ - if (cpu_smi_handler) - cpu_smi_handler(node, &state_save); - if (northbridge_smi_handler) - northbridge_smi_handler(node, &state_save); - if (southbridge_smi_handler) - southbridge_smi_handler(node, &state_save); + cpu_smi_handler(node, &state_save); + northbridge_smi_handler(node, &state_save); + southbridge_smi_handler(node, &state_save); smi_restore_pci_address(); @@ -201,3 +198,15 @@ void smi_handler(u32 smm_revision) /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); } + +/* Provide a default implementation for all weak handlers so that relocation + * entries in the modules make sense. Without default implementations the + * weak relocations w/o a symbol have a 0 address which is where the modules + * are linked at. */ +int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } +void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} +int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } +void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7b529e0..c16a6c5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -467,7 +467,7 @@ void smi_handler(u32 smm_revision); void io_trap_handler(int smif); int southbridge_io_trap_handler(int smif); -int __attribute__((weak)) mainboard_io_trap_handler(int smif); +int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); @@ -475,18 +475,14 @@ void southbridge_smi_set_eos(void); void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); +#else +void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +#endif /* CONFIG_SMM_MODULES */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#else -void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); - -void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts); -int __attribute__((weak)) mainboard_smi_apmc(u8 data); -void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); -#endif /* CONFIG_SMM_MODULES */ #if !CONFIG_SMM_TSEG void smi_release_lock(void); diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index d1b661b..af8c215 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occurred */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/amd/pi/avalon/smihandler.c b/src/southbridge/amd/pi/avalon/smihandler.c index e762d0b..6f2504b 100644 --- a/src/southbridge/amd/pi/avalon/smihandler.c +++ b/src/southbridge/amd/pi/avalon/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occured */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 1b8810f..e1773a9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 493a98e..ae9e9c6 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -353,8 +353,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -541,8 +540,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -584,12 +582,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 9b0c235..e27f623 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -441,12 +441,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16) + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 4959c4d..998bacb 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -369,7 +369,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -454,12 +454,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 6d17621..604e85f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -235,7 +235,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -322,12 +322,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index b6ca523..9f1d35c 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); }

1 0

New patch to review for coreboot: 76f1c62 intel baytrail broadwell: Include microcode updates
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7960 -gerrit commit 76f1c62b7772a487524dd3711670fe65f8ec8aeb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 12:57:06 2014 +0200 intel baytrail broadwell: Include microcode updates Commit 66e0c4c renamed the variable. Change-Id: I9e8dc3e7f140411d04b35a21ada76aaa578832fb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/intel/baytrail/Kconfig | 2 +- src/soc/intel/broadwell/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bc90b11..bcaa1ff 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -15,7 +15,7 @@ config CPU_SPECIFIC_OPTIONS select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1498489..019bed3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,7 +20,7 @@ config CPU_SPECIFIC_OPTIONS select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER

1 0

New patch to review for coreboot: 6362e57 intel: Fix UPDATE-FIT step in build
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7959 -gerrit commit 6362e57986d354952ede80e8549cf14f04899b27 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 11:55:47 2014 +0200 intel: Fix UPDATE-FIT step in build Regression in commit 88ca81a caused UPDATE-FIT step to no longer run when microcode was added to CBFS. Change-Id: I6ea4b6b6a8de598be810c930baa497f8c7fdc4b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index b1df7c5..b0289c0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -599,7 +599,7 @@ ifeq ($(CONFIG_PXE_ROM),y) $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) +ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y) @printf " UPDATE-FIT \n" $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) endif

1 0

New patch to review for coreboot: 1c34417 cbfstool: Fix update-fit command
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7958 -gerrit commit 1c34417235165862340413b50f8b0854b82a9eda Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 13:08:54 2014 +0200 cbfstool: Fix update-fit command Regression in commit 3fcde22 caused parse_microcode_blob() to access data outside cpu_microcode_blob.bin file in CBFS and create invalid Intel Firmware Interface Table entries. Change-Id: I1a687060084c2acd6cac5f5053b74a332b4ac714 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/cbfstool/fit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index bf6c6d4..0652129 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -207,8 +207,8 @@ static int parse_microcode_blob(struct cbfs_image *image, uint32_t current_offset; uint32_t file_length; - current_offset = (int)((char *)mcode_file - image->buffer.data); fit_header(mcode_file, &current_offset, &file_length); + current_offset += (int)((char *)mcode_file - image->buffer.data); num_mcus = 0; while (file_length > sizeof(struct microcode_header))

1 0

New patch to review for coreboot: 234f02e intel: Fix microcode alignment
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7957 -gerrit commit 234f02e8cf1cbb98018b305cd8aeefa0e708dc91 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 11:47:21 2014 +0200 intel: Fix microcode alignment CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS. Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only used with PLATFORM_FSP. CPU_MICROCODE_CBFS_LEN was no longer used at all. Change-Id: I0454397924d2526d97b1f095cc371ba962873c99 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/Kconfig | 13 ------------- src/cpu/Makefile.inc | 2 +- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index b0f7a14..9ab0556 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -159,16 +159,3 @@ config CPU_MICROCODE_FILE default "cpu_microcode.bin" help The path and filename of the file containing the CPU microcode. - -config CPU_MICROCODE_CBFS_LOC - hex "Microcode address in CBFS" - depends on CPU_MICROCODE_IN_CBFS - default 0 - -config CPU_MICROCODE_CBFS_LEN - hex "Microcode length in CBFS" - depends on CPU_MICROCODE_IN_CBFS - default 0xC000 - help - The microcode needs a specific length to get correctly - detected and loaded by all CPUs. diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 60864ef..2411aeb 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -29,7 +29,7 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin cbfs_include_ucode = y endif -ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC), 0) +ifeq ($(CONFIG_PLATFORM_USES_FSP), y) cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)" else cpu_ucode_cbfs_offset = "-b"

1 0

New patch to review for coreboot: 5835251 RELOCATABLE_RAMSTAGE: Fix weak symbols with option ROMs
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7956 -gerrit commit 58352511efb27427b54ae22e78d0246419382972 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 13:29:09 2014 +0200 RELOCATABLE_RAMSTAGE: Fix weak symbols with option ROMs After relocation the weak symbol map_oprom_vendev is no longer NULL. Always have empty stub function defined. Change-Id: I5b1bdeb3f37bb04363cf3d9dedaeafc9e193aaae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_rom.c | 6 ++++-- src/include/device/pci_rom.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 1bdccf0..dbc05ac 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -29,6 +29,9 @@ #include <string.h> #include <cbfs.h> +/* Rmodules don't like weak symbols. */ +u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } + struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header; @@ -41,8 +44,7 @@ struct rom_header *pci_rom_probe(struct device *dev) u32 vendev = (dev->vendor << 16) | dev->device; u32 mapped_vendev = vendev; - if (map_oprom_vendev) - mapped_vendev = map_oprom_vendev(vendev); + mapped_vendev = map_oprom_vendev(vendev); if (!rom_header) { if (vendev != mapped_vendev) { diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index fe77276..a929206 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -35,6 +35,6 @@ struct pci_data { struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); -u32 __attribute__((weak)) map_oprom_vendev(u32 vendev); +u32 map_oprom_vendev(u32 vendev); #endif

1 0

New patch to review for coreboot: ed621c9 RELOCATABLE_RAMSTAGE: Fix weak symbols in ACPI
by Kyösti Mälkki 27 Dec '14

27 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7955 -gerrit commit ed621c934e787192f860a9e0f35e61006f2779b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 13:29:09 2014 +0200 RELOCATABLE_RAMSTAGE: Fix weak symbols in ACPI After relocation the weak symbols are no longer NULL. Always have empty stub function defined. Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 16 ++++++++++++---- src/arch/x86/include/arch/acpi.h | 4 ++-- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 5abc178..61f0954 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -830,6 +830,10 @@ unsigned long write_acpi_tables(unsigned long start) #endif #if CONFIG_HAVE_ACPI_RESUME +void __attribute__((weak)) mainboard_suspend_resume(void) +{ +} + void acpi_resume(void *wake_vec) { #if CONFIG_HAVE_SMI_HANDLER @@ -844,8 +848,7 @@ void acpi_resume(void *wake_vec) #endif /* Call mainboard resume handler first, if defined. */ - if (mainboard_suspend_resume) - mainboard_suspend_resume(); + mainboard_suspend_resume(); post_code(POST_OS_RESUME); acpi_jump_to_wakeup(wake_vec); @@ -854,13 +857,18 @@ void acpi_resume(void *wake_vec) /* This is to be filled by SB code - startup value what was found. */ u8 acpi_slp_type = 0; +int __attribute__((weak)) acpi_get_sleep_type(void) +{ + return 0; +} + static void acpi_handoff_wakeup(void) { static int once = 0; if (once) return; - if (acpi_get_sleep_type) - acpi_slp_type = acpi_get_sleep_type(); + + acpi_slp_type = acpi_get_sleep_type(); once = 1; } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 54217b3..502c826 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -570,12 +570,12 @@ int acpi_is_wakeup_early(void); void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); void acpi_prepare_resume_backup(void); -void __attribute__((weak)) mainboard_suspend_resume(void); +void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); -int __attribute__((weak)) acpi_get_sleep_type(void); +int acpi_get_sleep_type(void); #endif /* IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) */ /* cpu/intel/speedstep/acpi.c */

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coreboot-gerrit December 2014