coreboot-gerrit December 2014

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Patch set updated for coreboot: c1be899 tegra124: Active dc/sor register change immediately
by Marc Jones 28 Dec '14

28 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7951 -gerrit commit c1be899192c43b895cbad4fa4af6b57bb4c402d8 Author: Vince Hsu <vinceh(a)nvidia.com> Date: Fri May 16 18:07:53 2014 +0800 tegra124: Active dc/sor register change immediately When doing DP attach, we need to make sure the register change to take effect immediately, otherwise it may fail to catch the attach timing. BRANCH=None BUG=chrome-os-partner:28128 TEST=Display works and system boots up on Nyan and Big Original-Change-Id: I569dc435a1aa4aac0d5ecd0655d2ad87a791246d Original-Signed-off-by: Vince Hsu <vinceh(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/200414 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 47b86e2893fa667bebada6a0e0b443886dd5ee02) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icf809b46e675bbdb8633d9a4f31d005d6644bd2a --- src/soc/nvidia/tegra124/sor.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 0e96764..2c059bf 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -762,9 +762,11 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor) tegra_dc_sor_super_update(sor); /* Enable dc */ + reg_val = READL(&disp_ctrl->cmd.state_access); + WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); - WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); + WRITEL(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST, NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,

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Patch merged into coreboot/master: 4851bf2 intel baytrail broadwell: Include microcode updates
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit 4851bf28228114016cf69720422c38e92ec091eb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 12:57:06 2014 +0200 intel baytrail broadwell: Include microcode updates Commit 66e0c4c renamed the variable. Change-Id: I9e8dc3e7f140411d04b35a21ada76aaa578832fb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7960 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7960 for details. -gerrit

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Patch merged into coreboot/master: d05a84c intel: Fix UPDATE-FIT step in build
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit d05a84c7e20768d6fcfa0b6086a53ba46d893a8c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 11:55:47 2014 +0200 intel: Fix UPDATE-FIT step in build Regression in commit 88ca81a caused UPDATE-FIT step to no longer run when microcode was added to CBFS. Change-Id: I6ea4b6b6a8de598be810c930baa497f8c7fdc4b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7959 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/7959 for details. -gerrit

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Patch merged into coreboot/master: f9b8ed8 cbfstool: Fix update-fit command
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit f9b8ed86dde6b9d5bb3f56259a7351ec6304f8ea Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 13:08:54 2014 +0200 cbfstool: Fix update-fit command Regression in commit 3fcde22 caused parse_microcode_blob() to access data outside cpu_microcode_blob.bin file in CBFS and create invalid Intel Firmware Interface Table entries. Change-Id: I1a687060084c2acd6cac5f5053b74a332b4ac714 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7958 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7958 for details. -gerrit

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Patch merged into coreboot/master: 78c6224 intel: Fix microcode alignment
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit 78c622443e17a0b6d72142a9a8ed68069f22b745 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 11:47:21 2014 +0200 intel: Fix microcode alignment CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS. Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only used with PLATFORM_FSP. CPU_MICROCODE_CBFS_LEN was no longer used at all. Change-Id: I0454397924d2526d97b1f095cc371ba962873c99 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7957 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7957 for details. -gerrit

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Patch merged into coreboot/master: 1bdd321 RELOCATABLE_RAMSTAGE: Fix weak symbols with option ROMs
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit 1bdd3217a245d3b93a41562814ee593664f0ad03 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 13:29:09 2014 +0200 RELOCATABLE_RAMSTAGE: Fix weak symbols with option ROMs After relocation the weak symbol map_oprom_vendev is no longer NULL. Always have empty stub function defined. Change-Id: I5b1bdeb3f37bb04363cf3d9dedaeafc9e193aaae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7956 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7956 for details. -gerrit

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Patch merged into coreboot/master: 134f504 RELOCATABLE_RAMSTAGE: Fix weak symbols in ACPI
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit 134f504cb79dd132d765dc8e4c074312199326cc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 13:29:09 2014 +0200 RELOCATABLE_RAMSTAGE: Fix weak symbols in ACPI After relocation the weak symbols are no longer NULL. Always have empty stub function defined. Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7955 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7955 for details. -gerrit

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Patch merged into coreboot/master: c7c0267 RELOCATABLE_RAMSTAGE: Fix weak symbols with ramstage_cache
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit c7c02673e45a1c35ee020049c3dcf6da7e7ed1f0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 13:28:35 2014 +0200 RELOCATABLE_RAMSTAGE: Fix weak symbols with ramstage_cache We had NULL reference with cache_loaded_ramstage() if CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM was not set so boot never proceeded to ramstage. Cache implementation outside CBMEM provides means for platform-specific location so there is no need of weak attributes here. Change-Id: I1eb1a713896395c424fde23252c374f9065fe74d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7954 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7954 for details. -gerrit

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Patch set updated for coreboot: 94cf4a1 macbook21: Add CST entries
by Mono Moosbart 28 Dec '14

28 Dec '14

Mono Moosbart (mono(a)posteo.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7923 -gerrit commit 94cf4a13b22eb6cba795230df58656c55fc3de7d Author: Mono <mono(a)posteo.de> Date: Thu Dec 25 08:11:54 2014 +0100 macbook21: Add CST entries Enable c1 and c2 state. Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13 Signed-off-by: Axel Holewa <mono(a)posteo.de> --- src/mainboard/apple/macbook21/mainboard.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 99527c1..19d794a 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -36,9 +36,15 @@ #include <drivers/intel/gma/int15.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 0, 0, { 0 }, 0, 0 } }, + { 2, 1, 500, { 0x7f, 1, 2, { 0 }, 0x10, 0 } }, +}; + int get_cst_entries(acpi_cstate_t **entries) { - return 0; + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); } static void mainboard_init(device_t dev)

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Patch merged into coreboot/master: d4b1139 3rdparty: Update to latest commit in blobs repository
by gerrit＠coreboot.org 28 Dec '14

28 Dec '14

the following patch was just integrated into master: commit d4b1139e289d8a786caee42e8ba198dd9a4538f4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Dec 28 12:09:23 2014 +0100 3rdparty: Update to latest commit in blobs repository Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error occurs) unintentionally reverted commit 16472743 (3dparty: Update to latest commit in blobs repository). Apply that commit again: 'blobs' now contains updates which allow binary AGESA to build with Clang. Pull those in, in anticipation of re-enabling -Werror on Clang builds. Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7963 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7963 for details. -gerrit

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coreboot-gerrit December 2014