coreboot-gerrit December 2014

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Patch set updated for coreboot: c399619 ipq/arm: Redesign hooks for bootblock
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7879 -gerrit commit c3996193e4a0db56241508f454426e4fbc1c8205 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 23 11:09:44 2014 -0700 ipq/arm: Redesign hooks for bootblock The following patches had to be squashed to properly build all the different ARM boards. ipq8064: storm: re-arrange bootblock initialization The recent addition of the storm bootblock initialization broke compilation of Exynos platforms. The SOC specific code needs to be kept in the respective source files, not in the common CPU code. As of now coreboot does not provide a separate SOC initialization API. In general it makes sense to invoke SOC initialization from the board initialization code, as the board knows what SOC it is running on. Presently all what's need initialization on 8064 is the timer. This patch adds the SOC initialization framework for 8064 and moves there the related code. BUG=chrome-os-partner:27784 TEST=manual . nyan_big, peach_pit, and storm targets build fine now. Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197835 (cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> arm: Redesign mainboard and SoC hooks for bootblock This patch makes some slight changes to the way bootblock_cpu_init() and bootblock_mainboard_init() are used on ARM. Experience has shown that nearly every board needs either one or both of these hooks, so having explicit Kconfigs for them has become unwieldy. Instead, this patch implements them as a weak symbol that can be overridden by mainboard/SoC code, as the more recent arm64_soc_init() is also doing. Since the whole concept of a single "CPU" on ARM systems has kinda died out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had already been done on Storm/ipq806x, which is now adjusted to directly use the generic hook.) Also add a proper license header to bootblock_common.h that was somehow missing. Leaving non-ARM32 architectures out for now, since they are still using the really old and weird x86 model of directly including a file. These architectures should also eventually be aligned with the cleaner ARM32 model as they mature. BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Compiled for Storm and confirmed in the disassembly that bootblock_soc_init() is still compiled in and called right before the (now no-op) bootblock_mainboard_init(). Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231940 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57 --- src/arch/arm/armv4/bootblock_simple.c | 5 ++++- src/arch/arm/armv7/bootblock_simple.c | 5 ++++- src/arch/arm/include/bootblock_common.h | 38 ++++++++++++++++++++++----------- src/cpu/allwinner/a10/bootblock.c | 2 +- src/cpu/armltd/cortex-a9/Kconfig | 6 ------ src/cpu/armltd/cortex-a9/bootblock.c | 17 --------------- src/cpu/ti/am335x/bootblock.c | 2 +- src/soc/qualcomm/ipq806x/Makefile.inc | 20 +++++++++++++++++ src/soc/qualcomm/ipq806x/bootblock.c | 24 +++++++++++++++++++++ src/soc/samsung/exynos5250/bootblock.c | 2 +- src/soc/samsung/exynos5420/bootblock.c | 2 +- 11 files changed, 81 insertions(+), 42 deletions(-) diff --git a/src/arch/arm/armv4/bootblock_simple.c b/src/arch/arm/armv4/bootblock_simple.c index 207279b..15b6bde 100644 --- a/src/arch/arm/armv4/bootblock_simple.c +++ b/src/arch/arm/armv4/bootblock_simple.c @@ -26,12 +26,15 @@ #include <console/console.h> #include <halt.h> +__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } +__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } + void main(void) { const char *stage_name = "fallback/romstage"; void *entry; - bootblock_cpu_init(); + bootblock_soc_init(); bootblock_mainboard_init(); if (CONFIG_BOOTBLOCK_CONSOLE) { diff --git a/src/arch/arm/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c index aad63b6..2fc000d 100644 --- a/src/arch/arm/armv7/bootblock_simple.c +++ b/src/arch/arm/armv7/bootblock_simple.c @@ -28,12 +28,15 @@ #include <halt.h> #include <smp/node.h> +__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } +__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } + void main(void) { const char *stage_name = "fallback/romstage"; void *entry; - bootblock_cpu_init(); + bootblock_soc_init(); bootblock_mainboard_init(); #if CONFIG_BOOTBLOCK_CONSOLE diff --git a/src/arch/arm/include/bootblock_common.h b/src/arch/arm/include/bootblock_common.h index 034a12b..413a206 100644 --- a/src/arch/arm/include/bootblock_common.h +++ b/src/arch/arm/include/bootblock_common.h @@ -1,15 +1,27 @@ -#if CONFIG_CPU_HAS_BOOTBLOCK_INIT -void bootblock_cpu_init(void); -#else -static void __attribute__((unused)) bootblock_cpu_init(void) -{ -} -#endif +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ -#if CONFIG_MAINBOARD_HAS_BOOTBLOCK_INIT +#ifndef __ARCH_BOOTBLOCK_COMMON_H +#define __ARCH_BOOTBLOCK_COMMON_H + +/* These are defined as weak no-ops that can be overridden by mainboard/SoC. */ void bootblock_mainboard_init(void); -#else -static void __attribute__((unused)) bootblock_mainboard_init(void) -{ -} -#endif +void bootblock_soc_init(void); + +#endif /* __ARCH_BOOTBLOCK_COMMON_H */ diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c index d470755..808982c 100644 --- a/src/cpu/allwinner/a10/bootblock.c +++ b/src/cpu/allwinner/a10/bootblock.c @@ -10,7 +10,7 @@ #include <arch/cache.h> #include <bootblock_common.h> -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { uint32_t sctlr; diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig index c456847..fb6cd0f 100644 --- a/src/cpu/armltd/cortex-a9/Kconfig +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -7,10 +7,4 @@ config CPU_ARMLTD_CORTEX_A9 if CPU_ARMLTD_CORTEX_A9 -config BOOTBLOCK_CPU_INIT - string - default "cpu/armltd/cortex-a9/bootblock.c" - help - CPU/SoC-specific bootblock code. - endif diff --git a/src/cpu/armltd/cortex-a9/bootblock.c b/src/cpu/armltd/cortex-a9/bootblock.c deleted file mode 100644 index 8925439..0000000 --- a/src/cpu/armltd/cortex-a9/bootblock.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -void bootblock_cpu_init(void); -void bootblock_cpu_init(void) -{ -} diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c index 04c9304..f586e17 100644 --- a/src/cpu/ti/am335x/bootblock.c +++ b/src/cpu/ti/am335x/bootblock.c @@ -22,7 +22,7 @@ #include <arch/cache.h> #include <bootblock_common.h> -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { uint32_t sctlr; diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index cffcc12..00a938f 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += bootblock.c bootblock-y += cbfs.c bootblock-y += clock.c bootblock-y += gpio.c diff --git a/src/soc/qualcomm/ipq806x/bootblock.c b/src/soc/qualcomm/ipq806x/bootblock.c new file mode 100644 index 0000000..f526c97 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/samsung/exynos5250/bootblock.c b/src/soc/samsung/exynos5250/bootblock.c index f524399..1f101d6 100644 --- a/src/soc/samsung/exynos5250/bootblock.c +++ b/src/soc/samsung/exynos5250/bootblock.c @@ -22,7 +22,7 @@ #include "clk.h" #include "wakeup.h" -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { /* kick off the multi-core timer. * We want to do this as early as we can. diff --git a/src/soc/samsung/exynos5420/bootblock.c b/src/soc/samsung/exynos5420/bootblock.c index 5d2d2b7..d5f92ee 100644 --- a/src/soc/samsung/exynos5420/bootblock.c +++ b/src/soc/samsung/exynos5420/bootblock.c @@ -29,7 +29,7 @@ #define SRAM_SIZE 1 #define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { /* kick off the multi-core timer. * We want to do this as early as we can.

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New patch to review for coreboot: c72d02a ipq8064: make timer services available
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7981 -gerrit commit c72d02a5ca259f5a2f1c2a1448d92d6ebdb45094 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Dec 29 16:52:59 2014 -0700 ipq8064: make timer services available Make sure it is initialized at different stages. BUG=chrome-os-partner:27784 TEST=manual . not much at this point, just verified that it compiles Original-Change-Id: I343e7a6648e2ca935606cd76befd204aabd93726 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196592 (cherry picked from commit aedc41924313e5c21aef97b036f5a0643d59082d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4a90ae5ba6c9a561b7d5c938d18b6ea2b855855f --- src/soc/qualcomm/ipq806x/Makefile.inc | 2 ++ src/soc/qualcomm/ipq806x/bootblock.c | 2 ++ src/soc/qualcomm/ipq806x/timer.c | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 00a938f..dfbbf3d 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -21,10 +21,12 @@ bootblock-y += bootblock.c bootblock-y += cbfs.c bootblock-y += clock.c bootblock-y += gpio.c +bootblock-y += timer.c romstage-y += cbfs.c romstage-y += clock.c romstage-y += gpio.c +romstage-y += timer.c ramstage-y += cbfs.c ramstage-y += clock.c diff --git a/src/soc/qualcomm/ipq806x/bootblock.c b/src/soc/qualcomm/ipq806x/bootblock.c index f526c97..a079d42 100644 --- a/src/soc/qualcomm/ipq806x/bootblock.c +++ b/src/soc/qualcomm/ipq806x/bootblock.c @@ -18,7 +18,9 @@ */ #include <bootblock_common.h> +#include <delay.h> void bootblock_soc_init(void) { + init_timer(); } diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 5c0dcb2..0d44e4a 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -40,7 +40,7 @@ #define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */ /** - * timer_init - initialize timer + * init_timer - initialize timer */ void init_timer(void) {

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Patch set updated for coreboot: 65f48b0 ipq8064: SOC UART driver belongs in the SOC directory
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7871 -gerrit commit 65f48b06780428f408ef039b910afa2e36da51f4 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 23 16:17:26 2014 -0700 ipq8064: SOC UART driver belongs in the SOC directory Move the driver to where it belongs. BUG=chrome-os-partner:27784 TEST=none Original-Change-Id: Iee33de0b29a6bb86ba7c37e7e89aabc0fee42e80 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196658 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 64afb0a2ac9b6cd4c202b879a484220e70ff5bbe) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iee33de0b29a6bb86ba7c37e7e89aabc0fee42e80 --- src/lib/uart_ipq806.c | 440 ---------------------------------------- src/soc/qualcomm/ipq806x/uart.c | 440 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 440 insertions(+), 440 deletions(-) diff --git a/src/lib/uart_ipq806.c b/src/lib/uart_ipq806.c deleted file mode 100644 index c65f876..0000000 --- a/src/lib/uart_ipq806.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK boot - * - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - - -#include <common.h> -#include <asm/arch-ipq806x/gsbi.h> -#include <asm/arch-ipq806x/clock.h> -#include <asm/arch-ipq806x/uart.h> -#include <serial.h> - -#define FIFO_DATA_SIZE 4 - -extern board_ipq806x_params_t *gboard_param; - -static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base); - -/* Received data is valid or not */ -static int valid_data = 0; - -/* Received data */ -static unsigned int word = 0; - -/** - * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer - * @uart_dm_base: UART controller base address - */ -static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base) -{ - /* Reset receiver */ - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - /* Enable receiver */ - writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, - MSM_BOOT_UART_DM_DMRX(uart_dm_base)); - - /* Clear stale event */ - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - /* Enable stale event */ - writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_dm_read - reads a word from the RX FIFO. - * @data: location where the read data is stored - * @count: no of valid data in the FIFO - * @wait: indicates blocking call or not blocking call - * - * Reads a word from the RX FIFO. If no data is available blocks if - * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. - */ -static unsigned int -msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) -{ - static int total_rx_data = 0; - static int rx_data_read = 0; - unsigned int base = 0; - uint32_t status_reg; - - base = gboard_param->uart_dm_base; - - if (data == NULL) - return MSM_BOOT_UART_DM_E_INVAL; - - status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); - - /* Check for DM_RXSTALE for RX transfer to finish */ - while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { - status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); - if (!wait) - return MSM_BOOT_UART_DM_E_RX_NOT_READY; - } - - /* Check for Overrun error. We'll just reset Error Status */ - if (readl(MSM_BOOT_UART_DM_SR(base)) & - MSM_BOOT_UART_DM_SR_UART_OVERRUN) { - writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, - MSM_BOOT_UART_DM_CR(base)); - total_rx_data = rx_data_read = 0; - msm_boot_uart_dm_init(base); - return MSM_BOOT_UART_DM_E_RX_NOT_READY; - } - - /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ - if (total_rx_data == 0) - total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); - - /* Data available in FIFO; read a word. */ - *data = readl(MSM_BOOT_UART_DM_RF(base, 0)); - - /* WAR for http://prism/CR/548280 */ - if (*data == 0) { - return MSM_BOOT_UART_DM_E_RX_NOT_READY; - } - - /* increment the total count of chars we've read so far */ - rx_data_read += FIFO_DATA_SIZE; - - /* actual count of valid data in word */ - *count = ((total_rx_data < rx_data_read) ? - (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : - FIFO_DATA_SIZE); - - /* If there are still data left in FIFO we'll read them before - * initializing RX Transfer again - */ - if (rx_data_read < total_rx_data) - return MSM_BOOT_UART_DM_E_SUCCESS; - - msm_boot_uart_dm_init_rx_transfer(base); - total_rx_data = rx_data_read = 0; - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n" - * @data_in: characters to be converted - * @num_of_chars: no. of characters - * @data_out: location where converted chars are stored - * - * Replace linefeed char "\n" with carriage return + linefeed - * "\r\n". Currently keeping it simple than efficient. - */ -static unsigned int -msm_boot_uart_replace_lr_with_cr(char *data_in, - int num_of_chars, - char *data_out, int *num_of_chars_out) -{ - int i = 0, j = 0; - - if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - for (i = 0, j = 0; i < num_of_chars; i++, j++) { - if (data_in[i] == '\n') - data_out[j++] = '\r'; - - data_out[j] = data_in[i]; - } - - *num_of_chars_out = j; - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_dm_write - transmit data - * @data: data to transmit - * @num_of_chars: no. of bytes to transmit - * - * Writes the data to the TX FIFO. If no space is available blocks - * till space becomes available. - */ -static unsigned int -msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) -{ - unsigned int tx_word_count = 0; - unsigned int tx_char_left = 0, tx_char = 0; - unsigned int tx_word = 0; - int i = 0; - char *tx_data = NULL; - char new_data[1024]; - unsigned int base = gboard_param->uart_dm_base; - - if ((data == NULL) || (num_of_chars <= 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */ - msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i); - - tx_data = new_data; - num_of_chars = i; - - /* Write to NO_CHARS_FOR_TX register number of characters - * to be transmitted. However, before writing TX_FIFO must - * be empty as indicated by TX_READY interrupt in IMR register - */ - /* Check if transmit FIFO is empty. - * If not we'll wait for TX_READY interrupt. */ - - if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { - while (!(readl(MSM_BOOT_UART_DM_ISR(base)) & MSM_BOOT_UART_DM_TX_READY)) - __udelay(1); - } - - /* We are here. FIFO is ready to be written. */ - /* Write number of characters to be written */ - writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); - - /* Clear TX_READY interrupt */ - writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base)); - - /* We use four-character word FIFO. So we need to divide data into - * four characters and write in UART_DM_TF register */ - tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) : - (num_of_chars / 4); - tx_char_left = num_of_chars; - - for (i = 0; i < (int)tx_word_count; i++) { - tx_char = (tx_char_left < 4) ? tx_char_left : 4; - PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word); - - /* Wait till TX FIFO has space */ - while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY)) - __udelay(1); - - /* TX FIFO has space. Write the chars */ - writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); - tx_char_left = num_of_chars - (i + 1) * 4; - tx_data = tx_data + 4; - } - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/* - * msm_boot_uart_dm_reset - resets UART controller - * @base: UART controller base address - */ -static unsigned int msm_boot_uart_dm_reset(unsigned int base) -{ - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/* - * msm_boot_uart_dm_init - initilaizes UART controller - * @uart_dm_base: UART controller base address - */ -static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) -{ - /* Configure UART mode registers MR1 and MR2 */ - /* Hardware flow control isn't supported */ - writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); - - /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ - writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base)); - - /* Configure Interrupt Mask register IMR */ - writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base)); - - /* - * Configure Tx and Rx watermarks configuration registers - * TX watermark value is set to 0 - interrupt is generated when - * FIFO level is less than or equal to 0 - */ - writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base)); - - /* RX watermark value */ - writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base)); - - /* Configure Interrupt Programming Register */ - /* Set initial Stale timeout value */ - writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, - MSM_BOOT_UART_DM_IPR(uart_dm_base)); - - /* Configure IRDA if required */ - /* Disabling IRDA mode */ - writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); - - /* Configure hunt character value in HCR register */ - /* Keep it in reset state */ - writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); - - /* - * Configure Rx FIFO base address - * Both TX/RX shares same SRAM and default is half-n-half. - * Sticking with default value now. - * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). - * We have found RAM_ADDR_WIDTH = 0x7f - */ - - /* Issue soft reset command */ - msm_boot_uart_dm_reset(uart_dm_base); - - /* Enable/Disable Rx/Tx DM interfaces */ - /* Data Mover not currently utilized. */ - writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); - - /* Enable transmitter */ - writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - /* Initialize Receive Path */ - msm_boot_uart_dm_init_rx_transfer(uart_dm_base); - - return 0; -} - -/** - * uart_dm_init - initializes UART - * - * Initializes clocks, GPIO and UART controller. - */ -static int uart_dm_init(void) -{ - unsigned int dm_base, gsbi_base; - - dm_base = gboard_param->uart_dm_base; - gsbi_base = gboard_param->uart_gsbi_base; - ipq_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS); - - /* Configure the uart clock */ - uart_clock_config(gboard_param->uart_gsbi, - gboard_param->mnd_value.m_value, - gboard_param->mnd_value.n_value, - gboard_param->mnd_value.d_value, - gboard_param->clk_dummy); - - writel(GSBI_PROTOCOL_CODE_I2C_UART << - GSBI_CTRL_REG_PROTOCOL_CODE_S, - GSBI_CTRL_REG(gsbi_base)); - writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); - /* Intialize UART_DM */ - msm_boot_uart_dm_init(dm_base); - - return 0; -} - -/** - * ipq806x_serial_putc - transmits a character - * @c: character to transmit - */ -static void ipq806x_serial_putc(char c) -{ - msm_boot_uart_dm_write(&c, 1); -} - -/** - * ipq806x_serial_puts - transmits a string of data - * @s: string to transmit - */ -static void ipq806x_serial_puts(const char *s) -{ - while (*s != '\0') - serial_putc(*s++); -} - -/** - * ipq806x_serial_tstc - checks if data available for reading - * - * Returns 1 if data available, 0 otherwise - */ -static int ipq806x_serial_tstc(void) -{ - /* Return if data is already read */ - if (valid_data) - return 1; - - /* Read data from the FIFO */ - if (msm_boot_uart_dm_read(&word, &valid_data, 0) != MSM_BOOT_UART_DM_E_SUCCESS) - return 0; - - return 1; -} - -/** - * ipq806x_serial_getc - reads a character - * - * Returns the character read from serial port. - */ -static int ipq806x_serial_getc(void) -{ - int byte; - - while (!serial_tstc()) { - /* wait for incoming data */ - } - - byte = (int)word & 0xff; - word = word >> 8; - valid_data--; - - return byte; -} - -static struct serial_device ipq_serial_device = { - .name = "ipq_serial", - .start = uart_dm_init, - .getc = ipq806x_serial_getc, - .tstc = ipq806x_serial_tstc, - .putc = ipq806x_serial_putc, - .puts = ipq806x_serial_puts, -}; - -__weak struct serial_device *default_serial_console(void) -{ - return &ipq_serial_device; -} - -/** - * ipq806x_serial_init - initializes serial controller - */ -void ipq806x_serial_initialize(void) -{ - serial_register(&ipq_serial_device); -} diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c new file mode 100644 index 0000000..c65f876 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK boot + * + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <common.h> +#include <asm/arch-ipq806x/gsbi.h> +#include <asm/arch-ipq806x/clock.h> +#include <asm/arch-ipq806x/uart.h> +#include <serial.h> + +#define FIFO_DATA_SIZE 4 + +extern board_ipq806x_params_t *gboard_param; + +static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base); + +/* Received data is valid or not */ +static int valid_data = 0; + +/* Received data */ +static unsigned int word = 0; + +/** + * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base) +{ + /* Reset receiver */ + writel(MSM_BOOT_UART_DM_CMD_RESET_RX, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + /* Enable receiver */ + writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, + MSM_BOOT_UART_DM_DMRX(uart_dm_base)); + + /* Clear stale event */ + writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + /* Enable stale event */ + writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * msm_boot_uart_dm_read - reads a word from the RX FIFO. + * @data: location where the read data is stored + * @count: no of valid data in the FIFO + * @wait: indicates blocking call or not blocking call + * + * Reads a word from the RX FIFO. If no data is available blocks if + * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. + */ +static unsigned int +msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) +{ + static int total_rx_data = 0; + static int rx_data_read = 0; + unsigned int base = 0; + uint32_t status_reg; + + base = gboard_param->uart_dm_base; + + if (data == NULL) + return MSM_BOOT_UART_DM_E_INVAL; + + status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); + + /* Check for DM_RXSTALE for RX transfer to finish */ + while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { + status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); + if (!wait) + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Check for Overrun error. We'll just reset Error Status */ + if (readl(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_UART_OVERRUN) { + writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, + MSM_BOOT_UART_DM_CR(base)); + total_rx_data = rx_data_read = 0; + msm_boot_uart_dm_init(base); + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ + if (total_rx_data == 0) + total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); + + /* Data available in FIFO; read a word. */ + *data = readl(MSM_BOOT_UART_DM_RF(base, 0)); + + /* WAR for http://prism/CR/548280 */ + if (*data == 0) { + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* increment the total count of chars we've read so far */ + rx_data_read += FIFO_DATA_SIZE; + + /* actual count of valid data in word */ + *count = ((total_rx_data < rx_data_read) ? + (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : + FIFO_DATA_SIZE); + + /* If there are still data left in FIFO we'll read them before + * initializing RX Transfer again + */ + if (rx_data_read < total_rx_data) + return MSM_BOOT_UART_DM_E_SUCCESS; + + msm_boot_uart_dm_init_rx_transfer(base); + total_rx_data = rx_data_read = 0; + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n" + * @data_in: characters to be converted + * @num_of_chars: no. of characters + * @data_out: location where converted chars are stored + * + * Replace linefeed char "\n" with carriage return + linefeed + * "\r\n". Currently keeping it simple than efficient. + */ +static unsigned int +msm_boot_uart_replace_lr_with_cr(char *data_in, + int num_of_chars, + char *data_out, int *num_of_chars_out) +{ + int i = 0, j = 0; + + if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0)) + return MSM_BOOT_UART_DM_E_INVAL; + + for (i = 0, j = 0; i < num_of_chars; i++, j++) { + if (data_in[i] == '\n') + data_out[j++] = '\r'; + + data_out[j] = data_in[i]; + } + + *num_of_chars_out = j; + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * msm_boot_uart_dm_write - transmit data + * @data: data to transmit + * @num_of_chars: no. of bytes to transmit + * + * Writes the data to the TX FIFO. If no space is available blocks + * till space becomes available. + */ +static unsigned int +msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) +{ + unsigned int tx_word_count = 0; + unsigned int tx_char_left = 0, tx_char = 0; + unsigned int tx_word = 0; + int i = 0; + char *tx_data = NULL; + char new_data[1024]; + unsigned int base = gboard_param->uart_dm_base; + + if ((data == NULL) || (num_of_chars <= 0)) + return MSM_BOOT_UART_DM_E_INVAL; + + /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */ + msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i); + + tx_data = new_data; + num_of_chars = i; + + /* Write to NO_CHARS_FOR_TX register number of characters + * to be transmitted. However, before writing TX_FIFO must + * be empty as indicated by TX_READY interrupt in IMR register + */ + /* Check if transmit FIFO is empty. + * If not we'll wait for TX_READY interrupt. */ + + if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { + while (!(readl(MSM_BOOT_UART_DM_ISR(base)) & MSM_BOOT_UART_DM_TX_READY)) + __udelay(1); + } + + /* We are here. FIFO is ready to be written. */ + /* Write number of characters to be written */ + writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); + + /* Clear TX_READY interrupt */ + writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base)); + + /* We use four-character word FIFO. So we need to divide data into + * four characters and write in UART_DM_TF register */ + tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) : + (num_of_chars / 4); + tx_char_left = num_of_chars; + + for (i = 0; i < (int)tx_word_count; i++) { + tx_char = (tx_char_left < 4) ? tx_char_left : 4; + PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word); + + /* Wait till TX FIFO has space */ + while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY)) + __udelay(1); + + /* TX FIFO has space. Write the chars */ + writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); + tx_char_left = num_of_chars - (i + 1) * 4; + tx_data = tx_data + 4; + } + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/* + * msm_boot_uart_dm_reset - resets UART controller + * @base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(unsigned int base) +{ + writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/* + * msm_boot_uart_dm_init - initilaizes UART controller + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base)); + + /* Configure Interrupt Mask register IMR */ + writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base)); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base)); + + /* RX watermark value */ + writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base)); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, + MSM_BOOT_UART_DM_IPR(uart_dm_base)); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); + + /* Enable transmitter */ + writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * uart_dm_init - initializes UART + * + * Initializes clocks, GPIO and UART controller. + */ +static int uart_dm_init(void) +{ + unsigned int dm_base, gsbi_base; + + dm_base = gboard_param->uart_dm_base; + gsbi_base = gboard_param->uart_gsbi_base; + ipq_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS); + + /* Configure the uart clock */ + uart_clock_config(gboard_param->uart_gsbi, + gboard_param->mnd_value.m_value, + gboard_param->mnd_value.n_value, + gboard_param->mnd_value.d_value, + gboard_param->clk_dummy); + + writel(GSBI_PROTOCOL_CODE_I2C_UART << + GSBI_CTRL_REG_PROTOCOL_CODE_S, + GSBI_CTRL_REG(gsbi_base)); + writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); + /* Intialize UART_DM */ + msm_boot_uart_dm_init(dm_base); + + return 0; +} + +/** + * ipq806x_serial_putc - transmits a character + * @c: character to transmit + */ +static void ipq806x_serial_putc(char c) +{ + msm_boot_uart_dm_write(&c, 1); +} + +/** + * ipq806x_serial_puts - transmits a string of data + * @s: string to transmit + */ +static void ipq806x_serial_puts(const char *s) +{ + while (*s != '\0') + serial_putc(*s++); +} + +/** + * ipq806x_serial_tstc - checks if data available for reading + * + * Returns 1 if data available, 0 otherwise + */ +static int ipq806x_serial_tstc(void) +{ + /* Return if data is already read */ + if (valid_data) + return 1; + + /* Read data from the FIFO */ + if (msm_boot_uart_dm_read(&word, &valid_data, 0) != MSM_BOOT_UART_DM_E_SUCCESS) + return 0; + + return 1; +} + +/** + * ipq806x_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +static int ipq806x_serial_getc(void) +{ + int byte; + + while (!serial_tstc()) { + /* wait for incoming data */ + } + + byte = (int)word & 0xff; + word = word >> 8; + valid_data--; + + return byte; +} + +static struct serial_device ipq_serial_device = { + .name = "ipq_serial", + .start = uart_dm_init, + .getc = ipq806x_serial_getc, + .tstc = ipq806x_serial_tstc, + .putc = ipq806x_serial_putc, + .puts = ipq806x_serial_puts, +}; + +__weak struct serial_device *default_serial_console(void) +{ + return &ipq_serial_device; +} + +/** + * ipq806x_serial_init - initializes serial controller + */ +void ipq806x_serial_initialize(void) +{ + serial_register(&ipq_serial_device); +}

1 0

Patch set updated for coreboot: 0978d5b ipq/arm: Redesign hooks for bootblock
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7879 -gerrit commit 0978d5ba014251e3f4dd8c9a50e8aedbc031f3fb Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 23 11:09:44 2014 -0700 ipq/arm: Redesign hooks for bootblock The IPQ following patches had to be squashed to properly build all the different ARM boards. ipq8064: storm: re-arrange bootblock initialization The recent addition of the storm bootblock initialization broke compilation of Exynos platforms. The SOC specific code needs to be kept in the respective source files, not in the common CPU code. As of now coreboot does not provide a separate SOC initialization API. In general it makes sense to invoke SOC initialization from the board initialization code, as the board knows what SOC it is running on. Presently all what's need initialization on 8064 is the timer. This patch adds the SOC initialization framework for 8064 and moves there the related code. BUG=chrome-os-partner:27784 TEST=manual . nyan_big, peach_pit, and storm targets build fine now. Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197835 (cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> arm: Redesign mainboard and SoC hooks for bootblock This patch makes some slight changes to the way bootblock_cpu_init() and bootblock_mainboard_init() are used on ARM. Experience has shown that nearly every board needs either one or both of these hooks, so having explicit Kconfigs for them has become unwieldy. Instead, this patch implements them as a weak symbol that can be overridden by mainboard/SoC code, as the more recent arm64_soc_init() is also doing. Since the whole concept of a single "CPU" on ARM systems has kinda died out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had already been done on Storm/ipq806x, which is now adjusted to directly use the generic hook.) Also add a proper license header to bootblock_common.h that was somehow missing. Leaving non-ARM32 architectures out for now, since they are still using the really old and weird x86 model of directly including a file. These architectures should also eventually be aligned with the cleaner ARM32 model as they mature. BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Compiled for Storm and confirmed in the disassembly that bootblock_soc_init() is still compiled in and called right before the (now no-op) bootblock_mainboard_init(). Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231940 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57 --- src/arch/arm/armv4/bootblock_simple.c | 5 ++++- src/arch/arm/armv7/bootblock_simple.c | 5 ++++- src/arch/arm/include/bootblock_common.h | 38 ++++++++++++++++++++++----------- src/cpu/allwinner/a10/bootblock.c | 2 +- src/cpu/armltd/cortex-a9/Kconfig | 6 ------ src/cpu/armltd/cortex-a9/bootblock.c | 17 --------------- src/cpu/ti/am335x/bootblock.c | 2 +- src/soc/qualcomm/ipq806x/Makefile.inc | 20 +++++++++++++++++ src/soc/qualcomm/ipq806x/bootblock.c | 24 +++++++++++++++++++++ src/soc/samsung/exynos5250/bootblock.c | 2 +- src/soc/samsung/exynos5420/bootblock.c | 2 +- 11 files changed, 81 insertions(+), 42 deletions(-) diff --git a/src/arch/arm/armv4/bootblock_simple.c b/src/arch/arm/armv4/bootblock_simple.c index 207279b..15b6bde 100644 --- a/src/arch/arm/armv4/bootblock_simple.c +++ b/src/arch/arm/armv4/bootblock_simple.c @@ -26,12 +26,15 @@ #include <console/console.h> #include <halt.h> +__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } +__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } + void main(void) { const char *stage_name = "fallback/romstage"; void *entry; - bootblock_cpu_init(); + bootblock_soc_init(); bootblock_mainboard_init(); if (CONFIG_BOOTBLOCK_CONSOLE) { diff --git a/src/arch/arm/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c index aad63b6..2fc000d 100644 --- a/src/arch/arm/armv7/bootblock_simple.c +++ b/src/arch/arm/armv7/bootblock_simple.c @@ -28,12 +28,15 @@ #include <halt.h> #include <smp/node.h> +__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } +__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } + void main(void) { const char *stage_name = "fallback/romstage"; void *entry; - bootblock_cpu_init(); + bootblock_soc_init(); bootblock_mainboard_init(); #if CONFIG_BOOTBLOCK_CONSOLE diff --git a/src/arch/arm/include/bootblock_common.h b/src/arch/arm/include/bootblock_common.h index 034a12b..413a206 100644 --- a/src/arch/arm/include/bootblock_common.h +++ b/src/arch/arm/include/bootblock_common.h @@ -1,15 +1,27 @@ -#if CONFIG_CPU_HAS_BOOTBLOCK_INIT -void bootblock_cpu_init(void); -#else -static void __attribute__((unused)) bootblock_cpu_init(void) -{ -} -#endif +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ -#if CONFIG_MAINBOARD_HAS_BOOTBLOCK_INIT +#ifndef __ARCH_BOOTBLOCK_COMMON_H +#define __ARCH_BOOTBLOCK_COMMON_H + +/* These are defined as weak no-ops that can be overridden by mainboard/SoC. */ void bootblock_mainboard_init(void); -#else -static void __attribute__((unused)) bootblock_mainboard_init(void) -{ -} -#endif +void bootblock_soc_init(void); + +#endif /* __ARCH_BOOTBLOCK_COMMON_H */ diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c index d470755..808982c 100644 --- a/src/cpu/allwinner/a10/bootblock.c +++ b/src/cpu/allwinner/a10/bootblock.c @@ -10,7 +10,7 @@ #include <arch/cache.h> #include <bootblock_common.h> -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { uint32_t sctlr; diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig index c456847..fb6cd0f 100644 --- a/src/cpu/armltd/cortex-a9/Kconfig +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -7,10 +7,4 @@ config CPU_ARMLTD_CORTEX_A9 if CPU_ARMLTD_CORTEX_A9 -config BOOTBLOCK_CPU_INIT - string - default "cpu/armltd/cortex-a9/bootblock.c" - help - CPU/SoC-specific bootblock code. - endif diff --git a/src/cpu/armltd/cortex-a9/bootblock.c b/src/cpu/armltd/cortex-a9/bootblock.c deleted file mode 100644 index 8925439..0000000 --- a/src/cpu/armltd/cortex-a9/bootblock.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -void bootblock_cpu_init(void); -void bootblock_cpu_init(void) -{ -} diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c index 04c9304..f586e17 100644 --- a/src/cpu/ti/am335x/bootblock.c +++ b/src/cpu/ti/am335x/bootblock.c @@ -22,7 +22,7 @@ #include <arch/cache.h> #include <bootblock_common.h> -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { uint32_t sctlr; diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index cffcc12..00a938f 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += bootblock.c bootblock-y += cbfs.c bootblock-y += clock.c bootblock-y += gpio.c diff --git a/src/soc/qualcomm/ipq806x/bootblock.c b/src/soc/qualcomm/ipq806x/bootblock.c new file mode 100644 index 0000000..f526c97 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/samsung/exynos5250/bootblock.c b/src/soc/samsung/exynos5250/bootblock.c index f524399..1f101d6 100644 --- a/src/soc/samsung/exynos5250/bootblock.c +++ b/src/soc/samsung/exynos5250/bootblock.c @@ -22,7 +22,7 @@ #include "clk.h" #include "wakeup.h" -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { /* kick off the multi-core timer. * We want to do this as early as we can. diff --git a/src/soc/samsung/exynos5420/bootblock.c b/src/soc/samsung/exynos5420/bootblock.c index 5d2d2b7..d5f92ee 100644 --- a/src/soc/samsung/exynos5420/bootblock.c +++ b/src/soc/samsung/exynos5420/bootblock.c @@ -29,7 +29,7 @@ #define SRAM_SIZE 1 #define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ -void bootblock_cpu_init(void) +void bootblock_soc_init(void) { /* kick off the multi-core timer. * We want to do this as early as we can.

1 0

Patch set updated for coreboot: 5477bd9 ipq8064: make UART driver work in bootblock
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7875 -gerrit commit 5477bd9195c475f1fc7bd52f41876675cf25e8d2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 23 14:26:01 2014 -0700 ipq8064: make UART driver work in bootblock This patch it the last one in the chain adapting the ipq9064 UART driver for use in coreboot. A new config option (CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of the driver. The previously introduced uart_wrapper.c is now included in the build to provide the console driver structure used by ramstage. Necessary configuration options are added to allow use of UART in the bootblock. BUG=chrome-os-partner:27784 TEST=with this change the coreboot image on AP148 prints a banner on start up: coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting... Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196663 (cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91 --- src/console/Makefile.inc | 2 ++ src/mainboard/google/storm/Kconfig | 1 + src/mainboard/google/storm/Makefile.inc | 3 +++ src/soc/qualcomm/ipq806x/Kconfig | 11 +++++++---- src/soc/qualcomm/ipq806x/Makefile.inc | 3 +++ 5 files changed, 16 insertions(+), 4 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d339500..51cafef 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -14,3 +14,5 @@ romstage-y += die.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += die.c + +ramstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart_wrapper.c diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 59c0bb6..a2bf740 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_QC_IPQ806X select BOARD_ROMSIZE_KB_4096 + select MAINBOARD_HAS_BOOTBLOCK_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index e0f5501..17f9676 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +bootblock-y += cdp.c + romstage-y += romstage.c ramstage-y += mainboard.c +ramstage-y += cdp.c diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 0fb780c..92ef3a1 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -1,9 +1,12 @@ config SOC_QC_IPQ806X + bool + default n select ARCH_BOOTBLOCK_ARMV4 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - bool - default n + select ARM_LPAE + select BOOTBLOCK_CONSOLE + select HAVE_UART_SPECIAL if SOC_QC_IPQ806X @@ -13,11 +16,11 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" - default 0x221000 + default 0x224000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" - default 0x221080 + default 0x224080 config MBN_ENCAPSULATION depends on USE_BLOBS diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index dfbbf3d..639b9d9 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -22,16 +22,19 @@ bootblock-y += cbfs.c bootblock-y += clock.c bootblock-y += gpio.c bootblock-y += timer.c +bootblock-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbfs.c romstage-y += clock.c romstage-y += gpio.c romstage-y += timer.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cbfs.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += timer.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ifeq ($(CONFIG_USE_BLOBS),y)

1 0

Patch set updated for coreboot: 1c4ba66 ipq8064: prepare uart driver for use in coreboot
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7874 -gerrit commit 1c4ba667ff86967c653e87ae30b27d55ef2008f6 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 23 14:00:59 2014 -0700 ipq8064: prepare uart driver for use in coreboot The IO accessor wrappers are used to allow integer register addresses. A structure defining UART interface configuration is declared and defined. A few long lines are wrapped. Interface functions are renamed to match the wrapper API. cdp.c is edited to fit into coreboot compilation environment, and the only function required by the UART driver if exposed, the rest are compiled out for now. BUG=chrome-os-partner:27784 TEST=after all patches are applied the serial console on AP148 becomes operational. Original-Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196662 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 5e9af53a069cd048334a3a28f0a4ce9df7c96992) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49 --- src/mainboard/google/storm/cdp.c | 43 +++----- src/soc/qualcomm/ipq806x/uart.c | 233 +++++++++++++++++++++++---------------- 2 files changed, 156 insertions(+), 120 deletions(-) diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index f26ae02..94845c7 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -1,25 +1,22 @@ /* * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.* */ -#include <common.h> -#include <linux/mtd/ipq_nand.h> -#include <asm/arch-ipq806x/gpio.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch-ipq806x/clock.h> -#include <asm/arch-ipq806x/ebi2.h> -#include <asm/arch-ipq806x/smem.h> -#include <asm/errno.h> -#include "ipq806x_board_param.h" -#include "ipq806x_cdp.h" -#include <asm/arch-ipq806x/nss/msm_ipq806x_gmac.h> -#include <asm/arch-ipq806x/timer.h> -#include <nand.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <types.h> +#include <cdp.h> +#include <gpio.h> +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) +{ + int i; + + for (i = 0; i < count; i++) { + gpio_tlmm_config(gpio->gpio, gpio->func, gpio->dir, + gpio->pull, gpio->drvstr, gpio->enable); + gpio++; + } +} +#if 0 /* Watchdog bite time set to default reset value */ #define RESET_WDT_BITE_TIME 0x31F3 @@ -354,17 +351,6 @@ int get_eth_mac_address(uchar *enetaddr, uint no_of_macs) return ret; } -void ipq_configure_gpio(gpio_func_data_t *gpio, uint count) -{ - int i; - - for (i = 0; i < count; i++) { - gpio_tlmm_config(gpio->gpio, gpio->func, gpio->dir, - gpio->pull, gpio->drvstr, gpio->enable); - gpio++; - } -} - int board_eth_init(bd_t *bis) { int status; @@ -377,3 +363,4 @@ int board_eth_init(bd_t *bis) status = ipq_gmac_init(gboard_param->gmac_cfg); return status; } +#endif diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index c65f876..f7b5d02 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -31,16 +31,56 @@ * SUCH DAMAGE. */ - -#include <common.h> -#include <asm/arch-ipq806x/gsbi.h> -#include <asm/arch-ipq806x/clock.h> -#include <asm/arch-ipq806x/uart.h> -#include <serial.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <delay.h> +#include <clock.h> +#include <gpio.h> +#include <gsbi.h> +#include <console/uart.h> +#include <ipq_uart.h> +#include <stdint.h> +#include <stdlib.h> #define FIFO_DATA_SIZE 4 -extern board_ipq806x_params_t *gboard_param; +typedef struct { + unsigned uart_dm_base; + unsigned uart_gsbi_base; + unsigned uart_gsbi; + uart_clk_mnd_t mnd_value; + gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; +} uart_params_t; + +/* + * All constants lifted from u-boot's + * board/qcom/ipq806x_cdp/ipq806x_board_param.h + */ +static const uart_params_t uart_board_param = { + .uart_dm_base = UART4_DM_BASE, + .uart_gsbi_base = UART_GSBI4_BASE, + .uart_gsbi = GSBI_4, + .mnd_value = { 12, 625, 313 }, + .dbg_uart_gpio = { + { + .gpio = 10, + .func = 1, + .dir = GPIO_OUTPUT, + .pull = GPIO_NO_PULL, + .drvstr = GPIO_12MA, + .enable = GPIO_DISABLE + }, + { + .gpio = 11, + .func = 1, + .dir = GPIO_INPUT, + .pull = GPIO_NO_PULL, + .drvstr = GPIO_12MA, + .enable = GPIO_DISABLE + }, + } +}; static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base); @@ -57,21 +97,21 @@ static unsigned int word = 0; static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base) { /* Reset receiver */ - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, + writel_i(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(uart_dm_base)); /* Enable receiver */ - writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, + writel_i(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR(uart_dm_base)); - writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, + writel_i(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX(uart_dm_base)); /* Clear stale event */ - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, + writel_i(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(uart_dm_base)); /* Enable stale event */ - writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, + writel_i(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR(uart_dm_base)); return MSM_BOOT_UART_DM_E_SUCCESS; @@ -86,6 +126,7 @@ static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base) * Reads a word from the RX FIFO. If no data is available blocks if * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. */ + #if 0 /* Not used yet */ static unsigned int msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) { @@ -94,24 +135,24 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) unsigned int base = 0; uint32_t status_reg; - base = gboard_param->uart_dm_base; + base = uart_board_param.uart_dm_base; if (data == NULL) return MSM_BOOT_UART_DM_E_INVAL; - status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); + status_reg = readl_i(MSM_BOOT_UART_DM_MISR(base)); /* Check for DM_RXSTALE for RX transfer to finish */ while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { - status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); + status_reg = readl_i(MSM_BOOT_UART_DM_MISR(base)); if (!wait) return MSM_BOOT_UART_DM_E_RX_NOT_READY; } /* Check for Overrun error. We'll just reset Error Status */ - if (readl(MSM_BOOT_UART_DM_SR(base)) & + if (readl_i(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_UART_OVERRUN) { - writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, + writel_i(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base)); total_rx_data = rx_data_read = 0; msm_boot_uart_dm_init(base); @@ -120,10 +161,10 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ if (total_rx_data == 0) - total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); + total_rx_data = readl_i(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); /* Data available in FIFO; read a word. */ - *data = readl(MSM_BOOT_UART_DM_RF(base, 0)); + *data = readl_i(MSM_BOOT_UART_DM_RF(base, 0)); /* WAR for http://prism/CR/548280 */ if (*data == 0) { @@ -149,6 +190,7 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) return MSM_BOOT_UART_DM_E_SUCCESS; } +#endif /** * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n" @@ -160,7 +202,7 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) * "\r\n". Currently keeping it simple than efficient. */ static unsigned int -msm_boot_uart_replace_lr_with_cr(char *data_in, +msm_boot_uart_replace_lr_with_cr(unsigned char *data_in, int num_of_chars, char *data_out, int *num_of_chars_out) { @@ -190,7 +232,7 @@ msm_boot_uart_replace_lr_with_cr(char *data_in, * till space becomes available. */ static unsigned int -msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) +msm_boot_uart_dm_write(unsigned char *data, unsigned int num_of_chars) { unsigned int tx_word_count = 0; unsigned int tx_char_left = 0, tx_char = 0; @@ -198,7 +240,7 @@ msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) int i = 0; char *tx_data = NULL; char new_data[1024]; - unsigned int base = gboard_param->uart_dm_base; + unsigned int base = uart_board_param.uart_dm_base; if ((data == NULL) || (num_of_chars <= 0)) return MSM_BOOT_UART_DM_E_INVAL; @@ -216,17 +258,19 @@ msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) /* Check if transmit FIFO is empty. * If not we'll wait for TX_READY interrupt. */ - if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { - while (!(readl(MSM_BOOT_UART_DM_ISR(base)) & MSM_BOOT_UART_DM_TX_READY)) - __udelay(1); + if (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { + while (!(readl_i(MSM_BOOT_UART_DM_ISR(base)) & + MSM_BOOT_UART_DM_TX_READY)) + udelay(1); } /* We are here. FIFO is ready to be written. */ /* Write number of characters to be written */ - writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); + writel_i(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); /* Clear TX_READY interrupt */ - writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base)); + writel_i(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, + MSM_BOOT_UART_DM_CR(base)); /* We use four-character word FIFO. So we need to divide data into * four characters and write in UART_DM_TF register */ @@ -239,11 +283,12 @@ msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word); /* Wait till TX FIFO has space */ - while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY)) - __udelay(1); + while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXRDY)) + udelay(1); /* TX FIFO has space. Write the chars */ - writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); + writel_i(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); tx_char_left = num_of_chars - (i + 1) * 4; tx_data = tx_data + 4; } @@ -257,11 +302,12 @@ msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) */ static unsigned int msm_boot_uart_dm_reset(unsigned int base) { - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); + writel_i(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); + writel_i(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); + writel_i(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, + MSM_BOOT_UART_DM_CR(base)); + writel_i(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); + writel_i(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); return MSM_BOOT_UART_DM_E_SUCCESS; } @@ -274,36 +320,40 @@ static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) { /* Configure UART mode registers MR1 and MR2 */ /* Hardware flow control isn't supported */ - writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); + writel_i(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ - writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base)); + writel_i(MSM_BOOT_UART_DM_8_N_1_MODE, + MSM_BOOT_UART_DM_MR2(uart_dm_base)); /* Configure Interrupt Mask register IMR */ - writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base)); + writel_i(MSM_BOOT_UART_DM_IMR_ENABLED, + MSM_BOOT_UART_DM_IMR(uart_dm_base)); /* * Configure Tx and Rx watermarks configuration registers * TX watermark value is set to 0 - interrupt is generated when * FIFO level is less than or equal to 0 */ - writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base)); + writel_i(MSM_BOOT_UART_DM_TFW_VALUE, + MSM_BOOT_UART_DM_TFWR(uart_dm_base)); /* RX watermark value */ - writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base)); + writel_i(MSM_BOOT_UART_DM_RFW_VALUE, + MSM_BOOT_UART_DM_RFWR(uart_dm_base)); /* Configure Interrupt Programming Register */ /* Set initial Stale timeout value */ - writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, + writel_i(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR(uart_dm_base)); /* Configure IRDA if required */ /* Disabling IRDA mode */ - writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); + writel_i(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); /* Configure hunt character value in HCR register */ /* Keep it in reset state */ - writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); + writel_i(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); /* * Configure Rx FIFO base address @@ -318,10 +368,10 @@ static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) /* Enable/Disable Rx/Tx DM interfaces */ /* Data Mover not currently utilized. */ - writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); + writel_i(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); /* Enable transmitter */ - writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, + writel_i(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR(uart_dm_base)); /* Initialize Receive Path */ @@ -331,110 +381,109 @@ static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) } /** - * uart_dm_init - initializes UART + * uart_init - initializes UART * * Initializes clocks, GPIO and UART controller. */ -static int uart_dm_init(void) +void uart_init(int idx) { + /* Note int idx isn't used in this driver. */ unsigned int dm_base, gsbi_base; - dm_base = gboard_param->uart_dm_base; - gsbi_base = gboard_param->uart_gsbi_base; - ipq_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS); + dm_base = uart_board_param.uart_dm_base; + gsbi_base = uart_board_param.uart_gsbi_base; + ipq_configure_gpio(uart_board_param.dbg_uart_gpio, + NO_OF_DBG_UART_GPIOS); /* Configure the uart clock */ - uart_clock_config(gboard_param->uart_gsbi, - gboard_param->mnd_value.m_value, - gboard_param->mnd_value.n_value, - gboard_param->mnd_value.d_value, - gboard_param->clk_dummy); + uart_clock_config(uart_board_param.uart_gsbi, + uart_board_param.mnd_value.m_value, + uart_board_param.mnd_value.n_value, + uart_board_param.mnd_value.d_value, + 0); - writel(GSBI_PROTOCOL_CODE_I2C_UART << + writel_i(GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S, GSBI_CTRL_REG(gsbi_base)); - writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); + writel_i(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); + /* Intialize UART_DM */ msm_boot_uart_dm_init(dm_base); +} - return 0; +#if 0 /* Not used yet */ +uint32_t uartmem_getbaseaddr(void) +{ + return uart_board_param.uart_dm_base; } +#endif /** - * ipq806x_serial_putc - transmits a character + * uart_tx_byte - transmits a character * @c: character to transmit */ -static void ipq806x_serial_putc(char c) +void uart_tx_byte(int idx, unsigned char c) { msm_boot_uart_dm_write(&c, 1); } /** - * ipq806x_serial_puts - transmits a string of data + * uart_tx_flush - transmits a string of data * @s: string to transmit */ -static void ipq806x_serial_puts(const char *s) +void uart_tx_flush(int idx) { - while (*s != '\0') - serial_putc(*s++); + unsigned int base = uart_board_param.uart_dm_base; + + while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + ; } /** - * ipq806x_serial_tstc - checks if data available for reading + * uart_can_rx_byte - checks if data available for reading * * Returns 1 if data available, 0 otherwise */ -static int ipq806x_serial_tstc(void) + #if 0 /* Not used yet */ +int uart_can_rx_byte(void) { /* Return if data is already read */ if (valid_data) return 1; /* Read data from the FIFO */ - if (msm_boot_uart_dm_read(&word, &valid_data, 0) != MSM_BOOT_UART_DM_E_SUCCESS) + if (msm_boot_uart_dm_read(&word, &valid_data, 0) != + MSM_BOOT_UART_DM_E_SUCCESS) return 0; return 1; } +#endif /** * ipq806x_serial_getc - reads a character * * Returns the character read from serial port. */ -static int ipq806x_serial_getc(void) +uint8_t uart_rx_byte(int idx) { - int byte; + uint8_t byte; - while (!serial_tstc()) { +#if 0 /* Not used yet */ + while (!uart_can_rx_byte()) { /* wait for incoming data */ } - - byte = (int)word & 0xff; +#endif + byte = (uint8_t)(word & 0xff); word = word >> 8; valid_data--; return byte; } - -static struct serial_device ipq_serial_device = { - .name = "ipq_serial", - .start = uart_dm_init, - .getc = ipq806x_serial_getc, - .tstc = ipq806x_serial_tstc, - .putc = ipq806x_serial_putc, - .puts = ipq806x_serial_puts, -}; - -__weak struct serial_device *default_serial_console(void) -{ - return &ipq_serial_device; -} - -/** - * ipq806x_serial_init - initializes serial controller - */ -void ipq806x_serial_initialize(void) +#ifndef __PRE_RAM__ +/* TODO: Implement fuction */ +void uart_fill_lb(void *data) { - serial_register(&ipq_serial_device); } +#endif

1 0

Patch set updated for coreboot: 120e3e8 ipq8064: prepare include files before adding UART driver
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7873 -gerrit commit 120e3e8d5f398f386a2d2c136f9334232a55db1b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 23 13:42:22 2014 -0700 ipq8064: prepare include files before adding UART driver These patch modifies .h files to match the coreboot API. A few more significant changes are: - UART specific fields removed from common board structure in cdp.h. These fields are set at compile time in u-boot (where this structure comes from), they will be set in a different structure in the UART driver in an upcoming patch. - an inline wrapper is added in gpio.h to provide GPIO API the UART driver expects. - the ipq_configure_gpio() is passed the descriptor placed in ro data. BUG=chrome-os-partner:27784 TEST=none Original-Change-Id: Id49507fb0c72ef993a89b538cd417b6c86ae3786 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196661 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit ea400f1b720eb671fa411c5fd1df7efd14fdacd6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I2c7be09675b225de99be3c94b22e9ee2ebb2cb9a --- src/soc/qualcomm/ipq806x/include/cdp.h | 10 +--------- src/soc/qualcomm/ipq806x/include/gpio.h | 8 ++++++++ src/soc/qualcomm/ipq806x/include/gsbi.h | 2 -- src/soc/qualcomm/ipq806x/include/ipq_uart.h | 5 ++--- 4 files changed, 11 insertions(+), 14 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/include/cdp.h b/src/soc/qualcomm/ipq806x/include/cdp.h index 22ba192..15f91cb 100644 --- a/src/soc/qualcomm/ipq806x/include/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/cdp.h @@ -106,20 +106,12 @@ typedef struct { /* Board specific parameters */ typedef struct { - unsigned int machid; - unsigned int ddr_size; - unsigned int uart_gsbi; - unsigned int uart_gsbi_base; - unsigned int uart_dm_base; - unsigned int clk_dummy; #if 0 - uart_clk_mnd_t mnd_value; unsigned int gmac_gpio_count; gpio_func_data_t *gmac_gpio; ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; flash_desc flashdesc; spinorflash_params_t flash_param; - gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; #endif } __attribute__ ((__packed__)) board_ipq806x_params_t; @@ -141,5 +133,5 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) #endif unsigned int get_board_index(unsigned machid); -void ipq_configure_gpio(gpio_func_data_t *gpio, unsigned count); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); #endif diff --git a/src/soc/qualcomm/ipq806x/include/gpio.h b/src/soc/qualcomm/ipq806x/include/gpio.h index 678da0d..efaf30e 100644 --- a/src/soc/qualcomm/ipq806x/include/gpio.h +++ b/src/soc/qualcomm/ipq806x/include/gpio.h @@ -92,4 +92,12 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, void gpio_io_config_set(gpio_t gpio, unsigned int out); void gpio_io_config_get(gpio_t gpio, unsigned int *in, unsigned int *out); + +/* Keep this to maintain backwards compatibility with the vendor API. */ +static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func, + unsigned int dir, unsigned int pull, + unsigned int drvstr, unsigned int enable) +{ + gpio_tlmm_config_set(gpio, func, pull, drvstr, enable); +} #endif // __SOC_QUALCOMM_IPQ806X_GPIO_H_ diff --git a/src/soc/qualcomm/ipq806x/include/gsbi.h b/src/soc/qualcomm/ipq806x/include/gsbi.h index d2ba2b3..c12d6fd 100644 --- a/src/soc/qualcomm/ipq806x/include/gsbi.h +++ b/src/soc/qualcomm/ipq806x/include/gsbi.h @@ -19,8 +19,6 @@ #ifndef __GSBI_H_ #define __GSBI_H_ -#include <asm/io.h> - /* GSBI Registers */ #define GSBI_CTRL_REG(base) ((base) + 0x0) diff --git a/src/soc/qualcomm/ipq806x/include/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/ipq_uart.h index 6fff046..da943b9 100644 --- a/src/soc/qualcomm/ipq806x/include/ipq_uart.h +++ b/src/soc/qualcomm/ipq806x/include/ipq_uart.h @@ -32,14 +32,13 @@ #ifndef __UART_DM_H__ #define __UART_DM_H__ -#include <asm/io.h> -#include "common.h" +#define PERIPH_BLK_BLSP 0 + #define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ ((value << (32 - end_pos))\ >> (32 - (end_pos - start_pos))) -extern void dsb(void); #define PACK_CHARS_INTO_WORDS(a, cnt, word) { \ word = 0; \ int j; \

1 0

New patch to review for coreboot: 5a6ee99 libpayload/drivers/storage/ahci.c: Fix resource leak
by Paul Menzel 29 Dec '14

29 Dec '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7980 -gerrit commit 5a6ee99a66a789eaad6c23c08be1199132669e36 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Dec 29 21:48:55 2014 +0100 libpayload/drivers/storage/ahci.c: Fix resource leak CID 1260719: Resource leak (RESOURCE_LEAK) Variable "dev" going out of scope leaks the storage it points to. So free the memory space pointed to by `dev` before returning. Change-Id: Iabf00c9dc744a24d04adff6d253d0295b130d9c4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Found-by: Coverity Scan --- payloads/libpayload/drivers/storage/ahci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 4eef843..a17383a 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -120,12 +120,16 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, memset((void *)rcvd_fis, '\0', sizeof(*rcvd_fis)); /* Set command list base and received FIS base. */ - if (ahci_cmdengine_stop(port)) + if (ahci_cmdengine_stop(port)) { + free(dev); return 1; + } port->cmdlist_base = virt_to_phys(cmdlist); port->frameinfo_base = virt_to_phys(rcvd_fis); - if (ahci_cmdengine_start(port)) + if (ahci_cmdengine_start(port)) { + free(dev); return 1; + } /* Put port into active state. */ port->cmd_stat |= HBA_PxCMD_ICC_ACTIVE;

1 0

New patch to review for coreboot: f39f5d6 gm45: fix uneven backlight (native gfx init)
by Francis Rowe 29 Dec '14

29 Dec '14

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7979 -gerrit commit f39f5d6928824e59d1980a4d67fec0fad7825929 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Dec 29 21:02:48 2014 +0000 gm45: fix uneven backlight (native gfx init) When setting brightness levels low, backlight becomes uneven. This patch fixes that. Tested on X200. Change-Id: Ie71bf696ba4431ab25076f92dd5fdc9fdc167b09 Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/gm45/acpi/igd.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl index 199765b..6f0eb8c 100644 --- a/src/northbridge/intel/gm45/acpi/igd.asl +++ b/src/northbridge/intel/gm45/acpi/igd.asl @@ -206,14 +206,14 @@ Device (GFX0) Method (_BCM, 1, NotSerialized) { - Store (ShiftLeft (Arg0, 4), ^^BCLV) + Store (ShiftLeft (Arg0, 8), ^^BCLV) Store (0x80000000, ^^CR1) - Store (0x0610, ^^BCLM) + Store (ShiftLeft (0x61, 8), ^^BCLM) } Method (_BQC, 0, NotSerialized) { Store (^^BCLV, Local0) - ShiftRight (Local0, 4, Local0) + ShiftRight (Local0, 8, Local0) Return (Local0) }

1 0

New patch to review for coreboot: 0e0d510 libpayload: don't test for unsigned >= 0
by Patrick Georgi 29 Dec '14

29 Dec '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7978 -gerrit commit 0e0d510f583856cdb14588bca99ae4daf5c60c1f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Dec 29 20:41:37 2014 +0100 libpayload: don't test for unsigned >= 0 Change-Id: Ibeaf6de9505bc6f1e7358a4cfc80228dff7ddb69 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan --- payloads/libpayload/drivers/video/corebootfb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index d661466..34a895a 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -197,7 +197,7 @@ static void corebootfb_update_cursor(void) paint = CHARS[cursor_y * coreboot_video_console.columns + cursor_x]; } - if (cursor_y >= 0 && cursor_y < coreboot_video_console.rows) + if (cursor_y < coreboot_video_console.rows) corebootfb_putchar(cursor_y, cursor_x, paint); }

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coreboot-gerrit December 2014