coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

1 participants
1346 discussions

Patch set updated for coreboot: 8dd5989 elog: Use the RTC driver interface instead of reading CMOS directly.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7891 -gerrit commit 8dd5989b4a167846fc8d76cd9e1baf99bf5e6162 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 30 21:41:23 2014 -0700 elog: Use the RTC driver interface instead of reading CMOS directly. Use the RTC driver interface to find the timestamp for events instead of reading the CMOS based RTC directly on x86 or punting on ARM. This makes timestamps available on both architectures, assuming an RTC driver is available. BUG=None TEST=Built and booted on nyan_big and link and verified that the timestamps in the event log were accurate. BRANCH=nyan Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197798 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4fad296ecfeff8987e4a18054661190239245f32 --- src/drivers/elog/elog.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 92d5af3..85198e2 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -25,6 +25,8 @@ #if CONFIG_ARCH_X86 #include <pc80/mc146818rtc.h> #endif +#include <bcd.h> +#include <rtc.h> #include <smbios.h> #include <spi-generic.h> #include <spi_flash.h> @@ -637,20 +639,15 @@ int elog_init(void) */ static void elog_fill_timestamp(struct event_header *event) { -#if CONFIG_ARCH_X86 - event->second = cmos_read(RTC_CLK_SECOND); - event->minute = cmos_read(RTC_CLK_MINUTE); - event->hour = cmos_read(RTC_CLK_HOUR); - event->day = cmos_read(RTC_CLK_DAYOFMONTH); - event->month = cmos_read(RTC_CLK_MONTH); - event->year = cmos_read(RTC_CLK_YEAR); -#else - /* - * FIXME: We need to abstract the CMOS stuff on non-x86 platforms. - * Until then, use bogus data here to force the values to 0. - */ - event->month = 0xff; -#endif + struct rtc_time time; + + rtc_get(&time); + event->second = bin2bcd(time.sec); + event->minute = bin2bcd(time.min); + event->hour = bin2bcd(time.hour); + event->day = bin2bcd(time.mday); + event->month = bin2bcd(time.mon); + event->year = bin2bcd(time.year) & 0xff; /* Basic sanity check of expected ranges */ if (event->month > 0x12 || event->day > 0x31 || event->hour > 0x23 ||

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Patch set updated for coreboot: 5803eb9 rtc: Add an RTC API, and implement it for x86.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7889 -gerrit commit 5803eb9e7f73f16d2412bb4db37c194602ed0883 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Dec 29 21:31:44 2014 -0700 rtc: Add an RTC API, and implement it for x86. This CL adds an API for RTC drivers, and implements its two functions, rtc_get and rtc_set, for x86's RTC. The function which resets the clock when the CMOS as lost state now uses the RTC driver instead of accessing the those registers directly. BUG=None TEST=Built and booted on Link with the event log code modified to use the RTC interface. Verified that the event times were accurate. BRANCH=nyan Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197795 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> This is the first half of the patch. (cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I159f9b4872a0bb932961b4168b180c087dfb1883 --- src/drivers/pc80/Kconfig | 5 ++ src/drivers/pc80/Makefile.inc | 7 +- src/drivers/pc80/mc146818rtc.c | 149 +++++++++++++++++++++++++++-------------- src/include/bcd.h | 35 ++++++++++ src/include/rtc.h | 37 ++++++++++ 5 files changed, 179 insertions(+), 54 deletions(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 5fad3a5..5b05f46 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -22,3 +22,8 @@ config LPC_TPM Enable this option to enable TPM support in coreboot. If unsure, say N. + +config DRIVERS_MC146818 + bool + default y if ARCH_X86 + default n if !ARCH_X86 diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index fe6d11f..2926c56 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -1,5 +1,5 @@ -romstage-y += mc146818rtc.c -ramstage-y += mc146818rtc.c +romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c @@ -7,7 +7,10 @@ ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c +ifeq ($(CONFIG_DRIVERS_MC146818),y) romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c +endif + romstage-$(CONFIG_LPC_TPM) += tpm.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 014a8c9..9e77bd2 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -1,28 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bcd.h> #include <stdint.h> #include <version.h> #include <console/console.h> #include <pc80/mc146818rtc.h> #include <boot/coreboot_tables.h> +#include <rtc.h> #include <string.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #include <cbfs.h> #endif +#if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> +#endif -static void cmos_update_date(u8 has_century) +static void cmos_reset_date(u8 has_century) { /* Now setup a default date equals to the build date */ - cmos_write(0, RTC_CLK_SECOND); - cmos_write(0, RTC_CLK_MINUTE); - cmos_write(1, RTC_CLK_HOUR); - cmos_write(coreboot_build_date.weekday + 1, RTC_CLK_DAYOFWEEK); - cmos_write(coreboot_build_date.day, RTC_CLK_DAYOFMONTH); - cmos_write(coreboot_build_date.month, RTC_CLK_MONTH); - cmos_write(coreboot_build_date.year, RTC_CLK_YEAR); - if (has_century) - cmos_write(coreboot_build_date.century, RTC_CLK_ALTCENTURY); + struct rtc_time time = { + .sec = 0, + .min = 0, + .hour = 1, + .mday = bcd2bin(coreboot_build_date.day), + .mon = bcd2bin(coreboot_build_date.month), + .year = 2000 + bcd2bin(coreboot_build_date.year), + .wday = bcd2bin(coreboot_build_date.weekday) + }; + rtc_set(&time, has_century); } #if CONFIG_USE_OPTION_TABLE @@ -50,15 +74,8 @@ static void cmos_set_checksum(int range_start, int range_end, int cks_loc) } #endif -#if CONFIG_ARCH_X86 #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) -#else -#if CONFIG_ARCH_ALPHA -#define RTC_CONTROL_DEFAULT (RTC_SQWE | RTC_24H) -#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) -#endif -#endif #ifndef __SMM__ void cmos_init(int invalid) @@ -69,16 +86,15 @@ void cmos_init(int invalid) unsigned char x; #endif -#ifndef __PRE_RAM__ - /* - * Avoid clearing pending interrupts and resetting the RTC control +#if CONFIG_HAVE_ACPI_RESUME + /* Avoid clearing pending interrupts and resetting the RTC control * register in the resume path because the Linux kernel relies on - * this to know if it should restart the RTC timer queue if the wake + * this to know if it should restart the RTC timerqueue if the wake * was due to the RTC alarm. */ - if (acpi_is_wakeup_s3()) + if (acpi_get_sleep_type() == 3) return; -#endif /* __PRE_RAM__ */ +#endif printk(BIOS_DEBUG, "RTC Init\n"); @@ -107,7 +123,7 @@ void cmos_init(int invalid) cmos_write(0, i); #endif if (cmos_invalid) - cmos_update_date(RTC_HAS_NO_ALTCENTURY); + cmos_reset_date(RTC_HAS_NO_ALTCENTURY); printk(BIOS_WARNING, "RTC:%s%s%s%s\n", invalid?" Clear requested":"", @@ -142,14 +158,13 @@ void cmos_init(int invalid) #if CONFIG_USE_OPTION_TABLE /* - * This routine returns the value of the requested bits. + * This routine returns the value of the requested bits * input bit = bit count from the beginning of the cmos image * length = number of bits to include in the value - * ret = a character pointer to where the value is to be returned - * returns CB_SUCCESS = successful, cb_err code if an error occurred + * vret = a character pointer to where the value is to be returned + * returns 0 = successful, -1 = an error occurred */ -static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, - void *vret) +static int get_cmos_value(unsigned long bit, unsigned long length, void *vret) { unsigned char *ret; unsigned long byte,byte_bit; @@ -174,10 +189,10 @@ static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, ret[i] = cmos_read(byte); } } - return CB_SUCCESS; + return 0; } -enum cb_err get_option(void *dest, const char *name) +int get_option(void *dest, const char *name) { struct cmos_option_table *ct; struct cmos_entries *ce; @@ -193,7 +208,7 @@ enum cb_err get_option(void *dest, const char *name) if (!ct) { printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; + return -2; } ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length); for(; ce->tag == LB_TAG_OPTION; @@ -205,18 +220,18 @@ enum cb_err get_option(void *dest, const char *name) } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - return CB_CMOS_OPTION_NOT_FOUND; + return -2; } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) - return CB_CMOS_ACCESS_ERROR; - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) - return CB_CMOS_CHECKSUM_INVALID; - return CB_SUCCESS; + if (get_cmos_value(ce->bit, ce->length, dest)) + return -3; + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, + LB_CKS_LOC)) + return -4; + return 0 ; } -static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, - void *vret) +static int set_cmos_value(unsigned long bit, unsigned long length, void *vret) { unsigned char *ret; unsigned long byte,byte_bit; @@ -239,7 +254,7 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, chksum_update_needed = 1; } else { /* more that one byte so transfer the whole bytes */ if (byte_bit || length % 8) - return CB_ERR_ARG; + return -1; for (i = 0; length; i++, length -= 8, byte++) cmos_write(ret[i], byte); @@ -252,11 +267,11 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, cmos_set_checksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); } - return CB_SUCCESS; + return 0; } -enum cb_err set_option(const char *name, void *value) +int set_option(const char *name, void *value) { struct cmos_option_table *ct; struct cmos_entries *ce; @@ -273,7 +288,7 @@ enum cb_err set_option(const char *name, void *value) if (!ct) { printk(BIOS_ERR, "cmos_layout.bin could not be found. " "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; + return -2; } ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length); for(; ce->tag == LB_TAG_OPTION; @@ -285,22 +300,21 @@ enum cb_err set_option(const char *name, void *value) } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - return CB_CMOS_OPTION_NOT_FOUND; + return -2; } length = ce->length; if (ce->config == 's') { length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ - if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) - return (CB_CMOS_ACCESS_ERROR); + if ((set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}))) + return -3; } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) - return (CB_CMOS_ACCESS_ERROR); + if ((set_cmos_value(ce->bit, length, value))) + return -3; - return CB_SUCCESS; + return 0; } #endif /* CONFIG_USE_OPTION_TABLE */ @@ -323,5 +337,36 @@ void cmos_check_update_date(u8 has_century) * if the date is valid. */ if (century > 0x99 || year > 0x99) /* Invalid date */ - cmos_update_date(has_century); + cmos_reset_date(has_century); +} + +int rtc_set(const struct rtc_time *time, u8 has_century) +{ + cmos_write(bin2bcd(time->sec), RTC_CLK_SECOND); + cmos_write(bin2bcd(time->min), RTC_CLK_MINUTE); + cmos_write(bin2bcd(time->hour), RTC_CLK_HOUR); + cmos_write(bin2bcd(time->mday), RTC_CLK_DAYOFMONTH); + cmos_write(bin2bcd(time->mon), RTC_CLK_MONTH); + cmos_write(bin2bcd(time->year % 100), RTC_CLK_YEAR); + if (has_century) + cmos_write(bin2bcd(time->year / 100), + RTC_CLK_ALTCENTURY); + cmos_write(bin2bcd(time->wday + 1), RTC_CLK_DAYOFWEEK); + return 0; +} + +int rtc_get(struct rtc_time *time, u8 has_century) +{ + time->sec = bcd2bin(cmos_read(RTC_CLK_SECOND)); + time->min = bcd2bin(cmos_read(RTC_CLK_MINUTE)); + time->hour = bcd2bin(cmos_read(RTC_CLK_HOUR)); + time->mday = bcd2bin(cmos_read(RTC_CLK_DAYOFMONTH)); + time->mon = bcd2bin(cmos_read(RTC_CLK_MONTH)); + time->year = bcd2bin(cmos_read(RTC_CLK_YEAR)); + if (has_century) + time->year += bcd2bin(cmos_read(RTC_CLK_ALTCENTURY)) * 100; + else + time->year += 2000; + time->wday = bcd2bin(cmos_read(RTC_CLK_DAYOFWEEK)) - 1; + return 0; } diff --git a/src/include/bcd.h b/src/include/bcd.h new file mode 100644 index 0000000..a085027 --- /dev/null +++ b/src/include/bcd.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef _BCD_H_ +#define _BCD_H_ + +#include <stdint.h> + +static inline uint8_t bcd2bin(uint8_t val) +{ + return ((val >> 4) & 0xf) * 10 + (val & 0xf); +} + +static inline uint8_t bin2bcd(uint8_t val) +{ + return ((val / 10) << 4) | (val % 10); +} + +#endif /* _BCD_H_ */ diff --git a/src/include/rtc.h b/src/include/rtc.h new file mode 100644 index 0000000..ed32b69 --- /dev/null +++ b/src/include/rtc.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef _RTC_H_ +#define _RTC_H_ + +struct rtc_time +{ + int sec; + int min; + int hour; + int mday; + int mon; + int year; + int wday; +}; + +int rtc_set(const struct rtc_time *time, u8 has_century); +int rtc_get(struct rtc_time *time, u8 has_century); + +#endif /* _RTC_H_ */

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New patch to review for coreboot: 9996f8b mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIO
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7986 -gerrit commit 9996f8b16659d1611d3fa1c894b110f67a588b5e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 15:54:47 2014 +1100 mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIO These boards don't have Super I/O's, rather they use Embedded Controllers instead. No need to confuse with Super I/O related stuff showing up in menuconfig. Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/x200/Kconfig | 1 + src/mainboard/lenovo/x201/Kconfig | 1 + src/mainboard/lenovo/x220/Kconfig | 1 + src/mainboard/lenovo/x230/Kconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index d91ed67..98355d4 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 15e55c7..67fc388 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select DRIVERS_ICS_954309 select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index b1ca2f5..93bfb02 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select DRIVERS_ICS_954309 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 20e9527..c1aa046 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 1a1e018..5da62db 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE

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New patch to review for coreboot: d193de3 mainboard/lenovo/t530/Kconfig: No Super I/O on this board
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7985 -gerrit commit d193de310c011aa153b964e614dd09d10bf6ba13 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 15:34:43 2014 +1100 mainboard/lenovo/t530/Kconfig: No Super I/O on this board Disable Super I/O related topics showing in menuconfig. Change-Id: I246bc935147baf6ff2dfcb306079cc2d4c7cb153 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index d3cf1c5..2dcfa90 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE

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New patch to review for coreboot: 5e30ef8 mainboard/lenovo/t530/Kconfig: Enable VMX by default
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7984 -gerrit commit 5e30ef8fc40d6fba1ebe16c26f3742f03c09597f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 15:30:29 2014 +1100 mainboard/lenovo/t530/Kconfig: Enable VMX by default Fix a trivial tab/space indent inconsistency while here. Change-Id: I819d85293e1a070817cd13349a220ba85ba89951 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 33fcd7d..d3cf1c5 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init + select ENABLE_VMX # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE @@ -49,8 +50,8 @@ config MAX_CPUS default 8 config USBDEBUG_HCD_INDEX - int - default 2 + int + default 2 config DRAM_RESET_GATE_GPIO int

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Patch set updated for coreboot: e375dc3 soc/samsung/exynos: Layout common code framework
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7929 -gerrit commit e375dc315f732f049026f7c7bd79ad5d69f34791 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 26 13:58:56 2014 +1100 soc/samsung/exynos: Layout common code framework Layout the framework to merge common components between Exynos families. Change-Id: Ic8896e791dac9757c2bd19f390d0a5821f96fc06 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/samsung/Kconfig | 1 + src/soc/samsung/Makefile.inc | 1 + src/soc/samsung/exynos/Kconfig | 11 ++++++ src/soc/samsung/exynos/Makefile.inc | 19 ++++++++++ src/soc/samsung/exynos/bootblock.c | 55 +++++++++++++++++++++++++++ src/soc/samsung/exynos/cbmem.c | 27 +++++++++++++ src/soc/samsung/exynos/mct.c | 36 ++++++++++++++++++ src/soc/samsung/exynos/monotonic_timer.c | 34 +++++++++++++++++ src/soc/samsung/exynos/wakeup.c | 57 ++++++++++++++++++++++++++++ src/soc/samsung/exynos/wakeup.h | 43 +++++++++++++++++++++ src/soc/samsung/exynos5250/Kconfig | 8 +--- src/soc/samsung/exynos5250/Makefile.inc | 14 ++----- src/soc/samsung/exynos5250/bootblock.c | 55 --------------------------- src/soc/samsung/exynos5250/cbmem.c | 27 ------------- src/soc/samsung/exynos5250/mct.c | 36 ------------------ src/soc/samsung/exynos5250/monotonic_timer.c | 34 ----------------- src/soc/samsung/exynos5250/wakeup.c | 57 ---------------------------- src/soc/samsung/exynos5250/wakeup.h | 43 --------------------- src/soc/samsung/exynos5420/Kconfig | 9 +---- src/soc/samsung/exynos5420/Makefile.inc | 14 ++----- src/soc/samsung/exynos5420/bootblock.c | 55 --------------------------- src/soc/samsung/exynos5420/cbmem.c | 27 ------------- src/soc/samsung/exynos5420/mct.c | 36 ------------------ src/soc/samsung/exynos5420/monotonic_timer.c | 34 ----------------- src/soc/samsung/exynos5420/wakeup.c | 57 ---------------------------- src/soc/samsung/exynos5420/wakeup.h | 43 --------------------- 26 files changed, 292 insertions(+), 541 deletions(-) diff --git a/src/soc/samsung/Kconfig b/src/soc/samsung/Kconfig index 9241d27..8bb0aa2 100644 --- a/src/soc/samsung/Kconfig +++ b/src/soc/samsung/Kconfig @@ -1,2 +1,3 @@ +source src/soc/samsung/exynos/Kconfig source src/soc/samsung/exynos5250/Kconfig source src/soc/samsung/exynos5420/Kconfig diff --git a/src/soc/samsung/Makefile.inc b/src/soc/samsung/Makefile.inc index 496b5f7..7a4123f 100644 --- a/src/soc/samsung/Makefile.inc +++ b/src/soc/samsung/Makefile.inc @@ -1,2 +1,3 @@ +subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS) += exynos subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5250) += exynos5250 subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5420) += exynos5420 diff --git a/src/soc/samsung/exynos/Kconfig b/src/soc/samsung/exynos/Kconfig new file mode 100644 index 0000000..63f1a45 --- /dev/null +++ b/src/soc/samsung/exynos/Kconfig @@ -0,0 +1,11 @@ +config CPU_SAMSUNG_EXYNOS + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + select CPU_HAS_BOOTBLOCK_INIT + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select RELOCATABLE_MODULES + select DYNAMIC_CBMEM + bool + default n diff --git a/src/soc/samsung/exynos/Makefile.inc b/src/soc/samsung/exynos/Makefile.inc new file mode 100644 index 0000000..490c816 --- /dev/null +++ b/src/soc/samsung/exynos/Makefile.inc @@ -0,0 +1,19 @@ +bootblock-y += bootblock.c +bootblock-y += mct.c +##bootblock-y += mct.c power.c +bootblock-y += wakeup.c + +# Clock is required for UART +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c + +romstage-y += mct.c +romstage-y += monotonic_timer.c +romstage-y += cbmem.c +#romstage-y += power.c +romstage-y += wakeup.c + +ramstage-y += mct.c +ramstage-y += monotonic_timer.c +ramstage-y += cbmem.c +#ramstage-y += power.c +#ramstage-y += usb.c diff --git a/src/soc/samsung/exynos/bootblock.c b/src/soc/samsung/exynos/bootblock.c new file mode 100644 index 0000000..5d2d2b7 --- /dev/null +++ b/src/soc/samsung/exynos/bootblock.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> +#include <arch/cache.h> + +#include "clk.h" +#include "wakeup.h" +#include "cpu.h" + +/* convenient shorthand (in MB) */ +#define SRAM_START (EXYNOS5_SRAM_BASE >> 20) +#define SRAM_SIZE 1 +#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ + +void bootblock_cpu_init(void) +{ + /* kick off the multi-core timer. + * We want to do this as early as we can. + */ + mct_start(); + + if (get_wakeup_state() == WAKEUP_DIRECT) { + wakeup(); + /* Never returns. */ + } + + /* set up dcache and MMU */ + mmu_init(); + mmu_disable_range(0, SRAM_START); + mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); + dcache_mmu_enable(); + + /* For most ARM systems, we have to initialize firmware media source + * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is + * already handled by iROM so there's no need to setup again. + */ +} diff --git a/src/soc/samsung/exynos/cbmem.c b/src/soc/samsung/exynos/cbmem.c new file mode 100644 index 0000000..4650320 --- /dev/null +++ b/src/soc/samsung/exynos/cbmem.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> +#include "cpu.h" + +void *cbmem_top(void) +{ + return (void *)(get_fb_base_kb() * KiB); +} diff --git a/src/soc/samsung/exynos/mct.c b/src/soc/samsung/exynos/mct.c new file mode 100644 index 0000000..bbb90e4 --- /dev/null +++ b/src/soc/samsung/exynos/mct.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include "clk.h" + +uint64_t mct_raw_value(void) +{ + uint64_t upper = readl(&exynos_mct->g_cnt_u); + uint64_t lower = readl(&exynos_mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void mct_start(void) +{ + writel(readl(&exynos_mct->g_tcon) | (0x1 << 8), + &exynos_mct->g_tcon); +} diff --git a/src/soc/samsung/exynos/monotonic_timer.c b/src/soc/samsung/exynos/monotonic_timer.c new file mode 100644 index 0000000..89ac416 --- /dev/null +++ b/src/soc/samsung/exynos/monotonic_timer.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <timer.h> + +#include "clk.h" + +static const uint32_t clocks_per_usec = MCT_HZ/1000000; + +void timer_monotonic_get(struct mono_time *mt) +{ + /* We don't have to call mct_start() here + * because it was already called in the bootblock + */ + + mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec); +} diff --git a/src/soc/samsung/exynos/wakeup.c b/src/soc/samsung/exynos/wakeup.c new file mode 100644 index 0000000..a240717 --- /dev/null +++ b/src/soc/samsung/exynos/wakeup.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <console/console.h> +#include "power.h" +#include "wakeup.h" + +void wakeup(void) +{ + if (wakeup_need_reset()) + power_reset(); + + power_init(); /* Ensure ps_hold_setup() for early wakeup. */ + dcache_mmu_disable(); + power_exit_wakeup(); + /* Should never return. If we do, reset. */ + power_reset(); +} + +int get_wakeup_state(void) +{ + uint32_t status = power_read_reset_status(); + + /* DIDLE/LPA can be resumed without clock reset (ex, bootblock), + * and SLEEP requires resetting clock (should be done in ROM stage). + */ + + if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) + return WAKEUP_DIRECT; + + if (status == S5P_CHECK_SLEEP) + return WAKEUP_NEED_CLOCK_RESET; + + return IS_NOT_WAKEUP; +} + +void wakeup_enable_uart(void) +{ + power_release_uart_retention(); +} diff --git a/src/soc/samsung/exynos/wakeup.h b/src/soc/samsung/exynos/wakeup.h new file mode 100644 index 0000000..91025c3 --- /dev/null +++ b/src/soc/samsung/exynos/wakeup.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS_WAKEUP_H +#define CPU_SAMSUNG_EXYNOS_WAKEUP_H + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +enum { + // A normal boot (not suspend/resume) + IS_NOT_WAKEUP, + // A wake up event that can be resumed any time + WAKEUP_DIRECT, + // A wake up event that must be resumed only after + // clock and memory controllers are re-initialized + WAKEUP_NEED_CLOCK_RESET, +}; + +int wakeup_need_reset(void); +int get_wakeup_state(void); +void wakeup(void); +void wakeup_enable_uart(void); + +#endif /* CPU_SAMSUNG_EXYNOS_WAKEUP_H */ diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 8d7c867..2193126 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -1,13 +1,7 @@ config CPU_SAMSUNG_EXYNOS5250 - select ARCH_BOOTBLOCK_ARMV7 - select ARCH_ROMSTAGE_ARMV7 - select ARCH_RAMSTAGE_ARMV7 - select CPU_HAS_BOOTBLOCK_INIT - select HAVE_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select DYNAMIC_CBMEM bool default n + select CPU_SAMSUNG_EXYNOS if CPU_SAMSUNG_EXYNOS5250 diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 735ce2e..cce65e5 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -1,14 +1,11 @@ bootblock-y += spi.c alternate_cbfs.c -bootblock-y += bootblock.c -bootblock-y += pinmux.c mct.c power.c +bootblock-y += pinmux.c power.c # Clock is required for UART bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif -bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c @@ -19,16 +16,12 @@ romstage-y += pinmux.c # required by s3c24x0_i2c and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c -romstage-y += mct.c -romstage-y += monotonic_timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c -romstage-y += wakeup.c romstage-y += gpio.c romstage-y += timer.c romstage-y += trustzone.c romstage-y += i2c.c #romstage-y += wdt.c -romstage-y += cbmem.c ramstage-y += spi.c alternate_cbfs.c ramstage-y += clock.c @@ -38,15 +31,14 @@ ramstage-y += power.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c -ramstage-y += mct.c -ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c ramstage-y += usb.c -ramstage-y += cbmem.c + +CPPFLAGS_common += -Isrc/soc/samsung/exynos/ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@ diff --git a/src/soc/samsung/exynos5250/bootblock.c b/src/soc/samsung/exynos5250/bootblock.c deleted file mode 100644 index 5d2d2b7..0000000 --- a/src/soc/samsung/exynos5250/bootblock.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <bootblock_common.h> -#include <arch/cache.h> - -#include "clk.h" -#include "wakeup.h" -#include "cpu.h" - -/* convenient shorthand (in MB) */ -#define SRAM_START (EXYNOS5_SRAM_BASE >> 20) -#define SRAM_SIZE 1 -#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ - -void bootblock_cpu_init(void) -{ - /* kick off the multi-core timer. - * We want to do this as early as we can. - */ - mct_start(); - - if (get_wakeup_state() == WAKEUP_DIRECT) { - wakeup(); - /* Never returns. */ - } - - /* set up dcache and MMU */ - mmu_init(); - mmu_disable_range(0, SRAM_START); - mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); - mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); - dcache_mmu_enable(); - - /* For most ARM systems, we have to initialize firmware media source - * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is - * already handled by iROM so there's no need to setup again. - */ -} diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c deleted file mode 100644 index 4650320..0000000 --- a/src/soc/samsung/exynos5250/cbmem.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include <cbmem.h> -#include "cpu.h" - -void *cbmem_top(void) -{ - return (void *)(get_fb_base_kb() * KiB); -} diff --git a/src/soc/samsung/exynos5250/mct.c b/src/soc/samsung/exynos5250/mct.c deleted file mode 100644 index bbb90e4..0000000 --- a/src/soc/samsung/exynos5250/mct.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include "clk.h" - -uint64_t mct_raw_value(void) -{ - uint64_t upper = readl(&exynos_mct->g_cnt_u); - uint64_t lower = readl(&exynos_mct->g_cnt_l); - - return (upper << 32) | lower; -} - -void mct_start(void) -{ - writel(readl(&exynos_mct->g_tcon) | (0x1 << 8), - &exynos_mct->g_tcon); -} diff --git a/src/soc/samsung/exynos5250/monotonic_timer.c b/src/soc/samsung/exynos5250/monotonic_timer.c deleted file mode 100644 index 89ac416..0000000 --- a/src/soc/samsung/exynos5250/monotonic_timer.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <timer.h> - -#include "clk.h" - -static const uint32_t clocks_per_usec = MCT_HZ/1000000; - -void timer_monotonic_get(struct mono_time *mt) -{ - /* We don't have to call mct_start() here - * because it was already called in the bootblock - */ - - mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec); -} diff --git a/src/soc/samsung/exynos5250/wakeup.c b/src/soc/samsung/exynos5250/wakeup.c deleted file mode 100644 index a240717..0000000 --- a/src/soc/samsung/exynos5250/wakeup.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/cache.h> -#include <console/console.h> -#include "power.h" -#include "wakeup.h" - -void wakeup(void) -{ - if (wakeup_need_reset()) - power_reset(); - - power_init(); /* Ensure ps_hold_setup() for early wakeup. */ - dcache_mmu_disable(); - power_exit_wakeup(); - /* Should never return. If we do, reset. */ - power_reset(); -} - -int get_wakeup_state(void) -{ - uint32_t status = power_read_reset_status(); - - /* DIDLE/LPA can be resumed without clock reset (ex, bootblock), - * and SLEEP requires resetting clock (should be done in ROM stage). - */ - - if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) - return WAKEUP_DIRECT; - - if (status == S5P_CHECK_SLEEP) - return WAKEUP_NEED_CLOCK_RESET; - - return IS_NOT_WAKEUP; -} - -void wakeup_enable_uart(void) -{ - power_release_uart_retention(); -} diff --git a/src/soc/samsung/exynos5250/wakeup.h b/src/soc/samsung/exynos5250/wakeup.h deleted file mode 100644 index 690c6a3..0000000 --- a/src/soc/samsung/exynos5250/wakeup.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_WAKEUP_H -#define CPU_SAMSUNG_EXYNOS5250_WAKEUP_H - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -enum { - // A normal boot (not suspend/resume) - IS_NOT_WAKEUP, - // A wake up event that can be resumed any time - WAKEUP_DIRECT, - // A wake up event that must be resumed only after - // clock and memory controllers are re-initialized - WAKEUP_NEED_CLOCK_RESET, -}; - -int wakeup_need_reset(void); -int get_wakeup_state(void); -void wakeup(void); -void wakeup_enable_uart(void); - -#endif /* CPU_SAMSUNG_EXYNOS5250_WAKEUP_H */ diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 904091e..77d9cba 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -1,14 +1,7 @@ config CPU_SAMSUNG_EXYNOS5420 - select ARCH_BOOTBLOCK_ARMV7 - select ARCH_ROMSTAGE_ARMV7 - select ARCH_RAMSTAGE_ARMV7 - select CPU_HAS_BOOTBLOCK_INIT - select HAVE_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select RELOCATABLE_MODULES - select DYNAMIC_CBMEM bool default n + select CPU_SAMSUNG_EXYNOS if CPU_SAMSUNG_EXYNOS5420 diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index ac22620..e6d894c 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -1,14 +1,11 @@ bootblock-y += spi.c alternate_cbfs.c -bootblock-y += bootblock.c -bootblock-y += pinmux.c mct.c power.c +bootblock-y += pinmux.c power.c # Clock is required for UART bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif -bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c @@ -20,15 +17,11 @@ romstage-y += pinmux.c # required by s3c24x0_i2c and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c -romstage-y += mct.c -romstage-y += monotonic_timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c -romstage-y += wakeup.c romstage-y += gpio.c romstage-y += timer.c romstage-y += i2c.c #romstage-y += wdt.c -romstage-y += cbmem.c romstage-y += trustzone.c ramstage-y += spi.c alternate_cbfs.c @@ -39,14 +32,13 @@ ramstage-y += power.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c -ramstage-y += mct.c -ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp.c dp_lowlevel.c fimd.c ramstage-y += usb.c -ramstage-y += cbmem.c + +CPPFLAGS_common += -Isrc/soc/samsung/exynos/ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@ diff --git a/src/soc/samsung/exynos5420/bootblock.c b/src/soc/samsung/exynos5420/bootblock.c deleted file mode 100644 index 5d2d2b7..0000000 --- a/src/soc/samsung/exynos5420/bootblock.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <bootblock_common.h> -#include <arch/cache.h> - -#include "clk.h" -#include "wakeup.h" -#include "cpu.h" - -/* convenient shorthand (in MB) */ -#define SRAM_START (EXYNOS5_SRAM_BASE >> 20) -#define SRAM_SIZE 1 -#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ - -void bootblock_cpu_init(void) -{ - /* kick off the multi-core timer. - * We want to do this as early as we can. - */ - mct_start(); - - if (get_wakeup_state() == WAKEUP_DIRECT) { - wakeup(); - /* Never returns. */ - } - - /* set up dcache and MMU */ - mmu_init(); - mmu_disable_range(0, SRAM_START); - mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); - mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); - dcache_mmu_enable(); - - /* For most ARM systems, we have to initialize firmware media source - * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is - * already handled by iROM so there's no need to setup again. - */ -} diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c deleted file mode 100644 index 4650320..0000000 --- a/src/soc/samsung/exynos5420/cbmem.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include <cbmem.h> -#include "cpu.h" - -void *cbmem_top(void) -{ - return (void *)(get_fb_base_kb() * KiB); -} diff --git a/src/soc/samsung/exynos5420/mct.c b/src/soc/samsung/exynos5420/mct.c deleted file mode 100644 index bbb90e4..0000000 --- a/src/soc/samsung/exynos5420/mct.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include "clk.h" - -uint64_t mct_raw_value(void) -{ - uint64_t upper = readl(&exynos_mct->g_cnt_u); - uint64_t lower = readl(&exynos_mct->g_cnt_l); - - return (upper << 32) | lower; -} - -void mct_start(void) -{ - writel(readl(&exynos_mct->g_tcon) | (0x1 << 8), - &exynos_mct->g_tcon); -} diff --git a/src/soc/samsung/exynos5420/monotonic_timer.c b/src/soc/samsung/exynos5420/monotonic_timer.c deleted file mode 100644 index 89ac416..0000000 --- a/src/soc/samsung/exynos5420/monotonic_timer.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <timer.h> - -#include "clk.h" - -static const uint32_t clocks_per_usec = MCT_HZ/1000000; - -void timer_monotonic_get(struct mono_time *mt) -{ - /* We don't have to call mct_start() here - * because it was already called in the bootblock - */ - - mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec); -} diff --git a/src/soc/samsung/exynos5420/wakeup.c b/src/soc/samsung/exynos5420/wakeup.c deleted file mode 100644 index a240717..0000000 --- a/src/soc/samsung/exynos5420/wakeup.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/cache.h> -#include <console/console.h> -#include "power.h" -#include "wakeup.h" - -void wakeup(void) -{ - if (wakeup_need_reset()) - power_reset(); - - power_init(); /* Ensure ps_hold_setup() for early wakeup. */ - dcache_mmu_disable(); - power_exit_wakeup(); - /* Should never return. If we do, reset. */ - power_reset(); -} - -int get_wakeup_state(void) -{ - uint32_t status = power_read_reset_status(); - - /* DIDLE/LPA can be resumed without clock reset (ex, bootblock), - * and SLEEP requires resetting clock (should be done in ROM stage). - */ - - if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) - return WAKEUP_DIRECT; - - if (status == S5P_CHECK_SLEEP) - return WAKEUP_NEED_CLOCK_RESET; - - return IS_NOT_WAKEUP; -} - -void wakeup_enable_uart(void) -{ - power_release_uart_retention(); -} diff --git a/src/soc/samsung/exynos5420/wakeup.h b/src/soc/samsung/exynos5420/wakeup.h deleted file mode 100644 index 27ce8e2..0000000 --- a/src/soc/samsung/exynos5420/wakeup.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_WAKEUP_H -#define CPU_SAMSUNG_EXYNOS5420_WAKEUP_H - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -enum { - // A normal boot (not suspend/resume) - IS_NOT_WAKEUP, - // A wake up event that can be resumed any time - WAKEUP_DIRECT, - // A wake up event that must be resumed only after - // clock and memory controllers are re-initialized - WAKEUP_NEED_CLOCK_RESET, -}; - -int wakeup_need_reset(void); -int get_wakeup_state(void); -void wakeup(void); -void wakeup_enable_uart(void); - -#endif /* CPU_SAMSUNG_EXYNOS5420_WAKEUP_H */

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Patch set updated for coreboot: 40aff29 soc/samsung/exynos5250: Move MMU config into chipset support
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7930 -gerrit commit 40aff29efbe65703f407cba98518e8e370c0b6cf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 26 18:14:45 2014 +1100 soc/samsung/exynos5250: Move MMU config into chipset support Take configuration out of mainboard support into chipset support as per the FIXME. Change-Id: I925a888044452950fc85b0c5cf21a5fee0b031ec Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/daisy/mainboard.c | 9 ++------- src/soc/samsung/exynos5250/alternate_cbfs.c | 7 +++++++ src/soc/samsung/exynos5250/bootblock.c | 14 ++++++++++++++ src/soc/samsung/exynos5250/cpu.h | 2 ++ src/soc/samsung/exynos5250/wakeup.c | 2 ++ 5 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index cf25967..1218346 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -44,7 +44,6 @@ /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ /* Arbitrary range of DMA memory for depthcharge's drivers */ #define DMA_START (0x77300000) @@ -327,15 +326,11 @@ static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; - /* set up dcache and MMU */ - /* FIXME: this should happen via resource allocator */ exynos5250_config_l2_cache(); - mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); + + /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); - dcache_mmu_enable(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index 10b33f0..d19098b 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -22,6 +22,7 @@ #include <cbfs.h> /* This driver serves as a CBFS media source. */ #include <stdlib.h> #include <string.h> +#include <arch/cache.h> #include <console/console.h> #include "alternate_cbfs.h" #include "power.h" @@ -53,10 +54,13 @@ static int usb_cbfs_open(struct cbfs_media *media) if (!first_run) return 0; + dcache_mmu_disable(); if (!irom_load_usb()) { + dcache_mmu_enable(); printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n"); return -1; } + dcache_mmu_enable(); /* * We need to trust the host/irom to copy the image to our @@ -98,10 +102,13 @@ static int sdmmc_cbfs_open(struct cbfs_media *media) if (!first_run) return 0; + dcache_mmu_disable(); if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) { + dcache_mmu_enable(); printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n"); return -1; } + dcache_mmu_enable(); printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be" " at %p\n", alternate_cbfs_buffer); diff --git a/src/soc/samsung/exynos5250/bootblock.c b/src/soc/samsung/exynos5250/bootblock.c index f524399..5d2d2b7 100644 --- a/src/soc/samsung/exynos5250/bootblock.c +++ b/src/soc/samsung/exynos5250/bootblock.c @@ -18,9 +18,16 @@ */ #include <bootblock_common.h> +#include <arch/cache.h> #include "clk.h" #include "wakeup.h" +#include "cpu.h" + +/* convenient shorthand (in MB) */ +#define SRAM_START (EXYNOS5_SRAM_BASE >> 20) +#define SRAM_SIZE 1 +#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ void bootblock_cpu_init(void) { @@ -34,6 +41,13 @@ void bootblock_cpu_init(void) /* Never returns. */ } + /* set up dcache and MMU */ + mmu_init(); + mmu_disable_range(0, SRAM_START); + mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); + dcache_mmu_enable(); + /* For most ARM systems, we have to initialize firmware media source * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is * already handled by iROM so there's no need to setup again. diff --git a/src/soc/samsung/exynos5250/cpu.h b/src/soc/samsung/exynos5250/cpu.h index 10f9ef4..a813dca 100644 --- a/src/soc/samsung/exynos5250/cpu.h +++ b/src/soc/samsung/exynos5250/cpu.h @@ -22,6 +22,8 @@ #include <arch/io.h> +#define EXYNOS5_SRAM_BASE 0x02020000 + /* Base address registers */ #define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */ #define EXYNOS5_PRO_ID 0x10000000 diff --git a/src/soc/samsung/exynos5250/wakeup.c b/src/soc/samsung/exynos5250/wakeup.c index b7161cf..a240717 100644 --- a/src/soc/samsung/exynos5250/wakeup.c +++ b/src/soc/samsung/exynos5250/wakeup.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cache.h> #include <console/console.h> #include "power.h" #include "wakeup.h" @@ -27,6 +28,7 @@ void wakeup(void) power_reset(); power_init(); /* Ensure ps_hold_setup() for early wakeup. */ + dcache_mmu_disable(); power_exit_wakeup(); /* Should never return. If we do, reset. */ power_reset();

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Patch set updated for coreboot: 8b4d5a1 soc/samsung/exynos5420/uart.c: Implement 'uart_tx_flush()'
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7927 -gerrit commit 8b4d5a15bc30ea4d3d2180a85c8db881f158a803 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 26 12:44:08 2014 +1100 soc/samsung/exynos5420/uart.c: Implement 'uart_tx_flush()' This brings 'uart.c' implementations closer together between Exynos generations. Change-Id: Ifbc61794207ff36a9d8a98951e917f3b6d2ef205 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/samsung/exynos5420/uart.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 4d71155..7a7b79b 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -149,6 +149,11 @@ static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) writeb(data, &uart->utxh); } +static void exynos5_uart_tx_flush(struct s5p_uart *uart) +{ + while (readl(&uart->ufstat) & 0x1ff0000); +} + uintptr_t uart_platform_base(int idx) { if (idx < 4) @@ -177,7 +182,8 @@ void uart_tx_byte(int idx, unsigned char data) void uart_tx_flush(int idx) { - /* Exynos5250 implements this too. */ + struct s5p_uart *uart = uart_platform_baseptr(idx); + exynos5_uart_tx_flush(uart); } #ifndef __PRE_RAM__

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New patch to review for coreboot: 9fea799 ipq8064: modify SPI controller driver to work in coreboot
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7983 -gerrit commit 9fea79961b33c8400029bb583313f83fd1050584 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 30 13:25:12 2014 -0700 ipq8064: modify SPI controller driver to work in coreboot A typical SPI operation consists of two phases - command and data transfers. Command transfer is always from the host to the chip (i.e. is going in the 'write' direction), data transfer could be either read or write. We don't want the receive FIFO to be operating while the command phase is in progress. A simple way to keep the receive FIFO shut down is to not to enable it until the command phase is completed. Selective control of the receive FIFO allows to consolidate the receive and transmit functions in a single spi_xfer() function, as it happens in other SPI controller drivers. The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the next byte can be written or received, respectively. While data is being received the 0xFF bytes are transmitted per each received byte, to keep the SPI bus clocking. The data structure describing the three GSBI ports is moved from the .h file into .c file. A version of the clrsetbits macro is added to work with integer addresses instead of pointers. BUG=chrome-os-partner:27784 TEST=not yet, but with the res of the changes the bootblock loads and starts the rombase section successfully. Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197779 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f --- src/soc/qualcomm/ipq806x/Kconfig | 1 + src/soc/qualcomm/ipq806x/include/iomap.h | 7 +- src/soc/qualcomm/ipq806x/include/spi.h | 90 +---- src/soc/qualcomm/ipq806x/spi.c | 644 +++++++++++-------------------- 4 files changed, 255 insertions(+), 487 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 92ef3a1..09e1c1e 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,6 +7,7 @@ config SOC_QC_IPQ806X select ARM_LPAE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL + select SPI_ATOMIC_SEQUENCING if SOC_QC_IPQ806X diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index 8a4155c..be523a6 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -36,6 +36,9 @@ #ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_ #define __SOC_QUALCOMM_IPQ806X_IOMAP_H_ +#include <arch/io.h> +#include <cdp.h> + /* Typecast to allow integers being passed as address This needs to be included because vendor code is not compliant with our macros for read/write. Hence, special macros for readl_i and writel_i are @@ -43,8 +46,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v,a) write32(v,(void *)a) -#include <arch/io.h> -#include <cdp.h> +#define clrsetbits_le32_i(addr, clear, set) \ + clrsetbits_le32(((void *)(addr)), (clear), (set)) #define MSM_CLK_CTL_BASE 0x00900000 diff --git a/src/soc/qualcomm/ipq806x/include/spi.h b/src/soc/qualcomm/ipq806x/include/spi.h index 2020043..48073fa 100644 --- a/src/soc/qualcomm/ipq806x/include/spi.h +++ b/src/soc/qualcomm/ipq806x/include/spi.h @@ -3,8 +3,10 @@ * Copyright (c) 2012 The Linux Foundation. All rights reserved. */ -#ifndef _IPQ_SPI_H_ -#define _IPQ_SPI_H_ +#ifndef _IPQ806X_SPI_H_ +#define _IPQ806X_SPI_H_ + +#include <spi_flash.h> #define QUP5_BASE 0x1a280000 #define QUP6_BASE 0x16580000 @@ -70,6 +72,14 @@ #define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004) #define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004) +#define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x0000010c) +#define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x0000010c) +#define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x0000010c) + +#define GSBI5_QUP_IN_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x00000214) +#define GSBI6_QUP_IN_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x00000214) +#define GSBI7_QUP_IN_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x00000214) + #define GSBI5_QUP_INPUT_FIFOc_REG(c) \ (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c)) #define GSBI6_QUP_INPUT_FIFOc_REG(c) \ @@ -144,10 +154,14 @@ #define QUP_CONFIG_MINI_CORE_SPI (1 << 8) #define SPI_QUP_CONF_INPUT_MSK (1 << 7) #define SPI_QUP_CONF_INPUT_ENA (0 << 7) +#define SPI_QUP_CONF_NO_INPUT (1 << 7) #define SPI_QUP_CONF_OUTPUT_MSK (1 << 6) #define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) -#define QUP_STATE_RUN_STATE 0x1 +#define SPI_QUP_CONF_NO_OUTPUT (1 << 6) +#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) #define QUP_STATE_RESET_STATE 0x0 +#define QUP_STATE_RUN_STATE 0x1 +#define QUP_STATE_PAUSE_STATE 0x3 #define SPI_BIT_WORD_MSK 0x1F #define SPI_8_BIT_WORD 0x07 #define PROTOCOL_CODE_MSK (0x07 << 4) @@ -196,6 +210,7 @@ #define OUTPUT_SERVICE_FLAG (1 << 8) #define INPUT_SERVICE_FLAG (1 << 9) #define QUP_OUTPUT_FIFO_FULL (1 << 6) +#define QUP_INPUT_FIFO_NOT_EMPTY (1 << 5) #define SPI_INPUT_BLOCK_SIZE 4 #define SPI_OUTPUT_BLOCK_SIZE 4 #define GSBI5_SPI_CLK 21 @@ -226,6 +241,7 @@ #define SPI_RESET_STATE 0 #define SPI_RUN_STATE 1 +#define SPI_PAUSE_STATE 3 #define SPI_CORE_RESET 0 #define SPI_CORE_RUNNING 1 #define GSBI_SPI_MODE_0 0 @@ -257,79 +273,13 @@ struct gsbi_spi { unsigned int qup_md_reg; }; -static const struct gsbi_spi spi_reg[] = { - /* GSBI5 registers for SPI interface */ - { - GSBI5_SPI_CONFIG_REG, - GSBI5_SPI_IO_CONTROL_REG, - GSBI5_SPI_ERROR_FLAGS_REG, - GSBI5_SPI_ERROR_FLAGS_EN_REG, - GSBI5_GSBI_CTRL_REG_REG, - GSBI5_QUP_CONFIG_REG, - GSBI5_QUP_ERROR_FLAGS_REG, - GSBI5_QUP_ERROR_FLAGS_EN_REG, - GSBI5_QUP_OPERATIONAL_REG, - GSBI5_QUP_IO_MODES_REG, - GSBI5_QUP_STATE_REG, - GSBI5_QUP_INPUT_FIFOc_REG(0), - GSBI5_QUP_OUTPUT_FIFOc_REG(0), - GSBI5_QUP_MX_INPUT_COUNT_REG, - GSBI5_QUP_MX_OUTPUT_COUNT_REG, - GSBI5_QUP_SW_RESET_REG, - GSBIn_QUP_APPS_NS_REG(5), - GSBIn_QUP_APPS_MD_REG(5) - }, - /* GSBI6 registers for SPI interface */ - { - GSBI6_SPI_CONFIG_REG, - GSBI6_SPI_IO_CONTROL_REG, - GSBI6_SPI_ERROR_FLAGS_REG, - GSBI6_SPI_ERROR_FLAGS_EN_REG, - GSBI6_GSBI_CTRL_REG_REG, - GSBI6_QUP_CONFIG_REG, - GSBI6_QUP_ERROR_FLAGS_REG, - GSBI6_QUP_ERROR_FLAGS_EN_REG, - GSBI6_QUP_OPERATIONAL_REG, - GSBI6_QUP_IO_MODES_REG, - GSBI6_QUP_STATE_REG, - GSBI6_QUP_INPUT_FIFOc_REG(0), - GSBI6_QUP_OUTPUT_FIFOc_REG(0), - GSBI6_QUP_MX_INPUT_COUNT_REG, - GSBI6_QUP_MX_OUTPUT_COUNT_REG, - GSBI6_QUP_SW_RESET_REG, - GSBIn_QUP_APPS_NS_REG(6), - GSBIn_QUP_APPS_MD_REG(6) - }, - /* GSBI7 registers for SPI interface */ - { - GSBI7_SPI_CONFIG_REG, - GSBI7_SPI_IO_CONTROL_REG, - GSBI7_SPI_ERROR_FLAGS_REG, - GSBI7_SPI_ERROR_FLAGS_EN_REG, - GSBI7_GSBI_CTRL_REG_REG, - GSBI7_QUP_CONFIG_REG, - GSBI7_QUP_ERROR_FLAGS_REG, - GSBI7_QUP_ERROR_FLAGS_EN_REG, - GSBI7_QUP_OPERATIONAL_REG, - GSBI7_QUP_IO_MODES_REG, - GSBI7_QUP_STATE_REG, - GSBI7_QUP_INPUT_FIFOc_REG(0), - GSBI7_QUP_OUTPUT_FIFOc_REG(0), - GSBI7_QUP_MX_INPUT_COUNT_REG, - GSBI7_QUP_MX_OUTPUT_COUNT_REG, - GSBI7_QUP_SW_RESET_REG, - GSBIn_QUP_APPS_NS_REG(7), - GSBIn_QUP_APPS_MD_REG(7) - } -}; - struct ipq_spi_slave { struct spi_slave slave; const struct gsbi_spi *regs; - unsigned int core_state; unsigned int mode; unsigned int initialized; unsigned long freq; + int allocated; }; static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 45ecc0e..52d11c1 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -2,14 +2,13 @@ * Copyright (c) 2012 The Linux Foundation. All rights reserved. */ -#include <common.h> +#include <arch/io.h> +#include <delay.h> +#include <stdlib.h> +#include <string.h> #include <spi.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/errno.h> -#include "ipq_spi.h" -#include <asm/arch-ipq806x/gpio.h> -#include <asm/arch-ipq806x/iomap.h> +#include <gpio.h> +#include <iomap.h> #define SUCCESS 0 @@ -28,6 +27,11 @@ #define DRV_STR_IDX 4 #define GPIO_EN_IDX 5 +/* Arbitrarily assigned error code values */ +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + #define GSBI_IDX_TO_GSBI(idx) (idx + 5) /* @@ -138,14 +142,14 @@ static unsigned int qup_apps_clk_state[NUM_PORTS] = { static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay) { unsigned int count = TIMEOUT_CNT; - unsigned int bit_val = ((readl(reg_addr) >> bit_num) & 0x01); + unsigned int bit_val = ((readl_i(reg_addr) >> bit_num) & 0x01); while (bit_val != val) { count--; if (count == 0) return -ETIMEDOUT; udelay(us_delay); - bit_val = ((readl(reg_addr) >> bit_num) & 0x01); + bit_val = ((readl_i(reg_addr) >> bit_num) & 0x01); } return SUCCESS; @@ -168,7 +172,8 @@ static int check_qup_state_valid(struct ipq_spi_slave *ds) static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state) { uint32_t val; - int ret = SUCCESS; + int ret; + uint32_t new_state; ret = check_qup_state_valid(ds); if (ret != SUCCESS) @@ -176,32 +181,28 @@ static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state) switch (state) { case SPI_RUN_STATE: - /* Set the state to RUN */ - val = ((readl(ds->regs->qup_state) & ~QUP_STATE_MASK) - | QUP_STATE_RUN_STATE); - writel(val, ds->regs->qup_state); - ret = check_qup_state_valid(ds); - if (ret != SUCCESS) - return ret; - ds->core_state = SPI_CORE_RUNNING; + new_state = QUP_STATE_RUN_STATE; break; + case SPI_RESET_STATE: - /* Set the state to RESET */ - val = ((readl(ds->regs->qup_state) & ~QUP_STATE_MASK) - | QUP_STATE_RESET_STATE); - writel(val, ds->regs->qup_state); - ret = check_qup_state_valid(ds); - if (ret != SUCCESS) - return ret; - ds->core_state = SPI_CORE_RESET; + new_state = QUP_STATE_RESET_STATE; break; - default: - printf("err: unsupported GSBI SPI state : %d\n", state); - ret = -EINVAL; + + case SPI_PAUSE_STATE: + new_state = QUP_STATE_PAUSE_STATE; break; + + default: + printk(BIOS_ERR, + "err: unsupported GSBI SPI state : %d\n", state); + return -EINVAL; } - return ret; + /* Set the state as requested */ + val = (readl_i(ds->regs->qup_state) & ~QUP_STATE_MASK) + | new_state; + writel_i(val, ds->regs->qup_state); + return check_qup_state_valid(ds); } /* @@ -231,21 +232,22 @@ static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode) input_first_mode = 0; break; default: - printf("err : unsupported spi mode : %d\n", mode); + printk(BIOS_ERR, + "err : unsupported spi mode : %d\n", mode); return; } - val = readl(ds->regs->spi_config); + val = readl_i(ds->regs->spi_config); val |= input_first_mode; - writel(val, ds->regs->spi_config); + writel_i(val, ds->regs->spi_config); - val = readl(ds->regs->io_control); + val = readl_i(ds->regs->io_control); if (clk_idle_state) val |= SPI_IO_CONTROL_CLOCK_IDLE_HIGH; else val &= ~SPI_IO_CONTROL_CLOCK_IDLE_HIGH; - writel(val, ds->regs->io_control); + writel_i(val, ds->regs->io_control); } /* @@ -253,9 +255,6 @@ static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode) */ static int check_hclk_state(unsigned int core_num, int enable) { - if (clk_is_dummy()) - return 0; - return check_bit_state(CLK_HALT_CFPB_STATEB_REG, hclk_state[core_num], enable, 5); } @@ -265,9 +264,6 @@ static int check_hclk_state(unsigned int core_num, int enable) */ static int check_qup_clk_state(unsigned int core_num, int enable) { - if (clk_is_dummy()) - return 0; - return check_bit_state(CLK_HALT_CFPB_STATEB_REG, qup_apps_clk_state[core_num], enable, 5); } @@ -279,12 +275,12 @@ static void CS_change(int port_num, int cs_num, int enable) { unsigned int cs_gpio = cs_gpio_array[port_num][cs_num]; uint32_t addr = GPIO_IN_OUT_ADDR(cs_gpio); - uint32_t val = readl(addr); + uint32_t val = readl_i(addr); val &= (~(1 << GPIO_OUT)); if (!enable) val |= (1 << GPIO_OUT); - writel(val, addr); + writel_i(val, addr); } /* @@ -295,7 +291,7 @@ static void gsbi_pin_config(unsigned int port_num, int cs_num) unsigned int gpio; unsigned int i; /* Hold the GSBIn (core_num) core in reset */ - clrsetbits_le32(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)), + clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)), GSBI1_RESET_MSK, GSBI1_RESET); /* @@ -336,76 +332,79 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) int ret; /* Hold the GSBIn (core_num) core in reset */ - clrsetbits_le32(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI1_RESET_MSK, GSBI1_RESET); /* Disable GSBIn (core_num) QUP core clock branch */ - clrsetbits_le32(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, QUP_CLK_BRANCH_DIS); ret = check_qup_clk_state(ds->slave.bus, 1); if (ret) { - printf("QUP Clock Halt For GSBI%d failed!\n", ds->slave.bus); + printk(BIOS_ERR, + "QUP Clock Halt For GSBI%d failed!\n", ds->slave.bus); return ret; } /* Disable M/N:D counter and hold M/N:D counter in reset */ - clrsetbits_le32(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK), + clrsetbits_le32_i(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK), (MNCNTR_RST_ENA | MNCNTR_DIS)); /* Disable GSBIn (core_num) QUP core clock root */ - clrsetbits_le32(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS); + clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS); - clrsetbits_le32(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK, + clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK, GSBIn_PLL_SRC_PLL8); - clrsetbits_le32(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK, + clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK, (0 << GSBI_PRE_DIV_SEL_SHFT)); /* Program M/N:D values for GSBIn_QUP_APPS_CLK @50MHz */ - clrsetbits_le32(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK, + clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK, (0x01 << GSBI_M_VAL_SHFT)); - clrsetbits_le32(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK, + clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK, (0xF7 << GSBI_D_VAL_SHFT)); - clrsetbits_le32(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK, + clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK, (0xF8 << GSBI_N_VAL_SHFT)); /* Set MNCNTR_MODE = 0: Bypass mode */ - clrsetbits_le32(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK, + clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK, MNCNTR_MODE_DUAL_EDGE); /* De-assert the M/N:D counter reset */ - clrsetbits_le32(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS); - clrsetbits_le32(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN); + clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS); + clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN); /* * Enable the GSBIn (core_num) QUP core clock root. * Keep MND counter disabled */ - clrsetbits_le32(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA); + clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA); /* Enable GSBIn (core_num) QUP core clock branch */ - clrsetbits_le32(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, QUP_CLK_BRANCH_ENA); ret = check_qup_clk_state(ds->slave.bus, 0); if (ret) { - printf("QUP Clock Enable For GSBI%d" + printk(BIOS_ERR, + "QUP Clock Enable For GSBI%d" " failed!\n", ds->slave.bus); return ret; } /* Enable GSBIn (core_num) core clock branch */ - clrsetbits_le32(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits_le32_i(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI_CLK_BRANCH_ENA_MSK, GSBI_CLK_BRANCH_ENA); ret = check_hclk_state(ds->slave.bus, 0); if (ret) { - printf("HCLK Enable For GSBI%d failed!\n", ds->slave.bus); + printk(BIOS_ERR, + "HCLK Enable For GSBI%d failed!\n", ds->slave.bus); return ret; } /* Release GSBIn (core_num) core from reset */ - clrsetbits_le32(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI1_RESET_MSK, 0); udelay(50); @@ -417,26 +416,87 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) */ static void spi_reset(struct ipq_spi_slave *ds) { - writel(0x1, ds->regs->qup_sw_reset); + writel_i(0x1, ds->regs->qup_sw_reset); udelay(5); } +static const struct gsbi_spi spi_reg[] = { + /* GSBI5 registers for SPI interface */ + { + GSBI5_SPI_CONFIG_REG, + GSBI5_SPI_IO_CONTROL_REG, + GSBI5_SPI_ERROR_FLAGS_REG, + GSBI5_SPI_ERROR_FLAGS_EN_REG, + GSBI5_GSBI_CTRL_REG_REG, + GSBI5_QUP_CONFIG_REG, + GSBI5_QUP_ERROR_FLAGS_REG, + GSBI5_QUP_ERROR_FLAGS_EN_REG, + GSBI5_QUP_OPERATIONAL_REG, + GSBI5_QUP_IO_MODES_REG, + GSBI5_QUP_STATE_REG, + GSBI5_QUP_INPUT_FIFOc_REG(0), + GSBI5_QUP_OUTPUT_FIFOc_REG(0), + GSBI5_QUP_MX_INPUT_COUNT_REG, + GSBI5_QUP_MX_OUTPUT_COUNT_REG, + GSBI5_QUP_SW_RESET_REG, + GSBIn_QUP_APPS_NS_REG(5), + GSBIn_QUP_APPS_MD_REG(5), + }, + /* GSBI6 registers for SPI interface */ + { + GSBI6_SPI_CONFIG_REG, + GSBI6_SPI_IO_CONTROL_REG, + GSBI6_SPI_ERROR_FLAGS_REG, + GSBI6_SPI_ERROR_FLAGS_EN_REG, + GSBI6_GSBI_CTRL_REG_REG, + GSBI6_QUP_CONFIG_REG, + GSBI6_QUP_ERROR_FLAGS_REG, + GSBI6_QUP_ERROR_FLAGS_EN_REG, + GSBI6_QUP_OPERATIONAL_REG, + GSBI6_QUP_IO_MODES_REG, + GSBI6_QUP_STATE_REG, + GSBI6_QUP_INPUT_FIFOc_REG(0), + GSBI6_QUP_OUTPUT_FIFOc_REG(0), + GSBI6_QUP_MX_INPUT_COUNT_REG, + GSBI6_QUP_MX_OUTPUT_COUNT_REG, + GSBI6_QUP_SW_RESET_REG, + GSBIn_QUP_APPS_NS_REG(6), + GSBIn_QUP_APPS_MD_REG(6), + }, + /* GSBI7 registers for SPI interface */ + { + GSBI7_SPI_CONFIG_REG, + GSBI7_SPI_IO_CONTROL_REG, + GSBI7_SPI_ERROR_FLAGS_REG, + GSBI7_SPI_ERROR_FLAGS_EN_REG, + GSBI7_GSBI_CTRL_REG_REG, + GSBI7_QUP_CONFIG_REG, + GSBI7_QUP_ERROR_FLAGS_REG, + GSBI7_QUP_ERROR_FLAGS_EN_REG, + GSBI7_QUP_OPERATIONAL_REG, + GSBI7_QUP_IO_MODES_REG, + GSBI7_QUP_STATE_REG, + GSBI7_QUP_INPUT_FIFOc_REG(0), + GSBI7_QUP_OUTPUT_FIFOc_REG(0), + GSBI7_QUP_MX_INPUT_COUNT_REG, + GSBI7_QUP_MX_OUTPUT_COUNT_REG, + GSBI7_QUP_SW_RESET_REG, + GSBIn_QUP_APPS_NS_REG(7), + GSBIn_QUP_APPS_MD_REG(7), + } +}; +static struct ipq_spi_slave spi_slave_pool[2]; + void spi_init() { - /* do nothing */ - + /* just in case */ + memset(spi_slave_pool, 0, sizeof(spi_slave_pool)); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { - struct ipq_spi_slave *ds; - - ds = malloc(sizeof(struct ipq_spi_slave)); - if (!ds) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } + struct ipq_spi_slave *ds = NULL; + int i; /* * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash @@ -447,44 +507,34 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, || ((bus == GSBI5_SPI) && (cs > 3)) || ((bus == GSBI6_SPI) && (cs > 0)) || ((bus == GSBI7_SPI) && (cs > 0))) { - printf("SPI error: unsupported bus %d " + printk(BIOS_ERR, "SPI error: unsupported bus %d " "(Supported busses 0,1 and 2) or chipselect\n", bus); - goto err; - } - ds->slave.bus = bus; - ds->slave.cs = cs; - - ds->regs = &spi_reg[bus]; - - /* TODO For different clock frequency */ - if (max_hz > MSM_GSBI_MAX_FREQ) { - printf("SPI error: unsupported frequency %d Hz " - "Max frequency is %d Hz\n", max_hz, MSM_GSBI_MAX_FREQ); - goto err; } - ds->freq = max_hz; - if (mode > GSBI_SPI_MODE_3) { - printf("SPI error: unsupported SPI mode %d\n", mode); - goto err; + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + if (spi_slave_pool[i].allocated) + continue; + ds = spi_slave_pool + i; + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = &spi_reg[bus]; + + /* + * TODO(vbendeb): + * hardcoded frequency and mode - we might need to find a way + * to configure this + */ + ds->freq = 10000000; + ds->mode = GSBI_SPI_MODE_0; + ds->allocated = 1; + + return &ds->slave; } - ds->mode = mode; - return &ds->slave; - -err: - free(ds); + printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); return NULL; } -void spi_free_slave(struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - if (ds != NULL) - free(ds); -} - /* * GSBIn SPI Hardware Initialisation */ @@ -492,7 +542,8 @@ static int spi_hw_init(struct ipq_spi_slave *ds) { int ret; - ds->initialized = 0; + if (ds->initialized) + return 0; /* GSBI module configuration */ spi_reset(ds); @@ -503,27 +554,27 @@ static int spi_hw_init(struct ipq_spi_slave *ds) return ret; /* Configure GSBI_CTRL register to set protocol_mode to SPI:011 */ - clrsetbits_le32(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK, + clrsetbits_le32_i(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK, PROTOCOL_CODE_SPI); /* * Configure Mini core to SPI core with Input Output enabled, * SPI master, N = 8 bits */ - clrsetbits_le32(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK | + clrsetbits_le32_i(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK | SPI_QUP_CONF_INPUT_MSK | SPI_QUP_CONF_OUTPUT_MSK | SPI_BIT_WORD_MSK), (QUP_CONFIG_MINI_CORE_SPI | - SPI_QUP_CONF_INPUT_ENA | - SPI_QUP_CONF_OUTPUT_ENA | + SPI_QUP_CONF_NO_INPUT | + SPI_QUP_CONF_NO_OUTPUT | SPI_8_BIT_WORD)); /* * Configure Input first SPI protocol, * SPI master mode and no loopback */ - clrsetbits_le32(ds->regs->spi_config, (LOOP_BACK_MSK | + clrsetbits_le32_i(ds->regs->spi_config, (LOOP_BACK_MSK | SLAVE_OPERATION_MSK), (NO_LOOP_BACK | SLAVE_OPERATION)); @@ -534,7 +585,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * MX_CS_MODE = 0 * NO_TRI_STATE = 1 */ - writel((CLK_ALWAYS_ON | MX_CS_MODE | NO_TRI_STATE), + writel_i((CLK_ALWAYS_ON | MX_CS_MODE | NO_TRI_STATE), ds->regs->io_control); /* @@ -543,7 +594,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * INPUT_MODE = Block Mode * OUTPUT MODE = Block Mode */ - clrsetbits_le32(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK | + clrsetbits_le32_i(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK | INPUT_BLOCK_MODE_MSK | OUTPUT_BLOCK_MODE_MSK), (OUTPUT_BIT_SHIFT_EN | @@ -553,8 +604,8 @@ static int spi_hw_init(struct ipq_spi_slave *ds) spi_set_mode(ds, ds->mode); /* Disable Error mask */ - writel(0, ds->regs->error_flags_en); - writel(0, ds->regs->qup_error_flags_en); + writel_i(0, ds->regs->error_flags_en); + writel_i(0, ds->regs->qup_error_flags_en); ds->initialized = 1; @@ -566,6 +617,9 @@ int spi_claim_bus(struct spi_slave *slave) struct ipq_spi_slave *ds = to_ipq_spi(slave); unsigned int ret; + if (ds->initialized) + return SUCCESS; + /* GPIO Configuration for SPI port */ gsbi_pin_config(ds->slave.bus, ds->slave.cs); @@ -590,276 +644,87 @@ void spi_release_bus(struct spi_slave *slave) ds->initialized = 0; } -/* Drain input fifo - * If input fifo is not empty drain the input FIFO. When the - * input fifo is drained make sure that the output fifo is also - * empty and break when the input fifo is completely drained. - */ -static void flush_fifos(struct ipq_spi_slave *ds) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned out_bytes, void *din, unsigned in_bytes) { - unsigned int fifo_data; - - while (1) { - if (readl(ds->regs->qup_operational) & - QUP_DATA_AVAILABLE_FOR_READ) { - fifo_data = readl(ds->regs->qup_input_fifo); - } else { - if (!(readl(ds->regs->qup_operational) & - QUP_OUTPUT_FIFO_NOT_EMPTY)) { - if (!(readl(ds->regs->qup_operational) & - QUP_DATA_AVAILABLE_FOR_READ)) - break; - } - } - } + int ret; + uint8_t* dbuf; + const uint8_t* dobuf; + struct ipq_spi_slave *ds = to_ipq_spi(slave); - (void)fifo_data; -} + /* Assert the chip select */ + CS_change(ds->slave.bus, ds->slave.cs, CS_ASSERT); -/* - * Function to write data to OUTPUT FIFO - */ -static void spi_write_byte(struct ipq_spi_slave *ds, unsigned char data) -{ - /* Wait for space in the FIFO */ - while ((readl(ds->regs->qup_operational) & QUP_OUTPUT_FIFO_FULL)) - udelay(1); + ret = config_spi_state(ds, SPI_RESET_STATE); + if (ret) + goto out; - /* Write the byte of data */ - writel(data, ds->regs->qup_output_fifo); -} + if (!out_bytes) + goto spi_receive; -/* - * Function to read data from Input FIFO - */ -static unsigned char spi_read_byte(struct ipq_spi_slave *ds) -{ - /* Wait for Data in FIFO */ - while (!(readl(ds->regs->qup_operational) & - QUP_DATA_AVAILABLE_FOR_READ)) { - udelay(1); - } + /* + * Let's do the write side of the transaction first. Enable output + * FIFO. + */ + clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK, + SPI_QUP_CONF_OUTPUT_ENA); - /* Read a byte of data */ - return readl(ds->regs->qup_input_fifo) & 0xff; -} + writel_i(out_bytes, ds->regs->qup_mx_output_count); -/* - * Function to check wheather Input or Output FIFO - * has data to be serviced - */ -static int check_fifo_status(uint32_t reg_addr) -{ - unsigned int count = TIMEOUT_CNT; - unsigned int status_flag; - unsigned int val; + ret = config_spi_state(ds, SPI_RUN_STATE); + if (ret) + goto out; - do { - val = readl(reg_addr); - count--; - if (count == 0) - return -ETIMEDOUT; - status_flag = ((val & OUTPUT_SERVICE_FLAG) | (val & INPUT_SERVICE_FLAG)); - } while (!status_flag); + dobuf = dout; /* Alias to make it possible to use pointer autoinc. */ - return SUCCESS; -} + while (out_bytes) { + if (readl_i(ds->regs->qup_operational) & QUP_OUTPUT_FIFO_FULL) + continue; -/* - * Function to read bytes number of data from the Input FIFO - */ -static int gsbi_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer, - unsigned int bytes, unsigned long flags) -{ - uint32_t val; - unsigned int i; - unsigned int read_bytes = bytes; - unsigned int fifo_count; - int ret = SUCCESS; - int state_config; - - if (flags & SPI_XFER_BEGIN) { - /* Assert chip select */ - CS_change(ds->slave.bus, ds->slave.cs, CS_ASSERT); - } - - /* Configure no of bytes to read */ - state_config = config_spi_state(ds, SPI_RESET_STATE); - if (state_config) - return state_config; - - writel(bytes, ds->regs->qup_mx_output_count); - writel(bytes, ds->regs->qup_mx_input_count); - - state_config = config_spi_state(ds, SPI_RUN_STATE); - if (state_config) - return state_config; - - while (read_bytes) { - - ret = check_fifo_status(ds->regs->qup_operational); - if (ret != SUCCESS) - goto out; - - val = readl(ds->regs->qup_operational); - if (val & INPUT_SERVICE_FLAG) { - /* - * acknowledge to hw that software will - * read input data - */ - val &= INPUT_SERVICE_FLAG; - writel(val, ds->regs->qup_operational); - - fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ? - SPI_INPUT_BLOCK_SIZE : read_bytes); - - for (i = 0; i < fifo_count; i++) { - *data_buffer = spi_read_byte(ds); - data_buffer++; - read_bytes--; - } - } + writel_i(*dobuf++, ds->regs->qup_output_fifo); + out_bytes--; - if (val & OUTPUT_SERVICE_FLAG) { - /* - * acknowledge to hw that software will - * write output data - */ - val &= OUTPUT_SERVICE_FLAG; - writel(val, ds->regs->qup_operational); - - fifo_count = ((read_bytes > SPI_OUTPUT_BLOCK_SIZE) ? - SPI_OUTPUT_BLOCK_SIZE : read_bytes); - - for (i = 0; i < fifo_count; i++) { - /* - * Write dummy data byte for the device - * to shift in actual data. Most of the SPI devices - * accepts dummy data value as 0. In case of any - * other value change DUMMY_DATA_VAL. - */ - spi_write_byte(ds, DUMMY_DATA_VAL); - } - } + /* Wait for output FIFO to drain. */ + if (!out_bytes) + while (readl_i(ds->regs->qup_operational) & + QUP_OUTPUT_FIFO_NOT_EMPTY) + ; } - if (flags & SPI_XFER_END) { - flush_fifos(ds); + ret = config_spi_state(ds, SPI_RESET_STATE); + if (ret) goto out; - } - return ret; - -out: - /* Deassert CS */ - CS_change(ds->slave.bus, ds->slave.cs, CS_DEASSERT); - - /* - * Put the SPI Core back in the Reset State - * to end the transfer - */ - (void)config_spi_state(ds, SPI_RESET_STATE); - - return ret; - -} - -/* - * Function to write data to the Output FIFO - */ -static int gsbi_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer, - unsigned int bytes, unsigned long flags) -{ - uint32_t val; - unsigned int i; - unsigned int write_len = bytes; - unsigned int read_len = bytes; - unsigned int fifo_count; - int ret = SUCCESS; - int state_config; - - if (flags & SPI_XFER_BEGIN) { - /* Select the chip select */ - CS_change(ds->slave.bus, ds->slave.cs, CS_ASSERT); - } +spi_receive: + if (!in_bytes) /* Nothing to read. */ + goto out; - state_config = config_spi_state(ds, SPI_RESET_STATE); - if (state_config) - return state_config; + /* Enable input FIFO */ + clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK, + SPI_QUP_CONF_INPUT_ENA); - /* No of bytes to be written in Output FIFO */ - writel(bytes, ds->regs->qup_mx_output_count); - writel(bytes, ds->regs->qup_mx_input_count); - state_config = config_spi_state(ds, SPI_RUN_STATE); - if (state_config) - return state_config; + writel_i(in_bytes, ds->regs->qup_mx_input_count); + writel_i(in_bytes, ds->regs->qup_mx_output_count); - /* - * read_len considered to ensure that we read the dummy data for the - * write we performed. This is needed to ensure with WR-RD transaction - * to get the actual data on the subsequent read cycle that happens - */ - while (write_len || read_len) { - - ret = check_fifo_status(ds->regs->qup_operational); - if (ret != SUCCESS) - goto out; - - val = readl(ds->regs->qup_operational); - if (val & OUTPUT_SERVICE_FLAG) { - /* - * acknowledge to hw that software will write - * expected output data - */ - val &= OUTPUT_SERVICE_FLAG; - writel(val, ds->regs->qup_operational); - - if (write_len > SPI_OUTPUT_BLOCK_SIZE) - fifo_count = SPI_OUTPUT_BLOCK_SIZE; - else - fifo_count = write_len; - - for (i = 0; i < fifo_count; i++) { - /* Write actual data to output FIFO */ - spi_write_byte(ds, *cmd_buffer); - cmd_buffer++; - write_len--; - } - } - if (val & INPUT_SERVICE_FLAG) { - /* - * acknowledge to hw that software - * will read input data - */ - val &= INPUT_SERVICE_FLAG; - writel(val, ds->regs->qup_operational); - - if (read_len > SPI_INPUT_BLOCK_SIZE) - fifo_count = SPI_INPUT_BLOCK_SIZE; - else - fifo_count = read_len; - - for (i = 0; i < fifo_count; i++) { - /* Read dummy data for the data written */ - (void)spi_read_byte(ds); - - /* Decrement the write count after reading the dummy data - * from the device. This is to make sure we read dummy data - * before we write the data to fifo - */ - read_len--; - } - } - } - - if (flags & SPI_XFER_END) { - flush_fifos(ds); + ret = config_spi_state(ds, SPI_RUN_STATE); + if (ret) goto out; - } - return ret; + /* Seed clocking */ + writel_i(0xff, ds->regs->qup_output_fifo); + dbuf = din; /* Alias for pointer autoincrement again. */ + while (in_bytes) { + if (!(readl_i(ds->regs->qup_operational) & + QUP_INPUT_FIFO_NOT_EMPTY)) + continue; + /* Keep it clocking */ + writel_i(0xff, ds->regs->qup_output_fifo); + + *dbuf++ = readl_i(ds->regs->qup_input_fifo) & 0xff; + in_bytes--; + } -out: + out: /* Deassert CS */ CS_change(ds->slave.bus, ds->slave.cs, CS_DEASSERT); @@ -871,54 +736,3 @@ out: return ret; } - -/* - * This function is invoked with either tx_buf or rx_buf. - * Calling this function with both null does a chip select change. - */ -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int len; - const u8 *txp = dout; - u8 *rxp = din; - int ret; - - if (bitlen & 0x07) { - printf("err : Invalid bit length"); - return -EINVAL; - } - - len = bitlen >> 3; - - if (dout != NULL) { - ret = gsbi_spi_write(ds, txp, len, flags); - if (ret != SUCCESS) - return ret; - } - - if (din != NULL) - return gsbi_spi_read(ds, rxp, len, flags); - - if ((din == NULL) && (dout == NULL)) - /* To handle only when chip select change is needed */ - ret = gsbi_spi_write(ds, NULL, 0, flags); - - return ret; -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - -}

1 0

New patch to review for coreboot: 89dc00a ipq8064: copy u-boot spi driver as is
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7982 -gerrit commit 89dc00aa6e7e210ed1ca81d34a5e29719a2baf9f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Apr 10 14:20:39 2014 -0700 ipq8064: copy u-boot spi driver as is This brings in the banana_cs version of the SPI driver. BUG=chrome-os-partner:27784 TEST=none Original-Change-Id: Ie93ec8c962c26fff1f0a235516cd8a4062cab40b Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194225 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 3cada6e4ed51a6d4f637aa31a1a836352a99d13d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0a58a4ddaf9375c22c9b2b249a2baa2c5538ba6c --- src/soc/qualcomm/ipq806x/include/spi.h | 340 ++++++++++++ src/soc/qualcomm/ipq806x/spi.c | 924 +++++++++++++++++++++++++++++++++ 2 files changed, 1264 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/include/spi.h b/src/soc/qualcomm/ipq806x/include/spi.h new file mode 100644 index 0000000..2020043 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/spi.h @@ -0,0 +1,340 @@ +/* + * Register definitions for the IPQ GSBI Controller + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + */ + +#ifndef _IPQ_SPI_H_ +#define _IPQ_SPI_H_ + +#define QUP5_BASE 0x1a280000 +#define QUP6_BASE 0x16580000 +#define QUP7_BASE 0x16680000 + +#define GSBI5_BASE 0x1a200000 +#define GSBI6_BASE 0x16500000 +#define GSBI7_BASE 0x16600000 + +#define GSBI5_QUP5_REG_BASE (QUP5_BASE + 0x00000000) +#define GSBI6_QUP6_REG_BASE (QUP6_BASE + 0x00000000) +#define GSBI7_QUP7_REG_BASE (QUP7_BASE + 0x00000000) + +#define GSBI5_REG_BASE (GSBI5_BASE + 0x00000000) +#define GSBI6_REG_BASE (GSBI6_BASE + 0x00000000) +#define GSBI7_REG_BASE (GSBI7_BASE + 0x00000000) + +#define BOOT_SPI_PORT5_BASE QUP5_BASE +#define BOOT_SPI_PORT6_BASE QUP6_BASE +#define BOOT_SPI_PORT7_BASE QUP7_BASE + +#define GSBI5_SPI_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000300) +#define GSBI6_SPI_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000300) +#define GSBI7_SPI_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000300) + +#define GSBI5_SPI_IO_CONTROL_REG (GSBI5_QUP5_REG_BASE + 0x00000304) +#define GSBI6_SPI_IO_CONTROL_REG (GSBI6_QUP6_REG_BASE + 0x00000304) +#define GSBI7_SPI_IO_CONTROL_REG (GSBI7_QUP7_REG_BASE + 0x00000304) + +#define GSBI5_SPI_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x00000308) +#define GSBI6_SPI_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x00000308) +#define GSBI7_SPI_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x00000308) + +#define GSBI5_SPI_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x0000030c) +#define GSBI6_SPI_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x0000030c) +#define GSBI7_SPI_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x0000030c) + +#define GSBI5_GSBI_CTRL_REG_REG (GSBI5_REG_BASE + 0x00000000) +#define GSBI6_GSBI_CTRL_REG_REG (GSBI6_REG_BASE + 0x00000000) +#define GSBI7_GSBI_CTRL_REG_REG (GSBI7_REG_BASE + 0x00000000) + +#define GSBI5_QUP_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000000) +#define GSBI6_QUP_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000000) +#define GSBI7_QUP_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000000) + +#define GSBI5_QUP_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x0000001c) +#define GSBI6_QUP_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x0000001c) +#define GSBI7_QUP_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x0000001c) + +#define GSBI5_QUP_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x00000020) +#define GSBI6_QUP_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x00000020) +#define GSBI7_QUP_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x00000020) + +#define GSBI5_QUP_OPERATIONAL_REG (GSBI5_QUP5_REG_BASE + 0x00000018) +#define GSBI6_QUP_OPERATIONAL_REG (GSBI6_QUP6_REG_BASE + 0x00000018) +#define GSBI7_QUP_OPERATIONAL_REG (GSBI7_QUP7_REG_BASE + 0x00000018) + +#define GSBI5_QUP_IO_MODES_REG (GSBI5_QUP5_REG_BASE + 0x00000008) +#define GSBI6_QUP_IO_MODES_REG (GSBI6_QUP6_REG_BASE + 0x00000008) +#define GSBI7_QUP_IO_MODES_REG (GSBI7_QUP7_REG_BASE + 0x00000008) + +#define GSBI5_QUP_STATE_REG (GSBI5_QUP5_REG_BASE + 0x00000004) +#define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004) +#define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004) + +#define GSBI5_QUP_INPUT_FIFOc_REG(c) \ + (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c)) +#define GSBI6_QUP_INPUT_FIFOc_REG(c) \ + (GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c)) +#define GSBI7_QUP_INPUT_FIFOc_REG(c) \ + (GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c)) + +#define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c)) +#define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c)) +#define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c)) + +#define GSBI5_QUP_MX_INPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000200) +#define GSBI6_QUP_MX_INPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000200) +#define GSBI7_QUP_MX_INPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000200) + +#define GSBI5_QUP_MX_OUTPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000100) +#define GSBI6_QUP_MX_OUTPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000100) +#define GSBI7_QUP_MX_OUTPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000100) + +#define GSBI5_QUP_SW_RESET_REG (GSBI5_QUP5_REG_BASE + 0x0000000c) +#define GSBI6_QUP_SW_RESET_REG (GSBI6_QUP6_REG_BASE + 0x0000000c) +#define GSBI7_QUP_SW_RESET_REG (GSBI7_QUP7_REG_BASE + 0x0000000c) + +#define CLK_CTL_REG_BASE 0x00900000 +#define GSBIn_RESET_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029dc + 32 * ((n)-1)) + +#define SFAB_AHB_S3_FCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x0000216c) +#define CFPB_CLK_NS_REG \ + (CLK_CTL_REG_BASE + 0x0000264c) +#define SFAB_CFPB_S_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x000026c0) +#define CFPB_SPLITTER_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x000026e0) +#define CFPB0_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x00002650) +#define CFPB2_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x00002658) +#define GSBIn_HCLK_CTL_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029c0 + 32 * ((n)-1)) +#define GSBIn_QUP_APPS_NS_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029cc + 32 * ((n)-1)) +#define GSBIn_QUP_APPS_MD_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029c8 + 32 * ((n)-1)) +#define CLK_HALT_CFPB_STATEB_REG \ + (CLK_CTL_REG_BASE + 0x00002fd0) + +#define GSBI5_HCLK 23 +#define GSBI6_HCLK 19 +#define GSBI7_HCLK 15 +#define GSBI5_QUP_APPS_CLK 20 +#define GSBI6_QUP_APPS_CLK 16 +#define GSBI7_QUP_APPS_CLK 12 +#define GSBI_CLK_BRANCH_ENA_MSK (1 << 4) +#define GSBI_CLK_BRANCH_ENA (1 << 4) +#define GSBI_CLK_BRANCH_DIS (0 << 4) +#define QUP_CLK_BRANCH_ENA_MSK (1 << 9) +#define QUP_CLK_BRANCH_ENA (1 << 9) +#define QUP_CLK_BRANCH_DIS (0 << 9) +#define CLK_ROOT_ENA_MSK (1 << 11) +#define CLK_ROOT_ENA (1 << 11) +#define CLK_ROOT_DIS (0 << 11) + +#define QUP_STATE_VALID_BIT 2 +#define QUP_STATE_VALID 1 +#define QUP_STATE_MASK 0x3 +#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) +#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) +#define SPI_QUP_CONF_INPUT_MSK (1 << 7) +#define SPI_QUP_CONF_INPUT_ENA (0 << 7) +#define SPI_QUP_CONF_OUTPUT_MSK (1 << 6) +#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) +#define QUP_STATE_RUN_STATE 0x1 +#define QUP_STATE_RESET_STATE 0x0 +#define SPI_BIT_WORD_MSK 0x1F +#define SPI_8_BIT_WORD 0x07 +#define PROTOCOL_CODE_MSK (0x07 << 4) +#define PROTOCOL_CODE_SPI (0x03 << 4) +#define LOOP_BACK_MSK (1 << 8) +#define NO_LOOP_BACK (0 << 8) +#define SLAVE_OPERATION_MSK (1 << 5) +#define SLAVE_OPERATION (0 << 5) +#define CLK_ALWAYS_ON (0 << 9) +#define MX_CS_MODE (0 << 8) +#define NO_TRI_STATE (1 << 0) +#define OUTPUT_BIT_SHIFT_MSK (1 << 16) +#define OUTPUT_BIT_SHIFT_EN (1 << 16) +#define INPUT_BLOCK_MODE_MSK (0x03 << 12) +#define INPUT_BLOCK_MODE (0x01 << 12) +#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10) +#define OUTPUT_BLOCK_MODE (0x01 << 10) +#define GSBI1_RESET (1 << 0) +#define GSBI1_RESET_MSK 0x1 + +#define GSBI_M_VAL_SHFT 16 +#define GSBIn_M_VAL_MSK (0xFF << GSBI_M_VAL_SHFT) +#define GSBI_N_VAL_SHFT 16 +#define GSBIn_N_VAL_MSK (0xFF << GSBI_N_VAL_SHFT) +#define GSBI_D_VAL_SHFT 0 +#define GSBIn_D_VAL_MSK (0xFF << GSBI_D_VAL_SHFT) +#define MNCNTR_RST_MSK (1 << 7) +#define MNCNTR_RST_ENA (1 << 7) +#define MNCNTR_RST_DIS (0 << 7) +#define MNCNTR_MSK (1 << 8) +#define MNCNTR_EN (1 << 8) +#define MNCNTR_DIS (0 << 8) +#define MNCNTR_MODE_MSK (0x3 << 5) +#define MNCNTR_MODE_BYPASS (0 << 5) +#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) +#define GSBI_PRE_DIV_SEL_SHFT 3 +#define GSBIn_PRE_DIV_SEL_MSK (0x3 << GSBI_PRE_DIV_SEL_SHFT) +#define GSBIn_PLL_SRC_MSK (0x03 << 0) +#define GSBIn_PLL_SRC_PXO (0 << 0) +#define GSBIn_PLL_SRC_PLL8 (0x3 << 0) + +#define SPI_INPUT_FIRST_MODE (1 << 9) +#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10) +#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5) +#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4) +#define OUTPUT_SERVICE_FLAG (1 << 8) +#define INPUT_SERVICE_FLAG (1 << 9) +#define QUP_OUTPUT_FIFO_FULL (1 << 6) +#define SPI_INPUT_BLOCK_SIZE 4 +#define SPI_OUTPUT_BLOCK_SIZE 4 +#define GSBI5_SPI_CLK 21 +#define GSBI5_SPI_MISO 19 +#define GSBI5_SPI_MOSI 18 +#define GSBI5_SPI_CS_0 20 +#define GSBI5_SPI_CS_1 61 +#define GSBI5_SPI_CS_2 62 +#define GSBI5_SPI_CS_3 2 +#define GSBI6_SPI_CLK 30 +#define GSBI6_SPI_CS_0 29 +#define GSBI6_SPI_MISO 28 +#define GSBI6_SPI_MOSI 27 +#define GSBI7_SPI_CLK 9 +#define GSBI7_SPI_CS_0 8 +#define GSBI7_SPI_MISO 7 +#define GSBI7_SPI_MOSI 6 + +#define GPIO_FUNC_ENABLE 1 +#define GPIO_FUNC_DISABLE 0 +#define FUNC_SEL_1 1 +#define FUNC_SEL_3 3 +#define FUNC_SEL_GPIO 0 +#define GPIO_DRV_STR_10MA 0x4 +#define GPIO_DRV_STR_11MA 0x7 +#define GPIO_OUT 1 +#define MSM_GSBI_MAX_FREQ 51200000 + +#define SPI_RESET_STATE 0 +#define SPI_RUN_STATE 1 +#define SPI_CORE_RESET 0 +#define SPI_CORE_RUNNING 1 +#define GSBI_SPI_MODE_0 0 +#define GSBI_SPI_MODE_1 1 +#define GSBI_SPI_MODE_2 2 +#define GSBI_SPI_MODE_3 3 +#define GSBI5_SPI 0 +#define GSBI6_SPI 1 +#define GSBI7_SPI 2 + +struct gsbi_spi { + unsigned int spi_config; + unsigned int io_control; + unsigned int error_flags; + unsigned int error_flags_en; + unsigned int gsbi_ctrl; + unsigned int qup_config; + unsigned int qup_error_flags; + unsigned int qup_error_flags_en; + unsigned int qup_operational; + unsigned int qup_io_modes; + unsigned int qup_state; + unsigned int qup_input_fifo; + unsigned int qup_output_fifo; + unsigned int qup_mx_input_count; + unsigned int qup_mx_output_count; + unsigned int qup_sw_reset; + unsigned int qup_ns_reg; + unsigned int qup_md_reg; +}; + +static const struct gsbi_spi spi_reg[] = { + /* GSBI5 registers for SPI interface */ + { + GSBI5_SPI_CONFIG_REG, + GSBI5_SPI_IO_CONTROL_REG, + GSBI5_SPI_ERROR_FLAGS_REG, + GSBI5_SPI_ERROR_FLAGS_EN_REG, + GSBI5_GSBI_CTRL_REG_REG, + GSBI5_QUP_CONFIG_REG, + GSBI5_QUP_ERROR_FLAGS_REG, + GSBI5_QUP_ERROR_FLAGS_EN_REG, + GSBI5_QUP_OPERATIONAL_REG, + GSBI5_QUP_IO_MODES_REG, + GSBI5_QUP_STATE_REG, + GSBI5_QUP_INPUT_FIFOc_REG(0), + GSBI5_QUP_OUTPUT_FIFOc_REG(0), + GSBI5_QUP_MX_INPUT_COUNT_REG, + GSBI5_QUP_MX_OUTPUT_COUNT_REG, + GSBI5_QUP_SW_RESET_REG, + GSBIn_QUP_APPS_NS_REG(5), + GSBIn_QUP_APPS_MD_REG(5) + }, + /* GSBI6 registers for SPI interface */ + { + GSBI6_SPI_CONFIG_REG, + GSBI6_SPI_IO_CONTROL_REG, + GSBI6_SPI_ERROR_FLAGS_REG, + GSBI6_SPI_ERROR_FLAGS_EN_REG, + GSBI6_GSBI_CTRL_REG_REG, + GSBI6_QUP_CONFIG_REG, + GSBI6_QUP_ERROR_FLAGS_REG, + GSBI6_QUP_ERROR_FLAGS_EN_REG, + GSBI6_QUP_OPERATIONAL_REG, + GSBI6_QUP_IO_MODES_REG, + GSBI6_QUP_STATE_REG, + GSBI6_QUP_INPUT_FIFOc_REG(0), + GSBI6_QUP_OUTPUT_FIFOc_REG(0), + GSBI6_QUP_MX_INPUT_COUNT_REG, + GSBI6_QUP_MX_OUTPUT_COUNT_REG, + GSBI6_QUP_SW_RESET_REG, + GSBIn_QUP_APPS_NS_REG(6), + GSBIn_QUP_APPS_MD_REG(6) + }, + /* GSBI7 registers for SPI interface */ + { + GSBI7_SPI_CONFIG_REG, + GSBI7_SPI_IO_CONTROL_REG, + GSBI7_SPI_ERROR_FLAGS_REG, + GSBI7_SPI_ERROR_FLAGS_EN_REG, + GSBI7_GSBI_CTRL_REG_REG, + GSBI7_QUP_CONFIG_REG, + GSBI7_QUP_ERROR_FLAGS_REG, + GSBI7_QUP_ERROR_FLAGS_EN_REG, + GSBI7_QUP_OPERATIONAL_REG, + GSBI7_QUP_IO_MODES_REG, + GSBI7_QUP_STATE_REG, + GSBI7_QUP_INPUT_FIFOc_REG(0), + GSBI7_QUP_OUTPUT_FIFOc_REG(0), + GSBI7_QUP_MX_INPUT_COUNT_REG, + GSBI7_QUP_MX_OUTPUT_COUNT_REG, + GSBI7_QUP_SW_RESET_REG, + GSBIn_QUP_APPS_NS_REG(7), + GSBIn_QUP_APPS_MD_REG(7) + } +}; + +struct ipq_spi_slave { + struct spi_slave slave; + const struct gsbi_spi *regs; + unsigned int core_state; + unsigned int mode; + unsigned int initialized; + unsigned long freq; +}; + +static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ipq_spi_slave, slave); +} + +#endif /* _IPQ_SPI_H_ */ diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c new file mode 100644 index 0000000..45ecc0e --- /dev/null +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -0,0 +1,924 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + */ + +#include <common.h> +#include <spi.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/errno.h> +#include "ipq_spi.h" +#include <asm/arch-ipq806x/gpio.h> +#include <asm/arch-ipq806x/iomap.h> + +#define SUCCESS 0 + +#define DUMMY_DATA_VAL 0 +#define TIMEOUT_CNT 100 +#define CS_ASSERT 1 +#define CS_DEASSERT 0 +#define NUM_PORTS 3 +#define NUM_GSBI_PINS 3 +#define TLMM_ARGS 6 +#define NUM_CS 4 +#define GSBI_PIN_IDX 0 +#define FUNC_SEL_IDX 1 +#define GPIO_DIR_IDX 2 +#define PULL_CONF_IDX 3 +#define DRV_STR_IDX 4 +#define GPIO_EN_IDX 5 + +#define GSBI_IDX_TO_GSBI(idx) (idx + 5) + +/* + * TLMM Configuration for SPI NOR + * gsbi_pin_conf[bus_num][GPIO_NUM, FUNC_SEL, I/O, + * PULL UP/DOWN, DRV_STR, GPIO_FUNC] + * gsbi_pin_conf[0][x][y] -- GSBI5 + * gsbi_pin_conf[1][x][y] -- GSBI6 + * gsbi_pin_conf[2][x][y] -- GSBI7 +*/ +static unsigned int gsbi_pin_conf[NUM_PORTS][NUM_GSBI_PINS][TLMM_ARGS] = { + { + /* GSBI5 CLK */ + { + GSBI5_SPI_CLK, FUNC_SEL_1, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_11MA, GPIO_FUNC_DISABLE + }, + /* GSBI5 MISO */ + { + GSBI5_SPI_MISO, FUNC_SEL_1, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_10MA, GPIO_FUNC_DISABLE + }, + /* GSBI5 MOSI */ + { + GSBI5_SPI_MOSI, FUNC_SEL_1, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_10MA, GPIO_FUNC_DISABLE + } + }, + { + /* GSBI6 CLK */ + { + GSBI6_SPI_CLK, FUNC_SEL_3, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_11MA, GPIO_FUNC_DISABLE + }, + /* GSBI6 MISO */ + { + GSBI6_SPI_MISO, FUNC_SEL_3, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_10MA, GPIO_FUNC_DISABLE + }, + /* GSBI6 MOSI */ + { + GSBI6_SPI_MOSI, FUNC_SEL_3, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_10MA, GPIO_FUNC_DISABLE + } + }, + { + /* GSBI7 CLK */ + { + GSBI7_SPI_CLK, FUNC_SEL_1, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_11MA, GPIO_FUNC_DISABLE + }, + /* GSBI7 MISO */ + { + GSBI7_SPI_MISO, FUNC_SEL_1, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_10MA, GPIO_FUNC_DISABLE + }, + /* GSBI7 MOSI */ + { + GSBI7_SPI_MOSI, FUNC_SEL_1, GPIO_INPUT, + GPIO_PULL_DOWN, GPIO_DRV_STR_10MA, GPIO_FUNC_DISABLE + } + } +}; + +/* + * CS GPIO number array cs_gpio_array[port_num][cs_num] + * cs_gpio_array[0][x] -- GSBI5 + * cs_gpio_array[1][x] -- GSBI6 + * cs_gpio_array[2][x] -- GSBI7 + */ +static unsigned int cs_gpio_array[NUM_PORTS][NUM_CS] = { + { + GSBI5_SPI_CS_0, GSBI5_SPI_CS_1, GSBI5_SPI_CS_2, GSBI5_SPI_CS_3 + }, + { + GSBI6_SPI_CS_0, 0, 0, 0 + }, + { + GSBI7_SPI_CS_0, 0, 0, 0 + } +}; + +/* + * GSBI HCLK state register bit + * hclk_state[0] -- GSBI5 + * hclk_state[1] -- GSBI6 + * hclk_state[2] -- GSBI7 +*/ +static unsigned int hclk_state[NUM_PORTS] = { + GSBI5_HCLK, + GSBI6_HCLK, + GSBI7_HCLK +}; + +/* + * GSBI QUP_APPS_CLK state register bit + * qup_apps_clk_state[0] -- GSBI5 + * qup_apps_clk_state[1] -- GSBI6 + * qup_apps_clk_state[2] -- GSBI7 +*/ +static unsigned int qup_apps_clk_state[NUM_PORTS] = { + GSBI5_QUP_APPS_CLK, + GSBI6_QUP_APPS_CLK, + GSBI7_QUP_APPS_CLK +}; + + +static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay) +{ + unsigned int count = TIMEOUT_CNT; + unsigned int bit_val = ((readl(reg_addr) >> bit_num) & 0x01); + + while (bit_val != val) { + count--; + if (count == 0) + return -ETIMEDOUT; + udelay(us_delay); + bit_val = ((readl(reg_addr) >> bit_num) & 0x01); + } + + return SUCCESS; +} + +/* + * Check whether GSBIn_QUP State is valid + */ +static int check_qup_state_valid(struct ipq_spi_slave *ds) +{ + + return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_BIT, + QUP_STATE_VALID, 1); + +} + +/* + * Configure GSBIn Core state + */ +static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state) +{ + uint32_t val; + int ret = SUCCESS; + + ret = check_qup_state_valid(ds); + if (ret != SUCCESS) + return ret; + + switch (state) { + case SPI_RUN_STATE: + /* Set the state to RUN */ + val = ((readl(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RUN_STATE); + writel(val, ds->regs->qup_state); + ret = check_qup_state_valid(ds); + if (ret != SUCCESS) + return ret; + ds->core_state = SPI_CORE_RUNNING; + break; + case SPI_RESET_STATE: + /* Set the state to RESET */ + val = ((readl(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RESET_STATE); + writel(val, ds->regs->qup_state); + ret = check_qup_state_valid(ds); + if (ret != SUCCESS) + return ret; + ds->core_state = SPI_CORE_RESET; + break; + default: + printf("err: unsupported GSBI SPI state : %d\n", state); + ret = -EINVAL; + break; + } + + return ret; +} + +/* + * Set GSBIn SPI Mode + */ +static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode) +{ + unsigned int clk_idle_state; + unsigned int input_first_mode; + uint32_t val; + + switch (mode) { + case GSBI_SPI_MODE_0: + clk_idle_state = 0; + input_first_mode = SPI_INPUT_FIRST_MODE; + break; + case GSBI_SPI_MODE_1: + clk_idle_state = 0; + input_first_mode = 0; + break; + case GSBI_SPI_MODE_2: + clk_idle_state = 1; + input_first_mode = SPI_INPUT_FIRST_MODE; + break; + case GSBI_SPI_MODE_3: + clk_idle_state = 1; + input_first_mode = 0; + break; + default: + printf("err : unsupported spi mode : %d\n", mode); + return; + } + + val = readl(ds->regs->spi_config); + val |= input_first_mode; + writel(val, ds->regs->spi_config); + + val = readl(ds->regs->io_control); + if (clk_idle_state) + val |= SPI_IO_CONTROL_CLOCK_IDLE_HIGH; + else + val &= ~SPI_IO_CONTROL_CLOCK_IDLE_HIGH; + + writel(val, ds->regs->io_control); +} + +/* + * Check for HCLK state + */ +static int check_hclk_state(unsigned int core_num, int enable) +{ + if (clk_is_dummy()) + return 0; + + return check_bit_state(CLK_HALT_CFPB_STATEB_REG, + hclk_state[core_num], enable, 5); +} + +/* + * Check for QUP APPS CLK state + */ +static int check_qup_clk_state(unsigned int core_num, int enable) +{ + if (clk_is_dummy()) + return 0; + + return check_bit_state(CLK_HALT_CFPB_STATEB_REG, + qup_apps_clk_state[core_num], enable, 5); +} + +/* + * Function to assert and De-assert chip select + */ +static void CS_change(int port_num, int cs_num, int enable) +{ + unsigned int cs_gpio = cs_gpio_array[port_num][cs_num]; + uint32_t addr = GPIO_IN_OUT_ADDR(cs_gpio); + uint32_t val = readl(addr); + + val &= (~(1 << GPIO_OUT)); + if (!enable) + val |= (1 << GPIO_OUT); + writel(val, addr); +} + +/* + * GSBIn TLMM configuration + */ +static void gsbi_pin_config(unsigned int port_num, int cs_num) +{ + unsigned int gpio; + unsigned int i; + /* Hold the GSBIn (core_num) core in reset */ + clrsetbits_le32(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)), + GSBI1_RESET_MSK, GSBI1_RESET); + + /* + * Configure SPI_CLK, SPI_MISO and SPI_MOSI + */ + for (i = 0; i < NUM_GSBI_PINS; i++) { + unsigned int func_sel; + unsigned int io_config; + unsigned int pull_config; + unsigned int drv_strength; + unsigned int gpio_en; + unsigned int *ptr; + + ptr = gsbi_pin_conf[port_num][i]; + gpio = *(ptr + GSBI_PIN_IDX); + func_sel = *(ptr + FUNC_SEL_IDX); + io_config = *(ptr + GPIO_DIR_IDX); + pull_config = *(ptr + PULL_CONF_IDX); + drv_strength = *(ptr + DRV_STR_IDX); + gpio_en = *(ptr + GPIO_EN_IDX); + + gpio_tlmm_config(gpio, func_sel, io_config, + pull_config, drv_strength, gpio_en); + } + + gpio = cs_gpio_array[port_num][cs_num]; + /* configure CS */ + gpio_tlmm_config(gpio, FUNC_SEL_GPIO, GPIO_OUTPUT, GPIO_PULL_UP, + GPIO_DRV_STR_10MA, GPIO_FUNC_ENABLE); + CS_change(port_num, cs_num, CS_DEASSERT); +} + +/* + * Clock configuration for GSBIn Core + */ +static int gsbi_clock_init(struct ipq_spi_slave *ds) +{ + int ret; + + /* Hold the GSBIn (core_num) core in reset */ + clrsetbits_le32(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + GSBI1_RESET_MSK, GSBI1_RESET); + + /* Disable GSBIn (core_num) QUP core clock branch */ + clrsetbits_le32(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + QUP_CLK_BRANCH_DIS); + + ret = check_qup_clk_state(ds->slave.bus, 1); + if (ret) { + printf("QUP Clock Halt For GSBI%d failed!\n", ds->slave.bus); + return ret; + } + + /* Disable M/N:D counter and hold M/N:D counter in reset */ + clrsetbits_le32(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK), + (MNCNTR_RST_ENA | MNCNTR_DIS)); + + /* Disable GSBIn (core_num) QUP core clock root */ + clrsetbits_le32(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS); + + clrsetbits_le32(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK, + GSBIn_PLL_SRC_PLL8); + clrsetbits_le32(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK, + (0 << GSBI_PRE_DIV_SEL_SHFT)); + + /* Program M/N:D values for GSBIn_QUP_APPS_CLK @50MHz */ + clrsetbits_le32(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK, + (0x01 << GSBI_M_VAL_SHFT)); + clrsetbits_le32(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK, + (0xF7 << GSBI_D_VAL_SHFT)); + clrsetbits_le32(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK, + (0xF8 << GSBI_N_VAL_SHFT)); + + /* Set MNCNTR_MODE = 0: Bypass mode */ + clrsetbits_le32(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK, + MNCNTR_MODE_DUAL_EDGE); + + /* De-assert the M/N:D counter reset */ + clrsetbits_le32(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS); + clrsetbits_le32(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN); + + /* + * Enable the GSBIn (core_num) QUP core clock root. + * Keep MND counter disabled + */ + clrsetbits_le32(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA); + + /* Enable GSBIn (core_num) QUP core clock branch */ + clrsetbits_le32(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + QUP_CLK_BRANCH_ENA); + + ret = check_qup_clk_state(ds->slave.bus, 0); + if (ret) { + printf("QUP Clock Enable For GSBI%d" + " failed!\n", ds->slave.bus); + return ret; + } + + /* Enable GSBIn (core_num) core clock branch */ + clrsetbits_le32(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + GSBI_CLK_BRANCH_ENA_MSK, GSBI_CLK_BRANCH_ENA); + + ret = check_hclk_state(ds->slave.bus, 0); + if (ret) { + printf("HCLK Enable For GSBI%d failed!\n", ds->slave.bus); + return ret; + } + + /* Release GSBIn (core_num) core from reset */ + clrsetbits_le32(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + GSBI1_RESET_MSK, 0); + udelay(50); + + return SUCCESS; +} + +/* + * Reset entire QUP and all mini cores + */ +static void spi_reset(struct ipq_spi_slave *ds) +{ + writel(0x1, ds->regs->qup_sw_reset); + udelay(5); +} + +void spi_init() +{ + /* do nothing */ + +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ipq_spi_slave *ds; + + ds = malloc(sizeof(struct ipq_spi_slave)); + if (!ds) { + printf("SPI error: malloc of SPI structure failed\n"); + return NULL; + } + + /* + * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash + * on different GSBI5, GSBI6 and GSBI7 + * with different number of chip selects (CS, channels): + */ + if ((bus < GSBI5_SPI) || (bus > GSBI7_SPI) + || ((bus == GSBI5_SPI) && (cs > 3)) + || ((bus == GSBI6_SPI) && (cs > 0)) + || ((bus == GSBI7_SPI) && (cs > 0))) { + printf("SPI error: unsupported bus %d " + "(Supported busses 0,1 and 2) or chipselect\n", bus); + goto err; + } + ds->slave.bus = bus; + ds->slave.cs = cs; + + ds->regs = &spi_reg[bus]; + + /* TODO For different clock frequency */ + if (max_hz > MSM_GSBI_MAX_FREQ) { + printf("SPI error: unsupported frequency %d Hz " + "Max frequency is %d Hz\n", max_hz, MSM_GSBI_MAX_FREQ); + goto err; + } + ds->freq = max_hz; + + if (mode > GSBI_SPI_MODE_3) { + printf("SPI error: unsupported SPI mode %d\n", mode); + goto err; + } + ds->mode = mode; + + return &ds->slave; + +err: + free(ds); + return NULL; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + if (ds != NULL) + free(ds); +} + +/* + * GSBIn SPI Hardware Initialisation + */ +static int spi_hw_init(struct ipq_spi_slave *ds) +{ + int ret; + + ds->initialized = 0; + + /* GSBI module configuration */ + spi_reset(ds); + + /* Set the GSBIn QUP state */ + ret = config_spi_state(ds, SPI_RESET_STATE); + if (ret) + return ret; + + /* Configure GSBI_CTRL register to set protocol_mode to SPI:011 */ + clrsetbits_le32(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK, + PROTOCOL_CODE_SPI); + + /* + * Configure Mini core to SPI core with Input Output enabled, + * SPI master, N = 8 bits + */ + clrsetbits_le32(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK | + SPI_QUP_CONF_INPUT_MSK | + SPI_QUP_CONF_OUTPUT_MSK | + SPI_BIT_WORD_MSK), + (QUP_CONFIG_MINI_CORE_SPI | + SPI_QUP_CONF_INPUT_ENA | + SPI_QUP_CONF_OUTPUT_ENA | + SPI_8_BIT_WORD)); + + /* + * Configure Input first SPI protocol, + * SPI master mode and no loopback + */ + clrsetbits_le32(ds->regs->spi_config, (LOOP_BACK_MSK | + SLAVE_OPERATION_MSK), + (NO_LOOP_BACK | + SLAVE_OPERATION)); + + /* + * Configure SPI IO Control Register + * CLK_ALWAYS_ON = 0 + * MX_CS_MODE = 0 + * NO_TRI_STATE = 1 + */ + writel((CLK_ALWAYS_ON | MX_CS_MODE | NO_TRI_STATE), + ds->regs->io_control); + + /* + * Configure SPI IO Modes. + * OUTPUT_BIT_SHIFT_EN = 1 + * INPUT_MODE = Block Mode + * OUTPUT MODE = Block Mode + */ + clrsetbits_le32(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK | + INPUT_BLOCK_MODE_MSK | + OUTPUT_BLOCK_MODE_MSK), + (OUTPUT_BIT_SHIFT_EN | + INPUT_BLOCK_MODE | + OUTPUT_BLOCK_MODE)); + + spi_set_mode(ds, ds->mode); + + /* Disable Error mask */ + writel(0, ds->regs->error_flags_en); + writel(0, ds->regs->qup_error_flags_en); + + ds->initialized = 1; + + return SUCCESS; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + /* GPIO Configuration for SPI port */ + gsbi_pin_config(ds->slave.bus, ds->slave.cs); + + /* Clock configuration */ + ret = gsbi_clock_init(ds); + if (ret) + return ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + + return SUCCESS; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + spi_reset(ds); + ds->initialized = 0; +} + +/* Drain input fifo + * If input fifo is not empty drain the input FIFO. When the + * input fifo is drained make sure that the output fifo is also + * empty and break when the input fifo is completely drained. + */ +static void flush_fifos(struct ipq_spi_slave *ds) +{ + unsigned int fifo_data; + + while (1) { + if (readl(ds->regs->qup_operational) & + QUP_DATA_AVAILABLE_FOR_READ) { + fifo_data = readl(ds->regs->qup_input_fifo); + } else { + if (!(readl(ds->regs->qup_operational) & + QUP_OUTPUT_FIFO_NOT_EMPTY)) { + if (!(readl(ds->regs->qup_operational) & + QUP_DATA_AVAILABLE_FOR_READ)) + break; + } + } + } + + (void)fifo_data; +} + +/* + * Function to write data to OUTPUT FIFO + */ +static void spi_write_byte(struct ipq_spi_slave *ds, unsigned char data) +{ + /* Wait for space in the FIFO */ + while ((readl(ds->regs->qup_operational) & QUP_OUTPUT_FIFO_FULL)) + udelay(1); + + /* Write the byte of data */ + writel(data, ds->regs->qup_output_fifo); +} + +/* + * Function to read data from Input FIFO + */ +static unsigned char spi_read_byte(struct ipq_spi_slave *ds) +{ + /* Wait for Data in FIFO */ + while (!(readl(ds->regs->qup_operational) & + QUP_DATA_AVAILABLE_FOR_READ)) { + udelay(1); + } + + /* Read a byte of data */ + return readl(ds->regs->qup_input_fifo) & 0xff; +} + +/* + * Function to check wheather Input or Output FIFO + * has data to be serviced + */ +static int check_fifo_status(uint32_t reg_addr) +{ + unsigned int count = TIMEOUT_CNT; + unsigned int status_flag; + unsigned int val; + + do { + val = readl(reg_addr); + count--; + if (count == 0) + return -ETIMEDOUT; + status_flag = ((val & OUTPUT_SERVICE_FLAG) | (val & INPUT_SERVICE_FLAG)); + } while (!status_flag); + + return SUCCESS; +} + +/* + * Function to read bytes number of data from the Input FIFO + */ +static int gsbi_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer, + unsigned int bytes, unsigned long flags) +{ + uint32_t val; + unsigned int i; + unsigned int read_bytes = bytes; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + + if (flags & SPI_XFER_BEGIN) { + /* Assert chip select */ + CS_change(ds->slave.bus, ds->slave.cs, CS_ASSERT); + } + + /* Configure no of bytes to read */ + state_config = config_spi_state(ds, SPI_RESET_STATE); + if (state_config) + return state_config; + + writel(bytes, ds->regs->qup_mx_output_count); + writel(bytes, ds->regs->qup_mx_input_count); + + state_config = config_spi_state(ds, SPI_RUN_STATE); + if (state_config) + return state_config; + + while (read_bytes) { + + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = readl(ds->regs->qup_operational); + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will + * read input data + */ + val &= INPUT_SERVICE_FLAG; + writel(val, ds->regs->qup_operational); + + fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ? + SPI_INPUT_BLOCK_SIZE : read_bytes); + + for (i = 0; i < fifo_count; i++) { + *data_buffer = spi_read_byte(ds); + data_buffer++; + read_bytes--; + } + } + + if (val & OUTPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will + * write output data + */ + val &= OUTPUT_SERVICE_FLAG; + writel(val, ds->regs->qup_operational); + + fifo_count = ((read_bytes > SPI_OUTPUT_BLOCK_SIZE) ? + SPI_OUTPUT_BLOCK_SIZE : read_bytes); + + for (i = 0; i < fifo_count; i++) { + /* + * Write dummy data byte for the device + * to shift in actual data. Most of the SPI devices + * accepts dummy data value as 0. In case of any + * other value change DUMMY_DATA_VAL. + */ + spi_write_byte(ds, DUMMY_DATA_VAL); + } + } + } + + if (flags & SPI_XFER_END) { + flush_fifos(ds); + goto out; + } + + return ret; + +out: + /* Deassert CS */ + CS_change(ds->slave.bus, ds->slave.cs, CS_DEASSERT); + + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, SPI_RESET_STATE); + + return ret; + +} + +/* + * Function to write data to the Output FIFO + */ +static int gsbi_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer, + unsigned int bytes, unsigned long flags) +{ + uint32_t val; + unsigned int i; + unsigned int write_len = bytes; + unsigned int read_len = bytes; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + + if (flags & SPI_XFER_BEGIN) { + /* Select the chip select */ + CS_change(ds->slave.bus, ds->slave.cs, CS_ASSERT); + } + + state_config = config_spi_state(ds, SPI_RESET_STATE); + if (state_config) + return state_config; + + /* No of bytes to be written in Output FIFO */ + writel(bytes, ds->regs->qup_mx_output_count); + writel(bytes, ds->regs->qup_mx_input_count); + state_config = config_spi_state(ds, SPI_RUN_STATE); + if (state_config) + return state_config; + + /* + * read_len considered to ensure that we read the dummy data for the + * write we performed. This is needed to ensure with WR-RD transaction + * to get the actual data on the subsequent read cycle that happens + */ + while (write_len || read_len) { + + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = readl(ds->regs->qup_operational); + if (val & OUTPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will write + * expected output data + */ + val &= OUTPUT_SERVICE_FLAG; + writel(val, ds->regs->qup_operational); + + if (write_len > SPI_OUTPUT_BLOCK_SIZE) + fifo_count = SPI_OUTPUT_BLOCK_SIZE; + else + fifo_count = write_len; + + for (i = 0; i < fifo_count; i++) { + /* Write actual data to output FIFO */ + spi_write_byte(ds, *cmd_buffer); + cmd_buffer++; + write_len--; + } + } + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software + * will read input data + */ + val &= INPUT_SERVICE_FLAG; + writel(val, ds->regs->qup_operational); + + if (read_len > SPI_INPUT_BLOCK_SIZE) + fifo_count = SPI_INPUT_BLOCK_SIZE; + else + fifo_count = read_len; + + for (i = 0; i < fifo_count; i++) { + /* Read dummy data for the data written */ + (void)spi_read_byte(ds); + + /* Decrement the write count after reading the dummy data + * from the device. This is to make sure we read dummy data + * before we write the data to fifo + */ + read_len--; + } + } + } + + if (flags & SPI_XFER_END) { + flush_fifos(ds); + goto out; + } + + return ret; + +out: + /* Deassert CS */ + CS_change(ds->slave.bus, ds->slave.cs, CS_DEASSERT); + + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, SPI_RESET_STATE); + + return ret; +} + +/* + * This function is invoked with either tx_buf or rx_buf. + * Calling this function with both null does a chip select change. + */ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int len; + const u8 *txp = dout; + u8 *rxp = din; + int ret; + + if (bitlen & 0x07) { + printf("err : Invalid bit length"); + return -EINVAL; + } + + len = bitlen >> 3; + + if (dout != NULL) { + ret = gsbi_spi_write(ds, txp, len, flags); + if (ret != SUCCESS) + return ret; + } + + if (din != NULL) + return gsbi_spi_read(ds, rxp, len, flags); + + if ((din == NULL) && (dout == NULL)) + /* To handle only when chip select change is needed */ + ret = gsbi_spi_write(ds, NULL, 0, flags); + + return ret; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + +}

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coreboot-gerrit December 2014