coreboot-gerrit December 2014

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Patch set updated for coreboot: 3fe7fe8 Remove IRQ_SLOT_COUNT on all boards without PIRQ table.
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7566 -gerrit commit 3fe7fe8d497157dc6ab9cf003073d2c8af4bf173 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 23 22:01:09 2014 +0100 Remove IRQ_SLOT_COUNT on all boards without PIRQ table. This config is used only to generate PIRQ table. If no such table is supplied there is no need for config. Change-Id: I537d440f53019a6bf7f190446074e75e7420545a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/Kconfig | 4 ---- src/mainboard/google/bolt/Kconfig | 4 ---- src/mainboard/google/butterfly/Kconfig | 4 ---- src/mainboard/google/falco/Kconfig | 4 ---- src/mainboard/google/link/Kconfig | 4 ---- src/mainboard/google/panther/Kconfig | 4 ---- src/mainboard/google/parrot/Kconfig | 4 ---- src/mainboard/google/peppy/Kconfig | 4 ---- src/mainboard/google/samus/Kconfig | 4 ---- src/mainboard/google/slippy/Kconfig | 4 ---- src/mainboard/google/stout/Kconfig | 4 ---- src/mainboard/intel/bakersport_fsp/Kconfig | 4 ---- src/mainboard/intel/baskingridge/Kconfig | 4 ---- src/mainboard/intel/bayleybay_fsp/Kconfig | 4 ---- src/mainboard/intel/cougar_canyon2/Kconfig | 4 ---- src/mainboard/intel/emeraldlake2/Kconfig | 4 ---- src/mainboard/intel/minnowmax/Kconfig | 6 +++--- src/mainboard/intel/mohonpeak/Kconfig | 4 ---- src/mainboard/intel/wtm2/Kconfig | 4 ---- src/mainboard/kontron/ktqm77/Kconfig | 4 ---- src/mainboard/lenovo/t520/Kconfig | 4 ---- src/mainboard/lenovo/t530/Kconfig | 4 ---- src/mainboard/lenovo/t60/Kconfig | 4 ---- src/mainboard/lenovo/x200/Kconfig | 4 ---- src/mainboard/lenovo/x201/Kconfig | 4 ---- src/mainboard/lenovo/x220/Kconfig | 4 ---- src/mainboard/lenovo/x230/Kconfig | 4 ---- src/mainboard/packardbell/ms2290/Kconfig | 4 ---- src/mainboard/roda/rk9/Kconfig | 4 ---- src/mainboard/samsung/lumpy/Kconfig | 4 ---- src/mainboard/samsung/stumpy/Kconfig | 4 ---- 31 files changed, 3 insertions(+), 123 deletions(-) diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 06188fd..6480097 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -48,10 +48,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 2 diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 7a756cc..5ffbb8d 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -36,10 +36,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 26ec09f..df7460a 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -30,10 +30,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index e89d14e..d8dc21e 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -39,10 +39,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 130f025..99baba5 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -27,10 +27,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index e96746f..607b690 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -35,10 +35,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index dcc4d5d..bf423df 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -29,10 +29,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index acc23f2..308b843 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -41,10 +41,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index c6cbd18..cbfe2f2 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -37,10 +37,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 88bf501..42764a6 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -38,10 +38,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 812926a..59871fa 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -27,10 +27,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index 567889d..5c0707f 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER string default "Bakersport CRB (FSP)" -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 16 diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 512591e..e3c2cf7 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -26,10 +26,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 16 diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 384a2db..2c62390 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER string default "Bayley Bay CRB (FSP)" -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 16 diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 3b25161..27b9a97 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -28,10 +28,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf8000000 # set to match FSP -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 16 diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index dc04631..d6f4157 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -25,10 +25,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 16 diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index aacf174..a31b60b 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -58,9 +58,9 @@ config MINNOWMAX_2GB_SKU bool "2GB" endchoice -config IRQ_SLOT_COUNT - int - default 18 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 config MAX_CPUS int diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index eb97663..a140f15 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -48,10 +48,6 @@ config MAINBOARD_PART_NUMBER string default "Mohon Peak CRB" -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 16 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 353279a..c868e73 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -28,10 +28,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 16 diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 5f92c6c..485978c 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -26,10 +26,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index be2f5aa..d91ed67 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -43,10 +43,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 80c04c1..33fcd7d 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -44,10 +44,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 0aa8204..3acee64 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -44,10 +44,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 2 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 2dc5e4b..15e55c7 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -37,10 +37,6 @@ config USBDEBUG_HCD_INDEX int default 2 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 2 diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index ac7f8df..b1ca2f5 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -31,10 +31,6 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 -config IRQ_SLOT_COUNT - int - default 18 - config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 2161a8f..20e9527 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -44,10 +44,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 2f8f7b2..1a1e018 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -44,10 +44,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 58053e2..3ea302a 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -38,10 +38,6 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 -config IRQ_SLOT_COUNT - int - default 18 - config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 9477848..a17717a 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -28,10 +28,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 2 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 7d03fa0..baf0eee 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -29,10 +29,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8 diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index eee3755..17484a9 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -26,10 +26,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config IRQ_SLOT_COUNT - int - default 18 - config MAX_CPUS int default 8

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Patch set updated for coreboot: 3004b7e i945: Consolidate interrupt routing.
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7107 -gerrit commit 3004b7e51e2232f93f93c34aacbd874769e8a80c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Nov 22 20:46:20 2014 +0100 i945: Consolidate interrupt routing. The old code tried to make routing per-board, presumably for optimizing IRQ balancing but instead failed at providing an error-free default. Rewrite in unified and simplified way at the cost of minor performance hit on very old OS. Change-Id: I1ccc8949844ddcf18ebf81781c1aa1701058b378 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- .../apple/macbook21/acpi/i945_pci_irqs.asl | 71 ----------- src/mainboard/apple/macbook21/devicetree.cb | 37 ++++-- src/mainboard/apple/macbook21/mptable.c | 76 ------------ src/mainboard/apple/macbook21/romstage.c | 19 --- src/mainboard/getac/p470/acpi/i945_pci_irqs.asl | 87 -------------- src/mainboard/getac/p470/devicetree.cb | 45 ++++--- src/mainboard/getac/p470/mptable.c | 85 ------------- src/mainboard/getac/p470/romstage.c | 15 --- src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl | 85 ------------- src/mainboard/ibase/mb899/devicetree.cb | 45 ++++--- src/mainboard/ibase/mb899/mptable.c | 133 --------------------- src/mainboard/ibase/mb899/romstage.c | 15 --- .../intel/d945gclf/acpi/i945_pci_irqs.asl | 85 ------------- src/mainboard/intel/d945gclf/devicetree.cb | 43 ++++--- src/mainboard/intel/d945gclf/mptable.c | 90 -------------- src/mainboard/intel/d945gclf/romstage.c | 15 --- .../kontron/986lcd-m/acpi/i945_pci_irqs.asl | 85 ------------- src/mainboard/kontron/986lcd-m/devicetree.cb | 43 ++++--- src/mainboard/kontron/986lcd-m/mptable.c | 116 ------------------ src/mainboard/kontron/986lcd-m/romstage.c | 15 --- src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl | 63 ---------- src/mainboard/lenovo/t60/devicetree.cb | 43 ++++--- src/mainboard/lenovo/t60/mptable.c | 76 ------------ src/mainboard/lenovo/t60/romstage.c | 19 --- src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl | 63 ---------- src/mainboard/lenovo/x60/devicetree.cb | 37 ++++-- src/mainboard/lenovo/x60/mptable.c | 78 ------------ src/mainboard/lenovo/x60/romstage.c | 19 --- src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl | 84 ------------- src/mainboard/roda/rk886ex/devicetree.cb | 41 ++++--- src/mainboard/roda/rk886ex/mptable.c | 85 ------------- src/mainboard/roda/rk886ex/romstage.c | 15 --- src/northbridge/intel/i945/acpi/hostbridge.asl | 3 - src/northbridge/intel/i945/early_init.c | 23 ++++ src/northbridge/intel/i945/i945.h | 1 + src/southbridge/intel/i82801gx/acpi/ich7.asl | 2 + src/southbridge/intel/i82801gx/acpi/irq.asl | 82 +++++++++++++ src/southbridge/intel/i82801gx/chip.h | 12 -- src/southbridge/intel/i82801gx/lpc.c | 43 +++---- 39 files changed, 348 insertions(+), 1646 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl deleted file mode 100644 index 6047def..0000000 --- a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0001FFFF, 0, 0, 0x10 }, - Package() { 0x0002FFFF, 0, 0, 0x10 }, - Package() { 0x0007FFFF, 0, 0, 0x10 }, - Package() { 0x001BFFFF, 0, 0, 0x16 }, - Package() { 0x001CFFFF, 0, 0, 0x11 }, - Package() { 0x001CFFFF, 1, 0, 0x10 }, - Package() { 0x001CFFFF, 2, 0, 0x12 }, - Package() { 0x001CFFFF, 3, 0, 0x13 }, - Package() { 0x001DFFFF, 0, 0, 0x15 }, - Package() { 0x001DFFFF, 1, 0, 0x13 }, - Package() { 0x001DFFFF, 2, 0, 0x12 }, - Package() { 0x001DFFFF, 3, 0, 0x10 }, - Package() { 0x001EFFFF, 0, 0, 0x16 }, - Package() { 0x001EFFFF, 1, 0, 0x14 }, - Package() { 0x001FFFFF, 0, 0, 0x12 }, - Package() { 0x001FFFFF, 1, 0, 0x13 }, - Package() { 0x001FFFFF, 3, 0, 0x10 } - }) - } Else { - Return (Package() { - Package() { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0007FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001BFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 8ca84f8..822d7a3 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -37,22 +37,21 @@ chip northbridge/intel/i945 device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 end - device pci 02.0 on # VGA controller + device pci 02.0 on + ioapic_irq 2 INTA 0x10 # VGA controller subsystemid 0x8086 0x7270 end device pci 02.1 on # display controller subsystemid 0x17aa 0x201a end + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -75,11 +74,20 @@ chip northbridge/intel/i945 register "p_cnt_throttling_supported" = "1" device pci 1b.0 on # Audio Controller + ioapic_irq 2 INTA 0x16 subsystemid 0x8384 0x7680 end - device pci 1c.0 on end # Ethernet + device pci 1c.0 on + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 end # Ethernet device pci 1c.1 on end # Atheros WLAN - device pci 1d.0 on # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 # USB UHCI subsystemid 0x8086 0x7270 end device pci 1d.1 on # USB UHCI @@ -94,7 +102,10 @@ chip northbridge/intel/i945 device pci 1d.7 on # USB2 EHCI subsystemid 0x8086 0x7270 end - device pci 1f.0 on # PCI-LPC bridge + device pci 1f.0 on + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 # PCI-LPC bridge subsystemid 0x8086 0x7270 end device pci 1f.1 on # IDE diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c deleted file mode 100644 index cc97e52..0000000 --- a/src/mainboard/apple/macbook21/mptable.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x16); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x11); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x15); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x12); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2) , 0x02, 0x13); /* Firewire 3:03.0 */ - - mptable_lintsrc(mc, isa_bus); - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 443fdc5..3bbb07a 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -197,25 +197,6 @@ static void rcba_config(void) /* V1CAP Virtual Channel 1 Resource Capability */ RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - RCBA32(0x3108) = 0x10004321; - - /* PCIe Interrupts */ - RCBA32(0x310c) = 0x00214321; - /* HD Audio Interrupt */ - RCBA32(0x3110) = 0x00000001; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0232; - RCBA16(0x3142) = 0x3246; - RCBA16(0x3144) = 0x0235; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x3216; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl deleted file mode 100644 index 7cd7401..0000000 --- a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Network - Package() { 0x0007ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Network 0:7.0 - Package() { 0x0007ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index ddcd749..919e9e3 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -31,19 +31,19 @@ chip northbridge/intel/i945 device pci 00.0 on end # host bridge # autodetect: #device pci 01.0 off end # i945 PCIe root port - #device pci 02.0 on end # vga controller + device pci 02.0 on + ioapic_irq 2 INTA 0x10 + end # vga controller #device pci 02.1 on end # display controller + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0a" - register "pirqb_routing" = "0x0a" - register "pirqc_routing" = "0x0a" - register "pirqd_routing" = "0x0a" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x0a" - register "pirqh_routing" = "0x0a" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -64,26 +64,43 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe port 1 + device pci 1b.0 on # High Definition Audio + ioapic_irq 2 INTA 0x16 + end + + device pci 1c.0 on # PCIe port 1 + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 + end device pci 1c.1 on end # PCIe port 2 device pci 1c.2 on end # PCIe port 3 device pci 1c.3 on end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on + ioapic_irq 2 INTA 0x16 + ioapic_irq 2 INTB 0x14 chip southbridge/ti/pcixx12 end end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + device pci 1f.0 on + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 # LPC bridge chip superio/smsc/fdc37n972 device pnp 2e.0 off # Floppy end diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c deleted file mode 100644 index 9b59bb4..0000000 --- a/src/mainboard/getac/p470/mptable.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - /* Builtin devices on Bus 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); - - /* Firewire 4:0.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); - - // riser slot top 5:8.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); - // riser slot middle 5:9.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); - // riser slot bottom 5:a.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); - - /* Onboard Ethernet */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, isa_bus); - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index b57e6b7..32323bc 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -176,21 +176,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042220; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0232; - RCBA16(0x3142) = 0x3246; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x3216; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl b/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl deleted file mode 100644 index 142cb80..0000000 --- a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - //Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 17 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19}, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index a26d7c2..ccf6405 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -8,19 +8,19 @@ chip northbridge/intel/i945 device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller + device pci 02.0 on + ioapic_irq 2 INTA 0x10 + end # vga controller device pci 02.1 on end # display controller + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -35,22 +35,37 @@ chip northbridge/intel/i945 register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - #device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe + device pci 1b.0 on + ioapic_irq 2 INTA 0x16 + end # High Definition Audio + device pci 1c.0 on + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 end # PCIe device pci 1c.1 on end # PCIe device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1e.0 on + ioapic_irq 2 INTA 0x16 + ioapic_irq 2 INTB 0x14 end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + device pci 1f.0 on + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 # LPC bridge chip superio/winbond/w83627ehg device pnp 4e.0 off end # Floppy device pnp 4e.1 off end # Parport diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c deleted file mode 100644 index 1baf728..0000000 --- a/src/mainboard/ibase/mb899/mptable.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct device *riser = NULL, *firewire = NULL; - int firewire_bus = 0, riser_bus = 0, isa_bus; - int ioapic_id; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - firewire = dev_find_device(0x104c, 0x8023, 0); - if (firewire) { - firewire_bus = firewire->bus->secondary; - printk(BIOS_SPEW, "Firewire device is on bus %x\n", - firewire_bus); - } - - // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the - // highest bus number on the pci bus. - riser = dev_find_device(0x3388, 0x0021, 0); - if (!riser) - riser = dev_find_device(0x3388, 0x0022, 0); - if (riser) { - riser_bus = riser->link_list->secondary; - printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus); - } - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - ioapic_id = 2; - smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf); - - /* Builtin devices on Bus 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11); - - /* Internal PCI bus (Firewire, PCI slot) */ - if (firewire) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14); - } - - if (riser) { - /* Old riser card */ - // riser slot top 5:8.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); - // riser slot middle 5:9.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); - // riser slot bottom 5:a.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16); - - /* New Riser Card */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16); - } - - /* PCIe slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11); - - /* Onboard Ethernet */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, isa_bus); - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 1); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index ece65d8..6f3e943 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -148,21 +148,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x0146; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x0146; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; } diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl deleted file mode 100644 index aa85527..0000000 --- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 2a3172b..9f9afff 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -29,19 +29,18 @@ chip northbridge/intel/i945 subsystemid 0x8086 0x464c inherit device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller + device pci 02.0 on + ioapic_irq 2 INTA 0x10 end # vga controller device pci 02.1 on end # display controller + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -56,22 +55,36 @@ chip northbridge/intel/i945 register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe + device pci 1b.0 on + ioapic_irq 2 INTA 0x16 end # High Definition Audio + device pci 1c.0 on + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 end # PCIe device pci 1c.1 on end # PCIe device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1e.0 on + ioapic_irq 2 INTA 0x16 + ioapic_irq 2 INTB 0x14 end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + device pci 1f.0 on + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 # LPC bridge chip superio/smsc/lpc47m15x device pnp 2e.0 off # Floppy end diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c deleted file mode 100644 index b0360bf..0000000 --- a/src/mainboard/intel/d945gclf/mptable.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - /* Builtin devices on Bus 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); - - /* Firewire 4:0.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); - - /* Old riser card */ - // riser slot top 5:8.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); - // riser slot middle 5:9.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); - // riser slot bottom 5:a.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); - - /* New Riser Card */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16); - - /* Onboard Ethernet */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, isa_bus); - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 4194a80..f8fc155 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -74,21 +74,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x0146; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x0146; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Disable unused devices */ //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA; // RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl deleted file mode 100644 index cd1fed5..0000000 --- a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 17 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19}, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 6a5b221..1fdd4e5 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -9,19 +9,19 @@ chip northbridge/intel/i945 device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller + device pci 02.0 on # vga controller + ioapic_irq 2 INTA 0x10 + end device pci 02.1 on end # display controller + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -35,22 +35,37 @@ chip northbridge/intel/i945 register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe + device pci 1b.0 on + ioapic_irq 2 INTA 0x16 + end # High Definition Audio + device pci 1c.0 on + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 end # PCIe device pci 1c.1 on end # PCIe device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1e.0 on + ioapic_irq 2 INTA 0x16 + ioapic_irq 2 INTB 0x14 end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 chip superio/winbond/w83627thg device pnp 2e.0 off # Floppy end diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c deleted file mode 100644 index 03f7370..0000000 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct device *riser = NULL, *firewire = NULL; - int firewire_bus = 0, riser_bus = 0, isa_bus; - int ioapic_id; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - firewire = dev_find_device(0x104c, 0x8023, 0); - if (firewire) { - firewire_bus = firewire->bus->secondary; - } - - // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the - // highest bus number on the pci bus. - riser = dev_find_device(0x3388, 0x0021, 0); - if (!riser) - riser = dev_find_device(0x3388, 0x0022, 0); - if (riser) { - riser_bus = riser->link_list->secondary; - } - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - ioapic_id = 2; - smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); - - /* Builtin devices on Bus 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11); - - /* Internal PCI bus (Firewire, PCI slot) */ - if (firewire) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14); - } - - if (riser) { - /* Old riser card */ - // riser slot top 5:8.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); - // riser slot middle 5:9.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); - // riser slot bottom 5:a.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16); - - /* New Riser Card */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16); - } - - /* PCIe slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11); - - /* Onboard Ethernet */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, isa_bus); - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 1); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 652d8cb..d25d0bc 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -207,21 +207,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x3241; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3210; - RCBA16(0x3148) = 0x3210; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Now, this is a bit ugly. As per PCI specification, function 0 of a * device always has to be implemented. So disabling ethernet port 1 * would essentially disable all three ethernet ports of the mainboard. diff --git a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl deleted file mode 100644 index e834ae1..0000000 --- a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x10 } // SATA - }) - } Else { - Return (Package() { - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA - }) - } -} diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 643cc7c..1d5f549 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -38,23 +38,22 @@ chip northbridge/intel/i945 end end - device pci 02.0 on # GMA Graphics controller + device pci 02.0 on + ioapic_irq 2 INTA 0x10 # GMA Graphics controller subsystemid 0x17aa 0x201a end device pci 02.1 on # display controller subsystemid 0x17aa 0x201a end + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -74,14 +73,23 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" - device pci 1b.0 on # Audio Controller + device pci 1b.0 on + ioapic_irq 2 INTA 0x16 # Audio Controller subsystemid 0x17aa 0x2010 end - device pci 1c.0 on # Ethernet + device pci 1c.0 on + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 # Ethernet subsystemid 0x17aa 0x2001 end device pci 1c.1 on end # WLAN - device pci 1d.0 on # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 # USB UHCI subsystemid 0x17aa 0x200a end device pci 1d.1 on # USB UHCI @@ -96,7 +104,9 @@ chip northbridge/intel/i945 device pci 1d.7 on # USB2 EHCI subsystemid 0x17aa 0x200b end - device pci 1e.0 on # PCI Bridge + device pci 1e.0 on + ioapic_irq 2 INTA 0x16 + ioapic_irq 2 INTB 0x14 # PCI Bridge chip southbridge/ti/pci1x2x device pci 00.0 on subsystemid 0x17aa 0x2012 @@ -106,7 +116,10 @@ chip northbridge/intel/i945 end end - device pci 1f.0 on # PCI-LPC bridge + device pci 1f.0 on + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 # PCI-LPC bridge subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c deleted file mode 100644 index 744ef30..0000000 --- a/src/mainboard/lenovo/t60/mptable.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ - - mptable_lintsrc(mc, isa_bus); - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 571a21c..8baeea6 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -118,25 +118,6 @@ static void rcba_config(void) RCBA32(0x0014) = 0x80000001; RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00001230; - RCBA32(0x3108) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(0x310c) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(0x3110) = 0x00000002; - - /* dev irq route register */ - RCBA16(0x3140) = 0x1007; - RCBA16(0x3142) = 0x0076; - RCBA16(0x3144) = 0x3210; - RCBA16(0x3146) = 0x7654; - RCBA16(0x3148) = 0x0010; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl deleted file mode 100644 index e834ae1..0000000 --- a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x10 } // SATA - }) - } Else { - Return (Package() { - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA - }) - } -} diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 91c9d73..5cf6ccf 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -37,22 +37,21 @@ chip northbridge/intel/i945 device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 end - device pci 02.0 on # VGA controller + device pci 02.0 on + ioapic_irq 2 INTA 0x10 # VGA controller subsystemid 0x17aa 0x201a end device pci 02.1 on # display controller subsystemid 0x17aa 0x201a end + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -74,11 +73,20 @@ chip northbridge/intel/i945 register "p_cnt_throttling_supported" = "1" device pci 1b.0 on # Audio Controller + ioapic_irq 2 INTA 0x16 subsystemid 0x17aa 0x2010 end - device pci 1c.0 on end # Ethernet + device pci 1c.0 on + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 end # Ethernet device pci 1c.1 on end # Atheros WLAN - device pci 1d.0 on # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 # USB UHCI subsystemid 0x17aa 0x200a end device pci 1d.1 on # USB UHCI @@ -93,7 +101,10 @@ chip northbridge/intel/i945 device pci 1d.7 on # USB2 EHCI subsystemid 0x17aa 0x200b end - device pci 1f.0 on # PCI-LPC bridge + device pci 1f.0 on + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 # PCI-LPC bridge subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c deleted file mode 100644 index 8ade71b..0000000 --- a/src/mainboard/lenovo/x60/mptable.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ - - mptable_lintsrc(mc, isa_bus); - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index af9b1be..fbfbd7c 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -125,25 +125,6 @@ static void rcba_config(void) RCBA32(0x0014) = 0x80000001; RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00001230; - RCBA32(0x3108) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(0x310c) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(0x3110) = 0x00000002; - - /* dev irq route register */ - RCBA16(0x3140) = 0x1007; - RCBA16(0x3142) = 0x0076; - RCBA16(0x3144) = 0x3210; - RCBA16(0x3146) = 0x7654; - RCBA16(0x3148) = 0x0010; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; RCBA32(0x3418) |= (1 << 0); // Required. diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl deleted file mode 100644 index 118319c..0000000 --- a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 1, 0, 20 }, - Package() { 0x001fffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 3fe8b2a..8e4a665 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -32,19 +32,18 @@ chip northbridge/intel/i945 device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller + device pci 02.0 on + ioapic_irq 2 INTA 0x10 end # vga controller device pci 02.1 on end # display controller + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "0" + register "base" = "0xfec00000" + device ioapic 2 on end + end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -63,19 +62,30 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe + device pci 1b.0 on + ioapic_irq 2 INTA 0x16 end # High Definition Audio + device pci 1c.0 on + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 end # PCIe device pci 1c.1 on end # PCIe device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI + device pci 1d.0 on + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on + ioapic_irq 2 INTA 0x16 + ioapic_irq 2 INTB 0x14 chip southbridge/ti/pci7420 register "smartcard_enabled" = "0x0" device pci 3.0 on end @@ -86,7 +96,10 @@ chip northbridge/intel/i945 end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + device pci 1f.0 on + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 # LPC bridge chip superio/smsc/lpc47n227 device pnp 2e.1 on # Parallel port io 0x60 = 0x378 diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c deleted file mode 100644 index 9b59bb4..0000000 --- a/src/mainboard/roda/rk886ex/mptable.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - /* Builtin devices on Bus 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); - - /* Firewire 4:0.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); - - // riser slot top 5:8.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); - // riser slot middle 5:9.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); - // riser slot bottom 5:a.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); - - /* Onboard Ethernet */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, isa_bus); - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e8ada36..c4bdcf4 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -154,21 +154,6 @@ static void rcba_config(void) //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042220; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0232; - RCBA16(0x3142) = 0x3246; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3201; - RCBA16(0x3148) = 0x3216; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index df81689..a1204bc 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -234,6 +234,3 @@ Method (_CRS, 0, Serialized) Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/i945_pci_irqs.asl" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b12ad3a..08977f2 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -870,6 +870,27 @@ static void ich7_setup_pci_express(void) pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } +static void ich7_setup_interrupts(void) +{ + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042220; + RCBA32(0x3108) = 0x10004321; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0232; + RCBA16(0x3142) = 0x3246; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x3216; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; +} + void i945_early_initialization(void) { /* Print some chipset specific information */ @@ -922,6 +943,8 @@ static void i945_prepare_resume(int s3resume) void i945_late_initialization(int s3resume) { + ich7_setup_interrupts(); + i945_setup_egress_port(); ich7_setup_root_complex_topology(); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index fe59ebe..a398453 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -355,6 +355,7 @@ void i945_late_initialization(int s3resume); /* provided by mainboard code */ void setup_ich7_gpios(void); +void southbridge_setup_interrupts(void); /* debugging functions */ void print_pci_devices(void); diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 665a80a..2df94dd 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -190,3 +190,5 @@ Scope(\) // SMBus #include "smbus.asl" + +#include "irq.asl" diff --git a/src/southbridge/intel/i82801gx/acpi/irq.asl b/src/southbridge/intel/i82801gx/acpi/irq.asl new file mode 100644 index 0000000..1257371 --- /dev/null +++ b/src/southbridge/intel/i82801gx/acpi/irq.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Network + Package() { 0x0007ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 16 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + // AC97 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 22 }, + Package() { 0x001effff, 1, 0, 20 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Network 0:7.0 + Package() { 0x0007ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + } +} diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 2bb81d6..589c082 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -21,18 +21,6 @@ #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H struct southbridge_intel_i82801gx_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; /** * GPI Routing configuration diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6b9d11e..4e4c6ba 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -93,42 +93,37 @@ static void i82801gx_enable_serial_irqs(struct device *dev) static void i82801gx_pirq_init(device_t dev) { device_t irq_dev; - /* Get the chip configuration */ - config_t *config = dev->chip_info; - - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + /* Interrupt 11 is not used by legacy devices and so can always be used for + PCI interrupts. Full legacy IRQ routing is complicated and hard to + get right. Fortunately all modern OS use MSI and so it's not that big of + an issue anyway. Still we have to provide a reasonable default. Using + interrupt 11 for it everywhere is a working default. ACPI-aware OS can + move it to any interrupt and others will just leave them at default. + */ + const u8 pirq_routing = 11; - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq_routing); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing); - /* Eric Biederman once said we should let the OS do this. - * I am not so sure anymore he was right. - */ + pci_write_config8(dev, PIRQE_ROUT, pirq_routing); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing); for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; - } - - if (!int_line) + if (int_pin == 0) continue; - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing); } }

1 0

Patch set updated for coreboot: fedd315 igd.asl rewrite
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7472 -gerrit commit fedd315f4fc903cfbebe278da4d1017e294c29ad Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Oct 31 09:16:31 2014 +0100 igd.asl rewrite Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/Kconfig | 4 + src/drivers/intel/gma/Makefile.inc | 1 + src/drivers/intel/gma/acpi.c | 135 +++++++ src/drivers/intel/gma/i915.h | 7 + src/drivers/intel/gma/igd.asl | 113 ++++++ src/mainboard/apple/macbook21/acpi/video.asl | 51 --- src/mainboard/apple/macbook21/acpi_tables.c | 7 - src/mainboard/apple/macbook21/cmos.default | 1 - src/mainboard/apple/macbook21/cmos.layout | 1 - src/mainboard/apple/macbook21/devicetree.cb | 5 +- src/mainboard/getac/p470/acpi/ec.asl | 2 +- src/mainboard/getac/p470/acpi/video.asl | 44 --- src/mainboard/getac/p470/acpi_tables.c | 8 - src/mainboard/getac/p470/devicetree.cb | 3 + src/mainboard/google/bolt/acpi_tables.c | 7 - src/mainboard/google/bolt/devicetree.cb | 3 + src/mainboard/google/butterfly/acpi_tables.c | 7 - src/mainboard/google/butterfly/devicetree.cb | 3 + src/mainboard/google/falco/acpi_tables.c | 7 - src/mainboard/google/falco/devicetree.cb | 3 + src/mainboard/google/link/acpi_tables.c | 8 - src/mainboard/google/link/devicetree.cb | 3 + src/mainboard/google/panther/acpi_tables.c | 7 - src/mainboard/google/panther/devicetree.cb | 3 + src/mainboard/google/parrot/acpi_tables.c | 7 - src/mainboard/google/parrot/devicetree.cb | 3 + src/mainboard/google/peppy/acpi_tables.c | 7 - src/mainboard/google/peppy/devicetree.cb | 3 + src/mainboard/google/samus/acpi_tables.c | 7 - src/mainboard/google/samus/devicetree.cb | 3 + src/mainboard/google/slippy/acpi_tables.c | 7 - src/mainboard/google/slippy/devicetree.cb | 3 + src/mainboard/google/stout/acpi_tables.c | 7 - src/mainboard/google/stout/devicetree.cb | 3 + src/mainboard/ibase/mb899/acpi/video.asl | 42 -- src/mainboard/ibase/mb899/acpi_tables.c | 7 - src/mainboard/ibase/mb899/devicetree.cb | 4 + src/mainboard/intel/baskingridge/acpi_tables.c | 7 - src/mainboard/intel/baskingridge/devicetree.cb | 3 + src/mainboard/intel/cougar_canyon2/acpi_tables.c | 9 - src/mainboard/intel/cougar_canyon2/devicetree.cb | 3 + src/mainboard/intel/d945gclf/acpi/video.asl | 42 -- src/mainboard/intel/emeraldlake2/acpi_tables.c | 7 - src/mainboard/intel/emeraldlake2/devicetree.cb | 3 + src/mainboard/intel/wtm2/acpi_tables.c | 7 - src/mainboard/intel/wtm2/devicetree.cb | 3 + src/mainboard/iwave/iWRainbowG6/acpi/video.asl | 44 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 8 - src/mainboard/iwave/iWRainbowG6/devicetree.cb | 3 + src/mainboard/kontron/986lcd-m/acpi/video.asl | 42 -- src/mainboard/kontron/986lcd-m/acpi_tables.c | 7 - src/mainboard/kontron/986lcd-m/devicetree.cb | 3 + src/mainboard/kontron/ktqm77/acpi_tables.c | 8 - src/mainboard/kontron/ktqm77/devicetree.cb | 3 + src/mainboard/lenovo/t520/acpi_tables.c | 7 - src/mainboard/lenovo/t520/devicetree.cb | 3 + src/mainboard/lenovo/t520/dsdt.asl | 5 +- src/mainboard/lenovo/t530/acpi_tables.c | 7 - src/mainboard/lenovo/t530/devicetree.cb | 3 + src/mainboard/lenovo/t530/dsdt.asl | 5 +- src/mainboard/lenovo/t60/acpi/video.asl | 24 +- src/mainboard/lenovo/t60/acpi_tables.c | 7 - src/mainboard/lenovo/t60/devicetree.cb | 3 + src/mainboard/lenovo/t60/dsdt.asl | 10 +- src/mainboard/lenovo/x200/acpi_tables.c | 7 - src/mainboard/lenovo/x200/devicetree.cb | 3 + src/mainboard/lenovo/x200/dsdt.asl | 4 +- src/mainboard/lenovo/x201/acpi_tables.c | 7 - src/mainboard/lenovo/x201/devicetree.cb | 3 + src/mainboard/lenovo/x201/dsdt.asl | 5 +- src/mainboard/lenovo/x220/acpi_tables.c | 6 - src/mainboard/lenovo/x220/devicetree.cb | 3 + src/mainboard/lenovo/x220/dsdt.asl | 5 +- src/mainboard/lenovo/x230/acpi_tables.c | 6 - src/mainboard/lenovo/x230/devicetree.cb | 3 + src/mainboard/lenovo/x230/dsdt.asl | 5 +- src/mainboard/lenovo/x60/acpi/video.asl | 55 --- src/mainboard/lenovo/x60/acpi_tables.c | 7 - src/mainboard/lenovo/x60/devicetree.cb | 3 + src/mainboard/lenovo/x60/dsdt.asl | 6 +- src/mainboard/packardbell/ms2290/acpi/ec.asl | 4 +- src/mainboard/packardbell/ms2290/acpi_tables.c | 7 - src/mainboard/packardbell/ms2290/devicetree.cb | 3 + src/mainboard/packardbell/ms2290/dsdt.asl | 2 - src/mainboard/roda/rk886ex/acpi/ec.asl | 2 +- src/mainboard/roda/rk886ex/acpi/video.asl | 44 --- src/mainboard/roda/rk886ex/acpi_tables.c | 7 - src/mainboard/roda/rk886ex/devicetree.cb | 3 + src/mainboard/roda/rk9/acpi_tables.c | 7 - src/mainboard/roda/rk9/devicetree.cb | 3 + src/mainboard/samsung/lumpy/acpi_tables.c | 7 - src/mainboard/samsung/lumpy/devicetree.cb | 3 + src/mainboard/samsung/stumpy/acpi_tables.c | 7 - src/mainboard/samsung/stumpy/devicetree.cb | 3 + src/northbridge/intel/fsp_sandybridge/Kconfig | 2 + src/northbridge/intel/fsp_sandybridge/acpi/igd.asl | 326 ++-------------- src/northbridge/intel/fsp_sandybridge/chip.h | 4 + src/northbridge/intel/fsp_sandybridge/gma.c | 22 ++ src/northbridge/intel/gm45/Kconfig | 1 + src/northbridge/intel/gm45/acpi/igd.asl | 423 ++------------------ src/northbridge/intel/gm45/gma.c | 22 ++ src/northbridge/intel/haswell/Kconfig | 1 + src/northbridge/intel/haswell/acpi/igd.asl | 326 ++-------------- src/northbridge/intel/haswell/chip.h | 4 + src/northbridge/intel/haswell/gma.c | 22 ++ src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/acpi/i945.asl | 6 - src/northbridge/intel/i945/acpi/igd.asl | 329 ++-------------- src/northbridge/intel/i945/chip.h | 3 + src/northbridge/intel/i945/gma.c | 22 ++ src/northbridge/intel/nehalem/Kconfig | 1 + src/northbridge/intel/nehalem/acpi/igd.asl | 431 ++------------------- src/northbridge/intel/nehalem/gma.c | 22 ++ src/northbridge/intel/sandybridge/Kconfig | 4 + src/northbridge/intel/sandybridge/acpi/igd.asl | 411 ++------------------ src/northbridge/intel/sandybridge/gma.c | 22 ++ src/northbridge/intel/sch/Kconfig | 1 + src/northbridge/intel/sch/acpi/igd.asl | 325 ++-------------- src/northbridge/intel/sch/acpi/sch.asl | 6 - src/northbridge/intel/sch/chip.h | 30 ++ src/northbridge/intel/sch/gma.c | 24 ++ src/southbridge/intel/bd82x6x/lpc.c | 4 + src/southbridge/intel/fsp_bd82x6x/lpc.c | 6 + src/southbridge/intel/i82801gx/lpc.c | 7 + src/southbridge/intel/i82801ix/lpc.c | 6 + src/southbridge/intel/ibexpeak/lpc.c | 5 + src/southbridge/intel/lynxpoint/lpc.c | 6 + src/southbridge/intel/sch/lpc.c | 6 + 128 files changed, 904 insertions(+), 2969 deletions(-) diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 6657224..112f262 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -36,3 +36,7 @@ config INTEL_EDID config INTEL_INT15 bool default n + +config INTEL_GMA_ACPI + bool + default n diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index d963df9..039d1d4 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -23,3 +23,4 @@ ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) ramstage-$(CONFIG_INTEL_INT15) += int15.c endif +ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c \ No newline at end of file diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c new file mode 100644 index 0000000..c3a9b8a --- /dev/null +++ b/src/drivers/intel/gma/acpi.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2014 Vladimir Serbinenko + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <string.h> +#include "i915.h" + +void +drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf) +{ + size_t i; + const char *names[] = { "UNK", "VGA", "TV", "DVI", "LCD" }; + int counters[ARRAY_SIZE(names)]; + + memset(counters, 0, sizeof(counters)); + + acpigen_write_scope("\\_SB.PCI0.GFX0"); + + /* + Method (_DOD, 0) + { + Return (Package() { + 0x5a5a5a5a, + 0x5a5a5a5a, + 0x5a5a5a5a + }) + } + */ + acpigen_write_method("_DOD", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_write_package(conf->ndid); + + for (i = 0; i < conf->ndid; i++) { + acpigen_write_dword (conf->did[i] | 0x80010000); + } + acpigen_pop_len(); /* End Package. */ + acpigen_pop_len(); /* End Method. */ + + for (i = 0; i < conf->ndid; i++) { + char name[10]; + char *ptr; + int kind; + kind = (conf->did[i] >> 8) & 0xf; + if (kind >= ARRAY_SIZE(names)) { + kind = 0; + } + strcpy(name, names[kind]); + for (ptr = name; *ptr; ptr++); + *ptr++ = counters[kind] + '0'; + *ptr++ = '\0'; + counters[kind]++; + acpigen_write_device(name); + /* Name (_ADR, 0x0410) */ + acpigen_write_name_dword("_ADR", conf->did[i] & 0xffff); + + /* ACPI brightness for LCD. */ + if (kind == 4) { + /* + Method (_BCL, 0, NotSerialized) + { + Return (^^XBCL()) + } + */ + acpigen_write_method("_BCL", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XBCL"); + acpigen_pop_len(); + + /* + Method (_BCM, 1, NotSerialized) + { + ^^XBCM(Arg0) + } + */ + acpigen_write_method("_BCM", 1); + acpigen_emit_namestring("^^XBCM"); + acpigen_emit_byte(0x68); /* Arg0Op. */ + acpigen_pop_len(); + + /* + Method (_BQC, 0, NotSerialized) + { + Return (^^XBQC()) + } + */ + acpigen_write_method("_BQC", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XBQC"); + acpigen_pop_len(); + } + + /* + Method(_DCS, 0) + { + Return (^^XDCS(<device number>)) + } + */ + acpigen_write_method("_DCS", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XDCS"); + acpigen_write_byte(i); + acpigen_pop_len(); + + /* + Method(_DGS, 0) + { + Return (^^XDGS(<device number>)) + } + */ + acpigen_write_method("_DGS", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XDGS"); + acpigen_write_byte(i); + acpigen_pop_len(); + + /* + Method(_DSS, 1) + { + ^^XDSS(0x5a, Arg0) + } + */ + acpigen_write_method("_DSS", 0); + acpigen_emit_namestring("^^XDSS"); + acpigen_write_byte(i); + acpigen_emit_byte(0x68); /* Arg0Op. */ + acpigen_pop_len(); + + acpigen_pop_len(); + } + + acpigen_pop_len(); +} diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 0d5b8af..c930a81 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -291,8 +291,15 @@ struct i915_gpu_controller_info int lvds_dual_channel; int link_frequency_270_mhz; int lvds_num_lanes; + int ndid; + u32 did[5]; }; +void +drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void); + int i915lightup(unsigned int physbase, unsigned int mmio, unsigned int gfx, unsigned int init_fb); int panel_lightup(struct intel_dp *dp, unsigned int init_fb); diff --git a/src/drivers/intel/gma/igd.asl b/src/drivers/intel/gma/igd.asl new file mode 100644 index 0000000..31e8fec --- /dev/null +++ b/src/drivers/intel/gma/igd.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + External(LCD0, DeviceObj) + + Name (BRCT, 0) + + Method(BRID, 1, NotSerialized) + { + Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) + If (LEqual (Local0, Ones)) + { + Return (Subtract(SizeOf(BRIG), One)) + } + Return (Local0) + } + + Method (XBCL, 0, NotSerialized) + { + Store (1, BRCT) + Return (BRIG) + } + + /* Display Output Switching */ + Method (_DOS, 1) + { + /* Windows 2000 and Windows XP call _DOS to enable/disable + * Display Output Switching during init and while a switch + * is already active + */ + Store (And(Arg0, 7), DSEN) + } + + /* Using Notify is the right way. But Windows doesn't handle + it well. So use both method in a way to avoid double action. + */ + Method (DECB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x87) + } Else { + Store (BRID (XBQC ()), Local0) + If (LNotEqual (Local0, 2)) + { + Decrement (Local0) + } + XBCM (DerefOf (Index (BRIG, Local0))) + } + } + + Method (INCB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x86) + } Else { + Store (BRID (XBQC ()), Local0) + If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One))) + { + Increment (Local0) + } + XBCM (DerefOf (Index (BRIG, Local0))) + } + } + + /* Device Current Status */ + Method(XDCS, 1) + { + TRAP(1) + If (And(CSTE, ShiftLeft (1, Arg0))) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(XDGS, 1) + { + If (And(NSTE, ShiftLeft (1, Arg0))) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(XDSS, 2) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } diff --git a/src/mainboard/apple/macbook21/acpi/video.asl b/src/mainboard/apple/macbook21/acpi/video.asl deleted file mode 100644 index c2f9dfb..0000000 --- a/src/mainboard/apple/macbook21/acpi/video.asl +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Device (DSPC) -{ - Name (_ADR, 0x00020001) - OperationRegion (DSPC, PCI_Config, 0x00, 0x100) - Field (DSPC, ByteAcc, NoLock, Preserve) - { - Offset (0xf4), - BRTC, 8 - } - - Method(BRTD, 0, NotSerialized) - { - Store(BRTC, Local0) - if (LGreater (Local0, 15)) - { - Subtract(Local0, 16, Local0) - Store(Local0, BRTC) - } - } - - Method(BRTU, 0, NotSerialized) - { - Store (BRTC, Local0) - if (LLess(Local0, 0xff)) - { - Add (Local0, 16, Local0) - Store(Local0, BRTC) - } - } -} diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index 48c6f89..f26ab7d 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -37,11 +37,4 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 0185e94..e0b992c 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -9,7 +9,6 @@ boot_default=0x40 cmos_defaults_loaded=Yes lpt=Enable volume=0x3 -tft_brightness=0xff first_battery=Primary bluetooth=Enable wlan=Enable diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 469371e..521a1e6 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -108,7 +108,6 @@ entries 1052 4 r 0 C1DRT1 1064 8 h 0 volume -1072 8 h 0 tft_brightness 1080 1 e 9 first_battery 1081 1 e 1 bluetooth 1082 1 e 1 wwan diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 822d7a3..dd27cb0 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -21,11 +21,14 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" register "gpu_lvds_is_dual_channel" = "0" - register "gpu_backlight" = "0x1280128" + register "gpu_backlight" = "0x1290128" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 1b1c157..23619bc 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -193,7 +193,7 @@ Device(EC0) { Store(0x3f, HOTK) If(IGDS) { - HKDS(10) + Notify (\_SB.PCI0.GFX0, 0x82) } Else { TRAP(0xE1) } diff --git a/src/mainboard/getac/p470/acpi/video.asl b/src/mainboard/getac/p470/acpi/video.asl deleted file mode 100644 index 3536913..0000000 --- a/src/mainboard/getac/p470/acpi/video.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 3e8abe5..df5e774 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -38,14 +38,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* Enable COM port(s) */ gnvs->cmap = 0x01; gnvs->cmbp = 0x00; - - /* IGD Displays */ - gnvs->ndid = 2; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000410; - gnvs->did[2] = 0x80000320; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } static long acpi_create_ecdt(acpi_ecdt_t * ecdt) diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 919e9e3..3d2b209 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -20,6 +20,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "2" + register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/google/bolt/acpi_tables.c b/src/mainboard/google/bolt/acpi_tables.c index 3b851c4..9b3a23d 100644 --- a/src/mainboard/google/bolt/acpi_tables.c +++ b/src/mainboard/google/bolt/acpi_tables.c @@ -66,13 +66,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb index f514bb4..e5be428 100644 --- a/src/mainboard/google/bolt/devicetree.cb +++ b/src/mainboard/google/bolt/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index cabc052..1c45c22 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -54,13 +54,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // TODO: MLR // The firmware read/write status is a "virtual" switch and diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index ed0d8d1..915b588 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/falco/acpi_tables.c b/src/mainboard/google/falco/acpi_tables.c index 5849087..444d9e9 100644 --- a/src/mainboard/google/falco/acpi_tables.c +++ b/src/mainboard/google/falco/acpi_tables.c @@ -60,13 +60,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index 428a060..eaf2064 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index d1d4fcb..547717a 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -64,14 +64,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 1; - gnvs->did[0] = 0x80000000; - gnvs->did[1] = 0x80000000; - gnvs->did[2] = 0x00000000; - gnvs->did[3] = 0x00000000; - gnvs->did[4] = 0x00000000; - #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 5333dfc..382a8c4 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "1" + register "gfx.did" = "{ 0x80000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c index 9340c5a..3954821 100644 --- a/src/mainboard/google/panther/acpi_tables.c +++ b/src/mainboard/google/panther/acpi_tables.c @@ -77,13 +77,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS // SuperIO is always RO diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index d37b622..79da543 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Disable eDP Hotplug register "gpu_dp_d_hotplug" = "0x00" diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 0041c98..3f5b719 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -55,13 +55,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index a4baafd..034309f 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort B Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" diff --git a/src/mainboard/google/peppy/acpi_tables.c b/src/mainboard/google/peppy/acpi_tables.c index 265fe65..369c7fb 100644 --- a/src/mainboard/google/peppy/acpi_tables.c +++ b/src/mainboard/google/peppy/acpi_tables.c @@ -69,13 +69,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 4c0d02d..4718435 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/samus/acpi_tables.c b/src/mainboard/google/samus/acpi_tables.c index 1978494..af05d5c 100644 --- a/src/mainboard/google/samus/acpi_tables.c +++ b/src/mainboard/google/samus/acpi_tables.c @@ -60,13 +60,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 12a21ec..06a7421 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 3b851c4..9b3a23d 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -66,13 +66,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 06ca93c..ecaa43e 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 23c47f9..9e5c6a1 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -58,13 +58,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 4ac89f6..cd33cd7 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/ibase/mb899/acpi/video.asl b/src/mainboard/ibase/mb899/acpi/video.asl deleted file mode 100644 index cca1a3b..0000000 --- a/src/mainboard/ibase/mb899/acpi/video.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index 54ee4f6..b032fe7 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -36,11 +36,4 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index ccf6405..b59a295 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -1,4 +1,8 @@ chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index d5a5f03..d3034a9 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -79,13 +79,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS /* Emerald Lake has no EC (?) */ diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index a173aaa..5576590 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/intel/cougar_canyon2/acpi_tables.c b/src/mainboard/intel/cougar_canyon2/acpi_tables.c index dca35b5..b89c865 100644 --- a/src/mainboard/intel/cougar_canyon2/acpi_tables.c +++ b/src/mainboard/intel/cougar_canyon2/acpi_tables.c @@ -62,16 +62,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - acpi_update_thermal_table(gnvs); - } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index c386853..d7c6aab 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/fsp_sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/intel/d945gclf/acpi/video.asl b/src/mainboard/intel/d945gclf/acpi/video.asl deleted file mode 100644 index 7baf995..0000000 --- a/src/mainboard/intel/d945gclf/acpi/video.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index f17e1f4..2953e2b 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -78,13 +78,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index e5a8ea0..0b3e788 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 20814ab..af02b76 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -76,13 +76,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS /* Emerald Lake has no EC (?) */ diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 2790cb9..52945d1 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/video.asl b/src/mainboard/iwave/iWRainbowG6/acpi/video.asl deleted file mode 100644 index 3536913..0000000 --- a/src/mainboard/iwave/iWRainbowG6/acpi/video.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c index 4dcda79..eb4ab22 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c @@ -40,14 +40,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) /* Enable both COM ports. */ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - - /* IGD Displays. */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb index 84cfc4b..29e9e5e 100644 --- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb +++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sch + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_441 diff --git a/src/mainboard/kontron/986lcd-m/acpi/video.asl b/src/mainboard/kontron/986lcd-m/acpi/video.asl deleted file mode 100644 index cca1a3b..0000000 --- a/src/mainboard/kontron/986lcd-m/acpi/video.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 54ee4f6..b032fe7 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -36,11 +36,4 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 1fdd4e5..d94530d 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index d2d70e9..b434d5f 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -52,14 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 0; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 855fd5c..24306ef 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index 15b9d9a..862a5e5 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -51,13 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index d2a4d6b..e08f213 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index 15b9d9a..862a5e5 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -51,13 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index c44f927..f84b70f 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl index 9a458e9..9dea2b0 100644 --- a/src/mainboard/lenovo/t60/acpi/video.asl +++ b/src/mainboard/lenovo/t60/acpi/video.asl @@ -21,35 +21,17 @@ #include "smi.h" -Device (DSPC) +Scope (\) { - Name (_ADR, 0x00020001) - OperationRegion (DSPC, PCI_Config, 0x00, 0x100) - Field (DSPC, ByteAcc, NoLock, Preserve) - { - Offset (0xf4), - BRTC, 8 - } - Method(BRTD, 0, NotSerialized) { Trap(SMI_BRIGHTNESS_DOWN) - Store(BRTC, Local0) - if (LGreater (Local0, 15)) - { - Subtract(Local0, 16, Local0) - Store(Local0, BRTC) - } + \_SB.PCI0.GFX0.DECB() } Method(BRTU, 0, NotSerialized) { Trap(SMI_BRIGHTNESS_UP) - Store (BRTC, Local0) - if (LLess(Local0, 0xff)) - { - Add (Local0, 16, Local0) - Store(Local0, BRTC) - } + \_SB.PCI0.GFX0.INCB() } } diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 48c6f89..f26ab7d 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -37,11 +37,4 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 1d5f549..76ec6e0 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 7807687..71ba71f 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -20,8 +20,8 @@ */ #define THINKPAD_EC_GPE 28 -#define BRIGHTNESS_UP \DSPC.BRTU -#define BRIGHTNESS_DOWN \DSPC.BRTD +#define BRIGHTNESS_UP \BRTU +#define BRIGHTNESS_DOWN \BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 DefinitionBlock( @@ -46,6 +46,12 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" + Scope (\) + { + // backlight control, display switching, lid + #include "acpi/video.asl" + } + #include <cpu/intel/model_6dx/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 77491dc..ebdfe8f 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -41,13 +41,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 0; /* Will use default of 0x00000400. */ - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index acc6c3a..30a97a7 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/gm45 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.use_spread_spectrum_clock" = "1" register "gfx.lvds_dual_channel" = "0" diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 0409e66..ac40bcc 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -20,8 +20,8 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 85eabc7..bee0e06 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -39,13 +39,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_slit(unsigned long current) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 117c25c..78045a6 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 5265a91..f7ec349c 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 15b9d9a..eadc44b 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -52,12 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 982e30b..fc96c1d 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index 15b9d9a..eadc44b 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -52,12 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 5130410..3624bea 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x60/acpi/video.asl b/src/mainboard/lenovo/x60/acpi/video.asl deleted file mode 100644 index b38d82b..0000000 --- a/src/mainboard/lenovo/x60/acpi/video.asl +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include "smi.h" - -Device (DSPC) -{ - Name (_ADR, 0x00020001) - OperationRegion (DSPC, PCI_Config, 0x00, 0x100) - Field (DSPC, ByteAcc, NoLock, Preserve) - { - Offset (0xf4), - BRTC, 8 - } - - Method(BRTD, 0, NotSerialized) - { - Store(BRTC, Local0) - if (LGreater (Local0, 15)) - { - Subtract(Local0, 16, Local0) - Store(Local0, BRTC) - Trap(SMI_SAVE_CMOS) - } - } - - Method(BRTU, 0, NotSerialized) - { - Store (BRTC, Local0) - if (LLess(Local0, 0xff)) - { - Add (Local0, 16, Local0) - Store(Local0, BRTC) - Trap(SMI_SAVE_CMOS) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 48c6f89..f26ab7d 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -37,11 +37,4 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 5cf6ccf..25073bf 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 7807687..d8990ef 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -19,9 +19,11 @@ * MA 02110-1301 USA */ +#include "smi.h" + #define THINKPAD_EC_GPE 28 -#define BRIGHTNESS_UP \DSPC.BRTU -#define BRIGHTNESS_DOWN \DSPC.BRTD +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 DefinitionBlock( diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl index 3735f20..e53c367 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ec.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl @@ -122,12 +122,12 @@ Device(EC) /* Decrease brightness. */ Method(_Q1D, 0, NotSerialized) { - \_SB.PCI0.GFX0.LCD0.DECB() + \_SB.PCI0.GFX0.DECB() } /* Increase brightness. */ Method(_Q1C, 0, NotSerialized) { - \_SB.PCI0.GFX0.LCD0.INCB() + \_SB.PCI0.GFX0.INCB() } #include "battery.asl" diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index 85eabc7..bee0e06 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -39,13 +39,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_slit(unsigned long current) diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 2f4bce1..ae2c5ed 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gpu_dp_b_hotplug" = "0x04" register "gpu_dp_c_hotplug" = "0x04" diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index f0eb8ec..f9c0112 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -19,8 +19,6 @@ * MA 02110-1301 USA */ -#define HAVE_LCD_SCREEN 1 - DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index d174e98..f3b6021 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -98,8 +98,8 @@ Device(EC0) Method (_Q12, 0) { Store("_Q12: Fn-F9 (Display Switch) pressed", Debug) + Notify (\_SB.PCI0.GFX0, 0x82) // Store(1, TLST) - // HKDS(10) } Method (_Q30, 0) diff --git a/src/mainboard/roda/rk886ex/acpi/video.asl b/src/mainboard/roda/rk886ex/acpi/video.asl deleted file mode 100644 index 3536913..0000000 --- a/src/mainboard/roda/rk886ex/acpi/video.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index 48c6f89..f26ab7d 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -37,11 +37,4 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 8e4a665..1c59b2a 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -20,6 +20,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 77491dc..ebdfe8f 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -41,13 +41,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 0; /* Will use default of 0x00000400. */ - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index deece86..84ba59a 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/gm45 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 device lapic 0 on end diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 6d8517c..d115053 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -80,13 +80,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 9b0fc40..ceac051 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index dc2197a..9dc24cc 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -79,13 +79,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 60b112b..df91a72 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 4eb5b8e..44ec95d 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -22,11 +22,13 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE bool select CPU_INTEL_FSP_MODEL_206AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE bool select CPU_INTEL_FSP_MODEL_306AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl index 9399554..15a7df2 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl @@ -23,301 +23,57 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) + Offset (0x10), + BAR0, 64 } - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 } - - Device(DD03) + Name (BRIG, Package (0x12) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } - - Device(DD05) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } - +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h index 9b5f605..656d0f3 100644 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ b/src/northbridge/intel/fsp_sandybridge/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -38,4 +40,6 @@ struct northbridge_intel_fsp_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index d578d56..64b34b5 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -63,6 +63,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_fsp_sandybridge_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -71,6 +92,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fac7329..6783851 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -32,6 +32,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl index c5b4b6a..1b58383 100644 --- a/src/northbridge/intel/gm45/acpi/igd.asl +++ b/src/northbridge/intel/gm45/acpi/igd.asl @@ -28,9 +28,9 @@ Device (GFX0) { Offset (0x10), BAR0, 64 - } + } - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) { Offset (0x61250), @@ -39,399 +39,40 @@ Device (GFX0) BCLM, 16, } - /* Display Output Switching */ - Method (_DOS, 1) + Name (BRIG, Package (0x12) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many GM45 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD3, 0)) - Store (Or(0x00010000, DID2), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD4, 0)) - Store (Or(0x00010000, DID2), Index(DOD4, 1)) - Store (Or(0x00010000, DID3), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD5, 0)) - Store (Or(0x00010000, DID2), Index(DOD5, 1)) - Store (Or(0x00010000, DID3), Index(DOD5, 2)) - Store (Or(0x00010000, DID4), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x0610, BCLM) } - Device(DD01) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - -#ifdef DISPLAY_DEVICE_2_IS_LCD_SCREEN - Device (LCD0) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - Name (BRCT, 0) - - Name (BRIG, Package (0x12) - { - 0x61, - 0x61, - 0x2, - 0x4, - 0x5, - 0x7, - 0x9, - 0xb, - 0xd, - 0x11, - 0x14, - 0x17, - 0x1c, - 0x20, - 0x27, - 0x31, - 0x41, - 0x61, - }) - - Method (_BCL, 0, NotSerialized) - { - Store (1, BRCT) - Return (BRIG) - } - - Method (_BCM, 1, NotSerialized) - { - Store (ShiftLeft (Arg0, 4), ^^BCLV) - Store (0x80000000, ^^CR1) - Store (0x0610, ^^BCLM) - } - Method (_BQC, 0, NotSerialized) - { - Store (^^BCLV, Local0) - ShiftRight (Local0, 4, Local0) - Return (Local0) - } - - Method(BRID, 1, NotSerialized) - { - Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) - { - Return (0x11) - } - Return (Local0) - } - - /* Using Notify is the right way. But Windows doesn't handle - it well. So use both method in a way to avoid double action. - */ - Method (DECB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x87) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 2)) - { - Decrement (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - Method (INCB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x86) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 0x11)) - { - Increment (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - } -#else - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } -#endif - - Device(DD03) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD05) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74e16ad..25e31b2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -490,6 +490,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_gm45_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -498,6 +519,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index cac5c46..7e94143 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -27,6 +27,7 @@ config NORTHBRIDGE_INTEL_HASWELL select INTEL_DDI select INTEL_DP select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/haswell/acpi/igd.asl b/src/northbridge/intel/haswell/acpi/igd.asl index 9399554..15a7df2 100644 --- a/src/northbridge/intel/haswell/acpi/igd.asl +++ b/src/northbridge/intel/haswell/acpi/igd.asl @@ -23,301 +23,57 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) + Offset (0x10), + BAR0, 64 } - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 } - - Device(DD03) + Name (BRIG, Package (0x12) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } - - Device(DD05) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } - +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index d60504c..97c4036 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -38,6 +40,8 @@ struct northbridge_intel_haswell_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + struct i915_gpu_controller_info gfx; }; extern struct chip_operations northbridge_intel_haswell_ops; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 325edbd..5f49c00 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -487,6 +487,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_haswell_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -496,6 +517,7 @@ static struct device_operations gma_func0_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, + .acpi_fill_ssdt_generator = gma_ssdt, .scan_bus = 0, .enable = 0, .ops_pci = &gma_pci_ops, diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 086be8a..f3f4dbe 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -31,6 +31,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select LAPIC_MONOTONIC_TIMER select VGA select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 6a34b94..4eac006 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -100,9 +100,3 @@ Device (PDRC) // Integrated graphics 0:2.0 #include "igd.asl" - -Scope (\) -{ - // backlight control, display switching, lid - #include "acpi/video.asl" -} diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 9399554..1dc281f 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -23,301 +23,52 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + Name (BRIG, Package (0x12) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) - { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD03) + 0xf, + 0xf, + 0x0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC) +#ifdef SMI_SAVE_CMOS + Trap(SMI_SAVE_CMOS) +#endif } - - Device(DD04) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (^^DSPC.BRTC, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } +#include <drivers/intel/gma/igd.asl> +} - - Device(DD05) +Device (DSPC) +{ + Name (_ADR, 0x00020001) + OperationRegion (DSPC, PCI_Config, 0x00, 0x100) + Field (DSPC, ByteAcc, NoLock, Preserve) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0xf4), + BRTC, 8 } - -} +} \ No newline at end of file diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 9e25ecc..5706086 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -1,6 +1,9 @@ +#include <drivers/intel/gma/i915.h> + struct northbridge_intel_i945_config { u32 gpu_hotplug; u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; int gpu_lvds_is_dual_channel; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 204ba01..2949fea 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -495,6 +495,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_i945_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -504,6 +525,7 @@ static struct device_operations gma_func0_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, + .acpi_fill_ssdt_generator = gma_ssdt, .scan_bus = 0, .enable = 0, .disable = gma_func0_disable, diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index b49f331..370e7fe 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -27,6 +27,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl index a892ce2..15a7df2 100644 --- a/src/northbridge/intel/nehalem/acpi/igd.asl +++ b/src/northbridge/intel/nehalem/acpi/igd.asl @@ -24,407 +24,56 @@ Device (GFX0) Name (_ADR, 0x00020000) OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) - Field (GFXC, DWordAcc, NoLock, Preserve) - { - Offset (0x10), - BAR0, 64 - } - - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) - Field (GFRG, DWordAcc, NoLock, Preserve) - { - Offset (0x48254), - BCLV, 16, - Offset (0xc8250), - CR1, 32, - CR2, 32 - } - - /* Display Output Switching */ - Method (_DOS, 1) - { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) - { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) + Field (GFXC, DWordAcc, NoLock, Preserve) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x10), + BAR0, 64 } - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD03) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 } - - Device(DD04) + Name (BRIG, Package (0x12) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD05) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } -#ifdef HAVE_LCD_SCREEN - Device (LCD0) + Method (XBQC, 0, NotSerialized) { - Name (_ADR, 0x0400) - Name (BRCT, 0) - - Name (BRIG, Package (0x12) - { - 0x61, - 0x61, - 0x2, - 0x4, - 0x5, - 0x7, - 0x9, - 0xb, - 0xd, - 0x11, - 0x14, - 0x17, - 0x1c, - 0x20, - 0x27, - 0x31, - 0x41, - 0x61, - }) - - Method (_BCL, 0, NotSerialized) - { - Store (1, BRCT) - Return (BRIG) - } - - Method (_BCM, 1, NotSerialized) - { - Store (ShiftLeft (Arg0, 4), ^^BCLV) - Store (0x80000000, ^^CR1) - Store (0x061a061a, ^^CR2) - } - Method (_BQC, 0, NotSerialized) - { - Store (^^BCLV, Local0) - ShiftRight (Local0, 4, Local0) - Return (Local0) - } - - Method(BRID, 1, NotSerialized) - { - Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) - { - Return (0x11) - } - Return (Local0) - } - - /* Using Notify is the right way. But Windows doesn't handle - it well. So use both method in a way to avoid double action. - */ - Method (DECB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x87) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 2)) - { - Decrement (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - Method (INCB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x86) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 0x11)) - { - Increment (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } -#endif +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index c3e2a49..184781f 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -1066,6 +1066,27 @@ static void gma_read_resources(struct device *dev) res->size = (resource_t) 0x10000000; } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_nehalem_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -1074,6 +1095,7 @@ static struct device_operations gma_func0_ops = { .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 647b4fb..6e66de5 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE bool @@ -35,6 +36,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_IVYBRIDGE bool @@ -44,6 +46,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE bool @@ -54,6 +57,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl index d40fad5..15a7df2 100644 --- a/src/northbridge/intel/sandybridge/acpi/igd.asl +++ b/src/northbridge/intel/sandybridge/acpi/igd.asl @@ -40,391 +40,40 @@ Device (GFX0) CR2, 32 } - /* Display Output Switching */ - Method (_DOS, 1) + Name (BRIG, Package (0x12) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } - Device(DD01) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD03) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD05) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - -#ifdef HAVE_LCD_SCREEN - Device (LCD0) - { - Name (_ADR, 0x0400) - Name (BRCT, 0) - - Name (BRIG, Package (0x12) - { - 0x61, - 0x61, - 0x2, - 0x4, - 0x5, - 0x7, - 0x9, - 0xb, - 0xd, - 0x11, - 0x14, - 0x17, - 0x1c, - 0x20, - 0x27, - 0x31, - 0x41, - 0x61, - }) - - Method (_BCL, 0, NotSerialized) - { - Store (1, BRCT) - Return (BRIG) - } - - Method (_BCM, 1, NotSerialized) - { - Store (ShiftLeft (Arg0, 4), ^^BCLV) - Store (0x80000000, ^^CR1) - Store (0x061a061a, ^^CR2) - } - Method (_BQC, 0, NotSerialized) - { - Store (^^BCLV, Local0) - ShiftRight (Local0, 4, Local0) - Return (Local0) - } - - Method(BRID, 1, NotSerialized) - { - Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) - { - Return (0x11) - } - Return (Local0) - } - - /* Using Notify is the right way. But Windows doesn't handle - it well. So use both method in a way to avoid double action. - */ - Method (DECB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x87) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 2)) - { - Decrement (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - Method (INCB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x86) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 0x11)) - { - Increment (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } -#endif +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 247c723..117e9df 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -612,6 +612,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_sandybridge_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -620,6 +641,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index b8dad72..ac1f79a 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_SCH bool select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_SCH diff --git a/src/northbridge/intel/sch/acpi/igd.asl b/src/northbridge/intel/sch/acpi/igd.asl index 9399554..1b58383 100644 --- a/src/northbridge/intel/sch/acpi/igd.asl +++ b/src/northbridge/intel/sch/acpi/igd.asl @@ -23,301 +23,56 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) + Offset (0x10), + BAR0, 64 } - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x61250), + CR1, 32, + BCLV, 16, + BCLM, 16, } - - Device(DD03) + Name (BRIG, Package (0x12) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x0610, BCLM) } - - Device(DD05) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } - +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/sch/acpi/sch.asl b/src/northbridge/intel/sch/acpi/sch.asl index 5e0b3f8..d1acc48 100644 --- a/src/northbridge/intel/sch/acpi/sch.asl +++ b/src/northbridge/intel/sch/acpi/sch.asl @@ -80,9 +80,3 @@ Device (PDRC) // Integrated graphics 0:2.0 #include "igd.asl" - -Scope (\) -{ - // backlight control, display switching, lid - #include "acpi/video.asl" -} diff --git a/src/northbridge/intel/sch/chip.h b/src/northbridge/intel/sch/chip.h new file mode 100644 index 0000000..d39931f --- /dev/null +++ b/src/northbridge/intel/sch/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_SCH_CHIP_H +#define NORTHBRIDGE_INTEL_SCH_CHIP_H + +#include <drivers/intel/gma/i915.h> + +struct northbridge_intel_sch_config { + struct i915_gpu_controller_info gfx; +}; + +#endif /* NORTHBRIDGE_INTEL_SCH_CHIP_H */ diff --git a/src/northbridge/intel/sch/gma.c b/src/northbridge/intel/sch/gma.c index 59ff024..3b2bf81 100644 --- a/src/northbridge/intel/sch/gma.c +++ b/src/northbridge/intel/sch/gma.c @@ -21,6 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/i915.h> +#include "chip.h" static void gma_func0_init(struct device *dev) { @@ -44,6 +46,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_sch_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -52,6 +75,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 11b765a..ae10a33 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -678,6 +678,7 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -686,6 +687,9 @@ static void southbridge_inject_dsdt(void) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + #if CONFIG_CHROMEOS chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index f9961f9..d02a800 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -640,11 +640,17 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 22ffd7f..de02686 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -35,6 +35,7 @@ #include <arch/smp/mpspec.h> #include <cbmem.h> #include <string.h> +#include <drivers/intel/gma/i915.h> #include "nvs.h" #define NMI_OFF 0 @@ -641,12 +642,18 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + memset(gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index e12c724..38202bf 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -37,6 +37,7 @@ #include "i82801ix.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> +#include <drivers/intel/gma/i915.h> #define NMI_OFF 0 @@ -545,8 +546,13 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2124711..1210f4f 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -671,9 +671,14 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; /* And tell SMI about it */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 563cb0a..93384d6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -38,6 +38,7 @@ #include "pch.h" #include <arch/acpigen.h> #include <cbmem.h> +#include <drivers/intel/gma/i915.h> #define NMI_OFF 0 @@ -755,6 +756,8 @@ static void southbridge_inject_dsdt(void) } if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + acpi_create_gnvs(gnvs); gnvs->apic = 1; @@ -768,6 +771,9 @@ static void southbridge_inject_dsdt(void) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index dcf9e33..176e562 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -29,6 +29,7 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <string.h> +#include <drivers/intel/gma/i915.h> #include "nvs.h" #include "chip.h" @@ -193,8 +194,13 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL);

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Patch set updated for coreboot: 6d2d681 acer/aoa150: Autogenerate a new port.
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7572 -gerrit commit 6d2d68122e5bf95a64bb50c010442b7605c0b85d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 18 22:23:50 2014 +0200 acer/aoa150: Autogenerate a new port. Just running autoport. Several things need to be fixed, it's done in subsequent commit for now but both should be squashed before merge. Change-Id: I7b9e1ac5ce185d0db2c69edd36429061c4c14020 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/acer/Kconfig | 20 ++++ src/mainboard/acer/aoa150/Kconfig | 54 +++++++++++ src/mainboard/acer/aoa150/Makefile.inc | 2 + src/mainboard/acer/aoa150/acpi/ec.asl | 0 src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl | 74 +++++++++++++++ src/mainboard/acer/aoa150/acpi/platform.asl | 12 +++ src/mainboard/acer/aoa150/acpi/superio.asl | 0 src/mainboard/acer/aoa150/acpi_tables.c | 8 ++ src/mainboard/acer/aoa150/board_info.txt | 1 + src/mainboard/acer/aoa150/cstates.c | 8 ++ src/mainboard/acer/aoa150/devicetree.cb | 103 ++++++++++++++++++++ src/mainboard/acer/aoa150/dsdt.asl | 25 +++++ src/mainboard/acer/aoa150/early_southbridge.c | 116 +++++++++++++++++++++++ src/mainboard/acer/aoa150/hda_verb.c | 47 +++++++++ src/mainboard/acer/aoa150/mainboard.c | 50 ++++++++++ src/mainboard/acer/aoa150/romstage.c | 1 + src/mainboard/acer/aoa150/smihandler.c | 75 +++++++++++++++ 18 files changed, 599 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 29b439c..a29fc19 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -8,6 +8,8 @@ config VENDOR_AAEON bool "Aaeon" config VENDOR_ABIT bool "Abit" +config VENDOR_ACER + bool "Acer" config VENDOR_ADLINK bool "ADLINK" config VENDOR_ADVANSUS @@ -152,6 +154,7 @@ endchoice source "src/mainboard/a-trend/Kconfig" source "src/mainboard/aaeon/Kconfig" source "src/mainboard/abit/Kconfig" +source "src/mainboard/acer/Kconfig" source "src/mainboard/adlink/Kconfig" source "src/mainboard/advansus/Kconfig" source "src/mainboard/advantech/Kconfig" diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..bdaaa97 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,20 @@ +if VENDOR_ACER + +choice + prompt "Mainboard model" + +config BOARD_ACER_AOA150 + bool "Aspire One AOA150" + help + Consult wiki for details. + + +endchoice + +source "src/mainboard/acer/aoa150/Kconfig" + +config MAINBOARD_VENDOR + string + default "Acer" + +endif # VENDOR_APPLE diff --git a/src/mainboard/acer/aoa150/Kconfig b/src/mainboard/acer/aoa150/Kconfig new file mode 100644 index 0000000..99a4bb3 --- /dev/null +++ b/src/mainboard/acer/aoa150/Kconfig @@ -0,0 +1,54 @@ +if BOARD_ACER_AOA150 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select BOARD_ROMSIZE_KB_2048 + select CHANNEL_XOR_RANDOMIZATION + select CPU_INTEL_SOCKET_441 + select EARLY_CBMEM_INIT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select INTEL_EDID + select INTEL_INT15 + select MAINBOARD_DO_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM + select SOUTHBRIDGE_INTEL_I82801GX + select VGA + +config MAINBOARD_DIR + string + default acer/aoa150 + +config MAINBOARD_PART_NUMBER + string + default "AOA150" + +config VGA_BIOS_FILE + string + default "pci8086,27ae.rom" + +config VGA_BIOS_ID + string + default "8086,27ae" + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config MAX_CPUS + int + default 2 +endif diff --git a/src/mainboard/acer/aoa150/Makefile.inc b/src/mainboard/acer/aoa150/Makefile.inc new file mode 100644 index 0000000..2f60428 --- /dev/null +++ b/src/mainboard/acer/aoa150/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += early_southbridge.c +ramstage-y += cstates.c diff --git a/src/mainboard/acer/aoa150/acpi/ec.asl b/src/mainboard/acer/aoa150/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl b/src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..5354901 --- /dev/null +++ b/src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} diff --git a/src/mainboard/acer/aoa150/acpi/platform.asl b/src/mainboard/acer/aoa150/acpi/platform.asl new file mode 100644 index 0000000..62795d1 --- /dev/null +++ b/src/mainboard/acer/aoa150/acpi/platform.asl @@ -0,0 +1,12 @@ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Scope(\_SB) +{ + Method(_INI, 0) + { + \GOS() + } +} diff --git a/src/mainboard/acer/aoa150/acpi/superio.asl b/src/mainboard/acer/aoa150/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/acer/aoa150/acpi_tables.c b/src/mainboard/acer/aoa150/acpi_tables.c new file mode 100644 index 0000000..92ceaed --- /dev/null +++ b/src/mainboard/acer/aoa150/acpi_tables.c @@ -0,0 +1,8 @@ +#include <stdint.h> +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; +} diff --git a/src/mainboard/acer/aoa150/board_info.txt b/src/mainboard/acer/aoa150/board_info.txt new file mode 100644 index 0000000..0aeac00 --- /dev/null +++ b/src/mainboard/acer/aoa150/board_info.txt @@ -0,0 +1 @@ +Category: desktop \ No newline at end of file diff --git a/src/mainboard/acer/aoa150/cstates.c b/src/mainboard/acer/aoa150/cstates.c new file mode 100644 index 0000000..997623a --- /dev/null +++ b/src/mainboard/acer/aoa150/cstates.c @@ -0,0 +1,8 @@ +#include <arch/acpigen.h> +#include <device/device.h> +#include <northbridge/intel/i945/i945.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/acer/aoa150/devicetree.cb b/src/mainboard/acer/aoa150/devicetree.cb new file mode 100644 index 0000000..61fe7f1 --- /dev/null +++ b/src/mainboard/acer/aoa150/devicetree.cb @@ -0,0 +1,103 @@ +chip northbridge/intel/i945 + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + register "gpu_backlight" = "0x1280128" + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_is_dual_channel" = "0" + register "gpu_lvds_use_spread_spectrum_clock" = "1" + device cpu_cluster 0x0 on + chip cpu/intel/socket_441 + device lapic 0x0 on + end + end + end + device domain 0x0 on + chip southbridge/intel/i82801gx # Southbridge, FIXME: set gpiX_routing, gpe0_en and alt_gp_smi_en for EC support + register "c3_latency" = "0x03e9" + register "c4onc3_enable" = "1" + register "docking_supported" = "0" + register "ide_enable_primary" = "0" + register "ide_enable_secondary" = "0" + register "p_cnt_throttling_supported" = "1" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x5" + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1025 0x015b + ioapic_irq 2 INTA 0x16 + end + device pci 1c.0 on # PCIe Port #1 + ioapic_irq 2 INTA 0x11 + ioapic_irq 2 INTB 0x10 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x13 + end + device pci 1c.1 on # PCIe Port #2 + device pci 00.0 on # Unsupported PCI device 10ec:8136 + subsystemid 0x1025 0x015b + end + end + device pci 1c.2 on # PCIe Port #3 + device pci 00.0 on # Unsupported PCI device 168c:001c + subsystemid 0x105b 0xe008 + end + end + device pci 1c.3 on # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB UHCI + subsystemid 0x1025 0x015b + ioapic_irq 2 INTA 0x17 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTC 0x12 + ioapic_irq 2 INTD 0x10 + end + device pci 1d.1 on # USB UHCI + subsystemid 0x1025 0x015b + end + device pci 1d.2 on # USB UHCI + subsystemid 0x1025 0x015b + end + device pci 1d.3 on # USB UHCI + subsystemid 0x1025 0x015b + end + device pci 1d.7 on # USB EHCI + subsystemid 0x1025 0x015b + end + device pci 1e.0 on # PCI bridge + ioapic_irq 2 INTA 0x16 + ioapic_irq 2 INTB 0x14 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1025 0x015b + ioapic_irq 2 INTA 0x12 + ioapic_irq 2 INTB 0x13 + ioapic_irq 2 INTD 0x10 + end + device pci 1f.1 off # IDE Controller + end + device pci 1f.2 on # SATA Controller + subsystemid 0x1025 0x015b + end + device pci 1f.3 on # SMBus + subsystemid 0x1025 0x015b + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1025 0x015b + ioapic_irq 2 INTA 0x10 + end + device pci 02.0 on # VGA VGA controller + subsystemid 0x1025 0x015b + end + device pci 02.1 on # Display controller display controller + subsystemid 0x1025 0x015b + end + end +end diff --git a/src/mainboard/acer/aoa150/dsdt.asl b/src/mainboard/acer/aoa150/dsdt.asl new file mode 100644 index 0000000..dc477d9 --- /dev/null +++ b/src/mainboard/acer/aoa150/dsdt.asl @@ -0,0 +1,25 @@ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } +} diff --git a/src/mainboard/acer/aoa150/early_southbridge.c b/src/mainboard/acer/aoa150/early_southbridge.c new file mode 100644 index 0000000..6eda5b8 --- /dev/null +++ b/src/mainboard/acer/aoa150/early_southbridge.c @@ -0,0 +1,116 @@ +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" + +/* FIXME: hardcoded. */ +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + + outl(0x7f6af7fe, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0x8280ff81, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0x8080ffc1, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); + outl(0x00000780, DEFAULT_GPIOBASE + GPI_INV); + outl(0x000100ce, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x00000038, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0x000000c8, DEFAULT_GPIOBASE + GP_LVL2); +} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // Enable address decodes + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f03); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x0000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x0000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0069); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x0004); +} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable devices. */ + RCBA32(0x3418) = 0x00300063; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} +void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} diff --git a/src/mainboard/acer/aoa150/hda_verb.c b/src/mainboard/acer/aoa150/hda_verb.c new file mode 100644 index 0000000..62cf56b --- /dev/null +++ b/src/mainboard/acer/aoa150/hda_verb.c @@ -0,0 +1,47 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0268, /* Codec Vendor / Device ID: Realtek */ + 0x1025015b, /* Subsystem ID */ + + 0x0000000c, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x1025015b), + + /* NID 0x12: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x99a30920), + + /* NID 0x13: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0), + + /* NID 0x14: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x99130110), + + /* NID 0x15: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x0321401f), + + /* NID 0x16: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* NID 0x18: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a19830), + + /* NID 0x19: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1c: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), + + /* NID 0x1e: Subsystem ID. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/acer/aoa150/mainboard.c b/src/mainboard/acer/aoa150/mainboard.c new file mode 100644 index 0000000..1506bc8 --- /dev/null +++ b/src/mainboard/acer/aoa150/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_init(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, INT15_5F35_CL_DISPLAY_DEFAULT, 3); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/acer/aoa150/romstage.c b/src/mainboard/acer/aoa150/romstage.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/acer/aoa150/romstage.c @@ -0,0 +1 @@ +/* dummy file */ diff --git a/src/mainboard/acer/aoa150/smihandler.c b/src/mainboard/acer/aoa150/smihandler.c new file mode 100644 index 0000000..3cd7873 --- /dev/null +++ b/src/mainboard/acer/aoa150/smihandler.c @@ -0,0 +1,75 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* FIXME: EC support */ + break; + case APM_CNT_ACPI_DISABLE: + /* FIXME: EC support */ + break; + default: + break; + } + return 0; +}

1 0

Patch set updated for coreboot: 9924a3c acer/aoa150: Manual fixups on top of autport.
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7573 -gerrit commit 9924a3cd20312df0e3a45344ca760fd574602b72 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Nov 22 13:20:28 2014 +0100 acer/aoa150: Manual fixups on top of autport. * Chip is 1M and not 2M. * First 64K are used by EC. Leave them alone. * Half of the RAM is soldered and has no EEPROM. Just use hardcoded SPD. Change-Id: I5d6c3ad5f45d88c346b8c2142fb115d1c3317e12 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/acer/aoa150/Kconfig | 7 ++++++- src/mainboard/acer/aoa150/Makefile.inc | 3 +++ src/mainboard/acer/aoa150/early_southbridge.c | 15 +++++++++++---- src/mainboard/acer/aoa150/spd.bin | Bin 0 -> 128 bytes 4 files changed, 20 insertions(+), 5 deletions(-) diff --git a/src/mainboard/acer/aoa150/Kconfig b/src/mainboard/acer/aoa150/Kconfig index 99a4bb3..afe5367 100644 --- a/src/mainboard/acer/aoa150/Kconfig +++ b/src/mainboard/acer/aoa150/Kconfig @@ -3,7 +3,7 @@ if BOARD_ACER_AOA150 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select BOARD_ROMSIZE_KB_2048 + select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION select CPU_INTEL_SOCKET_441 select EARLY_CBMEM_INIT @@ -36,6 +36,11 @@ config VGA_BIOS_ID string default "8086,27ae" +# First 64K are used by EC +config CBFS_SIZE + hex + default 0xf0000 + config DCACHE_RAM_BASE hex default 0xffdf8000 diff --git a/src/mainboard/acer/aoa150/Makefile.inc b/src/mainboard/acer/aoa150/Makefile.inc index 2f60428..f71df63 100644 --- a/src/mainboard/acer/aoa150/Makefile.inc +++ b/src/mainboard/acer/aoa150/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += early_southbridge.c ramstage-y += cstates.c +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := raw diff --git a/src/mainboard/acer/aoa150/early_southbridge.c b/src/mainboard/acer/aoa150/early_southbridge.c index 6eda5b8..a334212 100644 --- a/src/mainboard/acer/aoa150/early_southbridge.c +++ b/src/mainboard/acer/aoa150/early_southbridge.c @@ -1,4 +1,6 @@ #include <stdint.h> +#include <cbfs.h> +#include <string.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> @@ -6,13 +8,18 @@ #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -/* FIXME: hardcoded. */ void mainboard_get_spd(spd_raw_data *spd) { - read_spd(&spd[0], 0x50); + void *spd_file; + size_t spd_file_len = 0; + /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", CBFS_TYPE_RAW, + &spd_file_len); + if (spd_file && spd_file_len >= 128) + memcpy(&spd[0], spd_file, 128); + + /* C0S0 is a DIMM slot. */ read_spd(&spd[1], 0x51); - read_spd(&spd[2], 0x52); - read_spd(&spd[3], 0x53); } void setup_ich7_gpios(void) diff --git a/src/mainboard/acer/aoa150/spd.bin b/src/mainboard/acer/aoa150/spd.bin new file mode 100644 index 0000000..aec1a53 Binary files /dev/null and b/src/mainboard/acer/aoa150/spd.bin differ

1 0

Patch set updated for coreboot: 7387d56 i945: Disable check for 2-dimm support.
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7568 -gerrit commit 7387d563b7aff8a5c3ab1fe0a2f60d2c453a8fcf Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Nov 22 21:12:14 2014 +0100 i945: Disable check for 2-dimm support. The check is wrong. On Acer Aspire One it returns 0 despite 2 DIMMs working fine on the same channel if this check is disabled (tested by memtest). On boards that have only 1 DIMM per channel, the code will simply find no SPD and skip empty slot. Change-Id: I5f2fdcd1d948ebf3eabebaea4441af4c19e47f8f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/i945/raminit.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 187bcf5..726fbfe 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -208,16 +208,6 @@ static int sdram_capabilities_enhanced_addressing_xor(void) return (!reg8); } -static int sdram_capabilities_two_dimms_per_channel(void) -{ - u8 reg8; - - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */ - reg8 &= (1 << 0); - - return (reg8 != 0); -} - // TODO check if we ever need this function #if 0 static int sdram_capabilities_MEM4G_disable(void) @@ -382,10 +372,6 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) if (!sdram_capabilities_dual_channel() && (dimmno >> 1)) continue; - /* Two DIMMs per channel not supported, but odd DIMM number? */ - if (!sdram_capabilities_two_dimms_per_channel() && (dimmno& 1)) - continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (dimmno >> 1), (dimmno & 1)); if (sysinfo->spd[dimmno][SPD_MEMORY_TYPE] != SPD_MEMORY_TYPE_SDRAM_DDR2) {

1 0

Patch set updated for coreboot: ad98013 macbook21: Move SB-specific early init to separate file
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7085 -gerrit commit ad98013e6e478ca7c470ccaa218386c94e68eb9d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 23:07:24 2014 +0200 macbook21: Move SB-specific early init to separate file Change-Id: I5995dd0c43a541c352af279a373bc783f51176a9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/Makefile.inc | 1 + src/mainboard/apple/macbook21/early_mainboard.h | 3 + src/mainboard/apple/macbook21/early_southbridge.c | 253 ++++++++++++++++++++++ src/mainboard/apple/macbook21/romstage.c | 231 +------------------- 4 files changed, 258 insertions(+), 230 deletions(-) diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc new file mode 100644 index 0000000..7b421c4 --- /dev/null +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -0,0 +1 @@ +romstage-y += early_southbridge.c \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/early_mainboard.h b/src/mainboard/apple/macbook21/early_mainboard.h new file mode 100644 index 0000000..6c9dbe9 --- /dev/null +++ b/src/mainboard/apple/macbook21/early_mainboard.h @@ -0,0 +1,3 @@ +void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); diff --git a/src/mainboard/apple/macbook21/early_southbridge.c b/src/mainboard/apple/macbook21/early_southbridge.c new file mode 100644 index 0000000..7e7b5a9 --- /dev/null +++ b/src/mainboard/apple/macbook21/early_southbridge.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "early_mainboard.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + + /* X60 GPIO: + * 1: HDD_PRESENCE# + * 6: Unknown (Pulled high by R215 to VCC3B) + * 7: BDC_PRESENCE# + * 8: H8_WAKE# + * 9: RTC_BAT_IN# + * 10: Unknown (Pulled high by R700 to VCC3M) + * 12: H8SCI# + * 13: SLICE_ON_3M# + * 14: Unknown (Pulled high by R321 to VCC3) + * 15: Unknown (Pulled high by R258 to VCC3) + * 19: Unknown (Pulled low by R594) + * 21: Unknown (Pulled high by R145 to VCC3) + * 22: FWH_WP# + * 25: MDC_KILL# + * 33: HDD_PRESENCE_2# + * 35: CLKREQ_SATA# + * 36: PLANARID0 + * 37: PLANARID1 + * 38: PLANARID2 + * 39: PLANARID3 + * 48: FWH_TBL# + */ + + outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // I/O Decode Ranges + // X60: 0x0210 == 00000010 00010000 + // Macbook21: 0x0010 == 00000000 00010000 + // Bit 9:8 LPT Decode Range. This field determines which range to + // decode for the LPT Port. + // 00 = 378h 37Fh and 778h 77Fh + // 10 = 3BCh 3BEh and 7BCh 7BEh + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + + // LPC_EN--LPC I/F Enables Register + // X60: 0x1f0d == 00011111 00001101 + // Macbook21: 0x3807 == 00111000 00000111 + // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh + // to the LPC interface. This range is used for + // Super I/O devices. + // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 62h and 66h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 60h and 64h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 208h to 20Fh + // to the LPC interface. This range is used for a gameport. + // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 200h to 207h + // to the LPC interface. This range is used for a gameport. + // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable + // 0 = Disable. + // 1 = Enables the decoding of the FDD range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 12). + // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable + // 0 = Disable. + // 1 = Enables the decoding of the LPT range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 9:8). + // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMB range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 6:4). + // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMA range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 3:2). + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); + + /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ + // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 + // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 + // Bit 31:24 Reserved. + // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any + // bit position indicates that any value in the corresponding + // address bit in a received cycle will be treated as a + // match. The corresponding bit in the Address field, below, + // is ignored. The mask is only provided for the lower 6 bits + // of the DWord address, allowing for decoding blocks up to + // 256 bytes in size. + // Bit 17:16 Reserved. + // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This + // address is aligned on a 128-byte boundary, and must have + // address lines 31:16 as 0. NOTE: The Intel ICH7 does not + // provide decode down to the word or byte level. + // Bit 1 Reserved. + // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. + // 0 = Disable. + // 1 = Enable the GEN1 I/O range to be forwarded to the LPC + // I/F + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); + + /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ + // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 + // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); + + /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ + // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 + // Macbook21: 0x0000 0x0000 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); + + /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ + // X60: 0x0000 0x0000 + // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); +} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable unused devices */ + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; + RCBA32(0x3418) |= (1 << 0); // Required. + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + // RCBA32(0x1e84) = 0x00020001; + // RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} + +void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 3bbb07a..4ec240d 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -26,243 +26,15 @@ #include <string.h> #include <arch/io.h> #include <device/pci_def.h> -#include <device/pnp_def.h> #include <cpu/intel/romstage.h> #include <cpu/x86/lapic.h> -#include <lib.h> -#include <cbmem.h> #include <timestamp.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" - -void setup_ich7_gpios(void) -{ - printk(BIOS_DEBUG, " GPIOS..."); - - /* X60 GPIO: - * 1: HDD_PRESENCE# - * 6: Unknown (Pulled high by R215 to VCC3B) - * 7: BDC_PRESENCE# - * 8: H8_WAKE# - * 9: RTC_BAT_IN# - * 10: Unknown (Pulled high by R700 to VCC3M) - * 12: H8SCI# - * 13: SLICE_ON_3M# - * 14: Unknown (Pulled high by R321 to VCC3) - * 15: Unknown (Pulled high by R258 to VCC3) - * 19: Unknown (Pulled low by R594) - * 21: Unknown (Pulled high by R145 to VCC3) - * 22: FWH_WP# - * 25: MDC_KILL# - * 33: HDD_PRESENCE_2# - * 35: CLKREQ_SATA# - * 36: PLANARID0 - * 37: PLANARID1 - * 38: PLANARID2 - * 39: PLANARID3 - * 48: FWH_TBL# - */ - - outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ -} - -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - - // I/O Decode Ranges - // X60: 0x0210 == 00000010 00010000 - // Macbook21: 0x0010 == 00000000 00010000 - // Bit 9:8 LPT Decode Range. This field determines which range to - // decode for the LPT Port. - // 00 = 378h 37Fh and 778h 77Fh - // 10 = 3BCh 3BEh and 7BCh 7BEh - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - - // LPC_EN--LPC I/F Enables Register - // X60: 0x1f0d == 00011111 00001101 - // Macbook21: 0x3807 == 00111000 00000111 - // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh - // to the LPC interface. This range is used for - // Super I/O devices. - // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 62h and 66h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 60h and 64h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 208h to 20Fh - // to the LPC interface. This range is used for a gameport. - // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 200h to 207h - // to the LPC interface. This range is used for a gameport. - // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable - // 0 = Disable. - // 1 = Enables the decoding of the FDD range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 12). - // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable - // 0 = Disable. - // 1 = Enables the decoding of the LPT range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 9:8). - // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMB range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 6:4). - // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMA range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 3:2). - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); - - /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ - // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 - // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 - // Bit 31:24 Reserved. - // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any - // bit position indicates that any value in the corresponding - // address bit in a received cycle will be treated as a - // match. The corresponding bit in the Address field, below, - // is ignored. The mask is only provided for the lower 6 bits - // of the DWord address, allowing for decoding blocks up to - // 256 bytes in size. - // Bit 17:16 Reserved. - // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This - // address is aligned on a 128-byte boundary, and must have - // address lines 31:16 as 0. NOTE: The Intel ICH7 does not - // provide decode down to the word or byte level. - // Bit 1 Reserved. - // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. - // 0 = Disable. - // 1 = Enable the GEN1 I/O range to be forwarded to the LPC - // I/F - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); - - /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ - // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 - // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); - - /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ - // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 - // Macbook21: 0x0000 0x0000 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); - - /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ - // X60: 0x0000 0x0000 - // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); -} - -static void rcba_config(void) -{ - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* V1CAP Virtual Channel 1 Resource Capability */ - RCBA32(0x001c) = 0x03128010; - - /* Disable unused devices */ - RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; - RCBA32(0x3418) |= (1 << 0); // Required. - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - // RCBA32(0x1e84) = 0x00020001; - // RCBA32(0x1e80) = 0x0000fe01; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; -} - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA32(0x3418) |= (1 << 0); - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} +#include "early_mainboard.h" void main(unsigned long bist) { @@ -328,5 +100,4 @@ void main(unsigned long bist) i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); - }

1 0

Patch set updated for coreboot: 5d08933 i945: Merge romstage main().
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7549 -gerrit commit 5d08933f0a374d1279a3ca506e4688b8af6e81e5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Nov 19 19:59:56 2014 +0100 i945: Merge romstage main(). main() is pretty similar on all i945 boards. Main differences after this change: * mobo supplies standard hooks to do one thing at specific romstage point * instead of supplying a SPD map mainboard supplies an SPD retrieval function with standard library function to get SPD from one EEPROM. This allows to support machines like Acer Aspire One which have no EEPROM for soldered RAM. * PCI reset is controlled by Kconfig * Artec dongle init is controlled by Kconfig. Probably should be always done but I have no hardware to test. Change-Id: Iecae53a9e9e2183377fcd760641894f810e40118 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/Kconfig | 1 + src/mainboard/apple/macbook21/early_mainboard.h | 3 - src/mainboard/apple/macbook21/early_southbridge.c | 10 +- src/mainboard/apple/macbook21/romstage.c | 104 +--------------- src/mainboard/getac/p470/romstage.c | 111 +++++------------ src/mainboard/ibase/mb899/romstage.c | 92 ++++---------- src/mainboard/intel/d945gclf/romstage.c | 67 ++--------- src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/kontron/986lcd-m/romstage.c | 113 +++++------------ src/mainboard/lenovo/t60/Kconfig | 2 + src/mainboard/lenovo/t60/romstage.c | 140 +++++++--------------- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/romstage.c | 129 +++++--------------- src/mainboard/roda/rk886ex/Kconfig | 2 + src/mainboard/roda/rk886ex/romstage.c | 121 +++++-------------- src/northbridge/intel/i945/Kconfig | 4 + src/northbridge/intel/i945/early_init.c | 87 ++++++++++++++ src/northbridge/intel/i945/raminit.c | 139 ++++++++++----------- src/northbridge/intel/i945/raminit.h | 12 +- 19 files changed, 378 insertions(+), 761 deletions(-) diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 8fd5f90..06188fd 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select VGA select MAINBOARD_DO_EDID select INTEL_EDID + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbook21/early_mainboard.h b/src/mainboard/apple/macbook21/early_mainboard.h deleted file mode 100644 index 6c9dbe9..0000000 --- a/src/mainboard/apple/macbook21/early_mainboard.h +++ /dev/null @@ -1,3 +0,0 @@ -void ich7_enable_lpc(void); -void rcba_config(void); -void early_ich7_init(void); diff --git a/src/mainboard/apple/macbook21/early_southbridge.c b/src/mainboard/apple/macbook21/early_southbridge.c index 7e7b5a9..70a9dbd 100644 --- a/src/mainboard/apple/macbook21/early_southbridge.c +++ b/src/mainboard/apple/macbook21/early_southbridge.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "northbridge/intel/i945/i945.h" #include "southbridge/intel/i82801gx/i82801gx.h" -#include "early_mainboard.h" +#include "northbridge/intel/i945/raminit.h" void setup_ich7_gpios(void) { @@ -251,3 +251,11 @@ void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } + +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 4ec240d..2997587 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -1,103 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - -#include <stdint.h> -#include <string.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <cpu/intel/romstage.h> -#include <cpu/x86/lapic.h> -#include <timestamp.h> -#include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "early_mainboard.h" - -void main(unsigned long bist) -{ - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); -} +/* dummy */ diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 32323bc..f9da4fe 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -30,8 +30,6 @@ #include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -81,26 +79,6 @@ void setup_ich7_gpios(void) outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ } -static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); - // Enable 0x02e0 - 0x2ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); - // Enable 0x600 - 0x6ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); - // Enable 0x68 - 0x6f - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); -} - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -170,7 +148,29 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); + // Enable 0x02e0 - 0x2ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); + // Enable 0x600 - 0x6ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); + // Enable 0x68 - 0x6f + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + + early_superio_config(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -194,7 +194,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -248,63 +248,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - -#if 0 - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); -#endif - - ich7_enable_lpc(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 6f3e943..3c26d89 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -32,8 +32,6 @@ #include <superio/winbond/w83627ehg/w83627ehg.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -57,20 +55,6 @@ void setup_ich7_gpios(void) outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); - // Enable HWM at 0x290 - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); -} - /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. @@ -142,7 +126,23 @@ static void early_superio_config_w83627ehg(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + // Enable HWM at 0x290 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); + + early_superio_config_w83627ehg(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -152,7 +152,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -206,56 +206,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - ich7_enable_lpc(); - early_superio_config_w83627ehg(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index f8fc155..1d0b5be 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -31,7 +31,6 @@ #include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -56,7 +55,7 @@ void setup_ich7_gpios(void) outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) +void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -66,9 +65,12 @@ static void ich7_enable_lpc(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); // Enable SuperIO Power Management Events pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); + /* Enable SuperIO PM */ + lpc47m15x_enable_serial(PME_DEV, 0x680); + lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ } -static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -84,7 +86,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -138,57 +140,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0, boot_mode = 0; - - if (bist == 0) - enable_lapic(); - - ich7_enable_lpc(); - /* Enable SuperIO PM */ - lpc47m15x_enable_serial(PME_DEV, 0x680); - lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : boot_mode, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 2a3cfe2..123222a 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select OVERRIDE_CLOCK_DISABLE + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index d25d0bc..abb8710 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -31,8 +31,6 @@ #include <pc80/mc146818rtc.h> #include "option_table.h" #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <superio/winbond/w83627thg/w83627thg.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" @@ -56,28 +54,6 @@ void setup_ich7_gpios(void) outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); - // Enable HWM at 0xa00 - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); - // COM3 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); - // COM4 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); -} - /* TODO: superio code should really not be in mainboard */ static void pnp_enter_func_mode(device_t dev) { @@ -199,7 +175,31 @@ static void early_superio_config_w83627thg(void) pnp_exit_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); + // Enable HWM at 0xa00 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); + + early_superio_config_w83627thg(); +} + +void rcba_config(void) { u32 reg32; @@ -258,7 +258,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -312,61 +312,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - early_superio_config_w83627thg(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index fbe2c72..0aa8204 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -22,6 +22,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET + config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 8baeea6..3a97c51 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -34,8 +34,6 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -74,8 +72,26 @@ void setup_ich7_gpios(void) outl(0x000300a3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ } -static void ich7_enable_lpc(void) +static void early_superio_config(void) { + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0xa0); + + while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void ich7_enable_lpc(void) +{ + int dock_err; + // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range @@ -94,25 +110,26 @@ static void ich7_enable_lpc(void) /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); -} -static void early_superio_config(void) -{ - int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0xa0); + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + /* Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + setup_ich7_gpios(); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) - udelay(1000); + dock_err = dlpc_init(); - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { + dock_connect(); + early_superio_config(); + } } -static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; @@ -131,7 +148,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -185,87 +202,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - int dock_err; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; - - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); - setup_ich7_gpios(); - - dock_err = dlpc_init(); - - /* We prefer Legacy I/O module over docking */ - if (legacy_io_present()) { - legacy_io_init(); - early_superio_config(); - } else if (!dock_err && dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Setup the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x52); + read_spd(&spd[2], 0x51); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 0125d8c..ecbc9e8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select INTEL_EDID + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index fbfbd7c..881a42e 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -34,8 +34,6 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -81,7 +79,23 @@ void setup_ich7_gpios(void) outl(0x00030043, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -static void ich7_enable_lpc(void) +static void early_superio_config(void) +{ + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0x06); + + while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -101,25 +115,19 @@ static void ich7_enable_lpc(void) /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); -} - -static void early_superio_config(void) -{ - int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0x06); - - while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) - udelay(1000); - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); + dlpc_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (dock_present()) { + dock_connect(); + early_superio_config(); + } } -static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; @@ -138,7 +146,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -192,81 +200,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; - - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - dlpc_init(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); - + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x52); + read_spd(&spd[2], 0x51); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index efe75a3..e0c7a15 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET + select NORTHBRIDGE_INTEL_ARTEC_DONGLE config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index c4bdcf4..ba56916 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -32,8 +32,6 @@ #include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -68,27 +66,6 @@ void setup_ich7_gpios(void) // ------------------------------------------------------------ } -static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); - // Enable 0x02e0 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); - // COM3 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); - // COM4 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); -} - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -148,7 +125,30 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); + // Enable 0x02e0 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + + early_superio_config(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -173,7 +173,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -227,71 +227,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -static void init_artec_dongle(void) -{ - // Enable 4MB decoding - outb(0xf1, 0x88); - outb(0xf4, 0x88); -} - -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - /* This has to happen after i945_early_initialization() */ - init_artec_dongle(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index c578011..086be8a 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -36,6 +36,10 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n config NORTHBRIDGE_INTEL_SUBTYPE_I945GM def_bool n +config NORTHBRIDGE_INTEL_EARLY_PCI_RESET + def_bool n +config NORTHBRIDGE_INTEL_ARTEC_DONGLE + def_bool n config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08977f2..b3730eb 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -26,6 +26,11 @@ #include <halt.h> #include <string.h> #include "i945.h" +#include <timestamp.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include "raminit.h" +#include <halt.h> int i945_silicon_revision(void) { @@ -980,3 +985,85 @@ void i945_late_initialization(int s3resume) i945_prepare_resume(s3resume); } + + +static void init_artec_dongle(void) +{ + // Enable 4MB decoding + outb(0xf1, 0x88); + outb(0xf4, 0x88); +} + +void main(unsigned long bist) +{ + int s3resume = 0; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_EARLY_PCI_RESET)) { + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + } + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + halt(); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* This probably should be unconditional as artec dongle can + be used on any board but I have no hardware to test it. + */ + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_ARTEC_DONGLE)) { + /* This has to happen after i945_early_initialization() */ + init_artec_dongle(); + } + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(s3resume ? 2 : 0); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); + + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e9b6e3f..187bcf5 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -51,18 +51,15 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) -static int get_dimm_spd_address(struct sys_info *sysinfo, int device) +void read_spd(spd_raw_data * spd, u8 addr) { - if (sysinfo->spd_addresses) - return sysinfo->spd_addresses[device]; - else - return DIMM0 + device; - -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); + int j; + int val; + val = smbus_read_byte(addr, 0); + if (val < 0) + return; + for (j = 1; j < 256; j++) + (*spd)[j] = smbus_read_byte(addr, j); } static __attribute__((noinline)) void do_ram_command(u32 command) @@ -330,7 +327,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; + int dimmno; /** * i945 supports two DIMMs, in two configurations: @@ -353,6 +350,9 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n"); } + memset(sysinfo->spd, 0, sizeof(sysinfo->spd)); + mainboard_get_spd(sysinfo->spd); + /** * Since we only support two DIMMs in total, there is a limited number * of combinations. This function returns the type of DIMMs. @@ -372,62 +372,61 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */ - for (i=0; i<(2 * DIMM_SOCKETS); i++) { - int device = get_dimm_spd_address(sysinfo, i); + for (dimmno=0; dimmno<(2 * DIMM_SOCKETS); dimmno++) { u8 reg8; /* Initialize the socket information with a sane value */ - sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_NOT_POPULATED; /* Dual Channel not supported, but Channel 1? Bail out */ - if (!sdram_capabilities_dual_channel() && (i >> 1)) + if (!sdram_capabilities_dual_channel() && (dimmno >> 1)) continue; /* Two DIMMs per channel not supported, but odd DIMM number? */ - if (!sdram_capabilities_two_dimms_per_channel() && (i& 1)) + if (!sdram_capabilities_two_dimms_per_channel() && (dimmno& 1)) continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (dimmno >> 1), (dimmno & 1)); - if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { + if (sysinfo->spd[dimmno][SPD_MEMORY_TYPE] != SPD_MEMORY_TYPE_SDRAM_DDR2) { printk(BIOS_DEBUG, "N/A\n"); continue; } - reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); + reg8 = sysinfo->spd[dimmno][SPD_DIMM_CONFIG_TYPE]; if (reg8 == ERROR_SCHEME_ECC) die("Error: ECC memory not supported by this chipset\n"); - reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); + reg8 = sysinfo->spd[dimmno][SPD_MODULE_ATTRIBUTES]; if (reg8 & MODULE_BUFFERED) die("Error: Buffered memory not supported by this chipset\n"); if (reg8 & MODULE_REGISTERED) die("Error: Registered memory not supported by this chipset\n"); - switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + switch (sysinfo->spd[dimmno][SPD_PRIMARY_SDRAM_WIDTH]) { case 0x08: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + switch (sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS] & 0x0f) { case 1: printk(BIOS_DEBUG, "x8DDS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X8DDS; break; case 0: printk(BIOS_DEBUG, "x8DS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X8DS; break; default: printk(BIOS_DEBUG, "Unsupported.\n"); } break; case 0x10: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + switch (sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS] & 0x0f) { case 1: printk(BIOS_DEBUG, "x16DS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X16DS; break; case 0: printk(BIOS_DEBUG, "x16SS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X16SS; break; default: printk(BIOS_DEBUG, "Unsupported.\n"); @@ -437,7 +436,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) die("Unsupported DDR-II memory width.\n"); } - dimm_mask |= (1 << i); + dimm_mask |= (1 << dimmno); } if (!dimm_mask) { @@ -465,7 +464,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo) continue; /* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (sysinfo->spd[i][SPD_NUM_DIMM_BANKS] & (1 << 4)) sysinfo->package = 1; } } @@ -482,8 +481,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) for (i=0; i<2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_ACCEPTABLE_CAS_LATENCIES); + cas_mask &= sysinfo->spd[i][SPD_ACCEPTABLE_CAS_LATENCIES]; } if(!cas_mask) { @@ -495,7 +493,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) { - int i, j, idx; + int dimmno, j, idx; int lowest_common_cas = 0; int max_ram_speed = 0; @@ -536,16 +534,15 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 int freq_cas_mask = cas_mask; PRINTK_DEBUG("Probing Speed %d\n", j); - for (i=0; i<2*DIMM_SOCKETS; i++) { - int device = get_dimm_spd_address(sysinfo, i); + for (dimmno=0; dimmno<2*DIMM_SOCKETS; dimmno++) { int current_cas_mask; - PRINTK_DEBUG(" DIMM: %d\n", i); - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + PRINTK_DEBUG(" DIMM: %d\n", dimmno); + if (sysinfo->dimm[dimmno] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES); + current_cas_mask = sysinfo->spd[dimmno][SPD_ACCEPTABLE_CAS_LATENCIES]; while (current_cas_mask) { int highest_supported_cas = 0, current_cas = 0; @@ -571,11 +568,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 idx = highest_supported_cas - current_cas; PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1])); + PRINTK_DEBUG("tCLK=%x, ", sysinfo->spd[dimmno][spd_lookup_table[2*idx]]); + PRINTK_DEBUG("tAC=%x", sysinfo->spd[dimmno][spd_lookup_table[(2*idx)+1]]); - if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { + if (sysinfo->spd[dimmno][spd_lookup_table[2*idx]] <= ddr2_speeds_table[2*j] && + sysinfo->spd[dimmno][spd_lookup_table[(2*idx)+1]] <= ddr2_speeds_table[(2*j)+1]) { PRINTK_DEBUG(": OK\n"); break; } @@ -587,7 +584,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 freq_cas_mask &= current_cas_mask; if (!current_cas_mask) { - PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); + PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", dimmno); break; } } @@ -639,7 +636,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + reg8 = sysinfo->spd[i][SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY]; if (!reg8) { die("Invalid tRAS value.\n"); } @@ -679,7 +676,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME); + reg8 = sysinfo->spd[i][SPD_MIN_ROW_PRECHARGE_TIME]; if (!reg8) { die("Invalid tRP value.\n"); } @@ -720,7 +717,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY); + reg8 = sysinfo->spd[i][SPD_MIN_RAS_TO_CAS_DELAY]; if (!reg8) { die("Invalid tRCD value.\n"); } @@ -760,7 +757,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME); + reg8 = sysinfo->spd[i][SPD_WRITE_RECOVERY_TIME]; if (!reg8) { die("Invalid tWR value.\n"); } @@ -841,8 +838,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_REFRESH) & ~(1 << 7); + refresh = sysinfo->spd[i][SPD_REFRESH] & ~(1 << 7); /* 15.6us */ if (!refresh) @@ -870,8 +866,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!(sysinfo->spd[i][SPD_SUPPORTED_BURST_LENGTHS] & SPD_BURST_LENGTH_8)) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1407,41 +1402,40 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, rows, columns, device; + int value, low, rows, columns; - device = get_dimm_spd_address(sysinfo, dimmno); sz.side1 = 0; sz.side2 = 0; - rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + rows = sysinfo->spd[dimmno][SPD_NUM_ROWS]; /* rows */ if (rows < 0) goto hw_err; if ((rows & 0xf) == 0) goto val_err; sz.side1 += rows & 0xf; - columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + columns = sysinfo->spd[dimmno][SPD_NUM_COLUMNS]; /* columns */ if (columns < 0) goto hw_err; if ((columns & 0xf) == 0) goto val_err; sz.side1 += columns & 0xf; - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + value = sysinfo->spd[dimmno][SPD_NUM_BANKS_PER_SDRAM]; /* banks */ if (value < 0) goto hw_err; if ((value & 0xff) == 0) goto val_err; sz.side1 += log2(value & 0xff); /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ + value = sysinfo->spd[dimmno][SPD_MODULE_DATA_WIDTH_MSB]; /* (high byte) */ if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ + low = sysinfo->spd[dimmno][SPD_MODULE_DATA_WIDTH_LSB]; /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); if ((value != 72) && (value != 64)) goto val_err; sz.side1 += log2(value); /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ + value = sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS]; /* number of physical banks */ if (value < 0) goto hw_err; value &= 7; @@ -1494,8 +1488,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) sz = sdram_get_dimm_size(sysinfo, i); - sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_NUM_BANKS_PER_SDRAM); /* banks */ + sysinfo->banks[i] = sysinfo->spd[i][SPD_NUM_BANKS_PER_SDRAM]; /* banks */ if (sz.side1 < 30) die("DDR-II rank size smaller than 128MB is not supported.\n"); @@ -1575,24 +1568,21 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i, value; + int dimmno, value; u16 dra0=0, dra1=0, dra = 0; printk(BIOS_DEBUG, "Setting row attributes... \n"); - for(i=0; i < 2 * DIMM_SOCKETS; i++) { - u16 device; + for(dimmno=0; dimmno < 2 * DIMM_SOCKETS; dimmno++) { u8 columnsrows; - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + if (sysinfo->dimm[dimmno] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - device = get_dimm_spd_address(sysinfo, i); - - value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + value = sysinfo->spd[dimmno][SPD_NUM_ROWS]; /* rows */ columnsrows = (value & 0x0f); - value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + value = sysinfo->spd[dimmno][SPD_NUM_COLUMNS]; /* columns */ columnsrows |= (value & 0xf) << 4; switch (columnsrows) { @@ -1605,14 +1595,14 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo) } /* Double Sided DIMMs? */ - if (sysinfo->banksize[(2 * i) + 1] != 0) { + if (sysinfo->banksize[(2 * dimmno) + 1] != 0) { dra = (dra << 4) | dra; } - if (i < DIMM_SOCKETS) - dra0 |= (dra << (i*8)); + if (dimmno < DIMM_SOCKETS) + dra0 |= (dra << (dimmno*8)); else - dra1 |= (dra << ((i - DIMM_SOCKETS)*8)); + dra1 |= (dra << ((dimmno - DIMM_SOCKETS)*8)); } MCHBAR16(C0DRA0) = dra0; @@ -3050,7 +3040,7 @@ static void sdram_setup_processor_side(void) /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ -void sdram_initialize(int boot_path, const u8 *spd_addresses) +void sdram_initialize(int boot_path) { struct sys_info sysinfo; u8 reg8, cas_mask; @@ -3060,7 +3050,6 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) memset(&sysinfo, 0, sizeof(sysinfo)); sysinfo.boot_path = boot_path; - sysinfo.spd_addresses = spd_addresses; /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */ sdram_get_dram_configuration(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 9eb4193..20fbe8c 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -20,6 +20,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <device/dram/ddr3.h> + #define DIMM_SOCKETS 2 #define DIMM_TCO_BASE 0x30 @@ -63,14 +65,18 @@ struct sys_info { u8 banks[2 * DIMM_SOCKETS]; u8 banksize[2 * 2 * DIMM_SOCKETS]; - const u8 *spd_addresses; - + spd_raw_data spd[4]; } __attribute__ ((packed)); void receive_enable_adjust(struct sys_info *sysinfo); -void sdram_initialize(int boot_path, const u8 *sdram_addresses); +void sdram_initialize(int boot_path); int fixup_i945_errata(void); void udelay(u32 us); +void mainboard_get_spd(spd_raw_data *spd); +void read_spd(spd_raw_data *spd, u8 addr); +void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); #if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void);

1 0

Patch set updated for coreboot: 8e96fbc autoport: Experimental stuff
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7131 -gerrit commit 8e96fbccd4a753a544acbde5d00f8ad6f09bcf9e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 21:51:47 2014 +0200 autoport: Experimental stuff Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/azalia.go | 62 +++++ util/autoport/bd82x6x.go | 319 +++++++++++++++++++++++ util/autoport/i82801gx.go | 530 +++++++++++++++++++++++++++++++++++++ util/autoport/i945.go | 120 +++++++++ util/autoport/log_maker.go | 85 ++++++ util/autoport/log_reader.go | 310 ++++++++++++++++++++++ util/autoport/main.go | 607 +++++++++++++++++++++++++++++++++++++++++++ util/autoport/rce823.go | 39 +++ util/autoport/root.go | 29 +++ util/autoport/sandybridge.go | 113 ++++++++ 10 files changed, 2214 insertions(+) diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go new file mode 100644 index 0000000..f98fe27 --- /dev/null +++ b/util/autoport/azalia.go @@ -0,0 +1,62 @@ +package main + +import ( + "fmt" + "sort" +) + +type azalia struct { +} + +func (i azalia) Scan(ctx Context, addr PCIDevData) { + az := Create(ctx, "hda_verb.c") + defer az.Close() + + az.WriteString( + `#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +`) + + for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { + fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n", + codec.VendorID, codec.Name) + fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n", + codec.SubsystemID) + fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n", + len(codec.PinConfig)+1) + fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n") + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + codec.CodecNo, codec.SubsystemID) + + keys := []int{} + for nid, _ := range codec.PinConfig { + keys = append(keys, nid) + } + + sort.Ints(keys) + + for _, nid := range keys { + fmt.Fprintf(az, "\n\t/* NID 0x%02x: Subsystem ID. */\n", nid) + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + codec.CodecNo, nid, codec.PinConfig[nid]) + } + } + + az.WriteString( + `}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; +`) + + PutPCIDev(addr, "Audio controller") +} + +func init() { + /* I82801GX/I945 */ + RegisterPCI(0x8086, 0x27d8, azalia{}) + /* C216/ivybridge */ + RegisterPCI(0x8086, 0x1e20, azalia{}) +} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go new file mode 100644 index 0000000..7bc0ae4 --- /dev/null +++ b/util/autoport/bd82x6x.go @@ -0,0 +1,319 @@ +package main + +import ( + "fmt" + "os" +) + +type bd82x6x struct { + variant string +} + +func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } +} + +func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h" +`) + + adresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := adresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`static const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true + /* FIXME: hardcoded */ + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + /* FIXME: hardcoded */ + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + /* FIXME: hardcoded */ + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + pcieHotplugMap := "{ " + + for port := 0; port < 7; port++ { + if b.IsPCIeHotplug(ctx, port) { + pcieHotplugMap += "1, " + } else { + pcieHotplugMap += "0, " + } + } + + if b.IsPCIeHotplug(ctx, 7) { + pcieHotplugMap += "1 }" + } else { + pcieHotplugMap += "0 }" + } + + cur := DevTreeNode{ + Chip: "southbridge/intel/bd82x6x", + Comment: "Intel Series 6 Cougar Point PCH", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "alt_gp_smi_en": "0x0000", + "gpi1_routing": "2", + "gpi8_routing": "2", + "sata_interface_speed_support": "0x3", + "gen1_dec": portDev.ConfigDump[0x84], + "gen2_dec": portDev.ConfigDump[0x88], + "gen3_dec": portDev.ConfigDump[0x8c], + "gen4_dec": portDev.ConfigDump[0x90], + "pcie_port_coalesce": "1", + "pcie_hotplug_map": pcieHotplugMap, + + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c2_latency": FormatHexLE16(FADT[96:98]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMStageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ +`) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI32Simple(sb, addr, 0x84) + RestorePCI32Simple(sb, addr, 0x88) + RestorePCI32Simple(sb, addr, 0x8c) + RestorePCI32Simple(sb, addr, 0x90) + + RestorePCI16Simple(sb, addr, 0x80) + + RestorePCI32Simple(sb, addr, 0xac) + + sb.WriteString(`} + +void rcba_config(void) +{ + /* Disable devices. */ +`) + RestoreRCBA32(sb, inteltool, 0x3414) + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString("\n}\n") + + sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") + + currentMap := map[uint32]int{ + 0x20000153: 0, + 0x20000f57: 1, + 0x2000055b: 2, + 0x20000f51: 3, + 0x2000094a: 4, + } + + for port := uint(0); port < 14; port++ { + var pinmask uint32 + OCPin := -1 + if port < 8 { + pinmask = inteltool.RCBA[0x35a0] + } else { + pinmask = inteltool.RCBA[0x35a4] + } + for pin := uint(0); pin < 4; pin++ { + if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 { + OCPin = int(pin) + if port >= 8 { + OCPin += 4 + } + } + } + fmt.Fprintf(sb, "{ %d, %d, %d }\n", + (inteltool.RCBA[0x359c]>>port)&1, + currentMap[inteltool.RCBA[uint16(0x3500+4*port)]], + OCPin) + } + sb.WriteString("};\n") + + sb.WriteString(` +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} +`) + + /* FIXME: hardcoded. */ + gnvs := Create(ctx, "gnvs.c") + defer gnvs.Close() + + gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} +`) + + AddRAMStageFile("gnvs.c", "") +} + +func init() { + RegisterPCI(0x8086, 0x1e55, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e31, GenericPCI{}) + RegisterPCI(0x8086, 0x1e26, GenericPCI{}) + RegisterPCI(0x8086, 0x1e2d, GenericPCI{}) + RegisterPCI(0x8086, 0x1e3a, GenericPCI{}) + RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1e10, GenericPCI{}) + RegisterPCI(0x8086, 0x1e12, GenericPCI{}) + RegisterPCI(0x8086, 0x1e14, GenericPCI{}) + RegisterPCI(0x8086, 0x1e03, GenericPCI{}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/i82801gx.go b/util/autoport/i82801gx.go new file mode 100644 index 0000000..323419a --- /dev/null +++ b/util/autoport/i82801gx.go @@ -0,0 +1,530 @@ +package main + +import ( + "fmt" + "os" +) + +type i82801gx struct { +} + +func (i i82801gx) writeGPIO(ctx Context, sb *os.File, inteltool InteltoolData, addr uint16, name string) { + fmt.Fprintf(sb, " outl(0x%08x, DEFAULT_GPIOBASE + %s);\n", + inteltool.GPIO[addr], name) +} + +func (i i82801gx) Scan(ctx Context, addr PCIDevData) { + + KconfigBool["HAVE_MP_TABLE"] = true + KconfigBool["SOUTHBRIDGE_INTEL_I82801GX"] = true + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMStageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + +`) + inteltool := ctx.InfoSource.GetInteltool() + i.writeGPIO(ctx, sb, inteltool, 0x0, "GPIO_USE_SEL") + i.writeGPIO(ctx, sb, inteltool, 0x4, "GP_IO_SEL") + i.writeGPIO(ctx, sb, inteltool, 0xc, "GP_LVL") + i.writeGPIO(ctx, sb, inteltool, 0x18, "GPO_BLINK") + i.writeGPIO(ctx, sb, inteltool, 0x2c, "GPI_INV") + i.writeGPIO(ctx, sb, inteltool, 0x30, "GPIO_USE_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x34, "GP_IO_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x38, "GP_LVL2") + + sb.WriteString(`} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // Enable address decodes +`) + + RestorePCI16Simple(sb, addr, 0x80) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI16Simple(sb, addr, 0x84) + RestorePCI16Simple(sb, addr, 0x86) + RestorePCI16Simple(sb, addr, 0x88) + RestorePCI16Simple(sb, addr, 0x8a) + RestorePCI16Simple(sb, addr, 0x8c) + RestorePCI16Simple(sb, addr, 0x8e) + RestorePCI16Simple(sb, addr, 0x90) + RestorePCI16Simple(sb, addr, 0x92) + + /* Just use the same interrupt map for all boards: just registers have to match ACPI. */ + sb.WriteString(`} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable devices. */ +`) + + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString(` + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} +`) + + /* FIXME: does this one need adjustments? */ + sb.WriteString(`void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +`) + + ioapic := DevTreeNode{ + Chip: "drivers/generic/ioapic", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "have_isa_interrupts": "1", + "irq_on_fsb": "1", + "enable_virtual_wire": "0", + "base": "0xfec00000", + }, + Children: []DevTreeNode{ + { + Chip: "ioapic", + Dev: 2, + }, + }, + } + + PutPCIChip(addr, ioapic) + + ideConfig := uint8(0) + ide, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 1}] + if ok { + ideConfig = ide.ConfigDump[0x54] + } + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/i82801gx", + Comment: "Southbridge, FIXME: set gpiX_routing, gpe0_en and alt_gp_smi_en for EC support", + MissingParent: "southbridge", + Registers: map[string]string{ + /* FIXME: should be a CMOS config */ + "sata_ahci": "0x1", + + "sata_ports_implemented": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0xf), + "ide_enable_primary": fmt.Sprintf("%d", (ideConfig>>1)&1), + "ide_enable_secondary": fmt.Sprintf("%d", (ideConfig>>3)&1), + "c4onc3_enable": fmt.Sprintf("%d", ((addr.ConfigDump[0xa0] >> 7) & 1)), + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c3_latency": FormatHexLE16(FADT[98:100]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 1}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 2}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 3}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 7}, writeEmpty: true, additionalComment: "USB EHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 1}, writeEmpty: true, additionalComment: "IDE Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + }, + } + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x00}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x07}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1b}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1c}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x11, 0x10, 0x12, 0x13}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1d}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x17, 0x13, 0x12, 0x10}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1e}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0x14, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1f}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x12, 0x13, 0, 0x10}} + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/ich7.asl", + }) + + ai := Create(ctx, "acpi/ich7_pci_irqs.asl") + defer ai.Close() + + /* FIXME: hardcoded. */ + ai.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} +`) + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + ec.WriteString("/* FIXME: Add EC support here. */") + + at := Create(ctx, "acpi_tables.c") + defer at.Close() + + /* FIXME: hardcoded. */ + at.WriteString( + `#include <stdint.h> +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; +} +`) + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() + si.WriteString("/* FIXME: Add superio support here. */") + + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + /* FIXME: hardcoded. */ + ap.WriteString( + `Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Scope(\_SB) +{ + Method(_INI, 0) + { + \GOS() + } +} +`) + + + + sh := Create(ctx, "smihandler.c") + defer sh.Close() + + /* FIXME: hardcoded. */ + sh.WriteString( + ` +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* FIXME: Add EC support here */ + break; + case APM_CNT_ACPI_DISABLE: + /* FIXME: Add EC support here */ + break; + default: + break; + } + return 0; +} +`) + mb := Create(ctx, "mainboard.c") + defer mb.Close() + + /* FIXME: hardcoded. */ + mb.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_init(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, INT15_5F35_CL_DISPLAY_DEFAULT, 3); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; +`) + +} + +func init() { + RegisterPCI(0x8086, 0x27b9, i82801gx{}) + RegisterPCI(0x8086, 0x27c8, GenericPCI{}) + RegisterPCI(0x8086, 0x27c9, GenericPCI{}) + RegisterPCI(0x8086, 0x27ca, GenericPCI{}) + RegisterPCI(0x8086, 0x27cb, GenericPCI{}) + RegisterPCI(0x8086, 0x27cc, GenericPCI{}) + + RegisterPCI(0x8086, 0x27d0, GenericPCI{}) + RegisterPCI(0x8086, 0x27d2, GenericPCI{}) + RegisterPCI(0x8086, 0x27d4, GenericPCI{}) + RegisterPCI(0x8086, 0x27d6, GenericPCI{}) + + RegisterPCI(0x8086, 0x2448, GenericPCI{}) + + RegisterPCI(0x8086, 0x27c5, GenericPCI{}) + RegisterPCI(0x8086, 0x27c4, GenericPCI{}) + RegisterPCI(0x8086, 0x27df, GenericPCI{}) + RegisterPCI(0x8086, 0x27da, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/i945.go b/util/autoport/i945.go new file mode 100644 index 0000000..91b1b98 --- /dev/null +++ b/util/autoport/i945.go @@ -0,0 +1,120 @@ +package main + +import ( + "log" + "strings" +) + +type i945mc struct { + variant string +} + +func (i i945mc) Scan(ctx Context, addr PCIDevData) { + + cpuModel := ctx.InfoSource.GetCPUModel()[0] + socket := "" + switch cpuModel >> 4 { + case 0x69, 0x6d, 0x6e, 0x6f: + socket = "mFCPGA478" + case 0x106c: + socket = "441" + default: + log.Fatalf("unsupported cpu: 0x%x", cpuModel) + } + DevTree = DevTreeNode{ + Chip: "northbridge/intel/i945", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_hotplug": "0x00000220", + "gpu_lvds_use_spread_spectrum_clock": "1", + "gpu_lvds_is_dual_channel": "0", + "gpu_backlight": "0x1280128", + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_" + socket, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + }, + }, + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "VGA"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 1}, writeEmpty: true, additionalComment: "Display controller"}, + }, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool["VGA"] = true + KconfigBool["MAINBOARD_DO_EDID"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_"+strings.ToUpper(socket)] = true + KconfigBool["NORTHBRIDGE_INTEL_I945"] = true + KconfigBool["CHANNEL_XOR_RANDOMIZATION"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigHex["DCACHE_RAM_BASE"] = 0xffdf8000 + KconfigHex["DCACHE_RAM_SIZE"] = 0x8000 + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 2 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_6dx/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/i945/acpi/i945.asl", + }) + + KconfigBool["NORTHBRIDGE_INTEL_SUBTYPE_" + i.variant] = true + + cs := Create(ctx, "cstates.c") + defer cs.Close() + AddRAMStageFile("cstates.c", "") + + /* FIXME: hardcoded. */ + cs.WriteString( + `#include <arch/acpigen.h> +#include <device/device.h> +#include <northbridge/intel/i945/i945.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} +`) +} + +func init() { + RegisterPCI(0x8086, 0x27a0, i945mc{variant:"I945GM"}) + RegisterPCI(0x8086, 0x27ac, i945mc{variant:"I945GM"}) + RegisterPCI(0x8086, 0x27a2, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27ae, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27a6, GenericPCI{Comment: "display controller"}) +} diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go new file mode 100644 index 0000000..3abea7e --- /dev/null +++ b/util/autoport/log_maker.go @@ -0,0 +1,85 @@ +package main + +import ( + "io" + "io/ioutil" + "log" + "os" + "os/exec" + "strings" +) + +func RunAndSave(output string, name string, arg ...string) { + cmd := exec.Command(name, arg...) + + f, err := os.Create(output) + if err != nil { + log.Fatal(err) + } + + cmd.Stdout = f + cmd.Stderr = f + + err = cmd.Start() + if err != nil { + log.Fatal(err) + } + cmd.Wait() +} + +func MakeLogs(outDir string) { + os.MkdirAll(outDir, 0700) + RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") + RunAndSave(outDir+"/dmidecode.log", "dmidecode") + RunAndSave(outDir+"/acpidump.log", "acpidump") + /* FIXME */ + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a") + + SysDir := "/sys/class/sound/card0/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/card0/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + in, err := os.Open("/proc/cpuinfo") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/cpuinfo.log") + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) +} diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go new file mode 100644 index 0000000..fda4b3a --- /dev/null +++ b/util/autoport/log_reader.go @@ -0,0 +1,310 @@ +package main + +import ( + "bufio" + "flag" + "fmt" + "log" + "os" + "strconv" + "strings" +) + +type LogDevReader struct { + InputDirectory string + ACPITables map[string][]byte +} + +func isXDigit(x uint8) bool { + if x >= '0' && x <= '9' { + return true + } + if x >= 'a' && x <= 'f' { + return true + } + if x >= 'A' && x <= 'F' { + return true + } + return false +} + +type HexLine struct { + length uint + values [16]byte + start uint +} + +func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) { + hex.start = 0 + line = strings.Trim(line, " ") + fmt.Sscanf(line, "%x:", &hex.start) + ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start, + &hex.values[0], &hex.values[1], &hex.values[2], + &hex.values[3], &hex.values[4], &hex.values[5], + &hex.values[6], &hex.values[7], &hex.values[8], + &hex.values[9], &hex.values[10], &hex.values[11], + &hex.values[12], &hex.values[13], &hex.values[14], + &hex.values[15]) + hex.length = uint(ll - 1) + return +} + +func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte { + hex := l.ReadHexLine(inp) + if hex.start+hex.length > uint(len(target)) { + target = target[0 : hex.start+hex.length] + } + copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length]) + return target +} + +func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { + if l.ACPITables != nil { + return l.ACPITables + } + l.ACPITables = Tables + + file, err := os.Open(l.InputDirectory + "/acpidump.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + Tables = map[string][]byte{} + + curTable := "" + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) >= 6 && line[5] == '@': + curTable = line[0:4] + Tables[curTable] = make([]byte, 0, 100000) + case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':': + Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) { + file, err := os.Open(l.InputDirectory + "/lspci.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + PCIList = []PCIDevData{} + + for scanner.Scan() { + line := scanner.Text() + switch { + case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + cur := PCIDevData{} + fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) + lc := strings.LastIndex(line, ":") + li := strings.LastIndex(line[0:lc], "[") + if li < 0 { + continue + } + ven := 0 + dev := 0 + fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) + cur.PCIDevID = uint16(dev) + cur.PCIVenID = uint16(ven) + cur.ConfigDump = make([]byte, 0x100, 0x1000) + PCIList = append(PCIList, cur) + case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': + start := 0 + fmt.Sscanf(line, "%x:", &start) + cur := &PCIList[len(PCIList)-1] + cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetInteltool() (ret InteltoolData) { + file, err := os.Open(l.InputDirectory + "/inteltool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + ret.GPIO = map[uint16]uint32{} + ret.RCBA = map[uint16]uint32{} + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.RCBA[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "gpiobase"): + addr, value := 0, 0 + fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value) + ret.GPIO[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "============="): + paragraph = strings.Trim(line, "= ") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetDMI() (ret DMIData) { + file, err := os.Open(l.InputDirectory + "/dmidecode.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + for scanner.Scan() { + line := scanner.Text() + if !strings.HasPrefix(line, "\t") { + paragraph = strings.TrimSpace(line) + continue + } + idx := strings.Index(line, ":") + if idx < 0 { + continue + } + name := strings.TrimSpace(line[0:idx]) + value := strings.TrimSpace(line[idx+1:]) + switch paragraph + ":" + name { + case "System Information:Manufacturer": + ret.Vendor = value + case "System Information:Product Name": + ret.Model = value + case "System Information:Version": + ret.Version = value + case "Chassis Information:Type": + ret.IsLaptop = (value == "Notebook" || value == "Laptop") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) { + for codecno := 0; codecno < 10; codecno++ { + cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}} + codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer codec.Close() + pin, err := os.Open(l.InputDirectory + "/pin_hwC0D" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer pin.Close() + + scanner := bufio.NewScanner(codec) + for scanner.Scan() { + line := scanner.Text() + if strings.HasPrefix(line, "Codec:") { + fmt.Sscanf(line, "Codec: %s", &cur.Name) + continue + } + if strings.HasPrefix(line, "Vendor Id:") { + fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID) + continue + } + if strings.HasPrefix(line, "Subsystem Id:") { + fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID) + continue + } + } + + scanner = bufio.NewScanner(pin) + for scanner.Scan() { + line := scanner.Text() + addr := 0 + val := uint32(0) + fmt.Sscanf(line, "0x%x 0x%x", &addr, &val) + cur.PinConfig[addr] = val + } + ret = append(ret, cur) + } + return +} + +func (l *LogDevReader) GetCPUModel() (ret []uint32) { + file, err := os.Open(l.InputDirectory + "/cpuinfo.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + ret = make([]uint32, 0, 100) + proc := 0 + for scanner.Scan() { + line := scanner.Text() + sep := strings.Index(line, ":") + if sep < 0 { + continue + } + key := strings.TrimSpace(line[0:sep]) + val := strings.TrimSpace(line[sep+1:]) + + if key == "processor" { + proc, _ := strconv.Atoi(val) + if len(ret) <= proc { + ret = ret[0 : proc+1] + } + continue + } + if key == "cpu family" { + family, _ := strconv.Atoi(val) + ret[proc] |= uint32(((family & 0xf) << 8) | ((family & 0xff0) << 16)) + } + if key == "model" { + model, _ := strconv.Atoi(val) + ret[proc] |= uint32(((model & 0xf) << 4) | ((model & 0xf0) << 12)) + } + if key == "stepping" { + stepping, _ := strconv.Atoi(val) + ret[proc] |= uint32(stepping & 0xf) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +var FlagLogInput = flag.String("input_log", ".", "Input log directory") +var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs") + +func MakeLogReader() *LogDevReader { + if *FlagLogMkLogs { + MakeLogs(*FlagLogInput) + } + return &LogDevReader{InputDirectory: *FlagLogInput} +} diff --git a/util/autoport/main.go b/util/autoport/main.go new file mode 100644 index 0000000..4d28465 --- /dev/null +++ b/util/autoport/main.go @@ -0,0 +1,607 @@ +/* This is just an experiment. Full automatic porting + is probably not possible but a lot can be automated. */ +package main + +import ( + "flag" + "fmt" + "log" + "os" + "sort" + "strings" +) + +type PCIAddr struct { + Bus int + Dev int + Func int +} + +type PCIDevData struct { + PCIAddr + PCIVenID uint16 + PCIDevID uint16 + ConfigDump []uint8 +} + +type PCIDevice interface { + Scan(ctx Context, addr PCIDevData) +} + +type InteltoolData struct { + GPIO map[uint16]uint32 + RCBA map[uint16]uint32 +} + +type DMIData struct { + Vendor string + Model string + Version string + IsLaptop bool +} + +type AzaliaCodec struct { + Name string + VendorID uint32 + SubsystemID uint32 + CodecNo int + PinConfig map[int]uint32 +} + +type DevReader interface { + GetPCIList() []PCIDevData + GetDMI() DMIData + GetInteltool() InteltoolData + GetAzaliaCodecs() []AzaliaCodec + GetACPI() map[string][]byte + GetCPUModel() []uint32 +} + +var ROMStageFiles map[string]string = map[string]string{} +var RAMStageFiles map[string]string = map[string]string{} + +type Context struct { + MoboID string + KconfigName string + Vendor string + Model string + BaseDirectory string + InfoSource DevReader +} + +type IOAPICIRQ struct { + APICID int + IRQNO [4]int +} + +var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} +var KconfigBool map[string]bool = map[string]bool{} +var KconfigString map[string]string = map[string]string{} +var KconfigStringUnquoted map[string]string = map[string]string{} +var KconfigHex map[string]uint32 = map[string]uint32{} +var KconfigInt map[string]int = map[string]int{} + +func FormatHexLE16(inp []byte) string { + return fmt.Sprintf("0x%04x", uint16(inp[0])|(uint16(inp[1])<<8)) +} + +func FormatBool(inp bool) string { + if inp { + return "1" + } else { + return "0" + } +} + +func sanitize(inp string) string { + result := strings.ToLower(inp) + result = strings.Replace(result, " ", "_", -1) + result = strings.Replace(result, ",", "_", -1) + for strings.HasSuffix(result, ".") { + result = result[0 : len(result)-1] + } + return result +} + +func AddROMStageFile(Name string, Condition string) { + ROMStageFiles[Name] = Condition +} + +func AddRAMStageFile(Name string, Condition string) { + RAMStageFiles[Name] = Condition +} + +var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory") + +func writeMF(mf *os.File, files map[string]string, category string) { + for file, condition := range files { + if condition == "" { + fmt.Fprintf(mf, "%s-y += %s\n", category, file) + } else { + fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, + condition, file) + } + } +} + +func Create(ctx Context, name string) *os.File { + li := strings.LastIndex(name, "/") + if li > 0 { + os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700) + } + mf, err := os.Create(ctx.BaseDirectory + "/" + name) + if err != nil { + log.Fatal(err) + } + return mf +} + +func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+3], + pcidev.ConfigDump[addr+2], + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) { + fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) +} + +type PCISlot struct { + PCIAddr + additionalComment string + writeEmpty bool +} + +type DevTreeNode struct { + Bus int + Dev int + Func int + Disabled bool + Registers map[string]string + Children []DevTreeNode + PCISlots []PCISlot + PCIController bool + ChildPCIBus int + MissingParent string + SubVendor uint16 + SubSystem uint16 + Chip string + Comment string +} + +var DevTree DevTreeNode +var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{} +var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} +var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} + +func Offset(dt *os.File, offset int) { + for i := 0; i < offset; i++ { + fmt.Fprintf(dt, "\t") + } +} + +func MatchDev(dev *DevTreeNode) { + for idx := range dev.Children { + MatchDev(&dev.Children[idx]) + } + + for _, slot := range dev.PCISlots { + slotChip, ok := unmatchedPCIChips[slot.PCIAddr] + + if !ok { + continue + } + + if slot.additionalComment != "" && slotChip.Comment != "" { + slotChip.Comment = slot.additionalComment + " " + slotChip.Comment + } else { + slotChip.Comment = slot.additionalComment + slotChip.Comment + } + + delete(unmatchedPCIChips, slot.PCIAddr) + MatchDev(&slotChip) + dev.Children = append(dev.Children, slotChip) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIChips { + if slot.Bus == dev.ChildPCIBus { + delete(unmatchedPCIChips, slot) + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + } + } + } + + for _, slot := range dev.PCISlots { + slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] + if !ok { + if slot.writeEmpty { + dev.Children = append(dev.Children, + DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: slot.Bus, + Dev: slot.Dev, + Func: slot.Func, + Comment: slot.additionalComment, + Disabled: true, + }, + ) + } + continue + } + + if slot.additionalComment != "" && slotDev.Comment != "" { + slotDev.Comment = slot.additionalComment + " " + slotDev.Comment + } else { + slotDev.Comment = slot.additionalComment + slotDev.Comment + } + + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot.PCIAddr) + } + + if dev.MissingParent != "" { + for _, child := range MissingChildren[dev.MissingParent] { + MatchDev(&child) + dev.Children = append(dev.Children, child) + } + delete(MissingChildren, dev.MissingParent) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIDevices { + if slot.Bus == dev.ChildPCIBus { + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot) + } + } + } +} + +func writeOn(dt *os.File, dev DevTreeNode) { + if dev.Disabled { + fmt.Fprintf(dt, "off") + } else { + fmt.Fprintf(dt, "on") + } +} + +func WriteDev(dt *os.File, offset int, dev DevTreeNode) { + Offset(dt, offset) + switch dev.Chip { + case "cpu_cluster", "lapic", "domain", "ioapic": + fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + case "pci": + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + writeOn(dt, dev) + default: + fmt.Fprintf(dt, "chip %s", dev.Chip) + } + if dev.Comment != "" { + fmt.Fprintf(dt, " # %s", dev.Comment) + } + fmt.Fprintf(dt, "\n") + if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem) + } + + ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}] + if dev.Chip == "pci" && ok { + for pin, irq := range ioapic.IRQNO { + if irq != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq) + } + } + } + + keys := []string{} + for reg, _ := range dev.Registers { + keys = append(keys, reg) + } + + sort.Strings(keys) + + for _, reg := range keys { + val := dev.Registers[reg] + Offset(dt, offset+1) + fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val) + } + + for _, child := range dev.Children { + WriteDev(dt, offset+1, child) + } + + Offset(dt, offset) + fmt.Fprintf(dt, "end\n") +} + +func PutChip(domain string, cur DevTreeNode) { + MissingChildren[domain] = append(MissingChildren[domain], cur) +} + +func PutPCIChip(addr PCIDevData, cur DevTreeNode) { + unmatchedPCIChips[addr.PCIAddr] = cur +} + +func PutPCIDevParent(addr PCIDevData, comment string, parent string) { + cur := DevTreeNode{ + Registers: map[string]string{}, + SubVendor: uint16(addr.ConfigDump[0x2c]) | (uint16(addr.ConfigDump[0x2d]) << 8), + SubSystem: uint16(addr.ConfigDump[0x2e]) | (uint16(addr.ConfigDump[0x2f]) << 8), + Chip: "pci", + Bus: addr.Bus, + Dev: addr.Dev, + Func: addr.Func, + MissingParent: parent, + Comment: comment, + } + if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 { + cur.PCIController = true + cur.ChildPCIBus = int(addr.ConfigDump[0x19]) + } + unmatchedPCIDevices[addr.PCIAddr] = cur +} + +func PutPCIDev(addr PCIDevData, comment string) { + PutPCIDevParent(addr, comment, "") +} + +type GenericPCI struct { + Comment string + Bus0Subdiv string + MissingParent string +} + +type GenericVGA struct { + GenericPCI +} + +type DSDTInclude struct { + Comment string + File string +} + +var DSDTIncludes []DSDTInclude +var DSDTPCI0Includes []DSDTInclude + +func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { + KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x", + addr.PCIVenID, + addr.PCIDevID) + KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom", + addr.PCIVenID, + addr.PCIDevID) + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func makeKconfig(ctx Context) { + kc := Create(ctx, "Kconfig") + defer kc.Close() + + fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName) + + fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n") + keys := []string{} + for name, val := range KconfigBool { + if val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, "\tselect %s\n", name) + } + + keys = nil + for name, val := range KconfigBool { + if !val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + string + default n +`, name) + } + + keys = nil + for name, _ := range KconfigStringUnquoted { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + string + default %s +`, name, KconfigStringUnquoted[name]) + } + + keys = nil + for name, _ := range KconfigString { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + string + default "%s" +`, name, KconfigString[name]) + } + + keys = nil + for name, _ := range KconfigHex { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + hex + default 0x%x +`, name, KconfigHex[name]) + } + + keys = nil + for name, _ := range KconfigInt { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s + int + default %d +`, name, KconfigInt[name]) + } + + fmt.Fprintf(kc, "endif\n") +} + +func main() { + flag.Parse() + + ctx := Context{} + + ctx.InfoSource = MakeLogReader() + + dmi := ctx.InfoSource.GetDMI() + + ctx.Vendor = dmi.Vendor + + if dmi.Vendor == "LENOVO" { + ctx.Model = dmi.Version + } else { + ctx.Model = dmi.Model + } + + if dmi.IsLaptop { + KconfigBool["SYSTEM_TYPE_LAPTOP"] = true + } + ctx.MoboID = sanitize(ctx.Vendor) + "/" + sanitize(ctx.Model) + ctx.KconfigName = "BOARD_" + strings.ToUpper(sanitize(ctx.Vendor)+"_"+sanitize(ctx.Model)) + ctx.BaseDirectory = *FlagOutDir + "/src/mainboard/" + ctx.MoboID + KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model + + /* Only x86 currently. */ + KconfigBool["ARCH_X86"] = true + + /* FIXME: hardcoded. */ + KconfigBool["BOARD_ROMSIZE_KB_2048"] = true + + os.MkdirAll(ctx.BaseDirectory, 0700) + + ScanRoot(ctx) + + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 { + mf := Create(ctx, "Makefile.inc") + defer mf.Close() + writeMF(mf, ROMStageFiles, "romstage") + writeMF(mf, RAMStageFiles, "ramstage") + } + + devtree := Create(ctx, "devicetree.cb") + defer devtree.Close() + + MatchDev(&DevTree) + WriteDev(devtree, 0, DevTree) + + bi := Create(ctx, "board_info.txt") + defer bi.Close() + + if dmi.IsLaptop { + bi.WriteString("Category: laptop") + } else { + /* FIXME: other categories. */ + bi.WriteString("Category: desktop") + } + + rs := Create(ctx, "romstage.c") + defer rs.Close() + rs.WriteString("/* dummy file */\n") + + /* FIXME: flash chip. */ + + makeKconfig(ctx) + + dsdt := Create(ctx, "dsdt.asl") + defer dsdt.Close() + + dsdt.WriteString( + `DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" +`) + + for _, x := range DSDTIncludes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File) + } + + dsdt.WriteString(` + Scope (\_SB) { + Device (PCI0) + { +`) + /* FIXME: use scoping at another level. */ + for _, x := range DSDTPCI0Includes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + } + dsdt.WriteString( + ` } + } +} +`) + +} diff --git a/util/autoport/rce823.go b/util/autoport/rce823.go new file mode 100644 index 0000000..07002f5 --- /dev/null +++ b/util/autoport/rce823.go @@ -0,0 +1,39 @@ +package main + +import "fmt" + +type rce823 struct { + variant string +} + +func (r rce823) Scan(ctx Context, addr PCIDevData) { + if addr.Dev == 0 && addr.Func == 0 { + cur := DevTreeNode{ + Chip: "drivers/ricoh/rce822", + Comment: "Ricoh cardreader", + Registers: map[string]string{ + + "sdwppol": fmt.Sprintf("%d", (addr.ConfigDump[0xfb]&2)>>1), + "disable_mask": fmt.Sprintf("0x%x", addr.ConfigDump[0xcb]), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 0}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 1}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 2}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 3}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 4}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 5}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 6}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 7}, writeEmpty: false}, + }, + } + PutPCIChip(addr, cur) + } + PutPCIDev(addr, "Ricoh SD card reader") + +} + +func init() { + RegisterPCI(0x1180, 0xe822, rce823{}) + RegisterPCI(0x1180, 0xe823, rce823{}) +} diff --git a/util/autoport/root.go b/util/autoport/root.go new file mode 100644 index 0000000..60b5ccd --- /dev/null +++ b/util/autoport/root.go @@ -0,0 +1,29 @@ +package main + +import "fmt" + +var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{} +var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{} + +func ScanRoot(ctx Context) { + for _, pciDev := range ctx.InfoSource.GetPCIList() { + PCIMap[pciDev.PCIAddr] = pciDev + } + for _, pciDev := range ctx.InfoSource.GetPCIList() { + vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID) + + dev, ok := supportedPCIDevices[vendevid] + if !ok { + fmt.Printf("Unsupported PCI device %04x:%04x\n", + pciDev.PCIVenID, pciDev.PCIDevID) + dev = GenericPCI{Comment: fmt.Sprintf("Unsupported PCI device %04x:%04x", + pciDev.PCIVenID, pciDev.PCIDevID)} + } + dev.Scan(ctx, pciDev) + } +} + +func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) { + vendevid := (uint32(DevID) << 16) | uint32(VenID) + supportedPCIDevices[vendevid] = dev +} diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go new file mode 100644 index 0000000..daabacf --- /dev/null +++ b/util/autoport/sandybridge.go @@ -0,0 +1,113 @@ +package main + +type sandybridgemc struct { + variant string +} + +func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/sandybridge", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_dp_d_hotplug": "0x06", + "gpu_panel_port_select": "0", + "gpu_panel_power_cycle_delay": "5", + "gpu_panel_power_up_delay": "300", + "gpu_panel_power_down_delay": "300", + "gpu_panel_power_backlight_on_delay": "2000", + "gpu_panel_power_backlight_off_delay": "2000", + "gfx.use_spread_spectrum_clock": "1", + "gfx.lvds_dual_channel": "0", + "gfx.link_frequency_270_mhz": "1", + "gfx.lvds_num_lanes": "4", + "gpu_cpu_backlight": "0x1155", + "gpu_pch_backlight": "0x06100610", + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_rPGA989", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + + { + Chip: "cpu/intel/model_206ax", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "pstate_coord_type": "0xfe", + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + }, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool[i.variant+"BRIDGE_LVDS"] = true + + KconfigBool["VGA"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true + KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigBool["HAVE_IFD_BIN"] = false + KconfigBool["HAVE_ME_BIN"] = false + + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_206ax/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"}) + RegisterPCI(0x8086, 0x0166, GenericVGA{GenericPCI{Comment: "VGA controller"}}) +}

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New patch to review for coreboot: 9c58c23 aarch64: Add aarch64-elf toolchain to crossgcc Makefile
by Marc Jones 05 Dec '14

05 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7661 -gerrit commit 9c58c234b9fe2427d321188d603b0e1fe06c1773 Author: Marcelo Povoa <marcelogp(a)chromium.org> Date: Thu Feb 13 11:39:21 2014 -0800 aarch64: Add aarch64-elf toolchain to crossgcc Makefile BUG=None BRANCH=none TEST=Build crosgcc for aarch64-elf Signed-off-by: Marcelo Povoa <marcelogp(a)chromium.org> Original-Change-Id: Ifc886b6bd125552855ad1cf49ee7c1b7a0350895 Original-Reviewed-on: https://chromium-review.googlesource.com/186413 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Tested-by: Marcelo Póvoa <marcelogp(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: Marcelo Póvoa <marcelogp(a)chromium.org> (cherry picked from commit 9959047c82c96108f4bdedad1db0219fcdc85378) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5e781443bb11a7db3420bb8cfc447de8494b1d24 --- util/crossgcc/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index bd7fa2f..22a10ba 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -5,6 +5,7 @@ build-i386: build-armv7a: bash ./buildgcc -G -p armv7a-eabi + bash ./buildgcc -G -p aarch64-elf build-aarch64: bash ./buildgcc -G -p aarch64-elf @@ -16,6 +17,7 @@ build-i386-without-gdb: .PHONY: build-armv7a-without-gdb build-armv7a-without-gdb: bash ./buildgcc -p armv7a-eabi + bash ./buildgcc -p aarch64-elf .PHONY: build-aarch64-without-gdb build-aarch64-without-gdb:

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coreboot-gerrit December 2014