coreboot-gerrit December 2014

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Patch set updated for coreboot: 6b69a03 intel/minnowmax: Update devicetree
by Martin Roth 06 Dec '14

06 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7663 -gerrit commit 6b69a034946e5da03ac64a6321a095341644c427 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Dec 5 14:55:07 2014 -0700 intel/minnowmax: Update devicetree - Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable function 1c.0 so the rest of the functions will be seen, even though the function is not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/minnowmax/devicetree.cb | 50 ++++++++++++++--------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 72849d6..6e456cb 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -21,8 +21,8 @@ chip soc/intel/fsp_baytrail #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" #### FSP register settings #### register "PcdSataMode" = "SATA_MODE_AHCI" @@ -34,25 +34,25 @@ chip soc/intel/fsp_baytrail register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" register "PcdGttSize" = "GTT_SIZE_DEFAULT" register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" - register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" - register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" - register "DRAMType" = "DRAM_TYPE_DDR3L" - register "DIMM0Enable" = "DIMM0_ENABLE" - register "DIMM1Enable" = "DIMM1_DISABLE" - register "DIMMDWidth" = "DIMM_DWIDTH_X16" - register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" - register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" - register "DIMMSides" = "DIMM_SIDES_1RANK" - register "DIMMtCL" = "11" - register "DIMMtRPtRCD" = "11" - register "DIMMtWR" = "12" - register "DIMMtWTR" = "6" - register "DIMMtRRD" = "6" - register "DIMMtRTP" = "6" - register "DIMMtFAW" = "20" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "11" + register "DIMMtRPtRCD" = "11" + register "DIMMtWR" = "12" + register "DIMMtWTR" = "6" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "6" + register "DIMMtFAW" = "20" device cpu_cluster 0 on device lapic 0 on end @@ -67,12 +67,12 @@ chip soc/intel/fsp_baytrail device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC - device pci 14.0 on end # 8086 0F35 - USB XHCI Onboard & HSEC + device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC device pci 17.0 off end # 8086 0F50 - MMC Port - device pci 18.0 on end # 8086 0F40 - SIO - DMA - device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) - - device pci 18.2 off end # 8086 0F42 - I2C Port 2 (1) - (testpoints) + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints) device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) - device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) - device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) - @@ -80,11 +80,11 @@ chip soc/intel/fsp_baytrail device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC device pci 1a.0 on end # 8086 0F18 - TXE - device pci 1b.0 off end # 8086 0F04 - HD Audio - - device pci 1c.0 off end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC - device pci 1d.0 off end # 8086 0F34 - USB EHCI - + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 1e.0 on end # 8086 0F06 - SIO - DMA - device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC

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Patch merged into coreboot/master: d2e5f68 southbridge/hudson: Disable USB controllers if devicetree says so
by gerrit＠coreboot.org 06 Dec '14

06 Dec '14

the following patch was just integrated into master: commit d2e5f6815e72ca1e52f5f08aa97dfabbd0ecbf67 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Apr 16 16:33:03 2014 -0500 southbridge/hudson: Disable USB controllers if devicetree says so Change-Id: I009a01d3324d48d2eeda87d74c8e3e7c27958ee2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5525 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5525 for details. -gerrit

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Patch set updated for coreboot: a98a0c6 southbridge/hudson: Disable USB controllers if devicetree says so
by Alexandru Gagniuc 06 Dec '14

06 Dec '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5525 -gerrit commit a98a0c68c41cd45f3a04e22847be7503e63f8811 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Apr 16 16:33:03 2014 -0500 southbridge/hudson: Disable USB controllers if devicetree says so Change-Id: I009a01d3324d48d2eeda87d74c8e3e7c27958ee2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/southbridge/amd/agesa/hudson/hudson.c | 48 ++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 3b57221..d5f11dc 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -82,11 +82,34 @@ u16 pm_read16(u16 reg) return read16(PM_MMIO_BASE + reg); } +#define PM_REG_USB_ENABLE 0xef + +enum usb_enable { + USB_EN_DEVFN_12_0 = (1 << 0), + USB_EN_DEVFN_12_2 = (1 << 1), + USB_EN_DEVFN_13_0 = (1 << 2), + USB_EN_DEVFN_13_2 = (1 << 3), + USB_EN_DEVFN_16_0 = (1 << 4), + USB_EN_DEVFN_16_2 = (1 << 5), +}; + +static void hudson_disable_usb(u8 disable) +{ + u8 reg8; + + /* Bit 7 handles routing, 6 is reserved. we don't mess with those */ + disable &= 0x3f; + + reg8 = pm_read8(PM_REG_USB_ENABLE); + reg8 &= ~disable; + pm_write8(PM_REG_USB_ENABLE, reg8); +} + void hudson_enable(device_t dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); switch (dev->path.pci.devfn) { - case (0x14 << 3) | 7: /* 0:14.7 SD */ + case PCI_DEVFN(0x14, 7): if (dev->enabled == 0) { // read the VENDEV ID device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7)); @@ -109,6 +132,29 @@ void hudson_enable(device_t dev) pm_write8(0xd3, reg8); } break; + + /* Make sure to disable other functions if function 0 is disabled */ + case PCI_DEVFN(0x12, 0): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_12_0); + case PCI_DEVFN(0x12, 2): /* Fall through */ + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_12_2); + break; + case PCI_DEVFN(0x13, 0): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_13_0); + case PCI_DEVFN(0x13, 2): /* Fall through */ + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_13_2); + break; + case PCI_DEVFN(0x16, 0): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_16_0); + case PCI_DEVFN(0x16, 2): /* Fall through */ + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_16_2); + break; default: break; }

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Patch set updated for coreboot: 92aa344 southbridge/hudson: Disable USB controllers if devicetree says so
by Alexandru Gagniuc 06 Dec '14

06 Dec '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5525 -gerrit commit 92aa3447d16cbe483decada9fb65e40efa4cf0d7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Apr 16 16:33:03 2014 -0500 southbridge/hudson: Disable USB controllers if devicetree says so Change-Id: I009a01d3324d48d2eeda87d74c8e3e7c27958ee2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/southbridge/amd/agesa/hudson/hudson.c | 49 ++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 3b57221..86e641d 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -82,11 +82,34 @@ u16 pm_read16(u16 reg) return read16(PM_MMIO_BASE + reg); } +#define PM_REG_USB_ENABLE 0xef + +enum usb_enable { + USB_EN_DEVFN_12_0 = (1 << 0), + USB_EN_DEVFN_12_2 = (1 << 1), + USB_EN_DEVFN_13_0 = (1 << 2), + USB_EN_DEVFN_13_2 = (1 << 3), + USB_EN_DEVFN_16_0 = (1 << 4), + USB_EN_DEVFN_16_2 = (1 << 5), +}; + +static void hudson_disable_usb(u8 disable) +{ + u8 reg8; + + /* Bit 7 handles routing, 6 is reserved. we don't mess with those */ + disable &= 0x3f; + + reg8 = pm_read8(PM_REG_USB_ENABLE); + reg8 &= ~disable; + pm_write8(PM_REG_USB_ENABLE, reg8); +} + void hudson_enable(device_t dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); switch (dev->path.pci.devfn) { - case (0x14 << 3) | 7: /* 0:14.7 SD */ + case PCI_DEVFN(0x14, 7): if (dev->enabled == 0) { // read the VENDEV ID device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7)); @@ -109,6 +132,30 @@ void hudson_enable(device_t dev) pm_write8(0xd3, reg8); } break; + case PCI_DEVFN(0x12, 0): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_12_0); + break; + case PCI_DEVFN(0x12, 2): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_12_2); + break; + case PCI_DEVFN(0x13, 0): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_13_0); + break; + case PCI_DEVFN(0x13, 2): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_13_2); + break; + case PCI_DEVFN(0x16, 0): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_16_0); + break; + case PCI_DEVFN(0x16, 2): + if (dev->enabled == 0) + hudson_disable_usb(USB_EN_DEVFN_16_2); + break; default: break; }

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Patch set updated for coreboot: a1b74e5 intel/minnowmax: Update devicetree
by Martin Roth 06 Dec '14

06 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7663 -gerrit commit a1b74e5b717c542815d990d2dfd7a092b443072d Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Dec 5 14:55:07 2014 -0700 intel/minnowmax: Update devicetree - Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable function 1c.0 so the rest of the functions will be seen, even though the function is not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/minnowmax/devicetree.cb | 50 ++++++++++++++--------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 72849d6..6e456cb 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -21,8 +21,8 @@ chip soc/intel/fsp_baytrail #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" #### FSP register settings #### register "PcdSataMode" = "SATA_MODE_AHCI" @@ -34,25 +34,25 @@ chip soc/intel/fsp_baytrail register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" register "PcdGttSize" = "GTT_SIZE_DEFAULT" register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" - register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" - register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" - register "DRAMType" = "DRAM_TYPE_DDR3L" - register "DIMM0Enable" = "DIMM0_ENABLE" - register "DIMM1Enable" = "DIMM1_DISABLE" - register "DIMMDWidth" = "DIMM_DWIDTH_X16" - register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" - register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" - register "DIMMSides" = "DIMM_SIDES_1RANK" - register "DIMMtCL" = "11" - register "DIMMtRPtRCD" = "11" - register "DIMMtWR" = "12" - register "DIMMtWTR" = "6" - register "DIMMtRRD" = "6" - register "DIMMtRTP" = "6" - register "DIMMtFAW" = "20" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "11" + register "DIMMtRPtRCD" = "11" + register "DIMMtWR" = "12" + register "DIMMtWTR" = "6" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "6" + register "DIMMtFAW" = "20" device cpu_cluster 0 on device lapic 0 on end @@ -67,12 +67,12 @@ chip soc/intel/fsp_baytrail device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC - device pci 14.0 on end # 8086 0F35 - USB XHCI Onboard & HSEC + device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC device pci 17.0 off end # 8086 0F50 - MMC Port - device pci 18.0 on end # 8086 0F40 - SIO - DMA - device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) - - device pci 18.2 off end # 8086 0F42 - I2C Port 2 (1) - (testpoints) + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints) device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) - device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) - device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) - @@ -80,11 +80,11 @@ chip soc/intel/fsp_baytrail device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC device pci 1a.0 on end # 8086 0F18 - TXE - device pci 1b.0 off end # 8086 0F04 - HD Audio - - device pci 1c.0 off end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC - device pci 1d.0 off end # 8086 0F34 - USB EHCI - + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 1e.0 on end # 8086 0F06 - SIO - DMA - device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC

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New patch to review for coreboot: 163f9b4 intel/minnowmax: Update devicetree
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7663 -gerrit commit 163f9b4753b915a846a4f42e86c4263fa4a6b97b Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Dec 5 14:55:07 2014 -0700 intel/minnowmax: Update devicetree - Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable functions 18.0 and 1c.0 so the rest of the functions will be seen, even though those two functions are not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/minnowmax/devicetree.cb | 52 ++++++++++++++--------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 72849d6..badb6b7 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -21,8 +21,8 @@ chip soc/intel/fsp_baytrail #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" #### FSP register settings #### register "PcdSataMode" = "SATA_MODE_AHCI" @@ -34,25 +34,25 @@ chip soc/intel/fsp_baytrail register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" register "PcdGttSize" = "GTT_SIZE_DEFAULT" register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" - register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" - register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" - register "DRAMType" = "DRAM_TYPE_DDR3L" - register "DIMM0Enable" = "DIMM0_ENABLE" - register "DIMM1Enable" = "DIMM1_DISABLE" - register "DIMMDWidth" = "DIMM_DWIDTH_X16" - register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" - register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" - register "DIMMSides" = "DIMM_SIDES_1RANK" - register "DIMMtCL" = "11" - register "DIMMtRPtRCD" = "11" - register "DIMMtWR" = "12" - register "DIMMtWTR" = "6" - register "DIMMtRRD" = "6" - register "DIMMtRTP" = "6" - register "DIMMtFAW" = "20" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "11" + register "DIMMtRPtRCD" = "11" + register "DIMMtWR" = "12" + register "DIMMtWTR" = "6" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "6" + register "DIMMtFAW" = "20" device cpu_cluster 0 on device lapic 0 on end @@ -67,12 +67,12 @@ chip soc/intel/fsp_baytrail device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC - device pci 14.0 on end # 8086 0F35 - USB XHCI Onboard & HSEC + device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC device pci 17.0 off end # 8086 0F50 - MMC Port - device pci 18.0 on end # 8086 0F40 - SIO - DMA - - device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) - - device pci 18.2 off end # 8086 0F42 - I2C Port 2 (1) - (testpoints) + device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) - + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints) device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) - device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) - device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) - @@ -80,11 +80,11 @@ chip soc/intel/fsp_baytrail device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC device pci 1a.0 on end # 8086 0F18 - TXE - device pci 1b.0 off end # 8086 0F04 - HD Audio - - device pci 1c.0 off end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC - device pci 1d.0 off end # 8086 0F34 - USB EHCI - + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 1e.0 on end # 8086 0F06 - SIO - DMA - device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC

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New patch to review for coreboot: d303110 i82801gx: Reserve LPC decodes.
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7662 -gerrit commit d303110dc2f14b0a3fc198c672135f427cfe8899 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Nov 24 21:05:56 2014 +0100 i82801gx: Reserve LPC decodes. Makes sure that LPC controller declares resources that it actually decodes. bd82x6x already does it but i82801gx doesn't leading to allocator potentially allocating something else to the same range. Change-Id: Ieca9852e54c08e31d4d41aea97f317d9a6919806 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801gx/lpc.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index de02686..b40dc4b 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -603,18 +603,20 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) static void i82801gx_lpc_read_resources(device_t dev) { struct resource *res; + u8 io_index = 0; + int i; /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | @@ -624,6 +626,20 @@ static void i82801gx_lpc_read_resources(device_t dev) res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Set IO decode ranges if required.*/ + for (i = 0; i < 4; i++) { + u32 gen_dec; + gen_dec = pci_read_config32(dev, 0x84 + 4 * i); + + if ((gen_dec & 0xFFFC) > 0x1000) { + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = gen_dec & 0xFFFC; + res->size = (gen_dec >> 16) & 0xFC; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + } } static void set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch set updated for coreboot: fefddf9 i945: Move SLIT and SRAT filling to northbridge code
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7109 -gerrit commit fefddf98def28606729ebca0e2ba5e7b1fd88960 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 18 02:24:00 2014 +0200 i945: Move SLIT and SRAT filling to northbridge code Change-Id: Ic7c50539cf72ab5db3f3c38a6f0dd0b205a9c2d0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/acpi_tables.c | 12 ------------ src/mainboard/getac/p470/acpi_tables.c | 12 ------------ src/mainboard/ibase/mb899/acpi_tables.c | 13 ------------- src/mainboard/intel/d945gclf/acpi_tables.c | 12 ------------ src/mainboard/kontron/986lcd-m/acpi_tables.c | 12 ------------ src/mainboard/lenovo/t60/acpi_tables.c | 12 ------------ src/mainboard/lenovo/x60/acpi_tables.c | 12 ------------ src/mainboard/roda/rk886ex/acpi_tables.c | 12 ------------ src/northbridge/intel/i945/acpi.c | 12 ++++++++++++ 9 files changed, 12 insertions(+), 97 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index f8b2246..48c6f89 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -45,15 +45,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[3] = 0x80000410; gnvs->did[4] = 0x00000005; } - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index f684808..3e8abe5 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -94,18 +94,6 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt) return header->length; } -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - #define ALIGN_CURRENT current = (ALIGN(current, 16)) unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) { diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index 24e3d35..54ee4f6 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -44,16 +44,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[3] = 0x80000410; gnvs->did[4] = 0x00000005; } - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index 965fd86..629a044 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -34,15 +34,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) { } - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 322ac0e..54ee4f6 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -44,15 +44,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[3] = 0x80000410; gnvs->did[4] = 0x00000005; } - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index f8b2246..48c6f89 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -45,15 +45,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[3] = 0x80000410; gnvs->did[4] = 0x00000005; } - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index f8b2246..48c6f89 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -45,15 +45,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[3] = 0x80000410; gnvs->did[4] = 0x00000005; } - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index f8b2246..48c6f89 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -45,15 +45,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[3] = 0x80000410; gnvs->did[4] = 0x00000005; } - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 6e89bd8..71235e1 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -74,3 +74,15 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +}

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Patch set updated for coreboot: 1afcc89 i945: Consolidate MADT handling
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7108 -gerrit commit 1afcc891818cc3be1dd3ff00a3eb2c6da77281e0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 18 02:13:11 2014 +0200 i945: Consolidate MADT handling Change-Id: Ic3cdfa6086a45aa231aa817d5ef6998823589818 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/acpi_tables.c | 28 --------------------------- src/mainboard/getac/p470/acpi_tables.c | 24 ----------------------- src/mainboard/ibase/mb899/acpi_tables.c | 18 ----------------- src/mainboard/intel/d945gclf/acpi_tables.c | 18 ----------------- src/mainboard/kontron/986lcd-m/acpi_tables.c | 18 ----------------- src/mainboard/lenovo/t60/acpi_tables.c | 28 --------------------------- src/mainboard/lenovo/x60/acpi_tables.c | 28 --------------------------- src/mainboard/roda/rk886ex/acpi_tables.c | 28 --------------------------- src/southbridge/intel/i82801gx/lpc.c | 29 ++++++++++++++++++++++++++++ 9 files changed, 29 insertions(+), 190 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index c890677..f8b2246 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -46,34 +46,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index d421101..f684808 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -94,30 +94,6 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt) return header->length; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, 0x0005, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, 0x0005, 0x01); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index dba2953..24e3d35 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -45,24 +45,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index 35c23a5..965fd86 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -35,24 +35,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) { } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 2e775ae..322ac0e 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -45,24 +45,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index c890677..f8b2246 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -46,34 +46,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index c890677..f8b2246 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -46,34 +46,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index c890677..f8b2246 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -46,34 +46,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4e4c6ba..22ffd7f 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -32,6 +32,7 @@ #include "i82801gx.h" #include <cpu/x86/smm.h> #include <arch/acpigen.h> +#include <arch/smp/mpspec.h> #include <cbmem.h> #include <string.h> #include "nvs.h" @@ -450,6 +451,34 @@ static void lpc_init(struct device *dev) i82801gx_fixups(dev); } +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} + void acpi_fill_fadt(acpi_fadt_t * fadt) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));

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Patch set updated for coreboot: 1787f2b kontron/986lcd-m: Fix PCI interrupt routing.
by Vladimir Serbinenko 05 Dec '14

05 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7477 -gerrit commit 1787f2b2ee96e66a2bdacb6aa65b1304129dc94a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Nov 15 20:40:04 2014 +0100 kontron/986lcd-m: Fix PCI interrupt routing. The current interrupt routing shares interrupt 5 between LPC and PCI which isn't possible. Use IRQ 11 for all devices in PCI mode. Move conflicting LPC to free IRQ. Change-Id: I3ac8c2f19195ef6b07f4ee7dde64dd038d024126 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/kontron/986lcd-m/devicetree.cb | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index dee2fda..6a5b221 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -13,14 +13,14 @@ chip northbridge/intel/i945 device pci 02.1 on end # display controller chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" # GPI routing # 0 No effect (default) @@ -101,11 +101,11 @@ chip northbridge/intel/i945 end device pnp 4e.2 on # COM3 io 0x60 = 0x3e8 - irq 0x70 = 11 + irq 0x70 = 6 end device pnp 4e.3 on # COM4 io 0x60 = 0x2e8 - irq 0x70 = 10 + irq 0x70 = 6 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq end device pnp 4e.5 off # Keyboard

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coreboot-gerrit December 2014