coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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1346 discussions

Patch merged into coreboot/master: f5c463f mainboard/*/acpi/superio.asl: Use non-local inclusion syntax
by gerrit＠coreboot.org 06 Dec '14

06 Dec '14

the following patch was just integrated into master: commit f5c463f5e6458ea45b9f3461f94800f9c87feea1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Dec 6 13:58:51 2014 +1100 mainboard/*/acpi/superio.asl: Use non-local inclusion syntax Use non-local inclusion syntax over relative paths for 'drivers/pc80/ps2_controller.asl'. Change-Id: Ie2bfa893dc268ec5118d2a9addadbc759d85d357 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7664 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7664 for details. -gerrit

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Patch merged into coreboot/master: 986349d vendorcode/amd/agesa/fam15tn: Clean #includes in public headers
by gerrit＠coreboot.org 06 Dec '14

06 Dec '14

the following patch was just integrated into master: commit 986349df6492068a7f01fdfd8a6e65b93eb1bc17 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 16:52:46 2014 -0500 vendorcode/amd/agesa/fam15tn: Clean #includes in public headers Right now, coreboot code using AGESA headers can only build if all the AGESA path are given to the compiler via the "-I" option. This is sub- optimal, as it requires us to have every AGESA source directory specified as a compiler include path. This pollutes our global include paths. We restrict the compiler include paths to only allow "AGESA_ROOT/" and "AGESA_ROOT/Include". We then modify the AGESA headers to specify non-local include files relative to "AGESA_ROOT/Include". We use the convention that includes relative to the directory of the header are included as "path/to/header.h", while includes relative to AGESA_ROOT are included as <path/to/header.h>. This change allows building coreboot code based on AGESA with the limited subset of include paths, but does not allow AGESA itself to build with this restricted subset. Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5424 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5424 for details. -gerrit

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New patch to review for coreboot: 1e06657 northbridge/intel/*/acpi/igd.asl: Trivial indent style fix
by Edward O'Callaghan 06 Dec '14

06 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7665 -gerrit commit 1e06657010505546803456b26083143d08c329eb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Dec 6 14:32:23 2014 +1100 northbridge/intel/*/acpi/igd.asl: Trivial indent style fix Change-Id: I26e92645264c69bbc032b0e7e44d7d31de2dfa4d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/gm45/acpi/igd.asl | 4 ++-- src/northbridge/intel/nehalem/acpi/igd.asl | 22 +++++++++++----------- src/northbridge/intel/sandybridge/acpi/igd.asl | 4 ++-- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl index c5b4b6a..199765b 100644 --- a/src/northbridge/intel/gm45/acpi/igd.asl +++ b/src/northbridge/intel/gm45/acpi/igd.asl @@ -27,8 +27,8 @@ Device (GFX0) Field (GFXC, DWordAcc, NoLock, Preserve) { Offset (0x10), - BAR0, 64 - } + BAR0, 64 + } OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl index a892ce2..8c6c174 100644 --- a/src/northbridge/intel/nehalem/acpi/igd.asl +++ b/src/northbridge/intel/nehalem/acpi/igd.asl @@ -24,21 +24,21 @@ Device (GFX0) Name (_ADR, 0x00020000) OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) - Field (GFXC, DWordAcc, NoLock, Preserve) - { - Offset (0x10), - BAR0, 64 - } + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64 + } - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) - { - Offset (0x48254), + { + Offset (0x48254), BCLV, 16, - Offset (0xc8250), - CR1, 32, + Offset (0xc8250), + CR1, 32, CR2, 32 - } + } /* Display Output Switching */ Method (_DOS, 1) diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl index d40fad5..8c6c174 100644 --- a/src/northbridge/intel/sandybridge/acpi/igd.asl +++ b/src/northbridge/intel/sandybridge/acpi/igd.asl @@ -27,10 +27,10 @@ Device (GFX0) Field (GFXC, DWordAcc, NoLock, Preserve) { Offset (0x10), - BAR0, 64 + BAR0, 64 } - OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) { Offset (0x48254),

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Patch set updated for coreboot: 6bd4d63 vendorcode/amd/agesa/fam15tn: Clean #includes in public headers
by Alexandru Gagniuc 06 Dec '14

06 Dec '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5424 -gerrit commit 6bd4d63042395edcfcfa5b3bfcf4e46d084c793d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 16:52:46 2014 -0500 vendorcode/amd/agesa/fam15tn: Clean #includes in public headers Right now, coreboot code using AGESA headers can only build if all the AGESA path are given to the compiler via the "-I" option. This is sub- optimal, as it requires us to have every AGESA source directory specified as a compiler include path. This pollutes our global include paths. We restrict the compiler include paths to only allow "AGESA_ROOT/" and "AGESA_ROOT/Include". We then modify the AGESA headers to specify non-local include files relative to "AGESA_ROOT/Include". We use the convention that includes relative to the directory of the header are included as "path/to/header.h", while includes relative to AGESA_ROOT are included as <path/to/header.h>. This change allows building coreboot code based on AGESA with the limited subset of include paths, but does not allow AGESA itself to build with this restricted subset. Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h | 2 +- .../agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionFamily15hInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h | 10 +++++----- src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h | 8 ++++---- src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h | 4 ++-- .../amd/agesa/f15tn/Include/OptionIoCstateInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h | 10 +++++----- .../amd/agesa/f15tn/Include/OptionMemoryRecovery.h | 6 +++--- .../amd/agesa/f15tn/Include/OptionMmioMapInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h | 2 +- .../amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h | 2 +- .../amd/agesa/f15tn/Include/OptionS3ScriptInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h | 12 ++++++------ .../f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h | 6 +++--- src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h | 6 +++--- 29 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h index e88d35b..368104c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_APM_INSTALL_H_ #define _OPTION_APM_INSTALL_H_ -#include "cpuApm.h" +#include <Proc/CPU/Feature/cpuApm.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h index 088d303..b6186c6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h @@ -44,7 +44,7 @@ #ifndef _OPTION_C6_STATE_INSTALL_H_ #define _OPTION_C6_STATE_INSTALL_H_ -#include "cpuC6State.h" +#include <Proc/CPU/Feature/cpuC6State.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h index b2fa7d6..308dc73 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_CPB_INSTALL_H_ #define _OPTION_CPB_INSTALL_H_ -#include "cpuCpb.h" +#include <Proc/CPU/Feature/cpuCpb.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h index f00ee23..8b5db5a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ #define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ -#include "cpuPostInit.h" +#include "Proc/CPU/cpuPostInit.h" /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h index 73e5041..fb1b54d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_DMI_INSTALL_H_ #define _OPTION_DMI_INSTALL_H_ -#include "cpuLateInit.h" +#include <Proc/CPU/cpuLateInit.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h index d1e5c5b..f0d9194 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h @@ -43,7 +43,7 @@ #ifndef _OPTION_FAMILY_15H_INSTALL_H_ #define _OPTION_FAMILY_15H_INSTALL_H_ -#include "cpuFamilyTranslation.h" +#include <Proc/CPU/cpuFamilyTranslation.h> /* * Pull in family specific services based on entry point diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h index bf4c208..4a8237a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h @@ -42,7 +42,7 @@ #ifndef _OPTION_FCH_INSTALL_H_ #define _OPTION_FCH_INSTALL_H_ -#include "AmdFch.h" +#include <Proc/Common/AmdFch.h> #ifndef FCH_SUPPORT #define FCH_SUPPORT FALSE diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h index 022eee3..f6fc162 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_GNB_INSTALL_H_ #define _OPTION_GNB_INSTALL_H_ -#include "S3SaveState.h" +#include <Proc/Common/S3SaveState.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. * Check to validate the definition @@ -82,13 +82,13 @@ // Service installation //--------------------------------------------------------------------------------------------------- - #include "Gnb.h" - #include "GnbPcie.h" - #include "GnbGfx.h" + #include <Proc/GNB/Common/Gnb.h> + #include <Proc/GNB/Common/GnbPcie.h> + #include <Proc/GNB/Common/GnbGfx.h> #define SERVICES_POINTER NULL #if (GNB_TYPE_TN == TRUE) - #include "GnbInitTNInstall.h" + #include <Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h> #endif GNB_SERVICE *ServiceTable = SERVICES_POINTER; diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h index d6055bc..5069412 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h @@ -45,10 +45,10 @@ #define _OPTION_HT_INSTALL_H_ #include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htTopologies.h" +#include <Proc/HT/htFeat.h> +#include <Proc/HT/htInterface.h> +#include <Proc/HT/htNb.h> +#include <Proc/HT/htTopologies.h> /* * Advanced Option only, hardware socket naming is the preferred method. */ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h index 0b6f4f0..671b0fb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_HTC_INSTALL_H_ #define _OPTION_HTC_INSTALL_H_ -#include "cpuHtc.h" +#include <Proc/CPU/Feature/cpuHtc.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h index 0f85c71..374ceb4 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_HW_C1E_INSTALL_H_ #define _OPTION_HW_C1E_INSTALL_H_ -#include "cpuHwC1e.h" +#include <Proc/CPU/Feature/cpuHwC1e.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h index 83c28d2..a60667f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h @@ -43,8 +43,8 @@ #define _OPTION_IDS_INSTALL_H_ #include "Ids.h" #include "IdsHt.h" -#include "IdsLib.h" -#include "IdsDebugPrint.h" +#include <Proc/IDS/IdsLib.h> +#include <Proc/IDS/Debug/IdsDebugPrint.h> #ifdef __IDS_EXTENDED__ #include OPTION_IDS_EXT_INSTALL_FILE #endif diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h index b94b043..b83ee6b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_IO_CSTATE_INSTALL_H_ #define _OPTION_IO_CSTATE_INSTALL_H_ -#include "cpuIoCstate.h" +#include <Proc/CPU/Feature/cpuIoCstate.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h index 981e7c9..5d188e2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_L3_FEATURES_INSTALL_H_ #define _OPTION_L3_FEATURES_INSTALL_H_ -#include "cpuL3Features.h" +#include <Proc/CPU/Feature/cpuL3Features.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h index 017c981..2494ba9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h @@ -45,11 +45,11 @@ #define _OPTION_MEMORY_H_ /* Memory Includes */ -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mp.h" +#include <Proc/Mem/mm.h> +#include <Proc/Mem/mn.h> +#include <Proc/Mem/mt.h> +#include <Proc/Mem/ma.h> +#include <Proc/Mem/mp.h> /*---------------------------------------------------------------------------------------- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h index 713e73d..710d218 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h @@ -44,9 +44,9 @@ #ifndef _OPTION_MEMORY_RECOVERY_H_ #define _OPTION_MEMORY_RECOVERY_H_ -#include "mm.h" -#include "mn.h" -#include "mt.h" +#include <Proc/Mem/mm.h> +#include <Proc/Mem/mn.h> +#include <Proc/Mem/mt.h> typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR ( IN OUT MEM_NB_BLOCK *NBPtr, diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h index f43ff86..5ba255d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_MMIO_MAP_INSTALL_H_ #define _OPTION_MMIO_MAP_INSTALL_H_ -#include "mmioMapManager.h" +#include <Proc/CPU/mmioMapManager.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h index 986690b..6d0aeef 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ #define _OPTION_MSG_BASED_C1E_INSTALL_H_ -#include "cpuMsgBasedC1e.h" +#include <Proc/CPU/Feature/cpuMsgBasedC1e.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h index d42175c..310dc54 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ #define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ -#include "PreserveMailbox.h" +#include <Proc/CPU/Feature/PreserveMailbox.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h index 83e4734..0053a49 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSI_INSTALL_H_ #define _OPTION_PSI_INSTALL_H_ -#include "cpuPsi.h" +#include <Proc/CPU/Feature/cpuPsi.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h index 1ffaf94..2b576b1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSTATE_H_ #define _OPTION_PSTATE_H_ -#include "cpuPstateTables.h" +#include <Proc/CPU/Feature/cpuPstateTables.h> /*---------------------------------------------------------------------------------------- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h index 6b7f7f7..5106ed2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_ #define _OPTION_PSTATE_HPC_MODE_INSTALL_H_ -#include "cpuPstateHpcMode.h" +#include <Proc/CPU/Feature/cpuPstateHpcMode.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h index 18f22ac..e80a69d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_PSTATE_INSTALL_H_ #define _OPTION_PSTATE_INSTALL_H_ -#include "cpuPstateTables.h" +#include <Proc/CPU/Feature/cpuPstateTables.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h index 5b62bdf..f470042 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_S3SCRIPT_INSTALL_H_ #define _OPTION_S3SCRIPT_INSTALL_H_ -#include "S3SaveState.h" +#include <Proc/Common/S3SaveState.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. * Check to validate the definition diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h index 34886ee..4fa53ce 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h @@ -44,7 +44,7 @@ #ifndef _OPTION_SW_C1E_INSTALL_H_ #define _OPTION_SW_C1E_INSTALL_H_ -#include "cpuSwC1e.h" +#include <Proc/CPU/Feature/cpuSwC1e.h> /* This option is designed to be included into the platform solution install * file. The platform solution install file will define the options status. diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h index f3e7116..48fcb24 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h @@ -45,7 +45,7 @@ #ifndef _CPU_REGISTERS_H_ #define _CPU_REGISTERS_H_ -#include "cpuFamRegisters.h" +#include "Family/cpuFamRegisters.h" /* *-------------------------------------------------------------- * diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h index b3ed917..bef3016 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h @@ -106,12 +106,12 @@ #endif #include "Fch.h" -#include "amdlib.h" -#include "FchCommonCfg.h" -#include "AcpiLib.h" -#include "FchDef.h" -#include "FchBiosRamUsage.h" -#include "AmdFch.h" +#include <Lib/amdlib.h> +#include "Common/FchCommonCfg.h" +#include "Common/AcpiLib.h" +#include "Common/FchDef.h" +#include "Common/FchBiosRamUsage.h" +#include <Proc/Common/AmdFch.h> extern BUILD_OPT_CFG UserOptions; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h index 6055818..1be9d7c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h @@ -50,9 +50,9 @@ // Specify definition used by module services //----------------------------------------------------------------------- -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbFamServices.h" +#include <Proc/GNB/Common/GnbPcie.h> +#include <Proc/GNB/Common/GnbPcieFamServices.h> +#include <Proc/GNB/Common/GnbFamServices.h> //----------------------------------------------------------------------- // Export services diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h index 904e72d..a30dc37 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h @@ -43,9 +43,9 @@ #ifndef _IDS_LIB_H_ #define _IDS_LIB_H_ #include "OptionsIds.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "Table.h" +#include <Proc/CPU/cpuRegisters.h> +#include <Proc/CPU/cpuApicUtilities.h> +#include <Proc/CPU/Table.h> ///Specific time stamp performance analysis which need ids control support #if IDSOPT_CONTROL_ENABLED == TRUE #define PERF_SPEC_TS_ANALYSE(StdHeader) IdsPerfSpecTsAnalyse(StdHeader)

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New patch to review for coreboot: 24c339b mainboard/*/acpi/superio.asl: Use non-local inclusion syntax
by Edward O'Callaghan 06 Dec '14

06 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7664 -gerrit commit 24c339bc60566f68d98544581b056b7fadfbc71c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Dec 6 13:58:51 2014 +1100 mainboard/*/acpi/superio.asl: Use non-local inclusion syntax Use non-local inclusion syntax over relative paths for 'drivers/pc80/ps2_controller.asl'. Change-Id: Ie2bfa893dc268ec5118d2a9addadbc759d85d357 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl | 2 +- src/mainboard/lenovo/t520/acpi/superio.asl | 2 +- src/mainboard/lenovo/t530/acpi/superio.asl | 2 +- src/mainboard/lenovo/x201/acpi/superio.asl | 2 +- src/mainboard/lenovo/x220/acpi/superio.asl | 2 +- src/mainboard/lenovo/x230/acpi/superio.asl | 2 +- src/mainboard/packardbell/ms2290/acpi/superio.asl | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl index 6dcb877..93ad32b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl @@ -19,4 +19,4 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "../../../../drivers/pc80/ps2_controller.asl" +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t520/acpi/superio.asl b/src/mainboard/lenovo/t520/acpi/superio.asl index a2657f1..03b65bc 100644 --- a/src/mainboard/lenovo/t520/acpi/superio.asl +++ b/src/mainboard/lenovo/t520/acpi/superio.asl @@ -1 +1 @@ -#include "../../../../drivers/pc80/ps2_controller.asl" +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t530/acpi/superio.asl b/src/mainboard/lenovo/t530/acpi/superio.asl index a2657f1..03b65bc 100644 --- a/src/mainboard/lenovo/t530/acpi/superio.asl +++ b/src/mainboard/lenovo/t530/acpi/superio.asl @@ -1 +1 @@ -#include "../../../../drivers/pc80/ps2_controller.asl" +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index a2657f1..03b65bc 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1 @@ -#include "../../../../drivers/pc80/ps2_controller.asl" +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x220/acpi/superio.asl b/src/mainboard/lenovo/x220/acpi/superio.asl index a2657f1..03b65bc 100644 --- a/src/mainboard/lenovo/x220/acpi/superio.asl +++ b/src/mainboard/lenovo/x220/acpi/superio.asl @@ -1 +1 @@ -#include "../../../../drivers/pc80/ps2_controller.asl" +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl index a2657f1..03b65bc 100644 --- a/src/mainboard/lenovo/x230/acpi/superio.asl +++ b/src/mainboard/lenovo/x230/acpi/superio.asl @@ -1 +1 @@ -#include "../../../../drivers/pc80/ps2_controller.asl" +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/packardbell/ms2290/acpi/superio.asl b/src/mainboard/packardbell/ms2290/acpi/superio.asl index a2657f1..03b65bc 100644 --- a/src/mainboard/packardbell/ms2290/acpi/superio.asl +++ b/src/mainboard/packardbell/ms2290/acpi/superio.asl @@ -1 +1 @@ -#include "../../../../drivers/pc80/ps2_controller.asl" +#include <drivers/pc80/ps2_controller.asl>

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Patch set updated for coreboot: ca6f58b mainboard/lenovo/g505s: Build in EC ASL support for KBD/AUX ports
by Edward O'Callaghan 06 Dec '14

06 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7651 -gerrit commit ca6f58b565bfc0d553084ab1f10e3f33c87e13f7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 22:46:02 2014 +1100 mainboard/lenovo/g505s: Build in EC ASL support for KBD/AUX ports Rather than have Linux report: i8042: PNP: No PS/2 controller found. Probing directly. and go off probing PNP config space, build in EC ASL for the PS/2 keyboard and mouse. The ASL explicitly passes these resources to the Linux to avoid said probe. ASL Details: PS/2 keyboard (PNP0303 at 0x60,0x64 irq 1 ) PS/2 mouse (PNP0F13 at 0x60,0x64 irq 12) Change-Id: I0697fab65915907fbe2b3551182b3a1b0d665ddb Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/acpi/superio.asl | 10 ++++++++++ src/mainboard/lenovo/g505s/mainboard.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl index e69de29..e3bb6fb 100644 --- a/src/mainboard/lenovo/g505s/acpi/superio.asl +++ b/src/mainboard/lenovo/g505s/acpi/superio.asl @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* Defines EC bits specific to the mainboard, needed by EC ASL */ +#include "mainboard.h" + +/* ACPI code for EC SuperIO functions */ +#include <ec/compal/ene932/acpi/superio.asl> diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h index 6131df2..49aaedd 100644 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -22,4 +22,7 @@ #define PME_GPE 0x0b #define PCIE_GPE 0x18 +/* Enable PS/2 Keyboard and Mouse */ +#define SIO_EC_ENABLE_PS2K + #endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */

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Patch set updated for coreboot: b07234a ec/compal/ene932/acpi/superio.asl: Provide PNP0F13 AUX ASL
by Edward O'Callaghan 06 Dec '14

06 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7650 -gerrit commit b07234ac8db53ced82ddaea043be4238fb1d03dc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 22:43:35 2014 +1100 ec/compal/ene932/acpi/superio.asl: Provide PNP0F13 AUX ASL Provide ASL to support the AUX port (a.k.a Mouse) found at 0x60,0x64 irq 12 on this EC. Change-Id: I6969ae4d492570136a8e14e42509638857e1ed85 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/ec/compal/ene932/acpi/superio.asl | 31 ++----------------------------- 1 file changed, 2 insertions(+), 29 deletions(-) diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index db4b412..bd6dbfa 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -23,35 +23,8 @@ Device (SIO) { Name (_UID, 0) Name (_ADR, 0) - +// Keyboard or AUX port (a.k.a Mouse) #ifdef SIO_EC_ENABLE_PS2K - Device (PS2K) // Keyboard - { - Name (_UID, 0) - Name (_ADR, 0) - Name (_HID, EISAID("PNP0303")) - Name (_CID, EISAID("PNP030B")) - - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate() - { - FixedIO (0x60, 0x01) - FixedIO (0x64, 0x01) - IRQNoFlags () {1} - }) - - Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { - FixedIO (0x60, 0x01) - FixedIO (0x64, 0x01) - IRQNoFlags () {1} - } - EndDependentFn () - }) - } + #include <drivers/pc80/ps2_controller.asl> #endif }

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Patch merged into coreboot/master: c5c21d3 mainboard/lenovo/g505s/buildOpts.c: Trivial variable rename
by gerrit＠coreboot.org 06 Dec '14

06 Dec '14

the following patch was just integrated into master: commit c5c21d3fe114063887653a91920dcc3a7c6a436a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Dec 6 05:07:33 2014 +1100 mainboard/lenovo/g505s/buildOpts.c: Trivial variable rename Minor fix to avoid confusion, nothing to see here. Change-Id: I89d56a91d2df049e85cf49c23218620caba84880 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/7654 for details. -gerrit

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Patch merged into coreboot/master: 14ca52b fsp_baytrail: Allow selection of USB controller by get_option
by gerrit＠coreboot.org 06 Dec '14

06 Dec '14

the following patch was just integrated into master: commit 14ca52bb964794fe4251d8848a6cefe12682cce4 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Dec 2 21:51:03 2014 -0700 fsp_baytrail: Allow selection of USB controller by get_option It was requested to be able to update XHCI vs EHCI via get_option, so I've added it here for minnow max. This could get moved to the chipset_fsp_util.c file later, but I'm adding it here for now. More checking needs to be added to this: - Are both controllers enabled in devicetree? If not, we don't want to allow the switch. Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7633 for details. -gerrit

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Patch merged into coreboot/master: cf52f97 intel/minnowmax: Update devicetree
by gerrit＠coreboot.org 06 Dec '14

06 Dec '14

the following patch was just integrated into master: commit cf52f9761fef3a8e46ff28d6593e0d573ff1d4ac Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Dec 5 14:55:07 2014 -0700 intel/minnowmax: Update devicetree - Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable function 1c.0 so the rest of the functions will be seen, even though the function is not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7663 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7663 for details. -gerrit

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coreboot-gerrit December 2014