coreboot-gerrit November 2014

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Patch set updated for coreboot: a23dcfa arm: Redesign, clarify and clean up cache related code
by Marc Jones 04 Nov '14

04 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6993 -gerrit commit a23dcfa43b8a555a1af7252b16f8721672c097a6 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Jan 21 20:11:22 2014 -0800 arm: Redesign, clarify and clean up cache related code This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) *** Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- payloads/libpayload/arch/arm/cache.c | 78 ++++----------------------- payloads/libpayload/include/arm/arch/cache.h | 19 +------ payloads/libpayload/include/x86/arch/cache.h | 2 +- src/arch/arm/armv4/cache.c | 7 +-- src/arch/arm/armv7/bootblock.S | 2 + src/arch/arm/armv7/bootblock_simple.c | 17 ------ src/arch/arm/armv7/cache.c | 79 ++++------------------------ src/arch/arm/armv7/cpu.S | 31 +++++++++++ src/arch/arm/armv7/mmu.c | 13 +++-- src/arch/arm/include/armv4/arch/cache.h | 7 +-- src/arch/arm/include/armv7/arch/cache.h | 19 +------ src/arch/arm/stages.c | 18 ++----- src/mainboard/google/daisy/mainboard.c | 1 - src/mainboard/google/nyan/romstage.c | 23 +++----- src/mainboard/google/nyan_big/romstage.c | 23 +++----- src/mainboard/google/peach_pit/mainboard.c | 1 - src/soc/samsung/exynos5420/wakeup.c | 1 - util/nvidia/cbootimage | 1 - 18 files changed, 94 insertions(+), 248 deletions(-) diff --git a/payloads/libpayload/arch/arm/cache.c b/payloads/libpayload/arch/arm/cache.c index defe640..63715bc 100644 --- a/payloads/libpayload/arch/arm/cache.c +++ b/payloads/libpayload/arch/arm/cache.c @@ -38,26 +38,9 @@ void tlb_invalidate_all(void) { - /* - * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction - * instruction vs. data TLBs is deprecated in ARMv7, however this does - * not seem to be the case as of Cortex-A15. - */ + /* TLBIALL includes dTLB and iTLB on systems that have them. */ tlbiall(); - dtlbiall(); - itlbiall(); - isb(); dsb(); -} - -void icache_invalidate_all(void) -{ - /* - * icache can be entirely invalidated with one operation. - * Note: If branch predictors are architecturally-visible, ICIALLU - * also performs a BPIALL operation (B2-1283 in arch manual) - */ - iciallu(); isb(); } @@ -135,6 +118,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) dcache_op_mva(addr, len, OP_DCIMVAC); } +/* + * CAUTION: This implementation assumes that coreboot never uses non-identity + * page tables for pages containing executed code. If you ever want to violate + * this assumption, have fun figuring out the associated problems on your own. + */ void dcache_mmu_disable(void) { uint32_t sctlr; @@ -150,58 +138,14 @@ void dcache_mmu_enable(void) uint32_t sctlr; sctlr = read_sctlr(); - dcache_clean_invalidate_all(); sctlr |= SCTLR_C | SCTLR_M; write_sctlr(sctlr); } -void arm_invalidate_caches(void) +void cache_sync_instructions(void) { - uint32_t clidr; - int level; - - /* Invalidate branch predictor */ - bpiall(); - - /* Iterate thru each cache identified in CLIDR and invalidate */ - clidr = read_clidr(); - for (level = 0; level < 7; level++) { - unsigned int ctype = (clidr >> (level * 3)) & 0x7; - uint32_t csselr; - - switch(ctype) { - case 0x0: - /* no cache */ - break; - case 0x1: - /* icache only */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - break; - case 0x2: - case 0x4: - /* dcache only or unified cache */ - csselr = level << 1; - write_csselr(csselr); - dcache_invalidate_all(); - break; - case 0x3: - /* separate icache and dcache */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - - csselr = level << 1; - write_csselr(csselr); - dcache_invalidate_all(); - break; - default: - /* reserved */ - break; - } - } - - /* Invalidate TLB */ - tlb_invalidate_all(); + dcache_clean_all(); /* includes trailing DSB (in assembly) */ + iciallu(); /* includes BPIALLU (architecturally) */ + dsb(); + isb(); } diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index 5210dfe..470eb55 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -93,18 +93,6 @@ static inline void isb(void) * Low-level TLB maintenance operations */ -/* invalidate entire data TLB */ -static inline void dtlbiall(void) -{ - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory"); -} - -/* invalidate entire instruction TLB */ -static inline void itlbiall(void) -{ - asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); -} - /* invalidate entire unified TLB */ static inline void tlbiall(void) { @@ -313,8 +301,8 @@ void dcache_mmu_disable(void); /* dcache and MMU enable */ void dcache_mmu_enable(void); -/* icache invalidate all (on current level given by CSSELR) */ -void icache_invalidate_all(void); +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); @@ -323,9 +311,6 @@ void tlb_invalidate_all(void); * Generalized setup/init functions */ -/* invalidate all caches on ARM */ -void arm_invalidate_caches(void); - /* mmu initialization (set page table address, set permissions, etc) */ void mmu_init(void); diff --git a/payloads/libpayload/include/x86/arch/cache.h b/payloads/libpayload/include/x86/arch/cache.h index 3960488..ffefcdb 100644 --- a/payloads/libpayload/include/x86/arch/cache.h +++ b/payloads/libpayload/include/x86/arch/cache.h @@ -41,6 +41,6 @@ #define dcache_invalidate_by_mva(addr, len) #define dcache_clean_invalidate_all() #define dcache_clean_invalidate_by_mva(addr, len) -#define icache_invalidate_all() +#define cache_sync_instructions() #endif diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index e5cf293..140beee 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -39,10 +39,6 @@ void tlb_invalidate_all(void) { } -void icache_invalidate_all(void) -{ -} - void dcache_clean_all(void) { } @@ -82,11 +78,10 @@ void dcache_mmu_disable(void) { } - void dcache_mmu_enable(void) { } -void arm_invalidate_caches(void) +void cache_sync_instructions(void) { } diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index 4258caf..9ed5d54 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -46,6 +46,8 @@ ENDPROC(_start) .thumb ENTRY(_thumb_start) + bl arm_init_caches + /* * From Cortex-A Series Programmer's Guide: * Only CPU 0 performs initialization. Other CPUs go into WFI diff --git a/src/arch/arm/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c index 5cd5970..248ea4e 100644 --- a/src/arch/arm/armv7/bootblock_simple.c +++ b/src/arch/arm/armv7/bootblock_simple.c @@ -32,23 +32,6 @@ void main(void) { const char *stage_name = "fallback/romstage"; void *entry; - uint32_t sctlr; - - /* Globally disable MMU, caches, and branch prediction (these should - * be disabled by default on reset) */ - sctlr = read_sctlr(); - sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); - write_sctlr(sctlr); - - arm_invalidate_caches(); - - /* - * Re-enable icache and branch prediction. MMU and dcache will be - * set up later. - */ - sctlr = read_sctlr(); - sctlr |= SCTLR_Z | SCTLR_I; - write_sctlr(sctlr); bootblock_cpu_init(); bootblock_mainboard_init(); diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index 7db86c8..31819f7 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -37,26 +37,9 @@ void tlb_invalidate_all(void) { - /* - * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction - * instruction vs. data TLBs is deprecated in ARMv7, however this does - * not seem to be the case as of Cortex-A15. - */ + /* TLBIALL includes dTLB and iTLB on systems that have them. */ tlbiall(); - dtlbiall(); - itlbiall(); - isb(); dsb(); -} - -void icache_invalidate_all(void) -{ - /* - * icache can be entirely invalidated with one operation. - * Note: If branch predictors are architecturally-visible, ICIALLU - * also performs a BPIALL operation (B2-1283 in arch manual) - */ - iciallu(); isb(); } @@ -133,6 +116,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) dcache_op_mva(addr, len, OP_DCIMVAC); } +/* + * CAUTION: This implementation assumes that coreboot never uses non-identity + * page tables for pages containing executed code. If you ever want to violate + * this assumption, have fun figuring out the associated problems on your own. + */ void dcache_mmu_disable(void) { uint32_t sctlr; @@ -143,64 +131,19 @@ void dcache_mmu_disable(void) write_sctlr(sctlr); } - void dcache_mmu_enable(void) { uint32_t sctlr; sctlr = read_sctlr(); - dcache_clean_invalidate_all(); sctlr |= SCTLR_C | SCTLR_M; write_sctlr(sctlr); } -void arm_invalidate_caches(void) +void cache_sync_instructions(void) { - uint32_t clidr; - int level; - - /* Invalidate branch predictor */ - bpiall(); - - /* Iterate thru each cache identified in CLIDR and invalidate */ - clidr = read_clidr(); - for (level = 0; level < 7; level++) { - unsigned int ctype = (clidr >> (level * 3)) & 0x7; - uint32_t csselr; - - switch(ctype) { - case 0x0: - /* no cache */ - break; - case 0x1: - /* icache only */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - break; - case 0x2: - case 0x4: - /* dcache only or unified cache */ - csselr = level << 1; - write_csselr(csselr); - dcache_invalidate_all(); - break; - case 0x3: - /* separate icache and dcache */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - - csselr = level << 1; - write_csselr(csselr); - dcache_invalidate_all(); - break; - default: - /* reserved */ - break; - } - } - - /* Invalidate TLB */ - tlb_invalidate_all(); + dcache_clean_all(); /* includes trailing DSB (in assembly) */ + iciallu(); /* includes BPIALLU (architecturally) */ + dsb(); + isb(); } diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 29a19e7..5738116 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -104,6 +104,37 @@ bx lr .endm +/* + * Bring an ARM processor we just gained control of (e.g. from IROM) into a + * known state regarding caches/SCTLR. Completely cleans and invalidates + * icache/dcache, disables MMU and dcache (if active), and enables unaligned + * accesses, icache and branch prediction (if inactive). Clobbers r4 and r5. + */ +ENTRY(arm_init_caches) + /* r4: SCTLR, return address: r5 (stay valid for the whole function) */ + mov r5, lr + mrc p15, 0, r4, c1, c0, 0 + + /* Activate ICache (12) and Branch Prediction (11) already for speed */ + orr r4, # (1 << 11) | (1 << 12) + mcr p15, 0, r4, c1, c0, 0 + + /* Flush and invalidate dcache in ascending order */ + bl dcache_clean_invalidate_all + + /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ + and r4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2) + mcr p15, 0, r4, c1, c0, 0 + + /* Invalidate icache and TLB for good measure */ + mcr p15, 0, r0, c7, c5, 0 + mcr p15, 0, r0, c8, c7, 0 + dsb + isb + + bx r5 +ENDPROC(arm_init_caches) + ENTRY(dcache_invalidate_all) dcache_apply_all crm=c6 ENDPROC(dcache_invalidate_all) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index cc915a6..d710030 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -106,11 +106,18 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, for (i = start_mb; i < start_mb + size_mb; i++) writel((i << 20) | attr, &ttb_entry[i]); - /* Flush the page table entries, and old translations from the TLB. */ - for (i = start_mb; i < start_mb + size_mb; i++) { + /* Flush the page table entries from the dcache. */ + for (i = start_mb; i < start_mb + size_mb; i++) dccmvac((uintptr_t)&ttb_entry[i]); + + dsb(); + + /* Invalidate the TLB entries. */ + for (i = start_mb; i < start_mb + size_mb; i++) tlbimvaa(i*MiB); - } + + dsb(); + isb(); } void mmu_init(void) diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index 6a3f593..e41ff9a 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -66,8 +66,8 @@ void dcache_mmu_disable(void); /* dcache and MMU enable */ void dcache_mmu_enable(void); -/* icache invalidate all (on current level given by CSSELR) */ -void icache_invalidate_all(void); +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); @@ -76,9 +76,6 @@ void tlb_invalidate_all(void); * Generalized setup/init functions */ -/* invalidate all caches on ARM */ -void arm_invalidate_caches(void); - /* mmu initialization (set page table address, set permissions, etc) */ void mmu_init(void); diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index 5210dfe..470eb55 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -93,18 +93,6 @@ static inline void isb(void) * Low-level TLB maintenance operations */ -/* invalidate entire data TLB */ -static inline void dtlbiall(void) -{ - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory"); -} - -/* invalidate entire instruction TLB */ -static inline void itlbiall(void) -{ - asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); -} - /* invalidate entire unified TLB */ static inline void tlbiall(void) { @@ -313,8 +301,8 @@ void dcache_mmu_disable(void); /* dcache and MMU enable */ void dcache_mmu_enable(void); -/* icache invalidate all (on current level given by CSSELR) */ -void icache_invalidate_all(void); +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); @@ -323,9 +311,6 @@ void tlb_invalidate_all(void); * Generalized setup/init functions */ -/* invalidate all caches on ARM */ -void arm_invalidate_caches(void); - /* mmu initialization (set page table address, set permissions, etc) */ void mmu_init(void); diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index 38d1b19..47f13fa 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -20,12 +20,7 @@ /* * This file contains entry/exit functions for each stage during coreboot * execution (bootblock entry and ramstage exit will depend on external - * loading. - * - * Unlike other files, this one should be compiled with a -m option to - * specify a pre-determined instruction set. This is to ensure consistency - * in the CPU operating mode (ARM or Thumb) when hand-off between stages - * occurs. + * loading). * * Entry points must be placed at the location the previous stage jumps * to (the lowest address in the stage image). This is done by giving @@ -49,13 +44,10 @@ void stage_entry(void) void stage_exit(void *addr) { void (*doit)(void) = addr; - /* make sure any code we installed is written to memory. Not all ARM have - * unified caches. - */ - dcache_clean_all(); - /* Because most stages copy code to memory, it's a safe and hygienic thing - * to flush the icache here. + /* + * Most stages load code so we need to sync caches here. Should maybe + * go into cbfs_load_stage() instead... */ - icache_invalidate_all(); + cache_sync_instructions(); doit(); } diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 0adadb6..8a252b1 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -334,7 +334,6 @@ static void mainboard_enable(device_t dev) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); - dcache_invalidate_all(); dcache_mmu_enable(); const unsigned epll_hz = 192000000; diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 3eaf38c..d7daea8 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -69,26 +69,13 @@ static void configure_l2actlr(void) write_l2actlr(val); } -void main(void) +static void __attribute__((noinline)) romstage(void) { int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif - // Globally disable MMU, caches and branch prediction (these should - // already be disabled by default on reset). - uint32_t sctlr = read_sctlr(); - sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); - write_sctlr(sctlr); - - arm_invalidate_caches(); - - // Renable icache and branch prediction. - sctlr = read_sctlr(); - sctlr |= SCTLR_Z | SCTLR_I; - write_sctlr(sctlr); - configure_l2ctlr(); configure_l2actlr(); @@ -110,7 +97,6 @@ void main(void) CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); - dcache_invalidate_all(); dcache_mmu_enable(); /* For quality of the user experience, it's important to get @@ -146,3 +132,10 @@ void main(void) #endif stage_exit(entry); } + +/* Stub to force arm_init_caches to the top, before any stack/memory accesses */ +void main(void) +{ + asm ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); + romstage(); +} diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 80eea77..5fd255e 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -69,26 +69,13 @@ static void configure_l2actlr(void) write_l2actlr(val); } -void main(void) +static void __attribute__((noinline)) romstage(void) { int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif - // Globally disable MMU, caches and branch prediction (these should - // already be disabled by default on reset). - uint32_t sctlr = read_sctlr(); - sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); - write_sctlr(sctlr); - - arm_invalidate_caches(); - - // Renable icache and branch prediction. - sctlr = read_sctlr(); - sctlr |= SCTLR_Z | SCTLR_I; - write_sctlr(sctlr); - configure_l2ctlr(); configure_l2actlr(); @@ -110,7 +97,6 @@ void main(void) CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); - dcache_invalidate_all(); dcache_mmu_enable(); /* For quality of the user experience, it's important to get @@ -146,3 +132,10 @@ void main(void) #endif stage_exit(entry); } + +/* Stub to force arm_init_caches to the top, before any stack/memory accesses */ +void main(void) +{ + asm ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); + romstage(); +} diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1fb441d..706447a 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -469,7 +469,6 @@ static void mainboard_enable(device_t dev) /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); - tlb_invalidate_all(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; diff --git a/src/soc/samsung/exynos5420/wakeup.c b/src/soc/samsung/exynos5420/wakeup.c index 753afd9..a240717 100644 --- a/src/soc/samsung/exynos5420/wakeup.c +++ b/src/soc/samsung/exynos5420/wakeup.c @@ -29,7 +29,6 @@ void wakeup(void) power_init(); /* Ensure ps_hold_setup() for early wakeup. */ dcache_mmu_disable(); - icache_invalidate_all(); power_exit_wakeup(); /* Should never return. If we do, reset. */ power_reset(); diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage deleted file mode 160000 index 62a83fa..0000000 --- a/util/nvidia/cbootimage +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 62a83faac08dba2591c5e188a0c8257dd64c9565

1 0

Patch set updated for coreboot: a21c9db drivers/net/ne2k.c: Collect headers and defines to top of file
by Edward O'Callaghan 04 Nov '14

04 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7292 -gerrit commit a21c9db1740b98928c80fab4cf3e236db89bcd12 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 12:37:49 2014 +1100 drivers/net/ne2k.c: Collect headers and defines to top of file Change-Id: I2ffb0dd9fe400132f6d430f115f962b5f8578efa Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/net/ne2k.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index b678d79..ac5230a 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -34,15 +34,25 @@ SMC8416 PIO support added by Andrew Bettison (andrewb(a)zip.com.au) on 4/3/02 #define ETH_DATA_ALIGN 2 /* Amount needed to align the data after an ethernet header */ #define ETH_MAX_MTU (ETH_FRAME_LEN-ETH_HLEN) -#include "ns8390.h" -#include <ip_checksum.h> -#include <console/ne2k.h> -#include <arch/io.h> - #define MEM_SIZE MEM_32768 #define TX_START 64 #define RX_START (64 + D8390_TXBUF_SIZE) +#include <arch/io.h> +#include <console/console.h> +#include <console/ne2k.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <stdlib.h> +#include <string.h> +#include <ip_checksum.h> + +#include "ns8390.h" + + static unsigned int get_count(unsigned int eth_nic_base) { unsigned int ret; @@ -415,17 +425,6 @@ int ne2k_init(unsigned int eth_nic_base) { #else -#include <delay.h> -#include <stdlib.h> -#include <string.h> -#include <arch/io.h> - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - static void read_resources(struct device *dev) { struct resource *res; @@ -455,4 +454,4 @@ static const struct pci_driver ne2k_driver __pci_driver = { .device = 0x8029, }; -#endif +#endif /* __PRE_RAM__ */

1 0

Patch merged into coreboot/master: ab83ef0 i82801gx: Handle whole FADT in southbridge.
by gerrit＠coreboot.org 04 Nov '14

04 Nov '14

the following patch was just integrated into master: commit ab83ef02c7131d23a28c6acbd79e6cd9997dcec8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 25 15:18:25 2014 +0200 i82801gx: Handle whole FADT in southbridge. Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks. Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7199 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7199 for details. -gerrit

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Patch merged into coreboot/master: 9c4f1b8 inteltool/sandybridge: Kill mch_registers codepath.
by gerrit＠coreboot.org 04 Nov '14

04 Nov '14

the following patch was just integrated into master: commit 9c4f1b8e05fbd659ebdb3d03d811f1ad39079a1a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:05:12 2014 +0100 inteltool/sandybridge: Kill mch_registers codepath. It never worked. Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7324 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7324 for details. -gerrit

1 0

Patch set updated for coreboot: 1a48081 amdfam10: Move to per-device ACPI
by Vladimir Serbinenko 04 Nov '14

04 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7027 -gerrit commit 1a48081002edb86056ec6c6aa8068e3553e84eb2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Oct 2 20:09:19 2014 +0200 amdfam10: Move to per-device ACPI Change-Id: I9ce2333e1ea527843f83d411dea2a669263156c2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/amd/model_10xxx/Makefile.inc | 1 + src/cpu/amd/model_10xxx/powernow_acpi.c | 31 ++ src/mainboard/advansus/a785e-i/acpi_tables.c | 173 ----------- src/mainboard/amd/bimini_fam10/acpi_tables.c | 173 ----------- src/mainboard/amd/inagua/acpi_tables.c | 6 - src/mainboard/amd/mahogany_fam10/acpi_tables.c | 136 -------- src/mainboard/amd/persimmon/acpi_tables.c | 6 - .../amd/serengeti_cheetah_fam10/acpi_tables.c | 116 +------ .../amd/serengeti_cheetah_fam10/mainboard.c | 15 + .../amd/serengeti_cheetah_fam10/mainboard.h | 2 + src/mainboard/amd/south_station/acpi_tables.c | 6 - src/mainboard/amd/tilapia_fam10/acpi_tables.c | 167 ---------- src/mainboard/amd/union_station/acpi_tables.c | 6 - src/mainboard/asrock/e350m1/acpi_tables.c | 6 - src/mainboard/asus/m4a78-em/acpi_tables.c | 167 ---------- src/mainboard/asus/m4a785-m/acpi_tables.c | 136 -------- src/mainboard/asus/m5a88-v/acpi_tables.c | 173 ----------- src/mainboard/avalue/eax-785e/acpi_tables.c | 173 ----------- src/mainboard/gigabyte/ma785gm/acpi_tables.c | 167 ---------- src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 167 ---------- src/mainboard/gigabyte/ma78gm/acpi_tables.c | 167 ---------- src/mainboard/gizmosphere/gizmo/acpi_tables.c | 6 - src/mainboard/iei/kino-780am2-fam10/acpi_tables.c | 136 -------- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 6 - src/mainboard/jetway/pa78vm5/acpi_tables.c | 167 ---------- src/mainboard/lippert/frontrunner-af/acpi_tables.c | 6 - src/mainboard/lippert/toucan-af/acpi_tables.c | 6 - src/mainboard/msi/ms9652_fam10/acpi_tables.c | 112 ------- src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 167 ---------- src/northbridge/amd/agesa/family10/Makefile.inc | 2 - src/northbridge/amd/agesa/family10/ssdt.asl | 345 --------------------- src/northbridge/amd/amdfam10/Kconfig | 1 + src/northbridge/amd/amdfam10/Makefile.inc | 1 - src/northbridge/amd/amdfam10/acpi.c | 209 ++++++++----- src/northbridge/amd/amdfam10/amdfam10.h | 6 + src/northbridge/amd/amdfam10/northbridge.c | 4 + src/northbridge/amd/amdfam10/ssdt.asl | 345 --------------------- src/northbridge/amd/amdfam10/sspr1.asl | 39 --- src/northbridge/amd/amdfam10/sspr2.asl | 40 --- src/northbridge/amd/amdfam10/sspr3.asl | 41 --- src/northbridge/amd/amdfam10/sspr4.asl | 42 --- src/northbridge/amd/amdfam10/sspr5.asl | 43 --- src/northbridge/amd/amdk8/acpi.c | 4 - src/northbridge/amd/amdk8/northbridge.c | 3 + src/southbridge/amd/cimx/sb800/late.c | 9 + src/southbridge/amd/sb800/lpc.c | 10 + 46 files changed, 209 insertions(+), 3535 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index c82a26e..5cfcc97 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,3 +3,4 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c new file mode 100644 index 0000000..b39532f --- /dev/null +++ b/src/cpu/amd/model_10xxx/powernow_acpi.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <arch/acpigen.h> +#include <cpu/amd/powernow.h> + +/* FIXME: this should be implemented but right now all boards hardcode it. */ +int amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) +{ + return 0; +} diff --git a/src/mainboard/advansus/a785e-i/acpi_tables.c b/src/mainboard/advansus/a785e-i/acpi_tables.c index 3f9bd60..ce32c97 100644 --- a/src/mainboard/advansus/a785e-i/acpi_tables.c +++ b/src/mainboard/advansus/a785e-i/acpi_tables.c @@ -29,22 +29,6 @@ #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -69,160 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/bimini_fam10/acpi_tables.c b/src/mainboard/amd/bimini_fam10/acpi_tables.c index 84abaaa..1f26283 100644 --- a/src/mainboard/amd/bimini_fam10/acpi_tables.c +++ b/src/mainboard/amd/bimini_fam10/acpi_tables.c @@ -29,22 +29,6 @@ #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -69,160 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 588345e..f9d4eda 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -54,12 +54,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c index 5efb0ee..bc3b49d 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -29,37 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - int lens; - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - lens = acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - lens += acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_patch_len(lens - 1); - - /* TODO: More HT and other tables need to go into this table generation. - * This should also be moved out to the silicon level if it can. - */ - - return (unsigned long) (acpigen_get_current()); -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -84,108 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); - ssdt = (acpi_header_t *) current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp,ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 588345e..f9d4eda 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -54,12 +54,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 32649ba..ea3ec6c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -28,9 +28,7 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" - -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; +#include "mainboard.h" #if CONFIG_ACPI_SSDTX_NUM >= 1 extern const unsigned char AmlCode_ssdt2[]; @@ -39,12 +37,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base=0x18; @@ -141,19 +133,9 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long write_acpi_tables(unsigned long start) +unsigned long mainboard_write_acpi_tables(unsigned long current, + acpi_rsdp_t *rsdp) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; acpi_header_t *ssdtx; void *p; @@ -161,97 +143,6 @@ unsigned long write_acpi_tables(unsigned long start) get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n", current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current+=madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current+=srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt, ssdt->length); - acpi_add_table(rsdp, ssdt); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different possition? We may have to copy, @@ -293,6 +184,5 @@ unsigned long write_acpi_tables(unsigned long start) } #endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c new file mode 100644 index 0000000..b9c88f6 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c @@ -0,0 +1,15 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include "mainboard.h" + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h new file mode 100644 index 0000000..8f17804 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h @@ -0,0 +1,2 @@ +unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); + diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 588345e..f9d4eda 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -54,12 +54,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index 30a7388..df89e8c 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -29,16 +29,6 @@ #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -63,160 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 588345e..f9d4eda 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -54,12 +54,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 65cb796..dc1506d 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -53,12 +53,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asus/m4a78-em/acpi_tables.c b/src/mainboard/asus/m4a78-em/acpi_tables.c index 7e159b4..41d2b6c 100644 --- a/src/mainboard/asus/m4a78-em/acpi_tables.c +++ b/src/mainboard/asus/m4a78-em/acpi_tables.c @@ -28,16 +28,6 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -62,160 +52,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index 1c0afeb..4de1ebf 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -29,37 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - int lens; - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - lens = acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - lens += acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_patch_len(lens - 1); - - /* TODO: More HT and other tables need to go into this table generation. - * This should also be moved out to the silicon level if it can. - */ - - return (unsigned long) (acpigen_get_current()); -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -84,108 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); - ssdt = (acpi_header_t *) current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp,ssdt); - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c index 3f9bd60..ce32c97 100644 --- a/src/mainboard/asus/m5a88-v/acpi_tables.c +++ b/src/mainboard/asus/m5a88-v/acpi_tables.c @@ -29,22 +29,6 @@ #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -69,160 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c index 3f9bd60..ce32c97 100644 --- a/src/mainboard/avalue/eax-785e/acpi_tables.c +++ b/src/mainboard/avalue/eax-785e/acpi_tables.c @@ -29,22 +29,6 @@ #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -69,160 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c index 4c0cb77..df89e8c 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c @@ -29,16 +29,6 @@ #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -63,160 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c index a9e72eb..5057442 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c @@ -27,16 +27,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -61,160 +51,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/gigabyte/ma78gm/acpi_tables.c b/src/mainboard/gigabyte/ma78gm/acpi_tables.c index a9e72eb..5057442 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma78gm/acpi_tables.c @@ -27,16 +27,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -61,160 +51,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index a9174c0..94cc462 100755 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -55,12 +55,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c index 5efb0ee..bc3b49d 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c +++ b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c @@ -29,37 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - int lens; - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - lens = acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - lens += acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_patch_len(lens - 1); - - /* TODO: More HT and other tables need to go into this table generation. - * This should also be moved out to the silicon level if it can. - */ - - return (unsigned long) (acpigen_get_current()); -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -84,108 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); - ssdt = (acpi_header_t *) current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp,ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 95f2a0e..4bb11b9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -54,12 +54,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/jetway/pa78vm5/acpi_tables.c b/src/mainboard/jetway/pa78vm5/acpi_tables.c index 1c5404f..3d5fd35 100644 --- a/src/mainboard/jetway/pa78vm5/acpi_tables.c +++ b/src/mainboard/jetway/pa78vm5/acpi_tables.c @@ -28,16 +28,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -62,160 +52,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index 588345e..f9d4eda 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -54,12 +54,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index 588345e..f9d4eda 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -54,12 +54,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c index 148ac1a..eb1531a 100644 --- a/src/mainboard/msi/ms9652_fam10/acpi_tables.c +++ b/src/mainboard/msi/ms9652_fam10/acpi_tables.c @@ -35,8 +35,6 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -89,113 +87,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - //k8acpi_write_vars(); - //amd_generate_powernow(0, 0, 0); - //return (unsigned long) (acpigen_get_current()); - return 0; -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8 *)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index 66a5239..5e3170d 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -29,16 +29,6 @@ #include "mb_sysconf.h" -extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - unsigned long acpi_fill_madt(unsigned long current) { device_t dev; @@ -76,160 +66,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp,ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/northbridge/amd/agesa/family10/Makefile.inc b/src/northbridge/amd/agesa/family10/Makefile.inc index a10a4a1..87f4927 100644 --- a/src/northbridge/amd/agesa/family10/Makefile.inc +++ b/src/northbridge/amd/agesa/family10/Makefile.inc @@ -18,5 +18,3 @@ # ramstage-y += northbridge.c - -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/agesa/family10/ssdt.asl b/src/northbridge/amd/agesa/family10/ssdt.asl deleted file mode 100644 index 63650fb..0000000 --- a/src/northbridge/amd/agesa/family10/ssdt.asl +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file - */ - -DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM15H", "AMD-ACPI", 0x1000) -{ - /* - * These objects were referenced but not defined in this table - */ - External (\_SB_.PCI0, DeviceObj) - - Scope (\_SB.PCI0) - { - Name (BUSN, Package (0x20) /* HC_NUMS */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x10101010, - 0x11111111, - 0x12121212, - 0x13131313, - 0x14141414, - 0x15151515, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc - }) - Name (MMIO, Package (0x80) /* HC_NUMS * 4 */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 - }) - Name (PCIO, Package (0x40) /* HC_NUMS * 2 */ - { - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444 - }) - Name (SBLK, 0x11) - Name (TOM1, 0xaaaaaaaa) - Name (SBDN, 0xbbbbbbbb) - Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 - }) - Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 - }) - Name (CBB, 0x99) - Name (CBST, 0x88) - Name (CBB2, 0x77) - Name (CBS2, 0x66) - - } -} diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index d26b05e..71339a7 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -24,6 +24,7 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT + select PER_DEVICE_ACPI_TABLES if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index b2e8143..ef4bef4 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -2,7 +2,6 @@ ramstage-y += northbridge.c ramstage-y += misc_control.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.asl ramstage-y += get_pci1234.c diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 513fa58..463fb7c 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <device/pci.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -162,131 +163,169 @@ unsigned long acpi_fill_slit(unsigned long current) return current; } -// moved from mb acpi_tables.c -static void intx_to_stream(u32 val, u32 len, u8 *dest) +void update_ssdtx(void *ssdtx, int i) { - int i; - for(i=0;i<len;i++) { - *(dest+i) = (val >> (8*i)) & 0xff; + u8 *PCI; + u8 *HCIN; + u8 *UID; + + PCI = ssdtx + 0x32; + HCIN = ssdtx + 0x39; + UID = ssdtx + 0x40; + + if (i < 7) { + *PCI = (u8) ('4' + i - 1); + } else { + *PCI = (u8) ('A' + i - 1 - 6); } -} + *HCIN = (u8) i; + *UID = (u8) (i + 3); + + /* FIXME: need to update the GSI id in the ssdtx too */ -static void int_to_stream(u32 val, u8 *dest) -{ - return intx_to_stream(val, 4, dest); } -// used by acpi_tables.h -void update_ssdt(void *ssdt) +void northbridge_acpi_write_vars(void) { - u8 *BUSN; - u8 *MMIO; - u8 *PCIO; - u8 *SBLK; - u8 *TOM1; - u8 *SBDN; - u8 *HCLK; - u8 *HCDN; - u8 *CBST; - u8 *CBBX; - u8 *CBS2; - u8 *CBB2; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + int i; + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - int i; - u32 dword; - msr_t msr; + acpigen_write_scope(pscope); - // the offset could be different if have different HC_NUMS, and HC_POSSIBLE_NUM and ssdt.asl - BUSN = ssdt+0x3b; //+5 will be next BUSN - MMIO = ssdt+0xe4; //+5 will be next MMIO - PCIO = ssdt+0x36d; //+5 will be next PCIO - SBLK = ssdt+0x4b2; // one byte - TOM1 = ssdt+0x4b9; // - SBDN = ssdt+0x4c3;// - HCLK = ssdt+0x4d1; //+5 will be next HCLK - HCDN = ssdt+0x57a; //+5 will be next HCDN - CBBX = ssdt+0x61f; // - CBST = ssdt+0x626; - CBB2 = ssdt+0x62d; // - CBS2 = ssdt+0x634; - - for(i=0;i<HC_NUMS;i++) { - dword = sysconf.ht_c_conf_bus[i]; - int_to_stream(dword, BUSN+i*5); + acpigen_write_name("BUSN"); + acpigen_write_package(HC_NUMS); + for(i=0; i<HC_NUMS; i++) { + acpigen_write_dword(sysconf.ht_c_conf_bus[i]); } + // minus the opcode + acpigen_pop_len(); + + acpigen_write_name("MMIO"); + + acpigen_write_package(HC_NUMS * 4); for(i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain - dword = sysconf.conf_mmio_addrx[i]; //base - int_to_stream(dword, MMIO+(i*2)*5); - dword = sysconf.conf_mmio_addr[i]; //mask - int_to_stream(dword, MMIO+(i*2+1)*5); + acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base + acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask } + // minus the opcode + acpigen_pop_len(); + + acpigen_write_name("PCIO"); + + acpigen_write_package(HC_NUMS * 2); + for(i=0;i<HC_NUMS;i++) { // FIXME: change to more chain - dword = sysconf.conf_io_addrx[i]; - int_to_stream(dword, PCIO+(i*2)*5); - dword = sysconf.conf_io_addr[i]; - int_to_stream(dword, PCIO+(i*2+1)*5); + acpigen_write_dword(sysconf.conf_io_addrx[i]); + acpigen_write_dword(sysconf.conf_io_addr[i]); } - *SBLK = (u8)(sysconf.sblk); + // minus the opcode + acpigen_pop_len(); + + acpigen_write_name_byte("SBLK", sysconf.sblk); msr = rdmsr(TOP_MEM); - int_to_stream(msr.lo, TOM1); + acpigen_write_name_dword("TOM1", msr.lo); + + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - int_to_stream(sysconf.sbdn, SBDN); + + acpigen_write_name_dword("SBDN", sysconf.sbdn); + + acpigen_write_name("HCLK"); + + acpigen_write_package(HC_POSSIBLE_NUM); for(i=0;i<sysconf.hc_possible_num;i++) { - int_to_stream(sysconf.pci1234[i], HCLK + i*5); - int_to_stream(sysconf.hcdn[i], HCDN + i*5); + acpigen_write_dword(sysconf.pci1234[i]); } for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 - int_to_stream(0x00000000, HCLK + i*5); - int_to_stream(0x20202020, HCDN + i*5); + acpigen_write_dword(0x00000000); } + // minus the opcode + acpigen_pop_len(); + + acpigen_write_name("HCDN"); + + acpigen_write_package(HC_POSSIBLE_NUM); - *CBBX = (u8)(CONFIG_CBB); + for(i=0;i<sysconf.hc_possible_num;i++) { + acpigen_write_dword(sysconf.hcdn[i]); + } + for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + acpigen_write_dword(0x20202020); + } + // minus the opcode + acpigen_pop_len(); + + acpigen_write_name_byte("CBB", CONFIG_CBB); + + u8 CBST, CBB2, CBS2; if(CONFIG_CBB == 0xff) { - *CBST = (u8) (0x0f); + CBST = (u8) (0x0f); } else { if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 - *CBST = (u8) (0x0f); + CBST = (u8) (0x0f); } else { - *CBST = (u8) (0x00); + CBST = (u8) (0x00); } } + acpigen_write_name_byte("CBST", CBST); + if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) { - *CBS2 = 0x0f; - *CBB2 = (u8)(CONFIG_CBB-1); + CBS2 = 0x0f; + CBB2 = (u8)(CONFIG_CBB-1); } else { - *CBS2 = 0x00; - *CBB2 = 0x00; + CBS2 = 0x00; + CBB2 = 0x00; } + acpigen_write_name_byte("CBB2", CBB2); + acpigen_write_name_byte("CBS2", CBS2); + + //minus opcode + acpigen_pop_len(); } -void update_ssdtx(void *ssdtx, int i) +unsigned long northbridge_write_acpi_tables(unsigned long current, + struct acpi_rsdp *rsdp) { - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (u8) ('4' + i - 1); - } else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ + acpi_srat_t *srat; + acpi_slit_t *slit; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + return current; } - diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 6e71b4e..d292306 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1200,4 +1200,10 @@ u8 get_sbbusn(u8 sblk); #include "northbridge/amd/amdht/porting.h" BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); +struct acpi_rsdp; + +unsigned long northbridge_write_acpi_tables(unsigned long start, + struct acpi_rsdp *rsdp); +void northbridge_acpi_write_vars(void); + #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 76ffc5d..819707d 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -613,6 +613,10 @@ static struct device_operations northbridge_operations = { .enable_resources = pci_dev_enable_resources, .init = mcf0_control_init, .scan_bus = amdfam10_scan_chains, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = northbridge_acpi_write_vars, +#endif .enable = 0, .ops_pci = 0, }; diff --git a/src/northbridge/amd/amdfam10/ssdt.asl b/src/northbridge/amd/amdfam10/ssdt.asl deleted file mode 100644 index 500446a..0000000 --- a/src/northbridge/amd/amdfam10/ssdt.asl +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file - */ - -DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925440) -{ - /* - * These objects were referenced but not defined in this table - */ - External (\_SB_.PCI0, DeviceObj) - - Scope (\_SB.PCI0) - { - Name (BUSN, Package (0x20) /* HC_NUMS */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x10101010, - 0x11111111, - 0x12121212, - 0x13131313, - 0x14141414, - 0x15151515, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc - }) - Name (MMIO, Package (0x80) /* HC_NUMS * 4 */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x11111111, - 0x22222222, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 - }) - Name (PCIO, Package (0x40) /* HC_NUMS * 2 */ - { - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0xaaaaaaaa, - 0xbbbbbbbb, - 0xcccccccc, - 0xdddddddd, - 0xeeeeeeee, - 0x77777777, - 0x88888888, - 0x99999999, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x99999999, - 0xaaaaaaaa, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444 - }) - Name (SBLK, 0x11) - Name (TOM1, 0xaaaaaaaa) - Name (SBDN, 0xbbbbbbbb) - Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 - }) - Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */ - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888, - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444, - 0x55555555, - 0x66666666, - 0x77777777, - 0x88888888 - }) - Name (CBB, 0x99) - Name (CBST, 0x88) - Name (CBB2, 0x77) - Name (CBS2, 0x66) - - } -} diff --git a/src/northbridge/amd/amdfam10/sspr1.asl b/src/northbridge/amd/amdfam10/sspr1.asl deleted file mode 100644 index ec1dc01..0000000 --- a/src/northbridge/amd/amdfam10/sspr1.asl +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441) -{ - Scope (\_SB) - { - Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated - { - Name(_PCT, Package () - { - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS - }) - - Name(_PSS, Package() - { - Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - }) - } - - } -} diff --git a/src/northbridge/amd/amdfam10/sspr2.asl b/src/northbridge/amd/amdfam10/sspr2.asl deleted file mode 100644 index d51f2b2..0000000 --- a/src/northbridge/amd/amdfam10/sspr2.asl +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441) -{ - Scope (\_SB) - { - Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated - { - Name(_PCT, Package () - { - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS - }) - - Name(_PSS, Package() - { - Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - }) - } - - } -} diff --git a/src/northbridge/amd/amdfam10/sspr3.asl b/src/northbridge/amd/amdfam10/sspr3.asl deleted file mode 100644 index ac99c47..0000000 --- a/src/northbridge/amd/amdfam10/sspr3.asl +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441) -{ - Scope (\_SB) - { - Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated - { - Name(_PCT, Package () - { - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS - }) - - Name(_PSS, Package() - { - Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - }) - } - - } -} diff --git a/src/northbridge/amd/amdfam10/sspr4.asl b/src/northbridge/amd/amdfam10/sspr4.asl deleted file mode 100644 index fac59bf..0000000 --- a/src/northbridge/amd/amdfam10/sspr4.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441) -{ - Scope (\_SB) - { - Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated - { - Name(_PCT, Package () - { - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS - }) - - Name(_PSS, Package() - { - Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - }) - } - - } -} diff --git a/src/northbridge/amd/amdfam10/sspr5.asl b/src/northbridge/amd/amdfam10/sspr5.asl deleted file mode 100644 index 19c0cc9..0000000 --- a/src/northbridge/amd/amdfam10/sspr5.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441) -{ - Scope (\_SB) - { - Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated - { - Name(_PCT, Package () - { - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL - ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS - }) - - Name(_PSS, Package() - { - Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - Package(0x06) {0xaaaa, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, - }) - } - - } -} diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index a2dedd3..2706c64 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -118,8 +118,6 @@ unsigned long acpi_fill_srat(unsigned long current) { struct acpi_srat_mem_state srat_mem_state; - get_bus_conf(); - /* create all subtables for processors */ current = acpi_create_srat_lapics(current); @@ -143,8 +141,6 @@ unsigned long acpi_fill_slit(unsigned long current) /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ - get_bus_conf(); - /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */ static u8 hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, 1, 0, 2, 1, 3, 2, 4, 3, diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a91a499..081ec6d 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -593,6 +593,9 @@ static unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsd current = start; + /* Fills sysconf structure needed for SRAT and SLIT. */ + get_bus_conf(); + current = ALIGN(current, 16); srat = (acpi_srat_t *) current; printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 7d6e221..cbb3797 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -147,10 +147,19 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 7a4dd83..314a963 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -26,8 +26,15 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/acpi.h> #include "sb800.h" +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + static void lpc_init(device_t dev) { u8 byte; @@ -243,6 +250,9 @@ static struct device_operations lpc_ops = { .read_resources = sb800_lpc_read_resources, .set_resources = sb800_lpc_set_resources, .enable_resources = sb800_lpc_enable_resources, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci,

1 0

Patch set updated for coreboot: 5b36fab i82801ix: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14

04 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7329 -gerrit commit 5b36fabb1429a484b5713dc7d0a873ebc40b4249 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:21:06 2014 +0100 i82801ix: Move to implicit length patching Change-Id: I4027bc8c017901781ae56c7d3bd751bac50719f2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801ix/lpc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 664088c..dc2cfe8 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -544,16 +544,15 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { - int scopelen; memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); /* Add it to SSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } } #endif

1 0

Patch set updated for coreboot: e70769d i82801gx: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14

04 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7328 -gerrit commit e70769d24983fa8554bec48b9b0d56c263be164a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:20:56 2014 +0100 i82801gx: Move to implicit length patching Change-Id: Idba0f33d231084d02392e23026f567c30f77b316 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801gx/lpc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 10e40be..0618676 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -606,16 +606,15 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { - int scopelen; memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); /* Add it to SSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } }

1 0

Patch set updated for coreboot: 3d301a5 lenovo/wacom: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14

04 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7331 -gerrit commit 3d301a57e82aa6b13d76b3907b69594d0fb91392 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:17:30 2014 +0100 lenovo/wacom: Move to implicit length patching Change-Id: Ica8a54ab215d09a2d2de93f316e3831ae4bfe5f5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/lenovo/wacom.c | 84 +++++++++++++++++++++------------------------- 1 file changed, 38 insertions(+), 46 deletions(-) diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 33a2879..4a79e9a 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -93,84 +93,76 @@ void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, int have_dock_serial) { - int scopelen, devicelen, reslen, methodlen; + int reslen; - scopelen = acpigen_write_scope(scope); + acpigen_write_scope(scope); if (drivers_lenovo_is_wacom_present()) { /* Device op. */ - scopelen += acpigen_emit_byte(0x5b); - scopelen += acpigen_emit_byte(0x82); - devicelen = acpigen_write_len_f(); - devicelen += acpigen_emit_namestring("DTR"); + acpigen_emit_byte(0x5b); + acpigen_emit_byte(0x82); + acpigen_write_len_f(); + acpigen_emit_namestring("DTR"); - devicelen += acpigen_write_name("_HID"); - devicelen += acpigen_emit_eisaid("WACF004"); + acpigen_write_name("_HID"); + acpigen_emit_eisaid("WACF004"); - devicelen += acpigen_write_name("_CRS"); + acpigen_write_name("_CRS"); reslen = acpigen_write_resourcetemplate_header(); reslen += acpigen_write_io16(0x200, 0x200, 1, 8, 1); reslen += acpigen_write_irq((1 << 5)); - devicelen += reslen; - devicelen += acpigen_write_resourcetemplate_footer(reslen); + acpigen_write_resourcetemplate_footer(reslen); /* method op */ - devicelen += acpigen_emit_byte(0x14); - methodlen = acpigen_write_len_f(); - methodlen += acpigen_emit_namestring("_STA"); + acpigen_emit_byte(0x14); + acpigen_write_len_f(); + acpigen_emit_namestring("_STA"); /* no fnarg */ - methodlen += acpigen_emit_byte(0x00); + acpigen_emit_byte(0x00); /* return */ - methodlen += acpigen_emit_byte(0xa4); - methodlen += acpigen_write_byte(0xf); + acpigen_emit_byte(0xa4); + acpigen_write_byte(0xf); + acpigen_pop_len(); - acpigen_patch_len(methodlen); - devicelen += methodlen; - - acpigen_patch_len(devicelen - 1); - scopelen += devicelen; + acpigen_pop_len(); } if (have_dock_serial) { /* Device op. */ - scopelen += acpigen_emit_byte(0x5b); - scopelen += acpigen_emit_byte(0x82); - devicelen = acpigen_write_len_f(); - devicelen += acpigen_emit_namestring("COMA"); - - devicelen += acpigen_write_name("_HID"); - devicelen += acpigen_emit_eisaid("PNP0501"); - devicelen += acpigen_write_name("_UID"); + acpigen_emit_byte(0x5b); + acpigen_emit_byte(0x82); + acpigen_write_len_f(); + acpigen_emit_namestring("COMA"); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0501"); + acpigen_write_name("_UID"); /* Byte */ - devicelen += acpigen_write_byte(0x2); + acpigen_write_byte(0x2); - devicelen += acpigen_write_name("_CRS"); + acpigen_write_name("_CRS"); reslen = acpigen_write_resourcetemplate_header(); reslen += acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); reslen += acpigen_write_irq(1 << 4); - devicelen += reslen; - devicelen += acpigen_write_resourcetemplate_footer(reslen); + acpigen_write_resourcetemplate_footer(reslen); /* method op */ - devicelen += acpigen_emit_byte(0x14); - methodlen = acpigen_write_len_f(); - methodlen += acpigen_emit_namestring("_STA"); + acpigen_emit_byte(0x14); + acpigen_write_len_f(); + acpigen_emit_namestring("_STA"); /* no fnarg */ - methodlen += acpigen_emit_byte(0x00); + acpigen_emit_byte(0x00); /* return */ - methodlen += acpigen_emit_byte(0xa4); - methodlen += acpigen_write_byte(0xf); - acpigen_patch_len(methodlen); - - devicelen += methodlen; + acpigen_emit_byte(0xa4); + acpigen_write_byte(0xf); + acpigen_pop_len(); - acpigen_patch_len(devicelen - 1); - scopelen += devicelen; + acpigen_pop_len(); } - acpigen_patch_len(scopelen - 1); + acpigen_pop_len(); }

1 0

Patch set updated for coreboot: f899b32 sch: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14

04 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7330 -gerrit commit f899b32cad4c34691b967c576d968d76644ff433 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:21:42 2014 +0100 sch: Move to implicit length patching Change-Id: I057e7d30fa3c661e83db09e27278ce9f0bec69d4 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/sch/lpc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index 7d209b1..dcf9e33 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -193,16 +193,15 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { - int scopelen; memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); /* Add it to SSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } }

1 0

Patch set updated for coreboot: 5fd7b0a ibexpeak, bd82x6x: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14

04 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7326 -gerrit commit 5fd7b0ac718d124257d6ed9fc175e6e7fcc37f55 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:09:23 2014 +0100 ibexpeak, bd82x6x: Move to implicit length patching Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/acpi.c | 98 ++++++++++++++------------------- src/cpu/intel/model_2065x/acpi.c | 58 +++++++++---------- src/cpu/intel/model_206ax/acpi.c | 91 ++++++++++++++---------------- src/cpu/intel/speedstep/acpi.c | 32 ++++------- src/southbridge/intel/bd82x6x/lpc.c | 8 +-- src/southbridge/intel/fsp_bd82x6x/lpc.c | 8 +-- src/southbridge/intel/ibexpeak/lpc.c | 8 +-- 7 files changed, 130 insertions(+), 173 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index 28aeb43..a57f0b5 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -51,7 +51,7 @@ static int get_cores_per_package(void) static int generate_cstate_entries(acpi_cstate_t *cstates, int c1, int c2, int c3) { - int length, cstate_count = 0; + int cstate_count = 0; /* Count number of active C-states */ if (c1 > 0) @@ -63,32 +63,30 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, if (!cstate_count) return 0; - length = acpigen_write_package(cstate_count + 1); - length += acpigen_write_byte(cstate_count); + acpigen_write_package(cstate_count + 1); + acpigen_write_byte(cstate_count); /* Add an entry if the level is enabled */ if (c1 > 0) { cstates[c1].ctype = 1; - length += acpigen_write_CST_package_entry(&cstates[c1]); + acpigen_write_CST_package_entry(&cstates[c1]); } if (c2 > 0) { cstates[c2].ctype = 2; - length += acpigen_write_CST_package_entry(&cstates[c2]); + acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { cstates[c3].ctype = 3; - length += acpigen_write_CST_package_entry(&cstates[c3]); + acpigen_write_CST_package_entry(&cstates[c3]); } - acpigen_patch_len(length - 1); - return length; + acpigen_pop_len(); } -static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { struct cpu_info *info; struct cpu_driver *cpu; - int len, lenif; struct device *lapic; struct cpu_intel_fsp_model_206ax_config *conf = NULL; @@ -108,27 +106,25 @@ static int generate_C_state_entries(void) if (!cpu || !cpu->cstates) return 0; - len = acpigen_emit_byte(0x14); /* MethodOp */ - len += acpigen_write_len_f(); /* PkgLength */ - len += acpigen_emit_namestring("_CST"); - len += acpigen_emit_byte(0x00); /* No Arguments */ + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */ /* If running on AC power */ - len += acpigen_emit_byte(0xa0); /* IfOp */ - lenif = acpigen_write_len_f(); /* PkgLength */ - lenif += acpigen_emit_namestring("PWRS"); - lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ - lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_acpower, conf->c2_acpower, conf->c3_acpower); - acpigen_patch_len(lenif - 1); - len += lenif; + acpigen_pop_len(); /* Else on battery power */ - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - len += generate_cstate_entries(cpu->cstates, conf->c1_battery, + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_battery, conf->c2_battery, conf->c3_battery); - acpigen_patch_len(len - 1); - return len; + acpigen_pop_len(); } static acpi_tstate_t tss_table_fine[] = { @@ -160,31 +156,27 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + cpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -210,7 +202,6 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) static int generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -245,16 +236,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + acpigen_write_PSD_package(core, cores_per_package, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = PSS_RATIO_STEP; @@ -267,13 +258,13 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -282,11 +273,11 @@ static int generate_P_state_entries(int core, int cores_per_package) ratio_turbo << 8); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); } /* First regular entry is max non-turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -302,7 +293,7 @@ static int generate_P_state_entries(int core, int cores_per_package) power = calculate_power(power_max, ratio_max, ratio); clock = ratio * SANDYBRIDGE_BCLK; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -312,15 +303,11 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); @@ -337,23 +324,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( cpuID-1, cores_per_package); /* Generate C-state tables */ - len_pr += generate_C_state_entries(); + generate_C_state_entries(); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( cpuID-1, cores_per_package); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 870020f..534f0c4 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -48,7 +48,7 @@ static int get_cores_per_package(void) return cores; } -static int generate_cstate_entries(acpi_cstate_t *cstates, +static void generate_cstate_entries(acpi_cstate_t *cstates, int c1, int c2, int c3) { int length, cstate_count = 0; @@ -61,27 +61,26 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, if (c3 > 0) ++cstate_count; if (!cstate_count) - return 0; + return; - length = acpigen_write_package(cstate_count + 1); - length += acpigen_write_byte(cstate_count); + acpigen_write_package(cstate_count + 1); + acpigen_write_byte(cstate_count); /* Add an entry if the level is enabled */ if (c1 > 0) { cstates[c1].ctype = 1; - length += acpigen_write_CST_package_entry(&cstates[c1]); + acpigen_write_CST_package_entry(&cstates[c1]); } if (c2 > 0) { cstates[c2].ctype = 2; - length += acpigen_write_CST_package_entry(&cstates[c2]); + acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { cstates[c3].ctype = 3; - length += acpigen_write_CST_package_entry(&cstates[c3]); + acpigen_write_CST_package_entry(&cstates[c3]); } - acpigen_patch_len(length - 1); - return length; + acpigen_pop_len(); } static int generate_C_state_entries(void) @@ -120,14 +119,14 @@ static int generate_C_state_entries(void) lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, conf->c2_acpower, conf->c3_acpower); - acpigen_patch_len(lenif - 1); + acpigen_pop_len(); len += lenif; /* Else on battery power */ len += acpigen_emit_byte(0xa4); /* ReturnOp */ len += generate_cstate_entries(cpu->cstates, conf->c1_battery, conf->c2_battery, conf->c3_battery); - acpigen_patch_len(len - 1); + acpigen_pop_len(); return len; } @@ -208,9 +207,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, num_entries; int ratio, power, clock, clock_max; @@ -242,16 +240,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = 25000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + acpigen_write_PSD_package(core, cores_per_package, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = PSS_RATIO_STEP; @@ -264,13 +262,13 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -279,11 +277,11 @@ static int generate_P_state_entries(int core, int cores_per_package) ratio_turbo); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); } /* First regular entry is max non-turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -299,7 +297,7 @@ static int generate_P_state_entries(int core, int cores_per_package) power = calculate_power(power_max, ratio_max, ratio); clock = ratio * NEHALEM_BCLK + ratio / 3; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -309,10 +307,7 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) @@ -334,23 +329,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( cpuID-1, cores_per_package); /* Generate C-state tables */ - len_pr += generate_C_state_entries(); + generate_C_state_entries(); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( cpuID-1, cores_per_package); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 21f9c3e..306ffb3 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -48,10 +48,10 @@ static int get_cores_per_package(void) return cores; } -static int generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) +static void generate_cstate_entries(acpi_cstate_t *cstates, + int c1, int c2, int c3) { - int length, cstate_count = 0; + int cstate_count = 0; /* Count number of active C-states */ if (c1 > 0) @@ -63,32 +63,30 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, if (!cstate_count) return 0; - length = acpigen_write_package(cstate_count + 1); - length += acpigen_write_byte(cstate_count); + acpigen_write_package(cstate_count + 1); + acpigen_write_byte(cstate_count); /* Add an entry if the level is enabled */ if (c1 > 0) { cstates[c1].ctype = 1; - length += acpigen_write_CST_package_entry(&cstates[c1]); + acpigen_write_CST_package_entry(&cstates[c1]); } if (c2 > 0) { cstates[c2].ctype = 2; - length += acpigen_write_CST_package_entry(&cstates[c2]); + acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { cstates[c3].ctype = 3; - length += acpigen_write_CST_package_entry(&cstates[c3]); + acpigen_write_CST_package_entry(&cstates[c3]); } - acpigen_patch_len(length - 1); - return length; + acpigen_pop_len(); } -static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { struct cpu_info *info; struct cpu_driver *cpu; - int len, lenif; struct device *lapic; struct cpu_intel_model_206ax_config *conf = NULL; @@ -108,27 +106,25 @@ static int generate_C_state_entries(void) if (!cpu || !cpu->cstates) return 0; - len = acpigen_emit_byte(0x14); /* MethodOp */ - len += acpigen_write_len_f(); /* PkgLength */ - len += acpigen_emit_namestring("_CST"); - len += acpigen_emit_byte(0x00); /* No Arguments */ + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */ /* If running on AC power */ - len += acpigen_emit_byte(0xa0); /* IfOp */ - lenif = acpigen_write_len_f(); /* PkgLength */ - lenif += acpigen_emit_namestring("PWRS"); - lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ - lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_patch_len(lenif - 1); - len += lenif; + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_acpower, + conf->c2_acpower, conf->c3_acpower); + acpigen_pop_len(); /* Else on battery power */ - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - len += generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_patch_len(len - 1); - return len; + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_battery, + conf->c2_battery, conf->c3_battery); + acpigen_pop_len(); } static acpi_tstate_t tss_table_fine[] = { @@ -210,7 +206,7 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) static int generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; + int len; int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -245,16 +241,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + acpigen_write_PSD_package(core, cores_per_package, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = PSS_RATIO_STEP; @@ -267,13 +263,13 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -282,11 +278,11 @@ static int generate_P_state_entries(int core, int cores_per_package) ratio_turbo << 8); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); } /* First regular entry is max non-turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -302,7 +298,7 @@ static int generate_P_state_entries(int core, int cores_per_package) power = calculate_power(power_max, ratio_max, ratio); clock = ratio * SANDYBRIDGE_BCLK; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -312,15 +308,11 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); @@ -337,23 +329,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( cpuID-1, cores_per_package); /* Generate C-state tables */ - len_pr += generate_C_state_entries(); + generate_C_state_entries(); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( cpuID-1, cores_per_package); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 98d1ee7..8a2bff1 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -82,18 +82,17 @@ static int get_fsb(void) return 600; } -static int gen_pstate_entries(const sst_table_t *const pstates, +static void gen_pstate_entries(const sst_table_t *const pstates, const int cpuID, const int cores_per_package, const uint8_t coordination) { int i; - int len, len_ps; int frequency; - len = acpigen_write_empty_PCT(); - len += acpigen_write_PSD_package( + acpigen_write_empty_PCT(); + acpigen_write_PSD_package( cpuID, cores_per_package, coordination); - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); const int fsb3 = get_fsb(); const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO( @@ -107,7 +106,7 @@ static int gen_pstate_entries(const sst_table_t *const pstates, printk(BIOS_DEBUG, "adding %x P-States between " "busratio %x and %x, ""incl. P0\n", pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); - len_ps = acpigen_write_package(pstates->num_states); + acpigen_write_package(pstates->num_states); for (i = 0; i < pstates->num_states; ++i) { const sst_state_t *const pstate = &pstates->states[i]; /* Report frequency of turbo mode as that of HFM + 1. */ @@ -119,19 +118,14 @@ static int gen_pstate_entries(const sst_table_t *const pstates, frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/12; else frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/6; - len_ps += acpigen_write_PSS_package( + acpigen_write_PSS_package( frequency, pstate->power, 0, 0, SPEEDSTEP_ENCODE_STATE(*pstate), SPEEDSTEP_ENCODE_STATE(*pstate)); } - len_ps--; - acpigen_patch_len(len_ps); + acpigen_pop_len(); - len += acpigen_write_PPC(0); - - len += len_ps; - - return len; + acpigen_write_PPC(0); } /** @@ -139,7 +133,6 @@ static int gen_pstate_entries(const sst_table_t *const pstates, */ void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; @@ -171,21 +164,20 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx. */ - len_pr = acpigen_write_processor( + acpigen_write_processor( cpuID * cores_per_package + coreID - 1, pcontrol_blk, plen); /* Generate p-state entries. */ - len_pr += gen_pstate_entries(&pstates, cpuID, + gen_pstate_entries(&pstates, cpuID, cores_per_package, coordination); /* Generate c-state entries. */ if (num_cstates > 0) - len_pr += acpigen_write_CST_package( + acpigen_write_CST_package( cstates, num_cstates); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0e3a4f6..1e16eb2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -680,8 +680,6 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { - int scopelen; - memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -700,9 +698,9 @@ static void southbridge_inject_dsdt(void) smm_setup_structures(gnvs, NULL, NULL); /* Add it to DSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } } diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..d149824 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -639,8 +639,6 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { - int scopelen; - memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -650,9 +648,9 @@ static void southbridge_inject_dsdt(void) smm_setup_structures(gnvs, NULL, NULL); /* Add it to DSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a833a3d..b08cb89 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -674,8 +674,6 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { - int scopelen; - memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -685,9 +683,9 @@ static void southbridge_inject_dsdt(void) smm_setup_structures(gnvs, NULL, NULL); /* Add it to SSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } }

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coreboot-gerrit November 2014