Patch set updated for coreboot: 0d90de4 lenovo/wacom: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14
by Vladimir Serbinenko 04 Nov '14
04 Nov '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7331
-gerrit
commit 0d90de4d03c2078d2cb6a96ec89857ada5baa504
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Tue Nov 4 21:17:30 2014 +0100
lenovo/wacom: Move to implicit length patching
Change-Id: Ica8a54ab215d09a2d2de93f316e3831ae4bfe5f5
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/drivers/lenovo/wacom.c | 84 +++++++++++++++++++++-------------------------
1 file changed, 38 insertions(+), 46 deletions(-)
diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c
index 33a2879..4a79e9a 100644
--- a/src/drivers/lenovo/wacom.c
+++ b/src/drivers/lenovo/wacom.c
@@ -93,84 +93,76 @@ void
drivers_lenovo_serial_ports_ssdt_generate(const char *scope,
int have_dock_serial)
{
- int scopelen, devicelen, reslen, methodlen;
+ int reslen;
- scopelen = acpigen_write_scope(scope);
+ acpigen_write_scope(scope);
if (drivers_lenovo_is_wacom_present()) {
/* Device op. */
- scopelen += acpigen_emit_byte(0x5b);
- scopelen += acpigen_emit_byte(0x82);
- devicelen = acpigen_write_len_f();
- devicelen += acpigen_emit_namestring("DTR");
+ acpigen_emit_byte(0x5b);
+ acpigen_emit_byte(0x82);
+ acpigen_write_len_f();
+ acpigen_emit_namestring("DTR");
- devicelen += acpigen_write_name("_HID");
- devicelen += acpigen_emit_eisaid("WACF004");
+ acpigen_write_name("_HID");
+ acpigen_emit_eisaid("WACF004");
- devicelen += acpigen_write_name("_CRS");
+ acpigen_write_name("_CRS");
reslen = acpigen_write_resourcetemplate_header();
reslen += acpigen_write_io16(0x200, 0x200, 1, 8, 1);
reslen += acpigen_write_irq((1 << 5));
- devicelen += reslen;
- devicelen += acpigen_write_resourcetemplate_footer(reslen);
+ acpigen_write_resourcetemplate_footer(reslen);
/* method op */
- devicelen += acpigen_emit_byte(0x14);
- methodlen = acpigen_write_len_f();
- methodlen += acpigen_emit_namestring("_STA");
+ acpigen_emit_byte(0x14);
+ acpigen_write_len_f();
+ acpigen_emit_namestring("_STA");
/* no fnarg */
- methodlen += acpigen_emit_byte(0x00);
+ acpigen_emit_byte(0x00);
/* return */
- methodlen += acpigen_emit_byte(0xa4);
- methodlen += acpigen_write_byte(0xf);
+ acpigen_emit_byte(0xa4);
+ acpigen_write_byte(0xf);
+ acpigen_pop_len();
- acpigen_patch_len(methodlen);
- devicelen += methodlen;
-
- acpigen_patch_len(devicelen - 1);
- scopelen += devicelen;
+ acpigen_pop_len();
}
if (have_dock_serial) {
/* Device op. */
- scopelen += acpigen_emit_byte(0x5b);
- scopelen += acpigen_emit_byte(0x82);
- devicelen = acpigen_write_len_f();
- devicelen += acpigen_emit_namestring("COMA");
-
- devicelen += acpigen_write_name("_HID");
- devicelen += acpigen_emit_eisaid("PNP0501");
- devicelen += acpigen_write_name("_UID");
+ acpigen_emit_byte(0x5b);
+ acpigen_emit_byte(0x82);
+ acpigen_write_len_f();
+ acpigen_emit_namestring("COMA");
+
+ acpigen_write_name("_HID");
+ acpigen_emit_eisaid("PNP0501");
+ acpigen_write_name("_UID");
/* Byte */
- devicelen += acpigen_write_byte(0x2);
+ acpigen_write_byte(0x2);
- devicelen += acpigen_write_name("_CRS");
+ acpigen_write_name("_CRS");
reslen = acpigen_write_resourcetemplate_header();
reslen += acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1);
reslen += acpigen_write_irq(1 << 4);
- devicelen += reslen;
- devicelen += acpigen_write_resourcetemplate_footer(reslen);
+ acpigen_write_resourcetemplate_footer(reslen);
/* method op */
- devicelen += acpigen_emit_byte(0x14);
- methodlen = acpigen_write_len_f();
- methodlen += acpigen_emit_namestring("_STA");
+ acpigen_emit_byte(0x14);
+ acpigen_write_len_f();
+ acpigen_emit_namestring("_STA");
/* no fnarg */
- methodlen += acpigen_emit_byte(0x00);
+ acpigen_emit_byte(0x00);
/* return */
- methodlen += acpigen_emit_byte(0xa4);
- methodlen += acpigen_write_byte(0xf);
- acpigen_patch_len(methodlen);
-
- devicelen += methodlen;
+ acpigen_emit_byte(0xa4);
+ acpigen_write_byte(0xf);
+ acpigen_pop_len();
- acpigen_patch_len(devicelen - 1);
- scopelen += devicelen;
+ acpigen_pop_len();
}
- acpigen_patch_len(scopelen - 1);
+ acpigen_pop_len();
}
1
0
Patch set updated for coreboot: e4e5374 sch: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14
by Vladimir Serbinenko 04 Nov '14
04 Nov '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7330
-gerrit
commit e4e537477ea3ff077b47878cf47edd44590dfab8
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Tue Nov 4 21:21:42 2014 +0100
sch: Move to implicit length patching
Change-Id: I057e7d30fa3c661e83db09e27278ce9f0bec69d4
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/southbridge/intel/sch/lpc.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index 7d209b1..dcf9e33 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -193,16 +193,15 @@ static void southbridge_inject_dsdt(void)
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
if (gnvs) {
- int scopelen;
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
/* Add it to SSDT. */
- scopelen = acpigen_write_scope("\\");
- scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
- acpigen_patch_len(scopelen - 1);
+ acpigen_write_scope("\\");
+ acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_pop_len();
}
}
1
0
Patch set updated for coreboot: eff094f haswell: Move to implicit length patching
by Vladimir Serbinenko 04 Nov '14
by Vladimir Serbinenko 04 Nov '14
04 Nov '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7327
-gerrit
commit eff094f36fd4b760246bf89c3019c65e4abb86f3
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Tue Nov 4 21:10:59 2014 +0100
haswell: Move to implicit length patching
Change-Id: I662ba2a08f9a176a84b8318c8004aa5db7239567
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/cpu/intel/haswell/acpi.c | 112 +++++++++++++++-------------------
src/southbridge/intel/lynxpoint/lpc.c | 8 +--
2 files changed, 52 insertions(+), 68 deletions(-)
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 544436f..6323d27 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -50,10 +50,10 @@ static int get_cores_per_package(void)
return cores;
}
-static int generate_cstate_entries(acpi_cstate_t *cstates,
+static void generate_cstate_entries(acpi_cstate_t *cstates,
int c1, int c2, int c3)
{
- int length, cstate_count = 0;
+ int cstate_count = 0;
/* Count number of active C-states */
if (c1 > 0)
@@ -63,74 +63,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates,
if (c3 > 0)
++cstate_count;
if (!cstate_count)
- return 0;
+ return;
- length = acpigen_write_package(cstate_count + 1);
- length += acpigen_write_byte(cstate_count);
+ acpigen_write_package(cstate_count + 1);
+ acpigen_write_byte(cstate_count);
/* Add an entry if the level is enabled */
if (c1 > 0) {
cstates[c1].ctype = 1;
- length += acpigen_write_CST_package_entry(&cstates[c1]);
+ acpigen_write_CST_package_entry(&cstates[c1]);
}
if (c2 > 0) {
cstates[c2].ctype = 2;
- length += acpigen_write_CST_package_entry(&cstates[c2]);
+ acpigen_write_CST_package_entry(&cstates[c2]);
}
if (c3 > 0) {
cstates[c3].ctype = 3;
- length += acpigen_write_CST_package_entry(&cstates[c3]);
+ acpigen_write_CST_package_entry(&cstates[c3]);
}
- acpigen_patch_len(length - 1);
- return length;
+ acpigen_pop_len();
}
-static int generate_C_state_entries(void)
+static void generate_C_state_entries(void)
{
struct cpu_info *info;
struct cpu_driver *cpu;
- int len, lenif;
struct device *lapic;
struct cpu_intel_haswell_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic)
- return 0;
+ return;
conf = lapic->chip_info;
if (!conf)
- return 0;
+ return;
/* Find CPU map of supported C-states */
info = cpu_info();
if (!info)
- return 0;
+ return;
cpu = find_cpu_driver(info->cpu);
if (!cpu || !cpu->cstates)
- return 0;
+ return;
- len = acpigen_emit_byte(0x14); /* MethodOp */
- len += acpigen_write_len_f(); /* PkgLength */
- len += acpigen_emit_namestring("_CST");
- len += acpigen_emit_byte(0x00); /* No Arguments */
+ acpigen_emit_byte(0x14); /* MethodOp */
+ acpigen_write_len_f(); /* PkgLength */
+ acpigen_emit_namestring("_CST");
+ acpigen_emit_byte(0x00); /* No Arguments */
/* If running on AC power */
- len += acpigen_emit_byte(0xa0); /* IfOp */
- lenif = acpigen_write_len_f(); /* PkgLength */
- lenif += acpigen_emit_namestring("PWRS");
- lenif += acpigen_emit_byte(0xa4); /* ReturnOp */
- lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+ acpigen_emit_byte(0xa0); /* IfOp */
+ acpigen_write_len_f(); /* PkgLength */
+ acpigen_emit_namestring("PWRS");
+ acpigen_emit_byte(0xa4); /* ReturnOp */
+ generate_cstate_entries(cpu->cstates, conf->c1_acpower,
conf->c2_acpower, conf->c3_acpower);
- acpigen_patch_len(lenif - 1);
- len += lenif;
+ acpigen_pop_len();
/* Else on battery power */
- len += acpigen_emit_byte(0xa4); /* ReturnOp */
- len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+ acpigen_emit_byte(0xa4); /* ReturnOp */
+ generate_cstate_entries(cpu->cstates, conf->c1_battery,
conf->c2_battery, conf->c3_battery);
- acpigen_patch_len(len - 1);
- return len;
+ acpigen_pop_len();
}
static acpi_tstate_t tss_table_fine[] = {
@@ -162,31 +158,27 @@ static acpi_tstate_t tss_table_coarse[] = {
{ 13, 125, 0, 0x19, 0 },
};
-static int generate_T_state_entries(int core, int cores_per_package)
+static void generate_T_state_entries(int core, int cores_per_package)
{
- int len;
-
/* Indicate SW_ALL coordination for T-states */
- len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+ acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */
- len += acpigen_write_empty_PTC();
+ acpigen_write_empty_PTC();
/* Set a T-state limit that can be modified in NVS */
- len += acpigen_write_TPC("\\TLVL");
+ acpigen_write_TPC("\\TLVL");
/*
* CPUID.(EAX=6):EAX[5] indicates support
* for extended throttle levels.
*/
if (cpuid_eax(6) & (1 << 5))
- len += acpigen_write_TSS_package(
+ acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_fine), tss_table_fine);
else
- len += acpigen_write_TSS_package(
+ acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
-
- return len;
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
@@ -210,9 +202,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
return (int)power;
}
-static int generate_P_state_entries(int core, int cores_per_package)
+static void generate_P_state_entries(int core, int cores_per_package)
{
- int len, len_pss;
int ratio_min, ratio_max, ratio_turbo, ratio_step;
int coord_type, power_max, power_unit, num_entries;
int ratio, power, clock, clock_max;
@@ -247,16 +238,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */
- len = acpigen_write_empty_PCT();
+ acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */
- len += acpigen_write_PPC_NVS();
+ acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
- len += acpigen_write_PSD_package(core, 1, coord_type);
+ acpigen_write_PSD_package(core, 1, coord_type);
/* Add P-state entries in _PSS table */
- len += acpigen_write_name("_PSS");
+ acpigen_write_name("_PSS");
/* Determine ratio points */
ratio_step = PSS_RATIO_STEP;
@@ -269,13 +260,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* P[T] is Turbo state if enabled */
if (get_turbo_state() == TURBO_ENABLED) {
/* _PSS package count including Turbo */
- len_pss = acpigen_write_package(num_entries + 2);
+ acpigen_write_package(num_entries + 2);
msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
ratio_turbo = msr.lo & 0xff;
/* Add entry for Turbo ratio */
- len_pss += acpigen_write_PSS_package(
+ acpigen_write_PSS_package(
clock_max + 1, /*MHz*/
power_max, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
@@ -284,11 +275,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
ratio_turbo << 8); /*status*/
} else {
/* _PSS package count without Turbo */
- len_pss = acpigen_write_package(num_entries + 1);
+ acpigen_write_package(num_entries + 1);
}
/* First regular entry is max non-turbo ratio */
- len_pss += acpigen_write_PSS_package(
+ acpigen_write_PSS_package(
clock_max, /*MHz*/
power_max, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
@@ -304,7 +295,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * HASWELL_BCLK;
- len_pss += acpigen_write_PSS_package(
+ acpigen_write_PSS_package(
clock, /*MHz*/
power, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
@@ -314,15 +305,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
}
/* Fix package length */
- len_pss--;
- acpigen_patch_len(len_pss);
-
- return len + len_pss;
+ acpigen_pop_len();
}
void generate_cpu_entries(void)
{
- int len_pr;
int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
@@ -339,23 +326,22 @@ void generate_cpu_entries(void)
}
/* Generate processor \_PR.CPUx */
- len_pr = acpigen_write_processor(
+ acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);
/* Generate P-state tables */
- len_pr += generate_P_state_entries(
+ generate_P_state_entries(
coreID-1, cores_per_package);
/* Generate C-state tables */
- len_pr += generate_C_state_entries();
+ generate_C_state_entries();
/* Generate T-state tables */
- len_pr += generate_T_state_entries(
+ generate_T_state_entries(
cpuID-1, cores_per_package);
- len_pr--;
- acpigen_patch_len(len_pr);
+ acpigen_pop_len();
}
}
}
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a202424..563cb0a 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -755,8 +755,6 @@ static void southbridge_inject_dsdt(void)
}
if (gnvs) {
- int scopelen;
-
acpi_create_gnvs(gnvs);
gnvs->apic = 1;
@@ -775,9 +773,9 @@ static void southbridge_inject_dsdt(void)
smm_setup_structures(gnvs, NULL, NULL);
/* Add it to DSDT. */
- scopelen = acpigen_write_scope("\\");
- scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
- acpigen_patch_len(scopelen - 1);
+ acpigen_write_scope("\\");
+ acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_pop_len();
}
}
1
0
Patch set updated for coreboot: 6891a10 mainboard: Don't hide pointer behind typedef
by Edward O'Callaghan 04 Nov '14
by Edward O'Callaghan 04 Nov '14
04 Nov '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7139
-gerrit
commit 6891a105c789697e28b34fe2626a9af3fc55b46c
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Tue Oct 21 09:54:41 2014 +1100
mainboard: Don't hide pointer behind typedef
Change-Id: I4a0e4e1598e16e13b43401c7e834b292121b63ce
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/advansus/a785e-i/get_bus_conf.c | 2 +-
src/mainboard/advansus/a785e-i/mainboard.c | 2 +-
src/mainboard/amd/bimini_fam10/get_bus_conf.c | 2 +-
src/mainboard/amd/bimini_fam10/mainboard.c | 4 ++--
src/mainboard/amd/dbm690t/get_bus_conf.c | 2 +-
src/mainboard/amd/dbm690t/mainboard.c | 4 ++--
src/mainboard/amd/dbm690t/mptable.c | 2 +-
src/mainboard/amd/dinar/mainboard.c | 2 +-
src/mainboard/amd/dinar/mptable.c | 2 +-
src/mainboard/amd/inagua/mainboard.c | 2 +-
src/mainboard/amd/inagua/mptable.c | 2 +-
src/mainboard/amd/mahogany/get_bus_conf.c | 2 +-
src/mainboard/amd/mahogany/mainboard.c | 8 ++++----
src/mainboard/amd/mahogany/mptable.c | 2 +-
src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 2 +-
src/mainboard/amd/mahogany_fam10/mainboard.c | 8 ++++----
src/mainboard/amd/mahogany_fam10/mptable.c | 2 +-
src/mainboard/amd/olivehill/mainboard.c | 2 +-
src/mainboard/amd/olivehill/mptable.c | 2 +-
src/mainboard/amd/olivehillplus/mainboard.c | 2 +-
src/mainboard/amd/olivehillplus/mptable.c | 2 +-
src/mainboard/amd/parmer/mainboard.c | 2 +-
src/mainboard/amd/parmer/mptable.c | 2 +-
src/mainboard/amd/persimmon/mainboard.c | 2 +-
src/mainboard/amd/persimmon/mptable.c | 2 +-
src/mainboard/amd/pistachio/get_bus_conf.c | 2 +-
src/mainboard/amd/pistachio/mainboard.c | 4 ++--
src/mainboard/amd/pistachio/mptable.c | 2 +-
src/mainboard/amd/rumba/mainboard.c | 2 +-
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 4 ++--
src/mainboard/amd/serengeti_cheetah/mainboard.c | 2 +-
src/mainboard/amd/serengeti_cheetah/mptable.c | 4 ++--
.../amd/serengeti_cheetah_fam10/get_bus_conf.c | 4 ++--
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c | 4 ++--
src/mainboard/amd/south_station/mainboard.c | 2 +-
src/mainboard/amd/south_station/mptable.c | 2 +-
src/mainboard/amd/thatcher/mainboard.c | 2 +-
src/mainboard/amd/thatcher/mptable.c | 2 +-
src/mainboard/amd/thatcher/romstage.c | 2 +-
src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 2 +-
src/mainboard/amd/tilapia_fam10/mainboard.c | 14 +++++++-------
src/mainboard/amd/tilapia_fam10/mptable.c | 2 +-
src/mainboard/amd/torpedo/mainboard.c | 2 +-
src/mainboard/amd/torpedo/mptable.c | 2 +-
src/mainboard/amd/union_station/mainboard.c | 2 +-
src/mainboard/amd/union_station/mptable.c | 2 +-
src/mainboard/apple/macbook21/mainboard.c | 4 ++--
src/mainboard/arima/hdama/debug.c | 4 ++--
src/mainboard/arima/hdama/mptable.c | 10 +++++-----
src/mainboard/asrock/939a785gmh/get_bus_conf.c | 2 +-
src/mainboard/asrock/939a785gmh/mainboard.c | 4 ++--
src/mainboard/asrock/939a785gmh/mptable.c | 2 +-
src/mainboard/asrock/e350m1/mainboard.c | 2 +-
src/mainboard/asrock/e350m1/mptable.c | 2 +-
src/mainboard/asrock/imb-a180/mainboard.c | 2 +-
src/mainboard/asrock/imb-a180/mptable.c | 2 +-
src/mainboard/asus/a8n_e/get_bus_conf.c | 2 +-
src/mainboard/asus/a8n_e/mptable.c | 2 +-
src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +-
src/mainboard/asus/a8v-e_se/romstage.c | 2 +-
src/mainboard/asus/dsbf/mainboard.c | 2 +-
src/mainboard/asus/f2a85-m/mainboard.c | 2 +-
src/mainboard/asus/f2a85-m/mptable.c | 2 +-
src/mainboard/asus/f2a85-m/romstage.c | 2 +-
src/mainboard/asus/k8v-x/mainboard.c | 2 +-
src/mainboard/asus/k8v-x/romstage.c | 2 +-
src/mainboard/asus/m2n-e/get_bus_conf.c | 2 +-
src/mainboard/asus/m2n-e/mainboard.c | 2 +-
src/mainboard/asus/m2n-e/mptable.c | 2 +-
src/mainboard/asus/m2n-e/romstage.c | 2 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 2 +-
src/mainboard/asus/m2v/mainboard.c | 2 +-
src/mainboard/asus/m2v/romstage.c | 4 ++--
src/mainboard/asus/m4a78-em/get_bus_conf.c | 2 +-
src/mainboard/asus/m4a78-em/mainboard.c | 8 ++++----
src/mainboard/asus/m4a78-em/mptable.c | 2 +-
src/mainboard/asus/m4a785-m/get_bus_conf.c | 2 +-
src/mainboard/asus/m4a785-m/mainboard.c | 10 +++++-----
src/mainboard/asus/m4a785-m/mptable.c | 2 +-
src/mainboard/asus/m5a88-v/get_bus_conf.c | 2 +-
src/mainboard/asus/m5a88-v/mainboard.c | 2 +-
src/mainboard/avalue/eax-785e/get_bus_conf.c | 2 +-
src/mainboard/avalue/eax-785e/mainboard.c | 2 +-
src/mainboard/bachmann/ot200/mainboard.c | 2 +-
src/mainboard/bcom/winnetp680/romstage.c | 2 +-
src/mainboard/broadcom/blast/get_bus_conf.c | 2 +-
src/mainboard/broadcom/blast/mptable.c | 4 ++--
src/mainboard/dmp/vortex86ex/mainboard.c | 2 +-
src/mainboard/emulation/qemu-armv7/mainboard.c | 2 +-
src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +-
src/mainboard/emulation/qemu-q35/mainboard.c | 2 +-
src/mainboard/getac/p470/mainboard.c | 6 +++---
src/mainboard/getac/p470/romstage.c | 8 ++++----
src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 2 +-
src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +-
src/mainboard/gigabyte/m57sli/get_bus_conf.c | 2 +-
src/mainboard/gigabyte/m57sli/mainboard.c | 2 +-
src/mainboard/gigabyte/m57sli/mptable.c | 2 +-
src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 2 +-
src/mainboard/gigabyte/ma785gm/mainboard.c | 8 ++++----
src/mainboard/gigabyte/ma785gm/mptable.c | 2 +-
src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 2 +-
src/mainboard/gigabyte/ma785gmt/mainboard.c | 12 ++++++------
src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +-
src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 2 +-
src/mainboard/gigabyte/ma78gm/mainboard.c | 6 +++---
src/mainboard/gigabyte/ma78gm/mptable.c | 2 +-
src/mainboard/gizmosphere/gizmo/mainboard.c | 4 ++--
src/mainboard/gizmosphere/gizmo/mptable.c | 2 +-
src/mainboard/google/bolt/mainboard.c | 6 +++---
src/mainboard/google/butterfly/mainboard.c | 6 +++---
src/mainboard/google/daisy/mainboard.c | 4 ++--
src/mainboard/google/falco/mainboard.c | 6 +++---
src/mainboard/google/link/mainboard.c | 6 +++---
src/mainboard/google/nyan/mainboard.c | 4 ++--
src/mainboard/google/nyan_big/mainboard.c | 4 ++--
src/mainboard/google/panther/mainboard.c | 4 ++--
src/mainboard/google/parrot/mainboard.c | 6 +++---
src/mainboard/google/peach_pit/mainboard.c | 4 ++--
src/mainboard/google/peppy/mainboard.c | 6 +++---
src/mainboard/google/rambi/mainboard.c | 6 +++---
src/mainboard/google/samus/mainboard.c | 6 +++---
src/mainboard/google/slippy/mainboard.c | 6 +++---
src/mainboard/google/storm/mainboard.c | 4 ++--
src/mainboard/google/stout/mainboard.c | 4 ++--
src/mainboard/hp/dl145_g1/get_bus_conf.c | 2 +-
src/mainboard/hp/dl145_g1/mptable.c | 2 +-
src/mainboard/hp/dl145_g3/get_bus_conf.c | 2 +-
src/mainboard/hp/dl145_g3/mptable.c | 8 ++++----
src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 2 +-
src/mainboard/hp/dl165_g6_fam10/mptable.c | 8 ++++----
src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +-
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 2 +-
src/mainboard/ibase/mb899/mainboard.c | 2 +-
src/mainboard/ibase/mb899/romstage.c | 2 +-
src/mainboard/ibm/e325/mptable.c | 4 ++--
src/mainboard/ibm/e326/mptable.c | 4 ++--
src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +-
src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +-
src/mainboard/intel/baskingridge/mainboard.c | 2 +-
src/mainboard/intel/bayleybay_fsp/mainboard.c | 2 +-
src/mainboard/intel/cougar_canyon2/mainboard.c | 2 +-
src/mainboard/intel/cougar_canyon2/romstage.c | 2 +-
src/mainboard/intel/eagleheights/debug.c | 4 ++--
src/mainboard/intel/eagleheights/mptable.c | 2 +-
src/mainboard/intel/emeraldlake2/mainboard.c | 2 +-
src/mainboard/intel/emeraldlake2/romstage.c | 2 +-
src/mainboard/intel/jarrell/debug.c | 4 ++--
src/mainboard/intel/jarrell/mptable.c | 4 ++--
src/mainboard/intel/jarrell/romstage.c | 2 +-
src/mainboard/intel/jarrell/watchdog.c | 8 ++++----
src/mainboard/intel/minnowmax/mainboard.c | 2 +-
src/mainboard/intel/mohonpeak/mainboard.c | 2 +-
src/mainboard/intel/truxton/mptable.c | 2 +-
src/mainboard/intel/wtm2/mainboard.c | 2 +-
src/mainboard/intel/xe7501devkit/mptable.c | 2 +-
src/mainboard/iwave/iWRainbowG6/mainboard.c | 2 +-
src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +-
src/mainboard/iwill/dk8_htx/get_bus_conf.c | 4 ++--
src/mainboard/iwill/dk8_htx/mainboard.c | 2 +-
src/mainboard/iwill/dk8_htx/mptable.c | 4 ++--
src/mainboard/iwill/dk8s2/mptable.c | 4 ++--
src/mainboard/iwill/dk8x/mptable.c | 4 ++--
src/mainboard/jetway/j7f2/romstage.c | 2 +-
src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +-
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +-
src/mainboard/jetway/pa78vm5/get_bus_conf.c | 2 +-
src/mainboard/jetway/pa78vm5/mainboard.c | 8 ++++----
src/mainboard/jetway/pa78vm5/mptable.c | 2 +-
src/mainboard/kontron/986lcd-m/mainboard.c | 2 +-
src/mainboard/kontron/986lcd-m/romstage.c | 6 +++---
src/mainboard/kontron/kt690/get_bus_conf.c | 2 +-
src/mainboard/kontron/kt690/mainboard.c | 4 ++--
src/mainboard/kontron/kt690/mptable.c | 2 +-
src/mainboard/kontron/ktqm77/mainboard.c | 6 +++---
src/mainboard/kontron/ktqm77/romstage.c | 6 +++---
src/mainboard/lenovo/t520/mainboard.c | 4 ++--
src/mainboard/lenovo/t530/mainboard.c | 4 ++--
src/mainboard/lenovo/t60/mainboard.c | 7 ++++---
src/mainboard/lenovo/t60/romstage.c | 2 +-
src/mainboard/lenovo/x200/mainboard.c | 4 ++--
src/mainboard/lenovo/x201/mainboard.c | 6 +++---
src/mainboard/lenovo/x220/mainboard.c | 4 ++--
src/mainboard/lenovo/x230/mainboard.c | 4 ++--
src/mainboard/lenovo/x60/mainboard.c | 8 +++++---
src/mainboard/lenovo/x60/romstage.c | 2 +-
src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +-
src/mainboard/lippert/frontrunner-af/mptable.c | 2 +-
src/mainboard/lippert/toucan-af/mainboard.c | 2 +-
src/mainboard/lippert/toucan-af/mptable.c | 2 +-
src/mainboard/msi/ms7135/get_bus_conf.c | 2 +-
src/mainboard/msi/ms7135/mptable.c | 2 +-
src/mainboard/msi/ms7260/get_bus_conf.c | 2 +-
src/mainboard/msi/ms7260/mainboard.c | 2 +-
src/mainboard/msi/ms7260/mptable.c | 2 +-
src/mainboard/msi/ms9185/get_bus_conf.c | 2 +-
src/mainboard/msi/ms9185/mptable.c | 4 ++--
src/mainboard/msi/ms9282/get_bus_conf.c | 2 +-
src/mainboard/msi/ms9282/mainboard.c | 2 +-
src/mainboard/msi/ms9282/mptable.c | 2 +-
src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 2 +-
src/mainboard/msi/ms9652_fam10/mainboard.c | 2 +-
src/mainboard/msi/ms9652_fam10/mptable.c | 2 +-
src/mainboard/newisys/khepri/mptable.c | 4 ++--
src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 2 +-
src/mainboard/nvidia/l1_2pvv/mainboard.c | 2 +-
src/mainboard/nvidia/l1_2pvv/mptable.c | 8 ++++----
src/mainboard/packardbell/ms2290/mainboard.c | 2 +-
src/mainboard/rca/rm4100/mainboard.c | 4 ++--
src/mainboard/roda/rk886ex/mainboard.c | 4 ++--
src/mainboard/roda/rk886ex/romstage.c | 8 ++++----
src/mainboard/roda/rk9/mainboard.c | 2 +-
src/mainboard/roda/rk9/romstage.c | 2 +-
src/mainboard/samsung/lumpy/mainboard.c | 8 +++-----
src/mainboard/samsung/stumpy/mainboard.c | 2 +-
src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 2 +-
src/mainboard/siemens/sitemp_g1p1/mainboard.c | 21 +++++++++++----------
src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +-
src/mainboard/sunw/ultra40/get_bus_conf.c | 2 +-
src/mainboard/sunw/ultra40/mptable.c | 2 +-
src/mainboard/supermicro/h8dme/get_bus_conf.c | 2 +-
src/mainboard/supermicro/h8dme/mptable.c | 2 +-
src/mainboard/supermicro/h8dmr/get_bus_conf.c | 2 +-
src/mainboard/supermicro/h8dmr/mptable.c | 2 +-
src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c | 2 +-
src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +-
src/mainboard/supermicro/h8qgi/mainboard.c | 2 +-
src/mainboard/supermicro/h8qgi/mptable.c | 2 +-
src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c | 2 +-
src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +-
src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++--
src/mainboard/supermicro/h8scm/mainboard.c | 2 +-
src/mainboard/supermicro/h8scm/mptable.c | 2 +-
src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c | 2 +-
src/mainboard/supermicro/h8scm_fam10/mainboard.c | 6 +++---
src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +-
src/mainboard/supermicro/x6dai_g/debug.c | 4 ++--
src/mainboard/supermicro/x6dai_g/mptable.c | 2 +-
src/mainboard/supermicro/x6dai_g/romstage.c | 2 +-
src/mainboard/supermicro/x6dai_g/watchdog.c | 2 +-
src/mainboard/supermicro/x6dhe_g/debug.c | 4 ++--
src/mainboard/supermicro/x6dhe_g/mptable.c | 4 ++--
src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +-
src/mainboard/supermicro/x6dhe_g/watchdog.c | 6 +++---
src/mainboard/supermicro/x6dhe_g2/debug.c | 4 ++--
src/mainboard/supermicro/x6dhe_g2/mptable.c | 4 ++--
src/mainboard/supermicro/x6dhe_g2/romstage.c | 2 +-
src/mainboard/supermicro/x6dhe_g2/watchdog.c | 6 +++---
src/mainboard/supermicro/x6dhr_ig/debug.c | 4 ++--
src/mainboard/supermicro/x6dhr_ig/mptable.c | 4 ++--
src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +-
src/mainboard/supermicro/x6dhr_ig/watchdog.c | 6 +++---
src/mainboard/supermicro/x6dhr_ig2/debug.c | 4 ++--
src/mainboard/supermicro/x6dhr_ig2/mptable.c | 4 ++--
src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +-
src/mainboard/supermicro/x6dhr_ig2/watchdog.c | 6 +++---
src/mainboard/supermicro/x7db8/mainboard.c | 2 +-
src/mainboard/technexion/tim5690/get_bus_conf.c | 2 +-
src/mainboard/technexion/tim5690/mainboard.c | 4 ++--
src/mainboard/technexion/tim5690/mptable.c | 2 +-
src/mainboard/technexion/tim8690/get_bus_conf.c | 2 +-
src/mainboard/technexion/tim8690/mainboard.c | 6 +++---
src/mainboard/technexion/tim8690/mptable.c | 2 +-
src/mainboard/thomson/ip1000/mainboard.c | 4 ++--
src/mainboard/tyan/s2735/mptable.c | 2 +-
src/mainboard/tyan/s2850/mptable.c | 4 ++--
src/mainboard/tyan/s2875/mptable.c | 4 ++--
src/mainboard/tyan/s2880/mptable.c | 6 +++---
src/mainboard/tyan/s2881/get_bus_conf.c | 2 +-
src/mainboard/tyan/s2881/mptable.c | 2 +-
src/mainboard/tyan/s2882/mptable.c | 6 +++---
src/mainboard/tyan/s2885/get_bus_conf.c | 2 +-
src/mainboard/tyan/s2885/mptable.c | 2 +-
src/mainboard/tyan/s2891/get_bus_conf.c | 2 +-
src/mainboard/tyan/s2891/mainboard.c | 2 +-
src/mainboard/tyan/s2891/mptable.c | 2 +-
src/mainboard/tyan/s2892/get_bus_conf.c | 2 +-
src/mainboard/tyan/s2892/mainboard.c | 2 +-
src/mainboard/tyan/s2892/mptable.c | 2 +-
src/mainboard/tyan/s2895/get_bus_conf.c | 2 +-
src/mainboard/tyan/s2895/mainboard.c | 2 +-
src/mainboard/tyan/s2895/mptable.c | 2 +-
src/mainboard/tyan/s2912/get_bus_conf.c | 2 +-
src/mainboard/tyan/s2912/mptable.c | 2 +-
src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 2 +-
src/mainboard/tyan/s2912_fam10/mptable.c | 2 +-
src/mainboard/tyan/s4880/mptable.c | 6 +++---
src/mainboard/tyan/s4882/mptable.c | 6 +++---
src/mainboard/tyan/s8226/mainboard.c | 2 +-
src/mainboard/tyan/s8226/mptable.c | 2 +-
src/mainboard/via/epia-cn/romstage.c | 2 +-
src/mainboard/via/epia-m/romstage.c | 6 +++---
src/mainboard/via/epia-m700/romstage.c | 8 ++++----
src/mainboard/via/epia-m850/mainboard.c | 2 +-
src/mainboard/via/epia-n/romstage.c | 4 ++--
src/mainboard/via/epia/romstage.c | 4 ++--
src/mainboard/via/vt8454c/romstage.c | 2 +-
src/mainboard/winent/mb6047/get_bus_conf.c | 2 +-
src/mainboard/winent/mb6047/mainboard.c | 2 +-
src/mainboard/winent/mb6047/mptable.c | 2 +-
302 files changed, 483 insertions(+), 481 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c
index 80e1d3e..2c5757a 100644
--- a/src/mainboard/advansus/a785e-i/get_bus_conf.c
+++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c
@@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index 9b6450d..686e968 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -73,7 +73,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in A785E-I board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
index f7c55143..6b31272 100644
--- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
@@ -64,7 +64,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index 32c8862..cd4f50e 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -100,7 +100,7 @@ static void get_ide_dma66(void)
{
u8 byte;
/*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
+ struct device * sm_dev, ide_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -123,7 +123,7 @@ static void get_ide_dma66(void)
* enable the dedicated function in bimini board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c
index 084e2b1..c959280 100644
--- a/src/mainboard/amd/dbm690t/get_bus_conf.c
+++ b/src/mainboard/amd/dbm690t/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
index 43a8d91..b92426c 100644
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ b/src/mainboard/amd/dbm690t/mainboard.c
@@ -119,7 +119,7 @@ static void set_thermal_config(void)
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -180,7 +180,7 @@ static void set_thermal_config(void)
* enable the dedicated function in dbm690t board.
* This function called early than rs690_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index 09d137a..c154fe4 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
index 00f1a84..83171a0 100644
--- a/src/mainboard/amd/dinar/mainboard.c
+++ b/src/mainboard/amd/dinar/mainboard.c
@@ -68,7 +68,7 @@ void set_pcie_dereset(void *nbconfig)
/*************************************************
* enable the dedicated function in dinar board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
}
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index 4e481f5..e796ffe 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
int bus_isa;
u32 apicid_sb700;
u32 apicid_rd890;
- device_t dev;
+ struct device * dev;
u32 dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index dc23007..0c57350 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -74,7 +74,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 7686bd2..65f67cc 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c
index f05ce7f..2e5a44f 100644
--- a/src/mainboard/amd/mahogany/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 0e542ff..e851e8f 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -37,7 +37,7 @@ u8 is_dev3_present(void);
void set_pcie_dereset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -50,7 +50,7 @@ void set_pcie_dereset()
void set_pcie_reset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -70,7 +70,7 @@ static void get_ide_dma66(void)
{
u8 byte;
/*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
+ struct device * sm_dev, ide_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -97,7 +97,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in mahogany board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index bd31846..bebf041 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 7d4514a..8f90235 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -37,7 +37,7 @@ u8 is_dev3_present(void);
void set_pcie_dereset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -50,7 +50,7 @@ void set_pcie_dereset()
void set_pcie_reset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -70,7 +70,7 @@ static void get_ide_dma66(void)
{
u8 byte;
/*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
+ struct device * sm_dev, ide_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -98,7 +98,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in mahogany board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c
index ac40c84..961a111 100644
--- a/src/mainboard/amd/olivehill/mainboard.c
+++ b/src/mainboard/amd/olivehill/mainboard.c
@@ -32,7 +32,7 @@
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index db4a3ff..d209582 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c
index 6073fd4..1e58d88 100644
--- a/src/mainboard/amd/olivehillplus/mainboard.c
+++ b/src/mainboard/amd/olivehillplus/mainboard.c
@@ -32,7 +32,7 @@
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index 73660e4..0ca9217 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c
index 2ba714a..4b192c2 100644
--- a/src/mainboard/amd/parmer/mainboard.c
+++ b/src/mainboard/amd/parmer/mainboard.c
@@ -32,7 +32,7 @@
/*************************************************
* enable the dedicated function in parmer board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 05da01a..7999dd8 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 58ac983..34918a8 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -151,7 +151,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 1227d89..1ae44c4 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c
index 084e2b1..c959280 100644
--- a/src/mainboard/amd/pistachio/get_bus_conf.c
+++ b/src/mainboard/amd/pistachio/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index 75f92bd..db2cbcf 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -76,7 +76,7 @@ static void set_thermal_config(void)
u8 byte, byte2;
u16 word;
u32 dword;
- device_t sm_dev;
+ struct device * sm_dev;
/* set adt7475 */
ADT7475_write_byte(0x40, 0x04);
@@ -250,7 +250,7 @@ static void set_thermal_config(void)
* enable the dedicated function in pistachio board.
* This function called early than rs690_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index 09d137a..c154fe4 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c
index 5725c78..2f6af29 100644
--- a/src/mainboard/amd/rumba/mainboard.c
+++ b/src/mainboard/amd/rumba/mainboard.c
@@ -7,7 +7,7 @@
static void init(struct device *dev)
{
- device_t nic = NULL;
+ struct device * nic = NULL;
unsigned bus = 0;
unsigned devfn = PCI_DEVFN(0xd, 0);
int nicirq = 1;
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index f5cd846..f2d7f9e 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i)
unsigned devn = sysconf.hcdn[i] & 0xff;
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
@@ -76,7 +76,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i, j;
struct mb_sysconf_t *m;
diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c
index b9c88f6..26f61f8 100644
--- a/src/mainboard/amd/serengeti_cheetah/mainboard.c
+++ b/src/mainboard/amd/serengeti_cheetah/mainboard.c
@@ -5,7 +5,7 @@
#include <arch/acpigen.h>
#include "mainboard.h"
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
}
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 866875d..341b367 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
if (dev) {
@@ -114,7 +114,7 @@ static void *smp_write_config_table(void *v)
for(i=1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii;
- device_t dev;
+ struct device * dev;
struct resource *res;
switch(sysconf.hcid[i]) {
case 1:
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 48d5cc3..02dfb3c 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -71,7 +71,7 @@ static u32 get_hcid(u32 i)
u32 id = 0;
u32 busn = (sysconf.pci1234[i] >> 12) & 0xff;
u32 devn = sysconf.hcdn[i] & 0xff;
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
@@ -95,7 +95,7 @@ void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i, j;
struct mb_sysconf_t *m;
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 5335cb8..3b4731b 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
if (dev) {
@@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v)
if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii;
int jj;
- device_t dev;
+ struct device * dev;
struct resource *res;
switch(sysconf.hcid[i]) {
case 1:
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index 43d6a78..1be0c0a 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -77,7 +77,7 @@ static void southstation_led_init(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
southstation_led_init();
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index c2ec4a2..0446e6c 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c
index 834117e..e7b7ecf 100644
--- a/src/mainboard/amd/thatcher/mainboard.c
+++ b/src/mainboard/amd/thatcher/mainboard.c
@@ -32,7 +32,7 @@
/*************************************************
* enable the dedicated function in thatcher board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
msr_t msr;
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 8ddd1b6..e34b899 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index cc97866..8ebd6b4 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -46,7 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
hudson_lpc_port80();
diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index 48e4c17..efea2fa 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -45,7 +45,7 @@ void set_pcie_dereset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
@@ -70,7 +70,7 @@ void set_pcie_reset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
@@ -102,7 +102,7 @@ static void get_ide_dma66(void)
{
u8 byte;
/*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
+ struct device * sm_dev, ide_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -127,7 +127,7 @@ static void get_ide_dma66(void)
u8 is_dev3_present(void)
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* access the smbus extended register */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -157,7 +157,7 @@ static void set_gpio40_gfx(void)
{
u8 byte;
u32 dword;
- device_t sm_dev;
+ struct device * sm_dev;
/* disable the GPIO40 as CLKREQ2# function */
byte = pm_ioread(0xd3);
byte &= ~(1 << 7);
@@ -212,7 +212,7 @@ static void set_thermal_config(void)
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -273,7 +273,7 @@ static void set_thermal_config(void)
* enable the dedicated function in tilapia board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
index 9b52b89..f5f9c94 100644
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ b/src/mainboard/amd/torpedo/mainboard.c
@@ -52,7 +52,7 @@ void set_pcie_dereset(void)
/*************************************************
* enable the dedicated function in torpedo board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
}
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 477d97a..53038dd 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -186,7 +186,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index 8816e8d..ca2e887 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -50,7 +50,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index c2ec4a2..0446e6c 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c
index 99527c1..c9858d8 100644
--- a/src/mainboard/apple/macbook21/mainboard.c
+++ b/src/mainboard/apple/macbook21/mainboard.c
@@ -41,12 +41,12 @@ int get_cst_entries(acpi_cstate_t **entries)
return 0;
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
}
diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c
index a6f0d55..d29a5b9 100644
--- a/src/mainboard/arima/hdama/debug.c
+++ b/src/mainboard/arima/hdama/debug.c
@@ -11,7 +11,7 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -50,7 +50,7 @@ static void dump_pci_device(unsigned dev)
static void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 6ee2704..c1a6cef 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -13,7 +13,7 @@
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
- device_t dev;
+ struct device * dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
@@ -48,7 +48,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
static unsigned max_apicid(void)
{
unsigned max;
- device_t dev;
+ struct device * dev;
max = 0;
for(dev = all_devices; dev; dev = dev->next) {
if (dev->path.type != DEVICE_PATH_APIC)
@@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v)
apicid_8131_1 = apicid_base + 1;
apicid_8131_2 = apicid_base + 2;
{
- device_t dev;
+ struct device * dev;
/* HT chain 0 */
bus_chain_0 = node_link_to_bus(0, 0);
@@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v)
/* IOAPIC handling */
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1));
@@ -206,7 +206,7 @@ static void *smp_write_config_table(void *v)
static void reboot_if_hotswap(void)
{
/* Hack patch work around for hot swap enable 33mhz problem */
- device_t dev;
+ struct device * dev;
uint32_t data;
unsigned long htic;
int reset;
diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
index f05ce7f..2e5a44f 100644
--- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c
+++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 58ad8b2..a8d2913 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -67,7 +67,7 @@ static void get_ide_dma66(void)
{
u8 byte;
/*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
+ struct device * sm_dev, ide_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -95,7 +95,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in mahogany board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index 790d1da..0d174bc 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index a98a179..1f554f2 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -50,7 +50,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 14fa316..23b5261 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c
index ac40c84..961a111 100644
--- a/src/mainboard/asrock/imb-a180/mainboard.c
+++ b/src/mainboard/asrock/imb-a180/mainboard.c
@@ -32,7 +32,7 @@
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index d9ca7b7..38db63a 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -183,7 +183,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c
index a55401b..22d0123 100644
--- a/src/mainboard/asus/a8n_e/get_bus_conf.c
+++ b/src/mainboard/asus/a8n_e/get_bus_conf.c
@@ -63,7 +63,7 @@ static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned apicid_base, sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index a954d92..b6e1059 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index c137b14..32472ee 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -90,7 +90,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 5c78ab1..74b768e 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -90,7 +90,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c
index 1d666c9..cf0c044 100644
--- a/src/mainboard/asus/dsbf/mainboard.c
+++ b/src/mainboard/asus/dsbf/mainboard.c
@@ -27,7 +27,7 @@
#include <device/pci_ops.h>
#include <arch/io.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c
index 191eea8..ff4eb20 100644
--- a/src/mainboard/asus/f2a85-m/mainboard.c
+++ b/src/mainboard/asus/f2a85-m/mainboard.c
@@ -32,7 +32,7 @@
/*************************************************
* enable the dedicated function in thatcher board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
msr_t msr;
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index cc81819..e5d7603 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -149,7 +149,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index caa32ca..6126cb8 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -67,7 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c
index cd45213..2898b51 100644
--- a/src/mainboard/asus/k8v-x/mainboard.c
+++ b/src/mainboard/asus/k8v-x/mainboard.c
@@ -27,7 +27,7 @@
u32 vt8237_ide_80pin_detect(struct device *dev)
{
- device_t lpc_dev;
+ struct device * lpc_dev;
u16 acpi_io_base;
u32 gpio_in;
u32 res;
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 15b8682..4b897b1 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -88,7 +88,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c
index fd7d304..c9d113d 100644
--- a/src/mainboard/asus/m2n-e/get_bus_conf.c
+++ b/src/mainboard/asus/m2n-e/get_bus_conf.c
@@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned int apicid_base, sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c
index 2c18100..7bf4639 100644
--- a/src/mainboard/asus/m2n-e/mainboard.c
+++ b/src/mainboard/asus/m2n-e/mainboard.c
@@ -21,7 +21,7 @@
#include <device/device.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 333ec49..69a5260 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
unsigned int sbdn;
int i, j, bus_isa;
- device_t dev;
+ struct device * dev;
struct resource *res;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index d12b77c..df73222 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -72,7 +72,7 @@ static void sio_setup(void)
{
u8 byte;
u32 dword;
- device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
+ pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
/* Subject decoding */
byte = pci_read_config8(dev, 0x7b);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index adcdfc7..605c19d 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -107,7 +107,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c
index 21adac0..cbacc88 100644
--- a/src/mainboard/asus/m2v/mainboard.c
+++ b/src/mainboard/asus/m2v/mainboard.c
@@ -26,7 +26,7 @@
u32 vt8237_ide_80pin_detect(struct device *dev)
{
- device_t lpc_dev;
+ struct device * lpc_dev;
u16 acpi_io_base;
u32 gpio_in;
u32 res;
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 30ba468..74d2edc 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -91,7 +91,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
@@ -189,7 +189,7 @@ static void m2v_it8712f_gpio_init(void)
static void m2v_bus_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
printk(BIOS_SPEW, "m2v_bus_init\n");
diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/asus/m4a78-em/get_bus_conf.c
+++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 1a2e9fc..b32ca0c 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -36,7 +36,7 @@ void set_pcie_dereset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
@@ -61,7 +61,7 @@ void set_pcie_reset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
@@ -91,7 +91,7 @@ void set_pcie_reset()
u8 is_dev3_present(void)
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* access the smbus extended register */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -118,7 +118,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in this board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index b1154ab..edaecab 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -45,7 +45,7 @@ void set_pcie_dereset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
@@ -70,7 +70,7 @@ void set_pcie_reset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
@@ -100,7 +100,7 @@ void set_pcie_reset()
u8 is_dev3_present(void)
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* access the smbus extended register */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -129,7 +129,7 @@ static void set_thermal_config(void)
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -190,7 +190,7 @@ static void set_thermal_config(void)
* enable the dedicated function in this board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
index f90c6b8..4c8efff 100644
--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 8ee338e..1da327b 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -73,7 +73,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in M5A88-V board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c
index f90c6b8..4c8efff 100644
--- a/src/mainboard/avalue/eax-785e/get_bus_conf.c
+++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c
@@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
index 6ce3469..6ee5923 100644
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -73,7 +73,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in EAX-785E board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c
index d4b0b2d..ea13cef 100644
--- a/src/mainboard/bachmann/ot200/mainboard.c
+++ b/src/mainboard/bachmann/ot200/mainboard.c
@@ -46,7 +46,7 @@ static void init(struct device *dev)
u32 chksum = 0;
char block[20];
msr_t reset;
- device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
+ struct device * eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
if (eeprom_dev == 0) {
printk(BIOS_WARNING, "eeprom not found\n");
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 898ad1a..391263b 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c
index 5de8952..f95d70a 100644
--- a/src/mainboard/broadcom/blast/get_bus_conf.c
+++ b/src/mainboard/broadcom/blast/get_bus_conf.c
@@ -50,7 +50,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index d7ae6b7..9d415d2 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev = 0;
+ struct device * dev = 0;
struct resource *res;
for(i=0; i<3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c
index 2761035..381658a 100644
--- a/src/mainboard/dmp/vortex86ex/mainboard.c
+++ b/src/mainboard/dmp/vortex86ex/mainboard.c
@@ -25,7 +25,7 @@
#include <device/pci_def.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c
index 83a55e3..815f50e 100644
--- a/src/mainboard/emulation/qemu-armv7/mainboard.c
+++ b/src/mainboard/emulation/qemu-armv7/mainboard.c
@@ -16,7 +16,7 @@
#include <console/console.h>
#include <device/device.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Enable qemu/armv7 device...\n");
}
diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c
index a8a61c4..6d1f2b0 100644
--- a/src/mainboard/emulation/qemu-i440fx/mainboard.c
+++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c
@@ -30,7 +30,7 @@ static const unsigned char qemu_i440fx_irqs[] = {
11, 10, 10, 11,
};
-static void qemu_nb_init(device_t dev)
+static void qemu_nb_init(struct device * dev)
{
/* Map memory at 0xc0000 - 0xfffff */
int i;
diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c
index e991b53..622ea54 100644
--- a/src/mainboard/emulation/qemu-q35/mainboard.c
+++ b/src/mainboard/emulation/qemu-q35/mainboard.c
@@ -33,7 +33,7 @@ static const unsigned char qemu_q35_irqs[] = {
10, 10, 11, 11,
};
-static void qemu_nb_init(device_t dev)
+static void qemu_nb_init(struct device * dev)
{
/* Map memory at 0xc0000 - 0xfffff */
int i;
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index 2b33ff0..1dc881a 100644
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -62,7 +62,7 @@ static void pcie_limit_power(void)
// machine. It should set the slot numbers and enable power
// limitation for the PCIe slots.
- device_t dev;
+ struct device * dev;
dev = dev_find_slot(0, PCI_DEVFN(28,0));
if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0);
@@ -79,14 +79,14 @@ static void pcie_limit_power(void)
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
ec_enable();
}
// mainboard_enable is executed as first thing after
// enumerate_buses(). Is there no mainboard_init()?
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 3dab527..da40c55 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -105,19 +105,19 @@ static void ich7_enable_lpc(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0x55, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0xaa, port);
}
-static void pnp_write_register(device_t dev, int reg, int val)
+static void pnp_write_register(pnp_devfn_t dev, int reg, int val)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -126,7 +126,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x4e, 0x00);
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
index 9315cbd..c9c1950 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
@@ -69,7 +69,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index 0af6cf0..9e8c7bf 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
index c798415..db5b685 100644
--- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c
+++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
@@ -67,7 +67,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c
index 291d4f7..a668696 100644
--- a/src/mainboard/gigabyte/m57sli/mainboard.c
+++ b/src/mainboard/gigabyte/m57sli/mainboard.c
@@ -26,7 +26,7 @@
#include <device/pci_ops.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 1536823..43459bc 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index cd06069..9fe9c7f 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -35,7 +35,7 @@ void set_pcie_dereset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
@@ -60,7 +60,7 @@ void set_pcie_reset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
@@ -98,7 +98,7 @@ static void set_gpio40_gfx(void)
u8 byte;
// u16 word;
u32 dword;
- device_t sm_dev;
+ struct device * sm_dev;
/* disable the GPIO40 as CLKREQ2# function */
byte = pm_ioread(0xd3);
byte &= ~(1 << 7);
@@ -134,7 +134,7 @@ static void set_gpio40_gfx(void)
* enable the dedicated function in ma785gm board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/gigabyte/ma785gm/mptable.c
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index 89b50bb..f591ebb 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -45,7 +45,7 @@ void set_pcie_dereset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
@@ -70,7 +70,7 @@ void set_pcie_reset()
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
@@ -98,7 +98,7 @@ void set_pcie_reset()
int is_dev3_present(void)
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* access the smbus extended register */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -128,7 +128,7 @@ static void set_gpio40_gfx(void)
u8 byte;
// u16 word;
u32 dword;
- device_t sm_dev;
+ struct device * sm_dev;
/* disable the GPIO40 as CLKREQ2# function */
byte = pm_ioread(0xd3);
byte &= ~(1 << 7);
@@ -183,7 +183,7 @@ static void set_thermal_config(void)
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -244,7 +244,7 @@ static void set_thermal_config(void)
* enable the dedicated function in ma785gmt board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index 49df0c2..2fd5c52 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -38,7 +38,7 @@ u8 is_dev3_present(void);
void set_pcie_dereset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -51,7 +51,7 @@ void set_pcie_dereset()
void set_pcie_reset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -71,7 +71,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c
index a9afdfb..ad8fa58 100755
--- a/src/mainboard/gizmosphere/gizmo/mainboard.c
+++ b/src/mainboard/gizmosphere/gizmo/mainboard.c
@@ -55,7 +55,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
@@ -78,7 +78,7 @@ static void mainboard_enable(device_t dev)
void mainboard_final( void *chip_info );
void mainboard_final( void *chip_info )
{
- device_t ahci_dev;
+ struct device * ahci_dev;
u32 ABAR;
u8 *memptr;
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index b98598a..8301bd5 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/google/bolt/mainboard.c b/src/mainboard/google/bolt/mainboard.c
index 0ccf90d..7676d56 100644
--- a/src/mainboard/google/bolt/mainboard.c
+++ b/src/mainboard/google/bolt/mainboard.c
@@ -44,12 +44,12 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
mainboard_ec_init();
}
-static int mainboard_smbios_data(device_t dev, int *handle,
+static int mainboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index 655fc2f..c4006c6 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -194,7 +194,7 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
u32 search_address = 0x0;
size_t search_length = -1;
@@ -258,7 +258,7 @@ static void mainboard_init(device_t dev)
}
}
-static int butterfly_onboard_smbios_data(device_t dev, int *handle,
+static int butterfly_onboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -278,7 +278,7 @@ static int butterfly_onboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = butterfly_onboard_smbios_data;
diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c
index 0adadb6..fc9a08c 100644
--- a/src/mainboard/google/daisy/mainboard.c
+++ b/src/mainboard/google/daisy/mainboard.c
@@ -258,7 +258,7 @@ static void gpio_init(void)
}
/* this happens after cpu_init where exynos resources are set */
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
int dp_tries;
struct s5p_dp_device dp_device = {
@@ -322,7 +322,7 @@ static void mainboard_init(device_t dev)
// gpio_info();
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = &mainboard_init;
diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c
index 0ccf90d..7676d56 100644
--- a/src/mainboard/google/falco/mainboard.c
+++ b/src/mainboard/google/falco/mainboard.c
@@ -44,12 +44,12 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
mainboard_ec_init();
}
-static int mainboard_smbios_data(device_t dev, int *handle,
+static int mainboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index ed40f8f..d1a3856 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -149,7 +149,7 @@ static int int15_handler(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
/* Initialize the Embedded Controller */
link_ec_init();
@@ -166,7 +166,7 @@ static void mainboard_init(device_t dev)
}
}
-static int link_onboard_smbios_data(device_t dev, int *handle,
+static int link_onboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -204,7 +204,7 @@ static int link_onboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index 6fa8a95..d7df116 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -232,7 +232,7 @@ static void setup_ec_spi(void)
spi->rx_frame_header_enable = 1;
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
set_clock_sources();
@@ -284,7 +284,7 @@ static void mainboard_init(device_t dev)
setup_ec_spi();
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = &mainboard_init;
}
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
index 4a05991..908d610 100644
--- a/src/mainboard/google/nyan_big/mainboard.c
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -232,7 +232,7 @@ static void setup_ec_spi(void)
spi->rx_frame_header_enable = 1;
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
set_clock_sources();
@@ -281,7 +281,7 @@ static void mainboard_init(device_t dev)
setup_ec_spi();
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = &mainboard_init;
}
diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c
index 5058eca..a1bd459 100644
--- a/src/mainboard/google/panther/mainboard.c
+++ b/src/mainboard/google/panther/mainboard.c
@@ -44,7 +44,7 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
lan_init();
}
@@ -52,7 +52,7 @@ static void mainboard_init(device_t dev)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c
index 547680e..207bcfd 100644
--- a/src/mainboard/google/parrot/mainboard.c
+++ b/src/mainboard/google/parrot/mainboard.c
@@ -48,13 +48,13 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
/* Initialize the Embedded Controller */
parrot_ec_init();
}
-static int parrot_onboard_smbios_data(device_t dev, int *handle,
+static int parrot_onboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -85,7 +85,7 @@ static int parrot_onboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = parrot_onboard_smbios_data;
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index 1fb441d..53db9fa 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -405,7 +405,7 @@ static void sdmmc_vdd(void)
}
/* this happens after cpu_init where exynos resources are set */
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
/* we'll stick with the crummy u-boot struct for now.*/
/* doing this as an auto since the struct has to be writeable */
@@ -462,7 +462,7 @@ static void mainboard_init(device_t dev)
setup_usb();
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = &mainboard_init;
diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c
index 0ccf90d..7676d56 100644
--- a/src/mainboard/google/peppy/mainboard.c
+++ b/src/mainboard/google/peppy/mainboard.c
@@ -44,12 +44,12 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
mainboard_ec_init();
}
-static int mainboard_smbios_data(device_t dev, int *handle,
+static int mainboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index cd3fc48..b43928d 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -127,12 +127,12 @@ static int int15_handler(void)
}
#endif
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
mainboard_ec_init();
}
-static int mainboard_smbios_data(device_t dev, int *handle,
+static int mainboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -161,7 +161,7 @@ static int mainboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c
index 7977ce3..de7f434 100644
--- a/src/mainboard/google/samus/mainboard.c
+++ b/src/mainboard/google/samus/mainboard.c
@@ -42,12 +42,12 @@ void mainboard_suspend_resume(void)
outb(0xcb, 0xb2);
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
mainboard_ec_init();
}
-static int mainboard_smbios_data(device_t dev, int *handle,
+static int mainboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -112,7 +112,7 @@ static int mainboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c
index 0ccf90d..7676d56 100644
--- a/src/mainboard/google/slippy/mainboard.c
+++ b/src/mainboard/google/slippy/mainboard.c
@@ -44,12 +44,12 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
mainboard_ec_init();
}
-static int mainboard_smbios_data(device_t dev, int *handle,
+static int mainboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c
index 0b0182f..4792ea9 100644
--- a/src/mainboard/google/storm/mainboard.c
+++ b/src/mainboard/google/storm/mainboard.c
@@ -20,11 +20,11 @@
#include <device/device.h>
#include <boot/coreboot_tables.h>
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = &mainboard_init;
}
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
index 9bcbfe4..58d89b8 100644
--- a/src/mainboard/google/stout/mainboard.c
+++ b/src/mainboard/google/stout/mainboard.c
@@ -48,7 +48,7 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
struct device *ethernet_dev = NULL;
@@ -70,7 +70,7 @@ static void mainboard_init(device_t dev)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index acfa023..6a36ef7 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -51,7 +51,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index b9af38b..7e81143 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
if (dev) {
diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c
index ba0fc88..59b35aa 100644
--- a/src/mainboard/hp/dl145_g3/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c
@@ -70,7 +70,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i;
struct mb_sysconf_t *m;
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 6c71bad..6b3032b 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev = 0;
+ struct device * dev = 0;
int i;
struct resource *res;
for(i=0; i<3; i++) {
@@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v)
outb(0x0e, 0x4d1);
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
@@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v)
// hide XIOAPIC PCI configuration space
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x205, 0);
if (dev) {
uint32_t dword;
@@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v)
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index 099c41a..6561c94 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -71,7 +71,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i;
struct mb_sysconf_t *m;
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 86f2cc6..175cfe5 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev = 0;
+ struct device * dev = 0;
int i;
struct resource *res;
for(i=0; i<3; i++) {
@@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v)
outb(0x0e, 0x4d1);
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
@@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v)
// hide XIOAPIC PCI configuration space
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x205, 0);
if (dev) {
uint32_t dword;
@@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v)
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
index f858455..3384a9f 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
@@ -41,7 +41,7 @@ static void pavilion_cold_boot_init(void)
pavilion_m6_1035dx_ec_init();
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index f47b9d9..d12e759 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -144,7 +144,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c
index a2a10a1..ba6a09e 100644
--- a/src/mainboard/ibase/mb899/mainboard.c
+++ b/src/mainboard/ibase/mb899/mainboard.c
@@ -31,7 +31,7 @@
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3);
hwm_setup();
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 322907b..e8931f0 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -76,7 +76,7 @@ static void ich7_enable_lpc(void)
*/
static void early_superio_config_w83627ehg(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev = DUMMY_DEV;
pnp_enter_ext_func_mode(dev);
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 6eb6390..50f8031 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
@@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
/* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index f271166..d85e609 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
/* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
+++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index 43ff9c1..9d67e2b 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -53,7 +53,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in kino board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 11426c2..759ab30 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
index a83bf7e..0cb238b 100644
--- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c
+++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
@@ -69,7 +69,7 @@ void main(unsigned long bist)
console_init();
/* Enable COM3. */
- device_t dev = PNP_DEV(0x2e, 0x0b);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b);
u16 port = dev >> 8;
outb(0x55, port);
pnp_set_logical_device(dev);
diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c
index a6839fc..be142aa 100644
--- a/src/mainboard/intel/baskingridge/mainboard.c
+++ b/src/mainboard/intel/baskingridge/mainboard.c
@@ -44,7 +44,7 @@ void mainboard_suspend_resume(void)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c
index feae6ef..d32ca91 100644
--- a/src/mainboard/intel/bayleybay_fsp/mainboard.c
+++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c
@@ -38,7 +38,7 @@
* mainboard_enable is executed as first thing after enumerate_buses().
* This is the earliest point to add customization.
*/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c
index 0ea03d3..f0062d5 100644
--- a/src/mainboard/intel/cougar_canyon2/mainboard.c
+++ b/src/mainboard/intel/cougar_canyon2/mainboard.c
@@ -46,7 +46,7 @@ void mainboard_suspend_resume(void)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index cc956a7..c6cf529 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -56,7 +56,7 @@ static inline void reset_system(void)
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c
index e5795b6..c25b3a3 100644
--- a/src/mainboard/intel/eagleheights/debug.c
+++ b/src/mainboard/intel/eagleheights/debug.c
@@ -143,7 +143,7 @@ static void print_debug_pci_dev(unsigned dev)
static inline void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -210,7 +210,7 @@ static inline void dump_bar14(unsigned dev)
static inline void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 809feec..78dfb62 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
int bus_isa, i;
uint32_t pin, route;
- device_t dev;
+ struct device * dev;
struct resource *res;
unsigned long rcba;
diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c
index 347ce8a..1f92309 100644
--- a/src/mainboard/intel/emeraldlake2/mainboard.c
+++ b/src/mainboard/intel/emeraldlake2/mainboard.c
@@ -44,7 +44,7 @@ void mainboard_suspend_resume(void)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 220b1d7..f9f6a85 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -47,7 +47,7 @@
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c
index 93199d7..5ea10d2 100644
--- a/src/mainboard/intel/jarrell/debug.c
+++ b/src/mainboard/intel/jarrell/debug.c
@@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev)
static void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index 21664ce..6dcf7d7 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* ich5r */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
@@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
{
struct resource *res;
- device_t dev;
+ struct device * dev;
/* pxhd apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index f1cf4c3..29553fc 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -75,7 +75,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c
index 7f7a039..9722c04 100644
--- a/src/mainboard/intel/jarrell/watchdog.c
+++ b/src/mainboard/intel/jarrell/watchdog.c
@@ -6,7 +6,7 @@
#define ICH5_WDBASE 0x400
#define ICH5_GPIOBASE 0x500
-static void disable_sio_watchdog(device_t dev)
+static void disable_sio_watchdog(pci_devfn_t dev)
{
/* FIXME move me somewhere more appropriate */
pnp_set_logical_device(dev);
@@ -20,7 +20,7 @@ static void disable_sio_watchdog(device_t dev)
static void disable_ich5_watchdog(void)
{
/* FIXME move me somewhere more appropriate */
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
@@ -48,7 +48,7 @@ static void disable_ich5_watchdog(void)
static void disable_jarell_frb3(void)
{
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
@@ -97,7 +97,7 @@ static void disable_watchdogs(void)
static void ich5_watchdog_on(void)
{
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
unsigned char byte;
diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c
index 3da1e23..ce9872a 100644
--- a/src/mainboard/intel/minnowmax/mainboard.c
+++ b/src/mainboard/intel/minnowmax/mainboard.c
@@ -25,7 +25,7 @@
* mainboard_enable is executed as first thing after enumerate_buses().
* This is the earliest point to add customization.
*/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c
index 7559fc2..387931d 100644
--- a/src/mainboard/intel/mohonpeak/mainboard.c
+++ b/src/mainboard/intel/mohonpeak/mainboard.c
@@ -24,7 +24,7 @@
* mainboard_enable is executed as first thing after enumerate_buses().
* This is the earliest point to add customization.
*/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index 9ad6ea6..2c7eb92 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v)
u8 bus_pea0 = 0;
u8 bus_pea1 = 0;
u8 bus_aioc;
- device_t dev;
+ struct device * dev;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c
index a6839fc..be142aa 100644
--- a/src/mainboard/intel/wtm2/mainboard.c
+++ b/src/mainboard/intel/wtm2/mainboard.c
@@ -44,7 +44,7 @@ void mainboard_suspend_resume(void)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index cc7eda5..65e4bcc 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -19,7 +19,7 @@ static int bus_isa;
static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
{
- device_t dev;
+ struct device * dev;
struct resource *res;
// TODO: Gack. This is REALLY ugly.
diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c
index dfc6636..457c88f 100644
--- a/src/mainboard/iwave/iWRainbowG6/mainboard.c
+++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c
@@ -22,7 +22,7 @@
#include <console/console.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 87de022..da83738 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -36,7 +36,7 @@ void *smp_write_config_table(void *v)
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
if (dev) {
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
index 8868f46..be033f5 100644
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
@@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i)
unsigned devn = sysconf.hcdn[i] & 0xff;
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
@@ -76,7 +76,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i, j;
struct mb_sysconf_t *m;
diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c
index 0202b50..909e5a9 100644
--- a/src/mainboard/iwill/dk8_htx/mainboard.c
+++ b/src/mainboard/iwill/dk8_htx/mainboard.c
@@ -7,7 +7,7 @@
#include <cpu/amd/amdk8_sysconf.h>
#include "mainboard.h"
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
}
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index ff6e582..416cd17 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
if (dev) {
@@ -126,7 +126,7 @@ static void *smp_write_config_table(void *v)
for(i=1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii;
- device_t dev;
+ struct device * dev;
struct resource *res;
switch(sysconf.hcid[i]) {
case 1:
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index c7bb33d..622b412 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index c7bb33d..622b412 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
index a9c71c3..fe3f48c 100644
--- a/src/mainboard/jetway/j7f2/romstage.c
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index d67e072..92c8d70 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -153,7 +153,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 4390605..2c9606a 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -116,7 +116,7 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
index 47342fb..414b6e7 100644
--- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c
+++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index 373ebb5..6da52fc 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -39,7 +39,7 @@ u8 is_dev3_present(void);
void set_pcie_dereset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -52,7 +52,7 @@ void set_pcie_dereset()
void set_pcie_reset()
{
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -72,7 +72,7 @@ static void get_ide_dma66(void)
{
u8 byte;
/*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
+ struct device * sm_dev, ide_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -100,7 +100,7 @@ u8 is_dev3_present(void)
* enable the dedicated function in this board.
* This function called early than rs780_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index 7cabdf1..0c7130b 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
index afca796..0ae64b5 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard.c
@@ -164,7 +164,7 @@ static void hwm_setup(void)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3);
hwm_setup();
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 2c12c5d..a28593f 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -78,14 +78,14 @@ static void ich7_enable_lpc(void)
}
/* TODO: superio code should really not be in mainboard */
-static void pnp_enter_func_mode(device_t dev)
+static void pnp_enter_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_func_mode(device_t dev)
+static void pnp_exit_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
@@ -98,7 +98,7 @@ static void pnp_exit_func_mode(device_t dev)
*/
static void early_superio_config_w83627thg(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_func_mode(dev);
diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c
index 084e2b1..c959280 100644
--- a/src/mainboard/kontron/kt690/get_bus_conf.c
+++ b/src/mainboard/kontron/kt690/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
index 717c399..a88a2c8 100644
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ b/src/mainboard/kontron/kt690/mainboard.c
@@ -119,7 +119,7 @@ static void set_thermal_config(void)
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -180,7 +180,7 @@ static void set_thermal_config(void)
* enable the dedicated function in dbm690t board.
* This function called early than rs690_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 8b86b02..840a93a 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c
index 715ec56..6f6c2d8 100644
--- a/src/mainboard/kontron/ktqm77/mainboard.c
+++ b/src/mainboard/kontron/ktqm77/mainboard.c
@@ -172,7 +172,7 @@ static int int15_handler(void)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
/* Install custom int15 handler for VGA OPROM */
@@ -181,7 +181,7 @@ static void mainboard_enable(device_t dev)
unsigned disable = 0;
if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) {
- device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2));
+ struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2));
if (nic) {
printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n");
nic->enabled = 0;
@@ -189,7 +189,7 @@ static void mainboard_enable(device_t dev)
}
disable = 0;
if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) {
- device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3));
+ struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3));
if (nic) {
printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n");
nic->enabled = 0;
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 401314c..d1a6279 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -125,14 +125,14 @@ static void rcba_config(void)
RCBA32(FD) = reg32;
}
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
@@ -142,7 +142,7 @@ static void superio_gpio_config(void)
{
int lvds_3v = 0; // 0 (5V) or 1 (3V3)
int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled
- device_t dev = PNP_DEV(0x2e, 0x9);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c
index 387bbe0..ddd6d22 100644
--- a/src/mainboard/lenovo/t520/mainboard.c
+++ b/src/mainboard/lenovo/t520/mainboard.c
@@ -46,7 +46,7 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
@@ -65,7 +65,7 @@ static void mainboard_init(device_t dev)
/* mainboard_enable is executed as first thing after
enumerate_buses(). */
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c
index f8c9dae..922b424 100644
--- a/src/mainboard/lenovo/t530/mainboard.c
+++ b/src/mainboard/lenovo/t530/mainboard.c
@@ -46,7 +46,7 @@ void mainboard_suspend_resume(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
@@ -69,7 +69,7 @@ static void mainboard_init(device_t dev)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c
index 79b3da8..d960b11 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -61,10 +61,11 @@ const char *smbios_mainboard_bios_version(void)
return "CBET4000 " COREBOOT_VERSION;
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
struct southbridge_intel_i82801gx_config *config;
- device_t dev0, idedev;
+ struct device * dev0;
+ struct device * idedev;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3);
@@ -95,7 +96,7 @@ static void mainboard_init(device_t dev)
ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
}
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index f11b33e..24d4ab6 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -98,7 +98,7 @@ static void ich7_enable_lpc(void)
static void early_superio_config(void)
{
int timeout = 100000;
- device_t dev = PNP_DEV(0x2e, 3);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0xa0);
diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c
index 0054064..c79b552 100644
--- a/src/mainboard/lenovo/x200/mainboard.c
+++ b/src/mainboard/lenovo/x200/mainboard.c
@@ -45,7 +45,7 @@ const char *smbios_mainboard_bios_version(void)
return "CBET4000 " COREBOOT_VERSION;
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
/* This sneaked in here, because X200 SuperIO chip isn't really
connected to anything and hence we don't init it.
@@ -53,7 +53,7 @@ static void mainboard_init(device_t dev)
pc_keyboard_init();
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2);
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index 5b76be2..f61bb9a 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -71,7 +71,7 @@ const char *smbios_mainboard_bios_version(void)
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
printk(BIOS_SPEW, "starting SPI configuration\n");
@@ -117,9 +117,9 @@ static void fill_ssdt(void)
drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
- device_t dev0;
+ struct device * dev0;
u16 pmbase;
dev->ops->init = mainboard_init;
diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c
index 00e7991..c86825e 100644
--- a/src/mainboard/lenovo/x220/mainboard.c
+++ b/src/mainboard/lenovo/x220/mainboard.c
@@ -49,7 +49,7 @@ const char *smbios_mainboard_bios_version(void)
return "CBET4000 " COREBOOT_VERSION;
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
@@ -72,7 +72,7 @@ static void mainboard_init(device_t dev)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c
index a060015..28d7344 100644
--- a/src/mainboard/lenovo/x230/mainboard.c
+++ b/src/mainboard/lenovo/x230/mainboard.c
@@ -50,7 +50,7 @@ const char *smbios_mainboard_bios_version(void)
return "CBET4000 " COREBOOT_VERSION;
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
@@ -73,7 +73,7 @@ static void mainboard_init(device_t dev)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index 1d29c71..9f0cda4 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -56,9 +56,11 @@ int get_cst_entries(acpi_cstate_t **entries)
return ARRAY_SIZE(cst_entries);
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
- device_t dev0, idedev, sdhci_dev;
+ struct device * dev0;
+ struct device * idedev;
+ struct device * sdhci_dev;
ec_clr_bit(0x03, 2);
@@ -115,7 +117,7 @@ static void fill_ssdt(void)
drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_fill_ssdt_generator = fill_ssdt;
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 943143a..348b5fe 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -105,7 +105,7 @@ static void ich7_enable_lpc(void)
static void early_superio_config(void)
{
int timeout = 100000;
- device_t dev = PNP_DEV(0x2e, 3);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0x06);
diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c
index ee538c3..983df2c 100644
--- a/src/mainboard/lippert/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c
@@ -163,7 +163,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
dev->ops->init = init;
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 078601e..6d91730 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index 9e44a21..28ac9ba 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -130,7 +130,7 @@ void set_pcie_dereset(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
dev->ops->init = init;
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 078601e..6d91730 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c
index e364892..cb2bd5d 100644
--- a/src/mainboard/msi/ms7135/get_bus_conf.c
+++ b/src/mainboard/msi/ms7135/get_bus_conf.c
@@ -55,7 +55,7 @@ void get_bus_conf(void)
{
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
unsigned sbdn;
int i;
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index b43a516..0c7032f 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
u32 dword;
diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c
index 34d3834..97b2b70 100644
--- a/src/mainboard/msi/ms7260/get_bus_conf.c
+++ b/src/mainboard/msi/ms7260/get_bus_conf.c
@@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned int apicid_base, sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c
index 492693a..d4e111f 100644
--- a/src/mainboard/msi/ms7260/mainboard.c
+++ b/src/mainboard/msi/ms7260/mainboard.c
@@ -23,7 +23,7 @@
#if 0
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
#endif
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index ea003a8..a200b70 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c
index 3a70d83..86afc47 100644
--- a/src/mainboard/msi/ms9185/get_bus_conf.c
+++ b/src/mainboard/msi/ms9185/get_bus_conf.c
@@ -68,7 +68,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i;
struct mb_sysconf_t *m;
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index b30ab73..fc00858 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev = 0;
+ struct device * dev = 0;
struct resource *res;
for(i=0; i<3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
- device_t dev;
+ struct device * dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c
index 195ddc4..776fabb 100644
--- a/src/mainboard/msi/ms9282/get_bus_conf.c
+++ b/src/mainboard/msi/ms9282/get_bus_conf.c
@@ -70,7 +70,7 @@ void get_bus_conf(void)
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c
index c7e459a..54cdc3b 100644
--- a/src/mainboard/msi/ms9282/mainboard.c
+++ b/src/mainboard/msi/ms9282/mainboard.c
@@ -26,7 +26,7 @@
#include <device/pci_ops.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index 1764cf3..432e702 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
index 36ae12c..4ec04f5 100644
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -71,7 +71,7 @@ void get_bus_conf(void)
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
+ struct device *dev;
int i;
printk(BIOS_SPEW, "get_bus_conf()\n");
diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c
index 96760d6..7fc97f0 100644
--- a/src/mainboard/msi/ms9652_fam10/mainboard.c
+++ b/src/mainboard/msi/ms9652_fam10/mainboard.c
@@ -26,7 +26,7 @@
#include <device/pci_ops.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 09a25f2..1b9b349 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index 1d7c79e..ede913f 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
index 125b564..b77a355 100644
--- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
+++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
@@ -73,7 +73,7 @@ static unsigned get_hcid(unsigned i)
unsigned devn = sysconf.hcdn[i] & 0xff;
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c
index 291d4f7..a668696 100644
--- a/src/mainboard/nvidia/l1_2pvv/mainboard.c
+++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c
@@ -26,7 +26,7 @@
#include <device/pci_ops.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index e991efd..5cdad5b 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
@@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v)
//Slot PCIE
for (j = 2; j < 8; j++) {
- device_t dev;
+ struct device * dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0));
if (!dev || !dev->enabled)
continue;
@@ -128,7 +128,7 @@ static void *smp_write_config_table(void *v)
//Slot PCI 32
{
- device_t dev;
+ struct device * dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0));
if (dev && dev->enabled) {
for (i = 0; i < 4; i++)
@@ -148,7 +148,7 @@ static void *smp_write_config_table(void *v)
//Slot PCIE
for (j = 2; j < 8; j++) {
- device_t dev;
+ struct device * dev;
dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0));
if (!dev || !dev->enabled)
continue;
diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c
index c14e9b7..c5b51e0 100644
--- a/src/mainboard/packardbell/ms2290/mainboard.c
+++ b/src/mainboard/packardbell/ms2290/mainboard.c
@@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t ** entries)
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
u16 pmbase;
diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c
index 2e3191b..421c916 100644
--- a/src/mainboard/rca/rm4100/mainboard.c
+++ b/src/mainboard/rca/rm4100/mainboard.c
@@ -20,12 +20,12 @@
#include <device/device.h>
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
// TODO Switch parport LEDs again
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
// TODO Switch parport LEDs
dev->ops->init = mainboard_init;
diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c
index 4c7fffa..5421d13 100644
--- a/src/mainboard/roda/rk886ex/mainboard.c
+++ b/src/mainboard/roda/rk886ex/mainboard.c
@@ -63,14 +63,14 @@ static void dump_runtime_registers(void)
}
#endif
-static void mainboard_final(device_t dev)
+static void mainboard_final(struct device * dev)
{
/* Enable Dummy DCC ON# for DVI */
printk(BIOS_DEBUG, "Laptop handling...\n");
outb(inb(0x60f) & ~(1 << 5), 0x60f);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
/* Configure the MultiKey controller */
// m3885_configure_multikey();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 7cc1a1d..0278cdf 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -93,19 +93,19 @@ static void ich7_enable_lpc(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0x55, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0xaa, port);
}
-static void pnp_write_register(device_t dev, int reg, int val)
+static void pnp_write_register(pnp_devfn_t dev, int reg, int val)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -114,7 +114,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x2e, 0x00);
diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c
index acf8023..39ade3f 100644
--- a/src/mainboard/roda/rk9/mainboard.c
+++ b/src/mainboard/roda/rk9/mainboard.c
@@ -44,7 +44,7 @@ static void ec_setup(void)
send_ec_command(0xad); /* Set_Thml_Value */
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
ec_setup();
/* LCD panel type is SIO GPIO40-43.
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index c8b75e0..89026ac 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -88,7 +88,7 @@ static void default_superio_gpio_setup(void)
GP1 GP2 GP3 GP4
fd 17 88 14
*/
- const device_t sio = PNP_DEV(0x2e, 0);
+ const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
/* Enter super-io's configuration state. */
pnp_enter_conf_state(sio);
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
index 3bdd4d9..d53bf9e 100644
--- a/src/mainboard/samsung/lumpy/mainboard.c
+++ b/src/mainboard/samsung/lumpy/mainboard.c
@@ -46,9 +46,7 @@ void mainboard_suspend_resume(void)
send_ec_command(EC_ACPI_ENABLE);
}
-
-
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
/* Initialize the Embedded Controller */
lumpy_ec_init();
@@ -80,7 +78,7 @@ static int lumpy_smbios_type41_irq(int *handle, unsigned long *current,
}
-static int lumpy_onboard_smbios_data(device_t dev, int *handle,
+static int lumpy_onboard_smbios_data(struct device * dev, int *handle,
unsigned long *current)
{
int len = 0;
@@ -101,7 +99,7 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle,
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = lumpy_onboard_smbios_data;
diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c
index 347ce8a..1f92309 100644
--- a/src/mainboard/samsung/stumpy/mainboard.c
+++ b/src/mainboard/samsung/stumpy/mainboard.c
@@ -44,7 +44,7 @@ void mainboard_suspend_resume(void)
// mainboard_enable is executed as first thing after
// enumerate_buses().
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
index 084e2b1..c959280 100644
--- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
+++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index 77be0af..219527a 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -389,7 +389,7 @@ static void pm_init( void )
{
u16 word;
u8 byte;
- device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ struct device * sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
/* set SB600 GPIO 64 to GPIO with pull-up */
byte = pm2_ioread(0x42);
@@ -432,7 +432,7 @@ static void set_thermal_config(void)
{
u8 byte, byte2;
u8 cpu_pwm_conf, case_pwm_conf;
- device_t sm_dev;
+ struct device * sm_dev;
struct fan_control cpu_fan_control, case_fan_control;
const char *name = NULL;
@@ -614,8 +614,8 @@ static void patch_mmio_nonposted( void )
resource_t rbase, rend;
u32 base, limit;
struct resource *resource;
- device_t dev;
- device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
+ struct device * dev;
+ struct device * k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
printk(BIOS_DEBUG,"%s ...\n", __func__);
@@ -668,7 +668,7 @@ struct {
unsigned int plx_present = 0;
-static void update_subsystemid( device_t dev )
+static void update_subsystemid(struct device * dev)
{
int i;
@@ -680,7 +680,7 @@ static void update_subsystemid( device_t dev )
}
printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device );
for( i=0; slot[i].bus < 255; i++) {
- device_t d;
+ struct device * d;
d = dev_find_slot(slot[i].bus,slot[i].devfn);
if( d ) {
printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device);
@@ -695,10 +695,11 @@ static void update_subsystemid( device_t dev )
* @param
*/
-static void detect_hw_variant( device_t dev )
+static void detect_hw_variant(struct device * dev)
{
- device_t nb_dev =0, dev2 = 0;
+ struct device * nb_dev = NULL;
+ struct device * dev2 = NULL;
struct southbridge_amd_rs690_config *cfg;
u32 lc_state, id = 0;
@@ -807,7 +808,7 @@ static void smm_lock( void )
* @param the root device
*/
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
INT15_function_extensions int15_func;
@@ -833,7 +834,7 @@ static void mainboard_init(device_t dev)
* enable the dedicated function in sina board.
* This function called early than rs690_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index de5151d..194b5ba 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
index f57719a..f716158 100644
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40/get_bus_conf.c
@@ -67,7 +67,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
if (get_bus_conf_done == 1)
return; //do it only once
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 1ba1dcf..6259278 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c
index 0279f8f..8b5ec69 100644
--- a/src/mainboard/supermicro/h8dme/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c
@@ -71,7 +71,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index 17067ed..d53b498 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c
index 0279f8f..8b5ec69 100644
--- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c
@@ -71,7 +71,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 11db23f..5a24259 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
index a1de06c..71eb756 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
@@ -72,7 +72,7 @@ void get_bus_conf(void)
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
+ struct device *dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 4e2d48c..5c88156 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
index 8f12e22..cdce2f9 100644
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@@ -65,7 +65,7 @@ void set_pcie_dereset(void *nbconfig)
/*************************************************
* enable the dedicated function in h8qgi board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
}
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 5ec4a35..230cacc 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
int bus_isa;
u32 apicid_sp5100;
u32 apicid_sr5650;
- device_t dev;
+ struct device * dev;
u32 dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index 50e2b44..7a80f74 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -74,7 +74,7 @@ void get_bus_conf(void)
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
+ struct device *dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 4fbb4c8..79f8a5e 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 24ecb5d..ce348ba 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -115,14 +115,14 @@ static const u8 spd_addr[] = {
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
/* TODO: superio code should really not be in mainboard */
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c
index 23b1d72..de1dead 100644
--- a/src/mainboard/supermicro/h8scm/mainboard.c
+++ b/src/mainboard/supermicro/h8scm/mainboard.c
@@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig)
/*************************************************
* enable the dedicated function in h8scm board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
}
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 5ec4a35..230cacc 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
int bus_isa;
u32 apicid_sp5100;
u32 apicid_sr5650;
- device_t dev;
+ struct device * dev;
u32 dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
index 0560180..fc3a446 100644
--- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
@@ -65,7 +65,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
index 18e1e8c..4908dcb 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -49,7 +49,7 @@ u8 is_dev3_present(void)
***/
void set_pcie_reset(void)
{
- device_t pcie_core_dev;
+ struct device * pcie_core_dev;
pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
@@ -58,7 +58,7 @@ void set_pcie_reset(void)
void set_pcie_dereset(void)
{
- device_t pcie_core_dev;
+ struct device * pcie_core_dev;
pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
@@ -69,7 +69,7 @@ void set_pcie_dereset(void)
* enable the dedicated function in h8scm board.
* This function called early than sr5650_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 84593fc..864cdd1 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c
index 93199d7..5ea10d2 100644
--- a/src/mainboard/supermicro/x6dai_g/debug.c
+++ b/src/mainboard/supermicro/x6dai_g/debug.c
@@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev)
static void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c
index 0efae77..4185a54 100644
--- a/src/mainboard/supermicro/x6dai_g/mptable.c
+++ b/src/mainboard/supermicro/x6dai_g/mptable.c
@@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* southbridge */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 0385cad..0998b02 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -70,7 +70,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID)
die("Missing 6300ESB?");
diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c
index 2fd3274..bf9f9f1 100644
--- a/src/mainboard/supermicro/x6dai_g/watchdog.c
+++ b/src/mainboard/supermicro/x6dai_g/watchdog.c
@@ -8,7 +8,7 @@
static void disable_esb6300_watchdog(void)
{
/* FIXME move me somewhere more appropriate */
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c
index 93199d7..5ea10d2 100644
--- a/src/mainboard/supermicro/x6dhe_g/debug.c
+++ b/src/mainboard/supermicro/x6dhe_g/debug.c
@@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev)
static void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index ab73fc7..18fe954 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* esb6300_2 */
dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
@@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
{
struct resource *res;
- device_t dev;
+ struct device * dev;
/* PXHd apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 405a2bc..6e90958 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -73,7 +73,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID)
die("Missing esb6300?");
diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c
index 1d34f7d..3fab7f9 100644
--- a/src/mainboard/supermicro/x6dhe_g/watchdog.c
+++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c
@@ -5,7 +5,7 @@
#define ESB6300_WDBASE 0x400
#define ESB6300_GPIOBASE 0x500
-static void disable_sio_watchdog(device_t dev)
+static void disable_sio_watchdog(pci_devfn_t dev)
{
#if 0
/* FIXME move me somewhere more appropriate */
@@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev)
static void disable_esb6300_watchdog(void)
{
/* FIXME move me somewhere more appropriate */
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
@@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void)
static void disable_jarell_frb3(void)
{
#if 0
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c
index 93199d7..5ea10d2 100644
--- a/src/mainboard/supermicro/x6dhe_g2/debug.c
+++ b/src/mainboard/supermicro/x6dhe_g2/debug.c
@@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev)
static void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index a2b8c8d..c4d690e 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* esb6300_2 */
dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
@@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
{
struct resource *res;
- device_t dev;
+ struct device * dev;
/* PXHd apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index 48945eb..b9e0d50 100644
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -73,7 +73,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5r?");
diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c
index 1d34f7d..3fab7f9 100644
--- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c
+++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c
@@ -5,7 +5,7 @@
#define ESB6300_WDBASE 0x400
#define ESB6300_GPIOBASE 0x500
-static void disable_sio_watchdog(device_t dev)
+static void disable_sio_watchdog(pci_devfn_t dev)
{
#if 0
/* FIXME move me somewhere more appropriate */
@@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev)
static void disable_esb6300_watchdog(void)
{
/* FIXME move me somewhere more appropriate */
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
@@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void)
static void disable_jarell_frb3(void)
{
#if 0
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c
index 93199d7..5ea10d2 100644
--- a/src/mainboard/supermicro/x6dhr_ig/debug.c
+++ b/src/mainboard/supermicro/x6dhr_ig/debug.c
@@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev)
static void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c
index f9165d6..935ae8c 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c
@@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* ich5r */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
@@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
struct resource *res;
- device_t dev;
+ struct device * dev;
/* pxhd apic 3 */
dev = dev_find_slot(2, PCI_DEVFN(0x00,1));
if (dev) {
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 08b0ccd..e78d511 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -72,7 +72,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c
index a451c32..259ea79 100644
--- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c
+++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c
@@ -5,7 +5,7 @@
#define ICH5_WDBASE 0x400
#define ICH5_GPIOBASE 0x500
-static void disable_sio_watchdog(device_t dev)
+static void disable_sio_watchdog(pci_devfn_t dev)
{
#if 0
/* FIXME move me somewhere more appropriate */
@@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev)
static void disable_ich5_watchdog(void)
{
/* FIXME move me somewhere more appropriate */
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
@@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void)
static void disable_jarell_frb3(void)
{
#if 0
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c
index 93199d7..5ea10d2 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/debug.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c
@@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
@@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev)
static void dump_pci_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
index b5ba6b1..56aec2e 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
@@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* ich5r */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
@@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
struct resource *res;
- device_t dev;
+ struct device * dev;
/* pxhd apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index dfe0da2..5d6d89c 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -72,7 +72,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c
index a451c32..259ea79 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c
@@ -5,7 +5,7 @@
#define ICH5_WDBASE 0x400
#define ICH5_GPIOBASE 0x500
-static void disable_sio_watchdog(device_t dev)
+static void disable_sio_watchdog(pci_devfn_t dev)
{
#if 0
/* FIXME move me somewhere more appropriate */
@@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev)
static void disable_ich5_watchdog(void)
{
/* FIXME move me somewhere more appropriate */
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
@@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void)
static void disable_jarell_frb3(void)
{
#if 0
- device_t dev;
+ pci_devfn_t dev;
unsigned long value, base;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c
index 1d666c9..cf0c044 100644
--- a/src/mainboard/supermicro/x7db8/mainboard.c
+++ b/src/mainboard/supermicro/x7db8/mainboard.c
@@ -27,7 +27,7 @@
#include <device/pci_ops.h>
#include <arch/io.h>
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
}
diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c
index 084e2b1..c959280 100644
--- a/src/mainboard/technexion/tim5690/get_bus_conf.c
+++ b/src/mainboard/technexion/tim5690/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
index 3423e51..da4ed9a 100644
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ b/src/mainboard/technexion/tim5690/mainboard.c
@@ -117,7 +117,7 @@ static void set_thermal_config(void)
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -222,7 +222,7 @@ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
* enable the dedicated function in tim5690 board.
* This function called early than rs690_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
#if CONFIG_VGA_ROM_RUN
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 8b86b02..840a93a 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c
index 084e2b1..c959280 100644
--- a/src/mainboard/technexion/tim8690/get_bus_conf.c
+++ b/src/mainboard/technexion/tim8690/get_bus_conf.c
@@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 6010eb1..14811bb 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -53,7 +53,7 @@ static void enable_onboard_nic(void)
{
u8 byte;
- device_t sm_dev;
+ struct device * sm_dev;
printk(BIOS_INFO, "enable_onboard_nic.\n");
@@ -79,7 +79,7 @@ static void set_thermal_config(void)
{
u8 byte;
u16 word;
- device_t sm_dev;
+ struct device * sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -140,7 +140,7 @@ static void set_thermal_config(void)
* enable the dedicated function in tim8690 board.
* This function called early than rs690_enable.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 8b86b02..840a93a 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
- device_t dev;
+ struct device * dev;
u32 dword;
u8 byte;
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
index 7267696..9bd4f53 100644
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ b/src/mainboard/thomson/ip1000/mainboard.c
@@ -84,13 +84,13 @@ static void flash_gpios(void)
}
}
-static void mainboard_init(device_t dev)
+static void mainboard_init(struct device * dev)
{
parport_gpios();
flash_gpios();
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 9073728..9f65205 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
if (dev) {
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 371d9a3..3145e32 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -10,7 +10,7 @@
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
- device_t dev;
+ struct device * dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* HT chain 0 */
bus_chain_0 = node_link_to_bus(0, 0);
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 90299a7..798ea64 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -10,7 +10,7 @@
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
- device_t dev;
+ struct device * dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* HT chain 0 */
bus_chain_0 = node_link_to_bus(0, 0);
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 32fc639..cbefcdb 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -10,7 +10,7 @@
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
- device_t dev;
+ struct device * dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* HT chain 0 */
bus_chain_0 = node_link_to_bus(0, 0);
@@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
if (dev) {
diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c
index 332e578..b2177a4 100644
--- a/src/mainboard/tyan/s2881/get_bus_conf.c
+++ b/src/mainboard/tyan/s2881/get_bus_conf.c
@@ -53,7 +53,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index 7df5e87..d28a104 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 6c07965..b06b49c 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -11,7 +11,7 @@
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
- device_t dev;
+ struct device * dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* HT chain 0 */
bus_chain_0 = node_link_to_bus(0, 0);
@@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
if (dev) {
diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c
index 88706c0..dfd62b8 100644
--- a/src/mainboard/tyan/s2885/get_bus_conf.c
+++ b/src/mainboard/tyan/s2885/get_bus_conf.c
@@ -56,7 +56,7 @@ void get_bus_conf(void)
unsigned apicid_base;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index 26081c7..6413230 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c
index e94c608..5ff3e3b 100644
--- a/src/mainboard/tyan/s2891/get_bus_conf.c
+++ b/src/mainboard/tyan/s2891/get_bus_conf.c
@@ -60,7 +60,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c
index 9a8dd90..5f261c6 100644
--- a/src/mainboard/tyan/s2891/mainboard.c
+++ b/src/mainboard/tyan/s2891/mainboard.c
@@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) {
amd_generate_powernow(0, 0, 0);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator;
}
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index cb49434..f52a07b 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c
index 0ead854..e59cd33 100644
--- a/src/mainboard/tyan/s2892/get_bus_conf.c
+++ b/src/mainboard/tyan/s2892/get_bus_conf.c
@@ -58,7 +58,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c
index 9a8dd90..5f261c6 100644
--- a/src/mainboard/tyan/s2892/mainboard.c
+++ b/src/mainboard/tyan/s2892/mainboard.c
@@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) {
amd_generate_powernow(0, 0, 0);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator;
}
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index 882ac69..d3dc505 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c
index 11b1bc2..c6d9a08 100644
--- a/src/mainboard/tyan/s2895/get_bus_conf.c
+++ b/src/mainboard/tyan/s2895/get_bus_conf.c
@@ -66,7 +66,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c
index 604df51..85f5556 100644
--- a/src/mainboard/tyan/s2895/mainboard.c
+++ b/src/mainboard/tyan/s2895/mainboard.c
@@ -12,7 +12,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) {
amd_generate_powernow(0, 0, 0);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator;
}
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index 20fa92c..3c4242f 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c
index 7727c4b..fb38d32 100644
--- a/src/mainboard/tyan/s2912/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912/get_bus_conf.c
@@ -70,7 +70,7 @@ void get_bus_conf(void)
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
+ struct device *dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index 133ce43..8620cd4 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 0a3a9d8..6a9e2e9 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -71,7 +71,7 @@ void get_bus_conf(void)
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
+ struct device *dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index e15387d..0b7ce31 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index dcc0fd8..3ec04bb 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -10,7 +10,7 @@
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
- device_t dev;
+ struct device * dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* HT chain 0 */
bus_chain_0 = node_link_to_bus(0, 2);
@@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
if (dev) {
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index 350b55c..3d22fd9 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -10,7 +10,7 @@
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
- device_t dev;
+ struct device * dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
{
- device_t dev;
+ struct device * dev;
/* HT chain 0 */
bus_chain_0 = node_link_to_bus(0, 1);
@@ -119,7 +119,7 @@ static void *smp_write_config_table(void *v)
apicid_8131_2 = apicid_base+2;
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
- device_t dev;
+ struct device * dev;
struct resource *res;
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
if (dev) {
diff --git a/src/mainboard/tyan/s8226/mainboard.c b/src/mainboard/tyan/s8226/mainboard.c
index 9e8160a..6f094cb 100644
--- a/src/mainboard/tyan/s8226/mainboard.c
+++ b/src/mainboard/tyan/s8226/mainboard.c
@@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig)
/*************************************************
* enable the dedicated function in s8226 board.
*************************************************/
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
}
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
index 5ec4a35..230cacc 100644
--- a/src/mainboard/tyan/s8226/mptable.c
+++ b/src/mainboard/tyan/s8226/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
int bus_isa;
u32 apicid_sp5100;
u32 apicid_sr5650;
- device_t dev;
+ struct device * dev;
u32 dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 20f99cb..d3d5857 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -44,7 +44,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
index 3f2a0c4..2d66bbd 100644
--- a/src/mainboard/via/epia-m/romstage.c
+++ b/src/mainboard/via/epia-m/romstage.c
@@ -25,7 +25,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8235), 0);
@@ -57,7 +57,7 @@ static void enable_mainboard_devices(void)
static void enable_shadow_ram(void)
{
- device_t dev = 0; /* no need to look up 0:0.0 */
+ pci_devfn_t dev = 0; /* no need to look up 0:0.0 */
unsigned char shadowreg;
/* dev 0 for southbridge */
shadowreg = pci_read_config8(dev, 0x63);
@@ -69,7 +69,7 @@ static void enable_shadow_ram(void)
#include <cpu/intel/romstage.h>
static void main(unsigned long bist)
{
- device_t dev;
+ pci_devfn_t dev;
/* Enable VGA; 32MB buffer. */
pci_write_config8(0, 0xe1, 0xdd);
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index b00ece1..700d13f 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -55,7 +55,7 @@
*/
static int acpi_is_wakeup_early_via_vx800(void)
{
- device_t dev;
+ pci_devfn_t dev;
u16 tmp, result;
print_debug("In acpi_is_wakeup_early_via_vx800\n");
@@ -83,7 +83,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
/* All content of this function came from the cx700 port of coreboot. */
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
#if 0
/*
* Add and close this switch, since some line cause error, some
@@ -378,8 +378,8 @@ void main(unsigned long bist)
{
u16 boot_mode;
u8 rambits, Data8, Data;
- device_t device;
- /* device_t dev; */
+ pci_devfn_t device;
+ /* pci_devfn_t dev; */
/*
* Enable multifunction for northbridge. These 4 lines (until
diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c
index dbe682c..146c21b 100644
--- a/src/mainboard/via/epia-m850/mainboard.c
+++ b/src/mainboard/via/epia-m850/mainboard.c
@@ -95,7 +95,7 @@ static int vx900_int15_handler(void)
}
#endif
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
(void)dev;
diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 2ede8d8..f8ba755 100644
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -58,7 +58,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 reg;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
@@ -105,7 +105,7 @@ static void enable_shadow_ram(void)
static void main(unsigned long bist)
{
unsigned long x;
- device_t dev;
+ pci_devfn_t dev;
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c
index 1d312d7..aff85a5 100644
--- a/src/mainboard/via/epia/romstage.c
+++ b/src/mainboard/via/epia/romstage.c
@@ -24,7 +24,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* dev 0 for southbridge */
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
@@ -60,7 +60,7 @@ static void enable_mainboard_devices(void)
static void enable_shadow_ram(void)
{
- device_t dev = 0;
+ pci_devfn_t dev = 0;
unsigned char shadowreg;
shadowreg = pci_read_config8(dev, 0x63);
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index f6d58c8..97f1858 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -39,7 +39,7 @@
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
if (dev == PCI_DEV_INVALID) {
diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c
index 5b96b05..1c7e1da 100644
--- a/src/mainboard/winent/mb6047/get_bus_conf.c
+++ b/src/mainboard/winent/mb6047/get_bus_conf.c
@@ -35,7 +35,7 @@ void get_bus_conf(void)
unsigned apicid_base;
unsigned sbdn;
- device_t dev;
+ struct device *dev;
int i;
if (get_bus_conf_done == 1)
diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c
index 9a8dd90..5f261c6 100644
--- a/src/mainboard/winent/mb6047/mainboard.c
+++ b/src/mainboard/winent/mb6047/mainboard.c
@@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) {
amd_generate_powernow(0, 0, 0);
}
-static void mainboard_enable(device_t dev)
+static void mainboard_enable(struct device * dev)
{
dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator;
}
diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c
index 26e79ca..afbb8b9 100644
--- a/src/mainboard/winent/mb6047/mptable.c
+++ b/src/mainboard/winent/mb6047/mptable.c
@@ -33,7 +33,7 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
{
- device_t dev;
+ struct device * dev;
struct resource *res;
uint32_t dword;
1
0
Patch set updated for coreboot: 04cf77b Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'
by Edward O'Callaghan 04 Nov '14
by Edward O'Callaghan 04 Nov '14
04 Nov '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196
-gerrit
commit 04cf77b3cf8b51aafecc9e9800d08e9d8d728739
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun Oct 26 10:36:02 2014 +1100
Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'
Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/northbridge/amd/amdfam10/reset_test.c | 10 +++++-----
src/northbridge/amd/amdk8/reset_test.c | 4 ++--
src/southbridge/amd/amd8111/reset.c | 14 ++++++--------
src/southbridge/broadcom/bcm5785/reset.c | 6 ++----
src/southbridge/nvidia/ck804/reset.c | 6 ++----
src/southbridge/nvidia/mcp55/reset.c | 6 ++----
src/southbridge/sis/sis966/reset.c | 6 ++----
7 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 24f5397..de7949e 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -32,7 +32,7 @@
u32 cpu_init_detected(u8 nodeid)
{
u32 htic;
- device_t dev;
+ pci_devfn_t dev;
dev = NODE_PCI(nodeid, 0);
htic = pci_io_read_config32(dev, HT_INIT_CONTROL);
@@ -67,7 +67,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS
static void distinguish_cpu_resets(u8 nodeid)
{
u32 htic;
- device_t device;
+ pci_devfn_t device;
device = NODE_PCI(nodeid, 0);
htic = pci_io_read_config32(device, HT_INIT_CONTROL);
htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
@@ -77,7 +77,7 @@ static void distinguish_cpu_resets(u8 nodeid)
static u32 warm_reset_detect(u8 nodeid)
{
u32 htic;
- device_t device;
+ pci_devfn_t device;
device = NODE_PCI(nodeid, 0);
htic = pci_io_read_config32(device, HT_INIT_CONTROL);
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
@@ -89,7 +89,7 @@ void __attribute__ ((weak)) set_bios_reset(void)
u32 nodes;
u32 htic;
- device_t dev;
+ pci_devfn_t dev;
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
@@ -134,7 +134,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
int i;
int j;
u32 cfg_map_dest;
- device_t dev;
+ pci_devfn_t dev;
cfg_map_dest = (1<<7)|(1<<6)|link;
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index 6ef3ec0..8015290 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -10,7 +10,7 @@
static inline int cpu_init_detected(unsigned nodeid)
{
u32 htic;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x18 + nodeid, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
@@ -37,7 +37,7 @@ static inline int cold_reset_detected(void)
static inline void distinguish_cpu_resets(unsigned nodeid)
{
u32 htic;
- device_t device;
+ pci_devfn_t device;
device = PCI_DEV(0, 0x18 + nodeid, 0);
htic = pci_read_config32(device, HT_INIT_CONTROL);
htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index c96e898..8824550 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -10,9 +10,7 @@
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-typedef unsigned device_t;
-
-static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
outb(value, 0xCFC + (addr & 3));
}
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where)
}
#define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
{
- device_t dev, last;
+ pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
for(; dev <= last; dev += PCI_DEV(0,0,1)) {
@@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
void hard_reset(void)
{
- device_t dev;
+ pci_devfn_t dev;
unsigned bus;
unsigned node = 0;
unsigned link = get_sblk();
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 51ba6ec..b34cc86 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -26,9 +26,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c
index a241966..53c0c40 100644
--- a/src/southbridge/nvidia/ck804/reset.c
+++ b/src/southbridge/nvidia/ck804/reset.c
@@ -26,9 +26,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev >> 4) | where;
@@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev >> 4) | where;
diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c
index 0ec926f..520d836 100644
--- a/src/southbridge/nvidia/mcp55/reset.c
+++ b/src/southbridge/nvidia/mcp55/reset.c
@@ -29,9 +29,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c
index 0ec926f..520d836 100644
--- a/src/southbridge/sis/sis966/reset.c
+++ b/src/southbridge/sis/sis966/reset.c
@@ -29,9 +29,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
1
0
Patch set updated for coreboot: 5a9a263 soc: Don't hide pointers behind typedefs
by Edward O'Callaghan 04 Nov '14
by Edward O'Callaghan 04 Nov '14
04 Nov '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7277
-gerrit
commit 5a9a263aae86a4152f06b6b850874c0c719ec0b3
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Tue Oct 28 23:00:45 2014 +1100
soc: Don't hide pointers behind typedefs
Change-Id: I05bb3b09cd1059cf43905a310f5c1ba04ed32336
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++---
src/soc/intel/baytrail/chip.c | 6 ++---
src/soc/intel/baytrail/cpu.c | 4 ++--
src/soc/intel/baytrail/ehci.c | 4 ++--
src/soc/intel/baytrail/emmc.c | 2 +-
src/soc/intel/baytrail/gfx.c | 14 +++++------
src/soc/intel/baytrail/hda.c | 2 +-
src/soc/intel/baytrail/lpe.c | 12 +++++-----
src/soc/intel/baytrail/lpss.c | 10 ++++----
src/soc/intel/baytrail/northcluster.c | 2 +-
src/soc/intel/baytrail/pcie.c | 14 +++++------
src/soc/intel/baytrail/pmutil.c | 8 +++----
src/soc/intel/baytrail/ramstage.c | 2 +-
src/soc/intel/baytrail/sata.c | 2 +-
src/soc/intel/baytrail/scc.c | 2 +-
src/soc/intel/baytrail/sd.c | 2 +-
src/soc/intel/baytrail/smihandler.c | 2 +-
src/soc/intel/baytrail/southcluster.c | 24 +++++++++----------
src/soc/intel/baytrail/spi.c | 6 ++---
src/soc/intel/baytrail/xhci.c | 6 ++---
src/soc/intel/broadwell/acpi.c | 2 +-
src/soc/intel/broadwell/broadwell/me.h | 2 +-
src/soc/intel/broadwell/broadwell/pch.h | 2 +-
src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++--
src/soc/intel/broadwell/broadwell/xhci.h | 2 +-
src/soc/intel/broadwell/chip.c | 6 ++---
src/soc/intel/broadwell/cpu.c | 6 ++---
src/soc/intel/broadwell/ehci.c | 2 +-
src/soc/intel/broadwell/lpc.c | 18 +++++++--------
src/soc/intel/broadwell/me.c | 24 +++++++++----------
src/soc/intel/broadwell/pch.c | 6 ++---
src/soc/intel/broadwell/pcie.c | 32 +++++++++++++-------------
src/soc/intel/broadwell/romstage/uart.c | 2 +-
src/soc/intel/broadwell/sata.c | 2 +-
src/soc/intel/broadwell/smbus.c | 8 +++----
src/soc/intel/broadwell/smihandler.c | 2 +-
src/soc/intel/broadwell/smmrelocate.c | 6 ++---
src/soc/intel/broadwell/spi.c | 2 +-
src/soc/intel/broadwell/systemagent.c | 22 +++++++++---------
src/soc/intel/broadwell/xhci.c | 8 +++----
src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +-
src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++---
src/soc/intel/fsp_baytrail/chip.c | 8 +++----
src/soc/intel/fsp_baytrail/cpu.c | 4 ++--
src/soc/intel/fsp_baytrail/northcluster.c | 8 +++----
src/soc/intel/fsp_baytrail/pmutil.c | 4 ++--
src/soc/intel/fsp_baytrail/ramstage.c | 2 +-
src/soc/intel/fsp_baytrail/smihandler.c | 2 +-
src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++-----------
src/soc/intel/fsp_baytrail/spi.c | 6 ++---
src/soc/nvidia/tegra/dc.h | 2 +-
src/soc/nvidia/tegra124/display.c | 2 +-
src/soc/nvidia/tegra124/soc.c | 6 ++---
src/soc/samsung/exynos5250/cpu.c | 8 +++----
src/soc/samsung/exynos5420/cpu.c | 8 +++----
55 files changed, 191 insertions(+), 191 deletions(-)
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h
index a8b5fdc..4a7b536 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/baytrail/ramstage.h
@@ -26,16 +26,16 @@
/* The baytrail_init_pre_device() function is called prior to device
* initialization, but it's after console and cbmem has been reinitialized. */
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
-void baytrail_init_cpus(device_t dev);
+void baytrail_init_cpus(struct device *dev);
void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
+void southcluster_enable_dev(struct device *dev);
#if CONFIG_HAVE_REFCODE_BLOB
void baytrail_run_reference_code(void);
#else
static inline void baytrail_run_reference_code(void) {}
#endif
void baytrail_init_scc(void);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
index 7a5b9c2..a29bef2 100644
--- a/src/soc/intel/baytrail/chip.c
+++ b/src/soc/intel/baytrail/chip.c
@@ -26,7 +26,7 @@
#include <baytrail/ramstage.h>
#include "chip.h"
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@@ -49,7 +49,7 @@ static struct device_operations cpu_bus_ops = {
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
@@ -77,7 +77,7 @@ struct chip_operations soc_intel_baytrail_ops = {
.init = soc_init,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index e8f95ae..a5106dd 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -78,7 +78,7 @@ const struct reg_script core_msr_script[] = {
REG_SCRIPT_END
};
-void baytrail_init_cpus(device_t dev)
+void baytrail_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
const struct pattrs *pattrs = pattrs_get();
@@ -121,7 +121,7 @@ void baytrail_init_cpus(device_t dev)
restore_default_smm_area(default_smm_area);
}
-static void baytrail_core_init(device_t cpu)
+static void baytrail_core_init(struct device *cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index 5d1a4d8..accfed2 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = {
REG_SCRIPT_END
};
-static void usb2_phy_init(device_t dev)
+static void usb2_phy_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script usb2_phy_script[] = {
@@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev)
reg_script_run(usb2_phy_script);
}
-static void ehci_init(device_t dev)
+static void ehci_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script ehci_hc_init[] = {
diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c
index f88614b..74bdb4b 100644
--- a/src/soc/intel/baytrail/emmc.c
+++ b/src/soc/intel/baytrail/emmc.c
@@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = {
REG_SCRIPT_END,
};
-static void emmc_init(device_t dev)
+static void emmc_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 9d4768f..a47152d 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -38,7 +38,7 @@
* Lock Power Context Base Register to point to a 24KB block
* of memory in GSM. Power context save data is stored here.
*/
-static void gfx_lock_pcbase(device_t dev)
+static void gfx_lock_pcbase(struct device *dev)
{
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
@@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = {
REG_SCRIPT_END
};
-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
{
reg_script_run_on_dev(dev, ops);
}
-static void gfx_pre_vbios_init(device_t dev)
+static void gfx_pre_vbios_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
gfx_run_script(dev, gpu_pre_vbios_script);
}
-static void gfx_pm_init(device_t dev)
+static void gfx_pm_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Power Management Init\n");
gfx_run_script(dev, gfx_init_script);
@@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev)
gfx_lock_pcbase(dev);
}
-static void gfx_post_vbios_init(device_t dev)
+static void gfx_post_vbios_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
gfx_run_script(dev, gfx_post_vbios_script);
}
-static void gfx_panel_setup(device_t dev)
+static void gfx_panel_setup(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script gfx_pipea_init[] = {
@@ -340,7 +340,7 @@ static void gfx_panel_setup(device_t dev)
}
}
-static void gfx_init(device_t dev)
+static void gfx_init(struct device *dev)
{
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
index c5de654..5733b95 100644
--- a/src/soc/intel/baytrail/hda.c
+++ b/src/soc/intel/baytrail/hda.c
@@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = {
0x20671f58,
};
-static void hda_init(device_t dev)
+static void hda_init(struct device *dev)
{
struct resource *res;
int codec_mask;
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 581f42b..b6fb7c2 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -45,7 +45,7 @@
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
+static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
{
struct resource *res;
@@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
*field = res->base;
}
-static void lpe_enable_acpi_mode(device_t dev)
+static void lpe_enable_acpi_mode(struct device *dev)
{
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev)
reg_script_run_on_dev(dev, ops);
}
-static void setup_codec_clock(device_t dev)
+static void setup_codec_clock(struct device *dev)
{
uint32_t reg;
int clk_reg;
@@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev)
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
-static void lpe_stash_firmware_info(device_t dev)
+static void lpe_stash_firmware_info(struct device *dev)
{
struct resource *res;
struct resource *mmio;
@@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev)
}
}
-static void lpe_init(device_t dev)
+static void lpe_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -161,7 +161,7 @@ static void lpe_init(device_t dev)
lpe_enable_acpi_mode(dev);
}
-static void lpe_read_resources(device_t dev)
+static void lpe_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index 3ee648a..c548370 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -33,7 +33,7 @@
#include "chip.h"
-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
reg_script_run_on_dev(dev, ops);
}
-static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
+static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
{
struct reg_script ops[] = {
REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
@@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
reg_script_run_on_dev(dev, ops);
}
-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
{
*iosf_reg = -1;
*nvs_index = -1;
@@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
}
}
-static void i2c_disable_resets(device_t dev)
+static void i2c_disable_resets(struct device *dev)
{
/* Release the I2C devices from reset. */
static const struct reg_script ops[] = {
@@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev)
}
}
-static void lpss_init(device_t dev)
+static void lpss_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
int iosf_reg, nvs_index;
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index b119e24..2d4f20b 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void)
return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
}
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
{
unsigned long mmconf;
unsigned long bmbound;
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 4498f43..e530498 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -34,12 +34,12 @@
static int pll_en_off;
static uint32_t strpfusecfg;
-static inline int root_port_offset(device_t dev)
+static inline int root_port_offset(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn);
}
-static inline int is_first_port(device_t dev)
+static inline int is_first_port(struct device *dev)
{
return root_port_offset(dev) == PCIE_PORT1_FUNC;
}
@@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = {
REG_SCRIPT_END,
};
-static void byt_pcie_init(device_t dev)
+static void byt_pcie_init(struct device *dev)
{
struct reg_script init_script[] = {
REG_SCRIPT_NEXT(init_static_before_exit_latency),
@@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = {
REG_SCRIPT_END,
};
-static void check_port_enabled(device_t dev)
+static void check_port_enabled(struct device *dev)
{
int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
@@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev)
}
}
-static void check_device_present(device_t dev)
+static void check_device_present(struct device *dev)
{
/* Set slot implemented. */
pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);
@@ -172,7 +172,7 @@ static void check_device_present(device_t dev)
}
}
-static void byt_pcie_enable(device_t dev)
+static void byt_pcie_enable(struct device *dev)
{
if (is_first_port(dev)) {
struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev)
southcluster_enable_dev(dev);
}
-static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
+static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did)
{
uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index aee3726..935253c 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -28,9 +28,9 @@
#if defined(__SMM__)
-static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
+static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
-static inline device_t get_pcu_dev(void)
+static inline pci_devfn_t get_pcu_dev(void)
{
return pcu_dev;
}
@@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void)
#include <device/device.h>
#include <device/pci.h>
-static device_t pcu_dev;
-static device_t get_pcu_dev(void)
+static struct device *pcu_dev;
+static struct device *get_pcu_dev(void)
{
if (pcu_dev == NULL)
pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 9622930..10f7ff2 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -78,7 +78,7 @@ static const char *stepping_str[] = {
static void fill_in_pattrs(void)
{
- device_t dev;
+ struct device *dev;
msr_t msr;
struct pattrs *attrs = (struct pattrs *)pattrs_get();
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index 28a2f8c..3c69985 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -159,7 +159,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x98, reg32);
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
config_t *config = dev->chip_info;
u8 reg8;
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 7efb66d..e2bd1dd 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -87,7 +87,7 @@ void baytrail_init_scc(void)
reg_script_run(scc_after_dll);
}
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
index 97c8628..6068e61 100644
--- a/src/soc/intel/baytrail/sd.c
+++ b/src/soc/intel/baytrail/sd.c
@@ -34,7 +34,7 @@
#define CAP_OVERRIDE_HIGH 0xa4
# define USE_CAP_OVERRIDES (1 << 31)
-static void sd_init(device_t dev)
+static void sd_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 22b60c4..94e6d81 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 500a13d..d3d284d 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -43,12 +43,12 @@
#include "chip.h"
static inline void
-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
}
-static void sc_add_mmio_resources(device_t dev)
+static void sc_add_mmio_resources(struct device *dev)
{
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
@@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size)
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void sc_add_io_resource(device_t dev, int base, int size, int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
{
struct resource *res;
@@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void sc_add_io_resources(device_t dev)
+static void sc_add_io_resources(struct device *dev)
{
struct resource *res;
@@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev)
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
}
-static void sc_read_resources(device_t dev)
+static void sc_read_resources(struct device *dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -154,7 +154,7 @@ static void sc_rtc_init(void)
* or configuration. This is definitely a hack, but it helps the kernel
* along.
*/
-static void com1_configure_resume(device_t dev)
+static void com1_configure_resume(struct device *dev)
{
const uint16_t port = 0x3f8;
@@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev)
outb(3, port + UART8250_LCR);
}
-static void sc_init(device_t dev)
+static void sc_init(struct device *dev)
{
int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
@@ -224,7 +224,7 @@ static void sc_init(device_t dev)
*/
/* Set bit in function disble register to hide this device. */
-static void sc_disable_devfn(device_t dev)
+static void sc_disable_devfn(struct device *dev)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
@@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev)
}
}
-static inline void set_d3hot_bits(device_t dev, int offset)
+static inline void set_d3hot_bits(struct device *dev, int offset)
{
uint32_t reg8;
printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
@@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
* cannot put HDA into D3Hot. Instead perform this workaround to make some of
* the audio paths work for LPE audio. */
-static void hda_work_around(device_t dev)
+static void hda_work_around(struct device *dev)
{
unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
@@ -362,7 +362,7 @@ static void hda_work_around(device_t dev)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
-static int place_device_in_d3hot(device_t dev)
+static int place_device_in_d3hot(struct device *dev)
{
unsigned offset;
@@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev)
}
/* Common PCI device function disable. */
-void southcluster_enable_dev(device_t dev)
+void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 8677b61..112b878 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -290,13 +290,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
static ich9_spi_regs *spi_regs(void)
{
- device_t dev;
uint32_t sbase;
+/* N.B. dev is stage dependent typed */
#ifdef __SMM__
- dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
+ pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
#else
- dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
#endif
pci_read_config_dword(dev, SBASE, &sbase);
sbase &= ~0x1ff;
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 8d076c2..3f3ed91 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = {
};
/* Warm Reset a USB3 port */
-static void xhci_reset_port_usb3(device_t dev, int port)
+static void xhci_reset_port_usb3(struct device *dev, int port)
{
struct reg_script reset_port_usb3_script[] = {
/* Issue Warm Port Rest to the port */
@@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port)
}
/* Prepare ports to be routed to EHCI or XHCI */
-static void xhci_route_all(device_t dev)
+static void xhci_route_all(struct device *dev)
{
static const struct reg_script xhci_route_all_script[] = {
/* USB3 SuperSpeed Enable */
@@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev)
}
}
-static void xhci_init(device_t dev)
+static void xhci_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script xhci_hc_init[] = {
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index f4cac7b..3259308 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package)
static int generate_C_state_entries(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
acpi_cstate_t map[3];
int *set;
diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h
index ddecaf8..f3021ee 100644
--- a/src/soc/intel/broadwell/broadwell/me.h
+++ b/src/soc/intel/broadwell/broadwell/me.h
@@ -465,7 +465,7 @@ typedef struct {
} __attribute__ ((packed)) mbp_plat_time;
typedef struct {
- u32 device_type : 2;
+ u32 struct device *ype : 2;
u32 reserved : 30;
} __attribute__ ((packed)) mbp_nfc_data;
diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h
index e677215..c58b695 100644
--- a/src/soc/intel/broadwell/broadwell/pch.h
+++ b/src/soc/intel/broadwell/broadwell/pch.h
@@ -47,6 +47,6 @@ int pch_is_wpt(void);
int pch_is_wpt_ulx(void);
u32 pch_read_soft_strap(int id);
void pch_log_state(void);
-void pch_disable_devfn(device_t dev);
+void pch_disable_devfn(struct device *dev);
#endif
diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h
index 685de14..d66e8cc 100644
--- a/src/soc/intel/broadwell/broadwell/ramstage.h
+++ b/src/soc/intel/broadwell/broadwell/ramstage.h
@@ -24,8 +24,8 @@
#include <chip.h>
void broadwell_init_pre_device(void *chip_info);
-void broadwell_init_cpus(device_t dev);
-void broadwell_pch_enable_dev(device_t dev);
+void broadwell_init_cpus(struct device *dev);
+void broadwell_pch_enable_dev(struct device *dev);
#if CONFIG_HAVE_REFCODE_BLOB
void broadwell_run_reference_code(void);
diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h
index 3f4fb4e..a5536fc 100644
--- a/src/soc/intel/broadwell/broadwell/xhci.h
+++ b/src/soc/intel/broadwell/broadwell/xhci.h
@@ -55,7 +55,7 @@
#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
#ifdef __SMM__
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ);
#endif
#endif
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index 2a12820..ef19e8e 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -24,7 +24,7 @@
#include <broadwell/ramstage.h>
#include <chip.h>
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@@ -43,7 +43,7 @@ static struct device_operations cpu_bus_ops = {
.init = &broadwell_init_cpus,
};
-static void broadwell_enable(device_t dev)
+static void broadwell_enable(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
@@ -65,7 +65,7 @@ struct chip_operations soc_intel_broadwell_ops = {
.init = &broadwell_init_pre_device,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device)
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 58f81fc..416fe3c 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -444,7 +444,7 @@ static void configure_c_states(void)
static void configure_thermal_target(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
@@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
}
/* All CPUs including BSP will run the following function. */
-static void cpu_core_init(device_t cpu)
+static void cpu_core_init(struct device *cpu)
{
/* Clear out pending MCEs */
configure_mca();
@@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = {
.id_table = cpu_table,
};
-void broadwell_init_cpus(device_t dev)
+void broadwell_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
int num_threads;
diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c
index a59d3c8..30f4acd 100644
--- a/src/soc/intel/broadwell/ehci.c
+++ b/src/soc/intel/broadwell/ehci.c
@@ -28,7 +28,7 @@
#include <broadwell/ehci.h>
#include <broadwell/pch.h>
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
u8 access_cntl;
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 4b21326..270316c 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev)
* 0x80 - The PIRQ is not routed.
*/
-static void pch_pirq_init(device_t dev)
+static void pch_pirq_init(struct device *dev)
{
- device_t irq_dev;
+ struct device *irq_dev;
config_t *config = dev->chip_info;
pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
@@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev)
}
}
-static void pch_power_options(device_t dev)
+static void pch_power_options(struct device *dev)
{
u16 reg16;
const char *state;
@@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev)
RCBA32_OR(0x3a6c, 0x00000001);
}
-static void pch_cg_init(device_t dev)
+static void pch_cg_init(struct device *dev)
{
u32 reg32;
u16 reg16;
@@ -420,7 +420,7 @@ static void lpc_init(struct device *dev)
pch_set_acpi_mode();
}
-static void pch_lpc_add_mmio_resources(device_t dev)
+static void pch_lpc_add_mmio_resources(struct device *dev)
{
u32 reg;
struct resource *res;
@@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size)
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)
{
struct resource *res;
@@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)
{
/*
* Check if the register is enabled. If so and the base exceeds the
@@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
}
}
-static void pch_lpc_add_io_resources(device_t dev)
+static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev)
pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
}
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
{
global_nvs_t *gnvs;
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 15bcc34..19bc754 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = {
[ME_DISABLE_BIOS_PATH] = "Disable",
[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
};
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
/* MMIO base address for MEI interface */
static u32 mei_base_address;
-void intel_me_mbp_clear(device_t dev);
+void intel_me_mbp_clear(struct device *dev);
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
mei_dump(ptr, dword, offset, "WRITE");
}
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc,
* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
* state machine on the BIOS end doesn't match the ME's state machine.
*/
-static void intel_me_mbp_give_up(device_t dev)
+static void intel_me_mbp_give_up(struct device *dev)
{
struct mei_csr csr;
@@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev)
* mbp clear routine. This will wait for the ME to indicate that
* the MBP has been read and cleared.
*/
-void intel_me_mbp_clear(device_t dev)
+void intel_me_mbp_clear(struct device *dev)
{
int count;
struct me_hfs2 hfs2;
@@ -568,7 +568,7 @@ static int mkhi_end_of_post(void)
void intel_me_finalize(void)
{
- device_t dev = PCH_DEV_ME;
+ struct device *dev = PCH_DEV_ME;
struct me_hfs hfs;
u32 reg32;
@@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask)
}
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev)
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev)
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev)
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
config_t *config = dev->chip_info;
me_bios_path path = intel_me_path(dev);
@@ -829,7 +829,7 @@ static void intel_me_init(device_t dev)
*/
}
-static void intel_me_enable(device_t dev)
+static void intel_me_enable(struct device *dev)
{
#if CONFIG_HAVE_ACPI_RESUME
/* Avoid talking to the device in S3 path */
@@ -882,7 +882,7 @@ struct mbp_payload {
* mbp seems to be following its own flow, let's retrieve it in a dedicated
* function.
*/
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
{
mbp_header mbp_hdr;
u32 me2host_pending;
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index 82390a4..e681620 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id)
#ifndef __PRE_RAM__
/* Put device in D3Hot Power State */
-static void pch_enable_d3hot(device_t dev)
+static void pch_enable_d3hot(struct device *dev)
{
u32 reg32 = pci_read_config32(dev, PCH_PCS);
reg32 |= PCH_PCS_PS_D3HOT;
@@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev)
}
/* Set bit in Function Disble register to hide this device */
-void pch_disable_devfn(device_t dev)
+void pch_disable_devfn(struct device *dev)
{
switch (dev->path.pci.devfn) {
case PCH_DEVFN_ADSP: /* Audio DSP */
@@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev)
}
}
-void broadwell_pch_enable_dev(device_t dev)
+void broadwell_pch_enable_dev(struct device *dev)
{
u32 reg32;
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index a407f3c..08e4863 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -32,8 +32,8 @@
#include <broadwell/rcba.h>
#include <chip.h>
-static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
-static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
+static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or);
+static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or);
/* Low Power variant has 6 root ports. */
#define NUM_ROOT_PORTS 6
@@ -52,23 +52,23 @@ struct root_port_config {
int coalesce;
int gbe_port;
int num_ports;
- device_t ports[NUM_ROOT_PORTS];
+ struct device *ports[NUM_ROOT_PORTS];
};
static struct root_port_config rpc;
-static inline int root_port_is_first(device_t dev)
+static inline int root_port_is_first(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == 0;
}
-static inline int root_port_is_last(device_t dev)
+static inline int root_port_is_last(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
}
/* Root ports are numbered 1..N in the documentation. */
-static inline int root_port_number(device_t dev)
+static inline int root_port_number(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) + 1;
}
@@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void)
}
}
-static void root_port_init_config(device_t dev)
+static void root_port_init_config(struct device *dev)
{
int rp;
@@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev)
/* Update devicetree with new Root Port function number assignment */
static void pch_pcie_device_set_func(int index, int pci_func)
{
- device_t dev;
+ struct device *dev;
unsigned new_devfn;
dev = rpc.ports[index];
@@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void)
int enabled_ports = 0;
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
int rp;
dev = rpc.ports[i];
@@ -244,7 +244,7 @@ static void root_port_commit_config(void)
pcie_enable_clock_gating();
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
u32 reg32;
dev = rpc.ports[i];
@@ -297,7 +297,7 @@ static void root_port_commit_config(void)
RCBA32(RPFN) = rpc.new_rpfn;
}
-static void root_port_mark_disable(device_t dev)
+static void root_port_mark_disable(struct device *dev)
{
/* Mark device as disabled. */
dev->enabled = 0;
@@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev)
rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
}
-static void root_port_check_disable(device_t dev)
+static void root_port_check_disable(struct device *dev)
{
int rp;
@@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev)
}
}
-static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or)
+static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or)
{
u8 reg8;
@@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or)
pci_write_config8(dev, reg, reg8);
}
-static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
+static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or)
{
u32 reg32;
@@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev)
pci_write_config16(dev, 0x1e, reg16);
}
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
/* Add this device to the root port config structure. */
root_port_init_config(dev);
@@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev)
root_port_commit_config();
}
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device)
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
index 8214a8a..2517fef 100644
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -52,7 +52,7 @@ void pch_uart_init(void)
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
u32 gpiodf = 0x131f;
- device_t dev;
+ struct device *dev;
/* Put UART in byte access mode for 16550 compatibility */
switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index e8d1fbe..24a8ebe 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -221,7 +221,7 @@ static void sata_init(struct device *dev)
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c
index a1dbdfe..c214510 100644
--- a/src/soc/intel/broadwell/smbus.c
+++ b/src/soc/intel/broadwell/smbus.c
@@ -31,7 +31,7 @@
#include <broadwell/ramstage.h>
#include <broadwell/smbus.h>
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
@@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
@@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_BASE_ADDRESS;
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 6acd07c..49cf774 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ struct device *dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index bd1fc26..9ba6a00 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
}
}
-static u32 northbridge_get_base_reg(device_t dev, int reg)
+static u32 northbridge_get_base_reg(struct device *dev, int reg)
{
u32 value;
@@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg)
return value;
}
-static void fill_in_relocation_params(device_t dev,
+static void fill_in_relocation_params(struct device *dev,
struct smm_relocation_params *params)
{
u32 tseg_size;
@@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus,
static int cpu_smm_setup(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
int num_cpus;
msr_t msr;
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 353323a..6095cf7 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -286,7 +286,7 @@ void spi_init(void)
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
- device_t dev = PCH_DEV_LPC;
+ struct device *dev = PCH_DEV_LPC;
ich9_spi_regs *ich9_spi;
pci_read_config_dword(dev, 0xf0, &rcba);
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 2b3ce41..d940e33 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -37,7 +37,7 @@
#include <broadwell/ramstage.h>
#include <broadwell/systemagent.h>
-static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
u32 pciexbar_reg;
@@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
return 0;
}
-static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
+static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
u32 bar;
@@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
/* There are special BARs that actually are programmed in the MCHBAR. These
* Intel special features, but they do consume resources that need to be
* accounted for. */
-static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
u32 *len)
{
u32 bar;
@@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
struct fixed_mmio_descriptor {
unsigned int index;
u32 size;
- int (*get_resource)(device_t dev, unsigned int index,
+ int (*get_resource)(struct device *dev, unsigned int index,
u32 *base, u32 *size);
const char *description;
};
@@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = {
* Add all known fixed MMIO ranges that hang off the host bridge/memory
* controller device.
*/
-static void mc_add_fixed_mmio_resources(device_t dev)
+static void mc_add_fixed_mmio_resources(struct device *dev)
{
int i;
@@ -184,7 +184,7 @@ struct map_entry {
const char *description;
};
-static void read_map_entry(device_t dev, struct map_entry *entry,
+static void read_map_entry(struct device *dev, struct map_entry *entry,
uint64_t *result)
{
uint64_t value;
@@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
};
-static void mc_read_map_entries(device_t dev, uint64_t *values)
+static void mc_read_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
@@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values)
}
}
-static void mc_report_map_entries(device_t dev, uint64_t *values)
+static void mc_report_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
@@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values)
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
}
-static void mc_add_dram_resources(device_t dev)
+static void mc_add_dram_resources(struct device *dev)
{
unsigned long base_k, size_k;
unsigned long touud_k;
@@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev)
chromeos_reserve_ram_oops(dev, index++);
}
-static void systemagent_read_resources(device_t dev)
+static void systemagent_read_resources(struct device *dev)
{
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
@@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev)
set_power_limits(28);
}
-static void systemagent_enable(device_t dev)
+static void systemagent_enable(struct device *dev)
{
#if CONFIG_HAVE_ACPI_RESUME
struct romstage_handoff *handoff;
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 89e1139..9530422 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -27,7 +27,7 @@
#include <broadwell/xhci.h>
#ifdef __SMM__
-static u32 usb_xhci_mem_base(device_t dev)
+static u32 usb_xhci_mem_base(struct device *dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev)
return mem_base & ~0xf;
}
-static int usb_xhci_port_count_usb3(device_t dev)
+static int usb_xhci_port_count_usb3(struct device *dev)
{
/* PCH-LP has 4 SS ports */
return 4;
@@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
* b) Poll for warm reset complete
* c) Write 1 to port change status bits
*/
-static void usb_xhci_reset_usb3(device_t dev, int all)
+static void usb_xhci_reset_usb3(struct device *dev, int all)
{
u32 status, port_disabled;
int timeout, port;
@@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
}
/* Handler for XHCI controller on entry to S3/S4/S5 */
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
index d3a2377..d991d34 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
@@ -57,7 +57,7 @@ void rangeley_early_initialization(void);
int soc_silicon_revision(void);
int soc_silicon_type(void);
int soc_silicon_supported(int type, int rev);
-void soc_enable(device_t dev);
+void soc_enable(struct device *dev);
/* debugging functions */
void print_pci_devices(void);
diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
index 095f09c..c1114df 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
@@ -25,10 +25,10 @@
/* The baytrail_init_pre_device() function is called prior to device
* initialization, but it's after console and cbmem has been reinitialized. */
void baytrail_init_pre_device(void);
-void baytrail_init_cpus(device_t dev);
+void baytrail_init_cpus(struct device *dev);
void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void southcluster_enable_dev(struct device *dev);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c
index 732d1dc..5b54874 100644
--- a/src/soc/intel/fsp_baytrail/chip.c
+++ b/src/soc/intel/fsp_baytrail/chip.c
@@ -25,12 +25,12 @@
#include <drivers/intel/fsp/fsp_util.h>
#include "chip.h"
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
-static void finalize_dev (device_t dev)
+static void finalize_dev (struct device *dev)
{
/*
* Notify FSP for PostPciEnumeration.
@@ -58,7 +58,7 @@ static struct device_operations cpu_bus_ops = {
.scan_bus = NULL,
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
dev_name(dev), dev->path.type);
@@ -98,7 +98,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = {
.final = &finalize_chip,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 6f1e9c4..5c6375e 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = {
REG_SCRIPT_END
};
-void baytrail_init_cpus(device_t dev)
+void baytrail_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
const struct pattrs *pattrs = pattrs_get();
@@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev)
}
}
-static void baytrail_core_init(device_t cpu)
+static void baytrail_core_init(struct device *cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c
index 838e554..010063e 100644
--- a/src/soc/intel/fsp_baytrail/northcluster.c
+++ b/src/soc/intel/fsp_baytrail/northcluster.c
@@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void)
static int get_pcie_bar(u32 *base, u32 *len)
{
- device_t dev;
+ struct device *dev;
u32 pciexbar_reg;
*base = 0;
@@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index)
return index;
}
-static void mc_add_dram_resources(device_t dev)
+static void mc_add_dram_resources(struct device *dev)
{
u32 bmbound, bsmmrrl;
int index = 0;
@@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev)
index = add_fixed_resources(dev, index);
}
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
{
/* Call the normal read_resources */
pci_dev_read_resources(dev);
@@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev)
mc_add_dram_resources(dev);
}
-static void nc_enable(device_t dev)
+static void nc_enable(struct device *dev)
{
print_fsp_info();
}
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index aee3726..6a62a34 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void)
#include <device/device.h>
#include <device/pci.h>
-static device_t pcu_dev;
-static device_t get_pcu_dev(void)
+static struct device *pcu_dev;
+static struct device *get_pcu_dev(void)
{
if (pcu_dev == NULL)
pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c
index 814b16e..55abb4d 100644
--- a/src/soc/intel/fsp_baytrail/ramstage.c
+++ b/src/soc/intel/fsp_baytrail/ramstage.c
@@ -76,7 +76,7 @@ static const char *stepping_str[] = {
static void fill_in_pattrs(void)
{
- device_t dev;
+ struct device *dev;
msr_t msr;
struct pattrs *attrs = (struct pattrs *)pattrs_get();
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index 2225964..50b6ef4 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 2216902..307b006 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -51,12 +51,12 @@
typedef struct soc_intel_fsp_baytrail_config config_t;
static inline void
-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
}
-static void sc_add_mmio_resources(device_t dev)
+static void sc_add_mmio_resources(struct device *dev)
{
#ifndef CONFIG_VIRTUAL_ROM_SIZE
#error CONFIG_VIRTUAL_ROM_SIZE must be set.
@@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev)
*/
static void write_pci_config_irqs(void)
{
- device_t irq_dev;
- device_t targ_dev;
+ struct device *irq_dev;
+ struct device *targ_dev;
uint8_t int_line = 0;
uint8_t original_int_pin = 0;
uint8_t new_int_pin = 0;
@@ -255,7 +255,7 @@ static void write_pci_config_irqs(void)
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
-static void sc_pirq_init(device_t dev)
+static void sc_pirq_init(struct device *dev)
{
int i, j;
int pirq;
@@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size)
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void sc_add_io_resource(device_t dev, int base, int size, int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
{
struct resource *res;
@@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index)
IORESOURCE_FIXED;
}
-static void sc_add_io_resources(device_t dev)
+static void sc_add_io_resources(struct device *dev)
{
struct resource *res;
u8 io_index = 0;
@@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev)
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
}
-static void sc_read_resources(device_t dev)
+static void sc_read_resources(struct device *dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -409,7 +409,7 @@ static void sc_init(struct device *dev)
*/
/* Set bit in function disable register to hide this device. */
-static void sc_disable_devfn(device_t dev)
+static void sc_disable_devfn(struct device *dev)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
@@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev)
}
}
-static inline void set_d3hot_bits(device_t dev, int offset)
+static inline void set_d3hot_bits(struct device *dev, int offset)
{
uint32_t reg8;
printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
@@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
* cannot put HDA into D3Hot. Instead perform this workaround to make some of
* the audio paths work for LPE audio. */
-static void hda_work_around(device_t dev)
+static void hda_work_around(struct device *dev)
{
unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
@@ -534,7 +534,7 @@ static void hda_work_around(device_t dev)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
-static int place_device_in_d3hot(device_t dev)
+static int place_device_in_d3hot(struct device *dev)
{
unsigned offset;
@@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev)
}
/* Common PCI device function disable. */
-void southcluster_enable_dev(device_t dev)
+void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 4feb502..295e203 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -288,13 +288,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
static ich9_spi_regs *spi_regs(void)
{
- device_t dev;
uint32_t sbase;
+/* N.B. dev is type-dependent on stage */
#ifdef __SMM__
- dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
+ pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
#else
- dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
#endif
pci_read_config_dword(dev, SBASE, &sbase);
sbase &= ~0x1ff;
diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h
index 48ffbda..895fd89 100644
--- a/src/soc/nvidia/tegra/dc.h
+++ b/src/soc/nvidia/tegra/dc.h
@@ -567,7 +567,7 @@ struct disp_ctl_win {
u32 out_h; /* Height of output window in pixels */
};
-void display_startup(device_t dev);
+void display_startup(struct device *dev);
void dp_bringup(u32 winb_addr);
unsigned int fb_base_mb(void);
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c
index 00dfbb6..9cc0cf0 100644
--- a/src/soc/nvidia/tegra124/display.c
+++ b/src/soc/nvidia/tegra124/display.c
@@ -234,7 +234,7 @@ uint32_t fb_base_mb(void)
/* this is really aimed at the lcd panel. That said, there are two display
* devices on this part and we may someday want to extend it for other boards.
*/
-void display_startup(device_t dev)
+void display_startup(struct device *dev)
{
u32 val;
int i;
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c
index 8ad1aa9..5d95110 100644
--- a/src/soc/nvidia/tegra124/soc.c
+++ b/src/soc/nvidia/tegra124/soc.c
@@ -29,7 +29,7 @@
* Will break if we get 2. Sigh.
* We assume it's all multiples of MiB for MMUs sake.
*/
-static void soc_enable(device_t dev)
+static void soc_enable(struct device *dev)
{
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
@@ -39,7 +39,7 @@ static void soc_enable(device_t dev)
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
}
-static void soc_init(device_t dev)
+static void soc_init(struct device *dev)
{
display_startup(dev);
printk(BIOS_INFO, "CPU: Tegra124\n");
@@ -53,7 +53,7 @@ static struct device_operations soc_ops = {
.scan_bus = 0,
};
-static void enable_tegra124_dev(device_t dev)
+static void enable_tegra124_dev(struct device *dev)
{
dev->ops = &soc_ops;
}
diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c
index 60fa55a..639a45a 100644
--- a/src/soc/samsung/exynos5250/cpu.c
+++ b/src/soc/samsung/exynos5250/cpu.c
@@ -59,7 +59,7 @@ static void set_cpu_id(void)
* involving lots of machine and callbacks, is hard to debug and
* verify.
*/
-static void exynos_displayport_init(device_t dev, u32 lcdbase,
+static void exynos_displayport_init(struct device *dev, u32 lcdbase,
unsigned long fb_size)
{
struct soc_samsung_exynos5250_config *conf = dev->chip_info;
@@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase,
lcd_ctrl_init(fb_size, &panel, (void *)lcdbase);
}
-static void cpu_enable(device_t dev)
+static void cpu_enable(struct device *dev)
{
unsigned long fb_size = FB_SIZE_KB * KiB;
u32 lcdbase = get_fb_base_kb() * KiB;
@@ -123,7 +123,7 @@ static void cpu_enable(device_t dev)
set_cpu_id();
}
-static void cpu_init(device_t dev)
+static void cpu_init(struct device *dev)
{
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
cpu_id, get_arm_clk() / (1024*1024));
@@ -137,7 +137,7 @@ static struct device_operations cpu_ops = {
.scan_bus = 0,
};
-static void enable_exynos5250_dev(device_t dev)
+static void enable_exynos5250_dev(struct device *dev)
{
dev->ops = &cpu_ops;
}
diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c
index c904636..1f4d739 100644
--- a/src/soc/samsung/exynos5420/cpu.c
+++ b/src/soc/samsung/exynos5420/cpu.c
@@ -73,7 +73,7 @@ static void set_cpu_id(void)
* involving lots of machine and callbacks, is hard to debug and
* verify.
*/
-static void exynos_displayport_init(device_t dev, u32 lcdbase,
+static void exynos_displayport_init(struct device *dev, u32 lcdbase,
unsigned long fb_size)
{
struct soc_samsung_exynos5420_config *conf = dev->chip_info;
@@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index)
}
}
-static void cpu_enable(device_t dev)
+static void cpu_enable(struct device *dev)
{
unsigned long fb_size = FB_SIZE_KB * KiB;
u32 lcdbase = get_fb_base_kb() * KiB;
@@ -154,7 +154,7 @@ static void cpu_enable(device_t dev)
set_cpu_id();
}
-static void cpu_init(device_t dev)
+static void cpu_init(struct device *dev)
{
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
cpu_id, get_arm_clk() / 1000000);
@@ -168,7 +168,7 @@ static struct device_operations cpu_ops = {
.scan_bus = 0,
};
-static void enable_exynos5420_dev(device_t dev)
+static void enable_exynos5420_dev(struct device *dev)
{
dev->ops = &cpu_ops;
}
1
0
Patch set updated for coreboot: 334bbb8 pci_ops.{c, h}: Don't hide pointers behind typedefs
by Edward O'Callaghan 04 Nov '14
by Edward O'Callaghan 04 Nov '14
04 Nov '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7227
-gerrit
commit 334bbb8d0cc925ed881a99d46b0e9cc5b1093503
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Wed Oct 29 03:04:40 2014 +1100
pci_ops.{c,h}: Don't hide pointers behind typedefs
Change-Id: I7cf7c236f94314d7970b19063d73db788c8267e5
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/device/pci_ops.c | 28 ++++++++++++++--------------
src/include/device/pci_ops.h | 24 ++++++++++++------------
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c
index 5b633c8..6ddb493 100644
--- a/src/device/pci_ops.c
+++ b/src/device/pci_ops.c
@@ -34,7 +34,7 @@ const struct pci_bus_operations *pci_bus_default_ops(device_t dev)
#endif
}
-static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev)
+static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, struct device *dev)
{
const struct pci_bus_operations *bops;
bops = NULL;
@@ -50,7 +50,7 @@ static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t de
* The only consumer of the return value of get_pbus() is pci_bus_ops().
* pci_bus_ops() can handle being passed NULL and auto-picks working ops.
*/
-static struct bus *get_pbus(device_t dev)
+static struct bus *get_pbus(struct device *dev)
{
struct bus *pbus = NULL;
@@ -82,42 +82,42 @@ static struct bus *get_pbus(device_t dev)
return pbus;
}
-u8 pci_read_config8(device_t dev, unsigned int where)
+u8 pci_read_config8(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
-u16 pci_read_config16(device_t dev, unsigned int where)
+u16 pci_read_config16(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
-u32 pci_read_config32(device_t dev, unsigned int where)
+u32 pci_read_config32(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
-void pci_write_config8(device_t dev, unsigned int where, u8 val)
+void pci_write_config8(struct device *dev, unsigned int where, u8 val)
{
struct bus *pbus = get_pbus(dev);
pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
-void pci_write_config16(device_t dev, unsigned int where, u16 val)
+void pci_write_config16(struct device *dev, unsigned int where, u16 val)
{
struct bus *pbus = get_pbus(dev);
pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
-void pci_write_config32(device_t dev, unsigned int where, u32 val)
+void pci_write_config32(struct device *dev, unsigned int where, u32 val)
{
struct bus *pbus = get_pbus(dev);
pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary,
@@ -125,42 +125,42 @@ void pci_write_config32(device_t dev, unsigned int where, u32 val)
}
#if CONFIG_MMCONF_SUPPORT
-u8 pci_mmio_read_config8(device_t dev, unsigned int where)
+u8 pci_mmio_read_config8(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_ops_mmconf.read8(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
-u16 pci_mmio_read_config16(device_t dev, unsigned int where)
+u16 pci_mmio_read_config16(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_ops_mmconf.read16(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
-u32 pci_mmio_read_config32(device_t dev, unsigned int where)
+u32 pci_mmio_read_config32(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_ops_mmconf.read32(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
-void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val)
+void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val)
{
struct bus *pbus = get_pbus(dev);
pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn,
where, val);
}
-void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val)
+void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val)
{
struct bus *pbus = get_pbus(dev);
pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn,
where, val);
}
-void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val)
+void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val)
{
struct bus *pbus = get_pbus(dev);
pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn,
diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h
index ae58a01..920475a 100644
--- a/src/include/device/pci_ops.h
+++ b/src/include/device/pci_ops.h
@@ -6,20 +6,20 @@
#include <arch/pci_ops.h>
#ifndef __SIMPLE_DEVICE__
-u8 pci_read_config8(device_t dev, unsigned int where);
-u16 pci_read_config16(device_t dev, unsigned int where);
-u32 pci_read_config32(device_t dev, unsigned int where);
-void pci_write_config8(device_t dev, unsigned int where, u8 val);
-void pci_write_config16(device_t dev, unsigned int where, u16 val);
-void pci_write_config32(device_t dev, unsigned int where, u32 val);
+u8 pci_read_config8(struct device *dev, unsigned int where);
+u16 pci_read_config16(struct device *dev, unsigned int where);
+u32 pci_read_config32(struct device *dev, unsigned int where);
+void pci_write_config8(struct device *dev, unsigned int where, u8 val);
+void pci_write_config16(struct device *dev, unsigned int where, u16 val);
+void pci_write_config32(struct device *dev, unsigned int where, u32 val);
#if CONFIG_MMCONF_SUPPORT
-u8 pci_mmio_read_config8(device_t dev, unsigned int where);
-u16 pci_mmio_read_config16(device_t dev, unsigned int where);
-u32 pci_mmio_read_config32(device_t dev, unsigned int where);
-void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val);
-void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val);
-void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val);
+u8 pci_mmio_read_config8(struct device *dev, unsigned int where);
+u16 pci_mmio_read_config16(struct device *dev, unsigned int where);
+u32 pci_mmio_read_config32(struct device *dev, unsigned int where);
+void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val);
+void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val);
+void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val);
#endif
#endif
1
0
Patch set updated for coreboot: 2d183ab soutbridge/*/bootblock: Use pci_dev_t over device_t typedef
by Edward O'Callaghan 04 Nov '14
by Edward O'Callaghan 04 Nov '14
04 Nov '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7193
-gerrit
commit 2d183abd9efa5692a235cb6486834d4debaf31d8
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun Oct 26 10:12:15 2014 +1100
soutbridge/*/bootblock: Use pci_dev_t over device_t typedef
Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/southbridge/amd/agesa/hudson/bootblock.c | 2 +-
src/southbridge/amd/amd8111/bootblock.c | 2 +-
src/southbridge/amd/cimx/sb700/bootblock.c | 2 +-
src/southbridge/amd/cimx/sb800/bootblock.c | 6 +++---
src/southbridge/amd/cimx/sb900/bootblock.c | 2 +-
src/southbridge/amd/sb600/bootblock.c | 2 +-
src/southbridge/amd/sb700/bootblock.c | 2 +-
src/southbridge/amd/sb800/bootblock.c | 2 +-
src/southbridge/broadcom/bcm5785/bootblock.c | 2 +-
src/southbridge/intel/bd82x6x/bootblock.c | 4 ++--
src/southbridge/intel/fsp_bd82x6x/bootblock.c | 4 ++--
src/southbridge/intel/i82371eb/bootblock.c | 2 +-
src/southbridge/intel/i82801gx/bootblock.c | 2 +-
src/southbridge/intel/i82801ix/bootblock.c | 2 +-
src/southbridge/intel/lynxpoint/bootblock.c | 4 ++--
src/southbridge/nvidia/ck804/bootblock.c | 2 +-
src/southbridge/nvidia/mcp55/bootblock.c | 2 +-
src/southbridge/sis/sis966/bootblock.c | 2 +-
src/southbridge/via/vt8237r/bootblock.c | 2 +-
19 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 65810fa..3cdba8b 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -33,7 +33,7 @@
static void hudson_enable_rom(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index ba3dc43..4c00989 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -26,7 +26,7 @@
static void amd8111_enable_rom(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_8111_ISA), 0);
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 1027659..4ddfb92 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -24,7 +24,7 @@ static void sb700_enable_rom(void)
{
u32 word;
u32 dword;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 0x03);
/* SB700 LPC Bridge 0:20:3:44h.
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 4fd2739..188ba29 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -23,7 +23,7 @@ static void enable_rom(void)
{
u16 word;
u32 dword;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 0x03);
/* SB800 LPC Bridge 0:20:3:44h.
@@ -57,7 +57,7 @@ static void enable_rom(void)
static void enable_prefetch(void)
{
u32 dword;
- device_t dev = PCI_DEV(0, 0x14, 0x03);
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
/* Enable PrefetchEnSPIFromHost */
dword = pci_io_read_config32(dev, 0xb8);
@@ -67,7 +67,7 @@ static void enable_prefetch(void)
static void enable_spi_fast_mode(void)
{
u32 dword;
- device_t dev = PCI_DEV(0, 0x14, 0x03);
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
// set temp MMIO base
volatile u32 *spi_base = (void *)0xa0000000;
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index 9108a8b..561904e 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -23,7 +23,7 @@ static void sb900_enable_rom(void)
{
u32 word;
u32 dword;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 0x03);
/* SB900 LPC Bridge 0:20:3:44h.
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index e31a96c..94f5e6e 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -34,7 +34,7 @@
static void sb600_enable_rom(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SB600_LPC), 0);
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index c290806..67da3fa 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -35,7 +35,7 @@
static void sb700_enable_rom(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 9311b97..61ff284 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -33,7 +33,7 @@
static void sb800_enable_rom(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index 166464c..3c1d39c 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -26,7 +26,7 @@
static void bcm5785_enable_rom(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 85a940e..b1b53af 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
@@ -50,7 +50,7 @@ static void enable_spi_prefetch(void)
static void enable_port80_on_lpc(void)
{
- device_t dev = PCI_DEV(0, 0x1f, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
/* Enable port 80 POST on LPC */
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
index 7564442..61ff301 100644
--- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c
+++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
@@ -43,7 +43,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
@@ -55,7 +55,7 @@ static void enable_spi_prefetch(void)
static void enable_port80_on_lpc(void)
{
- device_t dev = PCI_DEV(0, 0x1f, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
/* Enable port 80 POST on LPC */
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index b350bde..67afc1c 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -26,7 +26,7 @@
static void i82371eb_enable_rom(void)
{
u16 reg16;
- device_t dev;
+ pci_devfn_t dev;
/*
* Note: The Intel 82371AB/EB/MB ISA device can be on different
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index ca0aa92..7b4cd7d 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -34,7 +34,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 80b200e..fa056a8 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -22,7 +22,7 @@
static void enable_spi_prefetch(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 9629118..40c6bb8 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
@@ -51,7 +51,7 @@ static void enable_spi_prefetch(void)
static void map_rcba(void)
{
- device_t dev = PCI_DEV(0, 0x1f, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
}
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index e2f6bc0..6e68404 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -29,7 +29,7 @@
static void ck804_enable_rom(void)
{
unsigned char byte;
- device_t addr;
+ pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
/* Locate the ck804 LPC. */
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index 431c426..807c5a0 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -29,7 +29,7 @@ static void mcp55_enable_rom(void)
{
u8 byte;
u16 word;
- device_t addr;
+ pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
#if 0
diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c
index ac4919a..dbaf127 100644
--- a/src/southbridge/sis/sis966/bootblock.c
+++ b/src/southbridge/sis/sis966/bootblock.c
@@ -30,7 +30,7 @@
static void sis966_enable_rom(void)
{
- device_t addr;
+ pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,
diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c
index 0d92073..41a224f 100644
--- a/src/southbridge/via/vt8237r/bootblock.c
+++ b/src/southbridge/via/vt8237r/bootblock.c
@@ -22,7 +22,7 @@
static void bootblock_southbridge_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* don't walk other busses, HT is not enabled */
/* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */
1
0
Patch set updated for coreboot: 75dc2d7 ARM: Use local versions of libgcc functions instead of linking against libgcc.
by Marc Jones 04 Nov '14
by Marc Jones 04 Nov '14
04 Nov '14
Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7322
-gerrit
commit 75dc2d795970a61ba1e8373315066020197ea79b
Author: Gabe Black <gabeblack(a)google.com>
Date: Tue Oct 8 18:24:10 2013 -0700
ARM: Use local versions of libgcc functions instead of linking against libgcc.
The flags used to compile libgcc may make it incompatible with the code it's
linked against, and/or the hardware it's going to run on. Rather than try to
tease the right libgcc from the compiler, lets just leave it out and use our
own implementations of the necessary functions.
Most of these implementations were taken from the Linux kernel, except for
uldivmod.S which was taken from a CL originally written for U-Boot by
Che-Liang Chiou in December of 2010. It was modified to not use the CLZ
instruction on machines that don't have it, anything earlier than ARMv5. The
top block was taken from an earlier version of the same CL which didn't use
CLZ in that spot. The later block was written from scratch.
BUG=None
TEST=Built and booted into the bootblock on nyan. Ran a series of tests which
divided and modded a 64 bit value by various 32 bit values which were powers
of 2. Confirmed that this function was used and that the returned value was
correct. Printed decimal and hex versions of some values and verified that
they equaled each other. Built and booted on pit with serial enabled.
BRANCH=None
Original-Change-Id: I7527e28af411b7aa7f94579be95a6b352a91a224
Original-Signed-off-by: Gabe Black <gabeblack(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/172401
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Original-Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402)
*** This second patch is cherry-picked and squashed again to
*** pick up the libgcc changes that were skipped previously.
arm: Move libgcc assembly macros to arch/asm.h
libgcc/macros.h contains some useful assembly macros that are common in
Linux kernel code and facilitate things such as unified ARM/THUMB
assembly. This patch moves it to a more general place where it can be
used by other code as well.
BUG=None
TEST=Snow still boots.
Original-Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182178
Original-Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org>
(cherry picked from commit a780670def94a969829811fa8cf257f12b88f085)
*** Additional changes for stage specific builds
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Change-Id: Ie3e48f34ebf6fbe20c3dd76ecbcbea7844e9466e
---
src/arch/arm/Makefile.inc | 18 +-
src/arch/arm/libgcc/Makefile.inc | 34 ++++
src/arch/arm/libgcc/ashldi3.S | 57 +++++++
src/arch/arm/libgcc/bpabi.c | 214 ++++++++++++++++++++++++
src/arch/arm/libgcc/bpabi_asm.S | 130 +++++++++++++++
src/arch/arm/libgcc/lib1funcs.S | 344 +++++++++++++++++++++++++++++++++++++++
src/arch/arm/libgcc/lshrdi3.S | 57 +++++++
src/arch/arm/libgcc/muldi3.S | 51 ++++++
src/arch/arm/libgcc/ucmpdi2.S | 51 ++++++
src/arch/arm/libgcc/uldivmod.S | 258 +++++++++++++++++++++++++++++
10 files changed, 1206 insertions(+), 8 deletions(-)
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 427e3a4..8044dba 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -2,7 +2,7 @@
##
## This file is part of the coreboot project.
##
-## Copyright (C) 2012 The ChromiumOS Authors
+## Copyright (C) 2012-2013 The ChromiumOS Authors
## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2009 Ronald G. Minnich
@@ -23,6 +23,7 @@
###############################################################################
# Take care of subdirectories
###############################################################################
+subdirs-y += libgcc/
subdirs-y += armv4/ armv7/
###############################################################################
@@ -58,13 +59,14 @@ bootblock-y += eabi_compat.c
bootblock-y += memset.S
bootblock-y += memcpy.S
bootblock-y += memmove.S
+bootblock-y += div0.c
$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD_bootblock) -m armelf_linux_eabi --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/arm/bootblock.ld
else
- $(CC_bootblock) $(CFLAGS_bootblock) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group
+ $(CC_bootblock) $(CFLAGS_bootblock) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) -Wl,--end-group
endif
endif # CONFIG_ARCH_BOOTBLOCK_ARM
@@ -89,7 +91,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm/romstage.ld $(obj)/
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD_romstage) -nostdlib -nostartfiles --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld
else
- $(CC_romstage) $(CFLAGS_romstage) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group
+ $(CC_romstage) $(CFLAGS_romstage) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group
endif
endif # CONFIG_ARCH_ROMSTAGE_ARM
@@ -111,20 +113,20 @@ ramstage-y += memcpy.S
ramstage-y += memmove.S
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
-$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions
+$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD_ramstage) -m armelf_linux_eabi --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld
else
- $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld
+ $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld
endif
-$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage)
+$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
- $(LD_ramstage) -m -m armelf_linux_eabi --gc-sections -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) --end-group
+ $(LD_ramstage) -m -m armelf_linux_eabi --gc-sections -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group
else
- $(CC_ramstage) $(CFLAGS_ramstage) $(CPPFLAGS_ramstage) -nostdlib -Wl,--gc-sections -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group
+ $(CC_ramstage) $(CFLAGS_ramstage) $(CPPFLAGS_ramstage) -nostdlib -Wl,--gc-sections -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) -Wl,--end-group
endif
endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc
new file mode 100644
index 0000000..a1d325d
--- /dev/null
+++ b/src/arch/arm/libgcc/Makefile.inc
@@ -0,0 +1,34 @@
+################################################################################
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+################################################################################
+
+libgcc_files = ashldi3.S lib1funcs.S lshrdi3.S muldi3.S ucmpdi2.S uldivmod.S
+
+ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y)
+bootblock-y += $(libgcc_files)
+endif
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
+romstage-y += $(libgcc_files)
+endif
+
+ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y)
+ramstage-y += $(libgcc_files)
+endif
diff --git a/src/arch/arm/libgcc/ashldi3.S b/src/arch/arm/libgcc/ashldi3.S
new file mode 100644
index 0000000..bf7e7e7
--- /dev/null
+++ b/src/arch/arm/libgcc/ashldi3.S
@@ -0,0 +1,57 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+ Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA. */
+
+
+#if defined __GNUC__
+
+#include <arch/asm.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+ENTRY(__ashldi3)
+ENTRY(__aeabi_llsl)
+
+ subs r3, r2, #32
+ rsb ip, r2, #32
+ movmi ah, ah, lsl r2
+ movpl ah, al, lsl r3
+ ARM( orrmi ah, ah, al, lsr ip )
+ THUMB( lsrmi r3, al, ip )
+ THUMB( orrmi ah, ah, r3 )
+ mov al, al, lsl r2
+ mov pc, lr
+
+ENDPROC(__ashldi3)
+ENDPROC(__aeabi_llsl)
+
+#endif
diff --git a/src/arch/arm/libgcc/bpabi.c b/src/arch/arm/libgcc/bpabi.c
new file mode 100644
index 0000000..8cb7ddf
--- /dev/null
+++ b/src/arch/arm/libgcc/bpabi.c
@@ -0,0 +1,214 @@
+/* Miscellaneous BPABI functions.
+
+ Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+ Contributed by CodeSourcery, LLC.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2, or (at your option) any
+ later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#if defined __GNUC__
+
+#include <stdint.h>
+
+uint64_t __udivmoddi4(uint64_t n, uint64_t d, uint64_t *rp);
+extern int64_t __divdi3(int64_t, int64_t);
+extern uint64_t __udivdi3(uint64_t, uint64_t);
+extern int64_t __gnu_ldivmod_helper(int64_t, int64_t, int64_t *);
+extern uint64_t __gnu_uldivmod_helper(uint64_t, uint64_t, uint64_t *);
+
+typedef union
+{
+ struct {
+ int32_t low;
+ int32_t high;
+ } s;
+ int64_t ll;
+} DWunion;
+
+uint64_t
+__udivmoddi4(uint64_t n, uint64_t d, uint64_t *rp)
+{
+ const DWunion nn = {.ll = n};
+ const DWunion dd = {.ll = d};
+ DWunion rr;
+ uint32_t d0, d1, n0, n1, n2;
+ uint32_t q0, q1;
+ uint32_t b, bm;
+
+ d0 = dd.s.low;
+ d1 = dd.s.high;
+ n0 = nn.s.low;
+ n1 = nn.s.high;
+
+ if (d1 == 0) {
+ if (d0 > n1) {
+ /* 0q = nn / 0D */
+ udiv_qrnnd(q0, n0, n1, n0, d0);
+ q1 = 0;
+ /* Remainder in n0. */
+ } else {
+ /* qq = NN / 0d */
+ if (d0 == 0)
+ d0 = 1 / d0; /* Divide intentionally by zero. */
+
+ udiv_qrnnd(q1, n1, 0, n1, d0);
+ udiv_qrnnd(q0, n0, n1, n0, d0);
+
+ /* Remainder in n0. */
+ }
+
+ if (rp != 0) {
+ rr.s.low = n0;
+ rr.s.high = 0;
+ *rp = rr.ll;
+ }
+ } else {
+ if (d1 > n1) {
+ /* 00 = nn / DD */
+ q0 = 0;
+ q1 = 0;
+
+ /* Remainder in n1n0. */
+ if (rp != 0) {
+ rr.s.low = n0;
+ rr.s.high = n1;
+ *rp = rr.ll;
+ }
+ } else {
+ /* 0q = NN / dd */
+
+ count_leading_zeros(bm, d1);
+ if (bm == 0) {
+ /* From (n1 >= d1) /\ (the most significant
+ bit of d1 is set), conclude (the most
+ significant bit of n1 is set) /\ (the
+ quotient digit q0 = 0 or 1).
+
+ This special case is necessary, not an
+ optimization. */
+
+ /* The condition on the next line takes
+ advantage of that n1 >= d1 (true due to
+ program flow). */
+ if (n1 > d1 || n0 >= d0) {
+ q0 = 1;
+ sub_ddmmss(n1, n0, n1, n0, d1, d0);
+ } else
+ q0 = 0;
+
+ q1 = 0;
+
+ if (rp != 0) {
+ rr.s.low = n0;
+ rr.s.high = n1;
+ *rp = rr.ll;
+ }
+ } else {
+ uint32_t m1, m0;
+ /* Normalize. */
+
+ b = 32 - bm;
+
+ d1 = (d1 << bm) | (d0 >> b);
+ d0 = d0 << bm;
+ n2 = n1 >> b;
+ n1 = (n1 << bm) | (n0 >> b);
+ n0 = n0 << bm;
+
+ udiv_qrnnd(q0, n1, n2, n1, d1);
+ umul_ppmm(m1, m0, q0, d0);
+
+ if (m1 > n1 || (m1 == n1 && m0 > n0)) {
+ q0--;
+ sub_ddmmss(m1, m0, m1, m0, d1, d0);
+ }
+
+ q1 = 0;
+
+ /* Remainder in (n1n0 - m1m0) >> bm. */
+ if (rp != 0) {
+ sub_ddmmss(n1, n0, n1, n0, m1, m0);
+ rr.s.low = (n1 << b) | (n0 >> bm);
+ rr.s.high = n1 >> bm;
+ *rp = rr.ll;
+ }
+ }
+ }
+ }
+
+ const DWunion ww = {{.low = q0, .high = q1}};
+ return ww.ll;
+}
+
+int64_t
+__divdi3(int64_t u, int64_t v)
+{
+ int32_t c = 0;
+ DWunion uu = {.ll = u};
+ DWunion vv = {.ll = v};
+ int64_t w;
+
+ if (uu.s.high < 0) {
+ c = ~c;
+ uu.ll = -uu.ll;
+ }
+ if (vv.s.high < 0) {
+ c = ~c;
+ vv.ll = -vv.ll;
+ }
+
+ w = __udivmoddi4(uu.ll, vv.ll, (uint64_t *)0);
+ if (c)
+ w = -w;
+
+ return w;
+}
+
+int64_t
+__gnu_ldivmod_helper (int64_t a, int64_t b, int64_t *remainder)
+{
+ int64_t quotient;
+
+ quotient = __divdi3(a, b);
+ *remainder = a - b * quotient;
+ return quotient;
+}
+
+uint64_t
+__udivdi3(uint64_t n, uint64_t d)
+{
+ return __udivmoddi4(n, d, (uint64_t *)0);
+}
+
+uint64_t
+__gnu_uldivmod_helper(uint64_t a, uint64_t b, uint64_t *remainder)
+{
+ uint64_t quotient;
+
+ quotient = __udivdi3(a, b);
+ *remainder = a - b * quotient;
+ return quotient;
+}
+
+#endif
diff --git a/src/arch/arm/libgcc/bpabi_asm.S b/src/arch/arm/libgcc/bpabi_asm.S
new file mode 100644
index 0000000..27b4a1c
--- /dev/null
+++ b/src/arch/arm/libgcc/bpabi_asm.S
@@ -0,0 +1,130 @@
+/* Miscellaneous BPABI functions.
+
+ Copyright (C) 2003, 2004, 2007, 2008 Free Software Foundation, Inc.
+ Contributed by CodeSourcery, LLC.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2, or (at your option) any
+ later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+
+#include <arch/asm.h>
+
+#ifdef __ARMEB__
+#define xxh r0
+#define xxl r1
+#define yyh r2
+#define yyl r3
+#else
+#define xxh r1
+#define xxl r0
+#define yyh r3
+#define yyl r2
+#endif
+
+#if defined __thumb2__
+
+.macro do_it cond
+ it \cond
+.endm
+#define do_push push
+#define do_pop pop
+
+#else
+
+.macro do_it cond
+.endm
+#define do_push stmfd sp!,
+#define do_pop ldmfd sp!,
+
+#endif
+
+ENTRY(__aeabi_lcmp)
+
+ cmp xxh, yyh
+ do_it lt
+ movlt r0, #-1
+ do_it gt
+ movgt r0, #1
+ do_it ne
+ movne pc, lr
+ subs r0, xxl, yyl
+ do_it lo
+ movlo r0, #-1
+ do_it hi
+ movhi r0, #1
+ mov pc, lr
+
+ENDPROC(__aeabi_lcmp)
+
+ENTRY(__aeabi_ulcmp)
+
+ cmp xxh, yyh
+ do_it lo
+ movlo r0, #-1
+ do_it hi
+ movhi r0, #1
+ do_it ne
+ movne pc, lr
+ cmp xxl, yyl
+ do_it lo
+ movlo r0, #-1
+ do_it hi
+ movhi r0, #1
+ do_it eq
+ moveq r0, #0
+ mov pc, lr
+
+ENDPROC(__aeabi_ulcmp)
+
+ENTRY(__aeabi_ldivmod)
+ sub sp, sp, #8
+#if defined(__thumb2__)
+ mov ip, sp
+ push {ip, lr}
+#else
+ do_push {sp, lr}
+#endif
+ bl __gnu_ldivmod_helper
+ ldr lr, [sp, #4]
+ add sp, sp, #8
+ do_pop {r2, r3}
+ mov pc, lr
+
+ENDPROC(__aeabi_ldivmod)
+
+ENTRY(__aeabi_uldivmod)
+ sub sp, sp, #8
+#if defined(__thumb2__)
+ mov ip, sp
+ push {ip, lr}
+#else
+ do_push {sp, lr}
+#endif
+ bl __gnu_uldivmod_helper
+ ldr lr, [sp, #4]
+ add sp, sp, #8
+ do_pop {r2, r3}
+ mov pc, lr
+
+ENDPROC(__aeabi_uldivmod)
diff --git a/src/arch/arm/libgcc/lib1funcs.S b/src/arch/arm/libgcc/lib1funcs.S
new file mode 100644
index 0000000..533c369
--- /dev/null
+++ b/src/arch/arm/libgcc/lib1funcs.S
@@ -0,0 +1,344 @@
+/*
+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+ *
+ * Author: Nicolas Pitre <nico(a)fluxnic.net>
+ * - contributed to gcc-3.4 on Sep 30, 2003
+ * - adapted for the Linux kernel on Oct 2, 2003
+ */
+
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+
+#if defined __GNUC__
+
+#include <arch/asm.h>
+
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __COREBOOT_ARM_ARCH__ >= 5
+
+ clz \curbit, \divisor
+ clz \result, \dividend
+ sub \result, \curbit, \result
+ mov \curbit, #1
+ mov \divisor, \divisor, lsl \result
+ mov \curbit, \curbit, lsl \result
+ mov \result, #0
+
+#else
+
+ @ Initially shift the divisor left 3 bits if possible,
+ @ set curbit accordingly. This allows for curbit to be located
+ @ at the left end of each 4 bit nibbles in the division loop
+ @ to save one loop in most cases.
+ tst \divisor, #0xe0000000
+ moveq \divisor, \divisor, lsl #3
+ moveq \curbit, #8
+ movne \curbit, #1
+
+ @ Unless the divisor is very big, shift it up in multiples of
+ @ four bits, since this is the amount of unwinding in the main
+ @ division loop. Continue shifting until the divisor is
+ @ larger than the dividend.
+1: cmp \divisor, #0x10000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #4
+ movlo \curbit, \curbit, lsl #4
+ blo 1b
+
+ @ For very big divisors, we must shift it a bit at a time, or
+ @ we will be in danger of overflowing.
+1: cmp \divisor, #0x80000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #1
+ movlo \curbit, \curbit, lsl #1
+ blo 1b
+
+ mov \result, #0
+
+#endif
+
+ @ Division loop
+1: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ orrhs \result, \result, \curbit
+ cmp \dividend, \divisor, lsr #1
+ subhs \dividend, \dividend, \divisor, lsr #1
+ orrhs \result, \result, \curbit, lsr #1
+ cmp \dividend, \divisor, lsr #2
+ subhs \dividend, \dividend, \divisor, lsr #2
+ orrhs \result, \result, \curbit, lsr #2
+ cmp \dividend, \divisor, lsr #3
+ subhs \dividend, \dividend, \divisor, lsr #3
+ orrhs \result, \result, \curbit, lsr #3
+ cmp \dividend, #0 @ Early termination?
+ movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
+ movne \divisor, \divisor, lsr #4
+ bne 1b
+
+.endm
+
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __COREBOOT_ARM_ARCH__ >= 5
+
+ clz \order, \divisor
+ rsb \order, \order, #31
+
+#else
+
+ cmp \divisor, #(1 << 16)
+ movhs \divisor, \divisor, lsr #16
+ movhs \order, #16
+ movlo \order, #0
+
+ cmp \divisor, #(1 << 8)
+ movhs \divisor, \divisor, lsr #8
+ addhs \order, \order, #8
+
+ cmp \divisor, #(1 << 4)
+ movhs \divisor, \divisor, lsr #4
+ addhs \order, \order, #4
+
+ cmp \divisor, #(1 << 2)
+ addhi \order, \order, #3
+ addls \order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __COREBOOT_ARM_ARCH__ >= 5
+
+ clz \order, \divisor
+ clz \spare, \dividend
+ sub \order, \order, \spare
+ mov \divisor, \divisor, lsl \order
+
+#else
+
+ mov \order, #0
+
+ @ Unless the divisor is very big, shift it up in multiples of
+ @ four bits, since this is the amount of unwinding in the main
+ @ division loop. Continue shifting until the divisor is
+ @ larger than the dividend.
+1: cmp \divisor, #0x10000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #4
+ addlo \order, \order, #4
+ blo 1b
+
+ @ For very big divisors, we must shift it a bit at a time, or
+ @ we will be in danger of overflowing.
+1: cmp \divisor, #0x80000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #1
+ addlo \order, \order, #1
+ blo 1b
+
+#endif
+
+ @ Perform all needed substractions to keep only the reminder.
+ @ Do comparisons in batch of 4 first.
+ subs \order, \order, #3 @ yes, 3 is intended here
+ blt 2f
+
+1: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ cmp \dividend, \divisor, lsr #1
+ subhs \dividend, \dividend, \divisor, lsr #1
+ cmp \dividend, \divisor, lsr #2
+ subhs \dividend, \dividend, \divisor, lsr #2
+ cmp \dividend, \divisor, lsr #3
+ subhs \dividend, \dividend, \divisor, lsr #3
+ cmp \dividend, #1
+ mov \divisor, \divisor, lsr #4
+ subges \order, \order, #4
+ bge 1b
+
+ tst \order, #3
+ teqne \dividend, #0
+ beq 5f
+
+ @ Either 1, 2 or 3 comparison/substractions are left.
+2: cmn \order, #2
+ blt 4f
+ beq 3f
+ cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ mov \divisor, \divisor, lsr #1
+3: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ mov \divisor, \divisor, lsr #1
+4: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+5:
+.endm
+
+
+ENTRY(__udivsi3)
+ENTRY(__aeabi_uidiv)
+
+ subs r2, r1, #1
+ moveq pc, lr
+ bcc Ldiv0
+ cmp r0, r1
+ bls 11f
+ tst r1, r2
+ beq 12f
+
+ ARM_DIV_BODY r0, r1, r2, r3
+
+ mov r0, r2
+ mov pc, lr
+
+11: moveq r0, #1
+ movne r0, #0
+ mov pc, lr
+
+12: ARM_DIV2_ORDER r1, r2
+
+ mov r0, r0, lsr r2
+ mov pc, lr
+
+ENDPROC(__udivsi3)
+ENDPROC(__aeabi_uidiv)
+
+ENTRY(__umodsi3)
+
+ subs r2, r1, #1 @ compare divisor with 1
+ bcc Ldiv0
+ cmpne r0, r1 @ compare dividend with divisor
+ moveq r0, #0
+ tsthi r1, r2 @ see if divisor is power of 2
+ andeq r0, r0, r2
+ movls pc, lr
+
+ ARM_MOD_BODY r0, r1, r2, r3
+
+ mov pc, lr
+
+ENDPROC(__umodsi3)
+
+ENTRY(__divsi3)
+ENTRY(__aeabi_idiv)
+
+ cmp r1, #0
+ eor ip, r0, r1 @ save the sign of the result.
+ beq Ldiv0
+ rsbmi r1, r1, #0 @ loops below use unsigned.
+ subs r2, r1, #1 @ division by 1 or -1 ?
+ beq 10f
+ movs r3, r0
+ rsbmi r3, r0, #0 @ positive dividend value
+ cmp r3, r1
+ bls 11f
+ tst r1, r2 @ divisor is power of 2 ?
+ beq 12f
+
+ ARM_DIV_BODY r3, r1, r0, r2
+
+ cmp ip, #0
+ rsbmi r0, r0, #0
+ mov pc, lr
+
+10: teq ip, r0 @ same sign ?
+ rsbmi r0, r0, #0
+ mov pc, lr
+
+11: movlo r0, #0
+ moveq r0, ip, asr #31
+ orreq r0, r0, #1
+ mov pc, lr
+
+12: ARM_DIV2_ORDER r1, r2
+
+ cmp ip, #0
+ mov r0, r3, lsr r2
+ rsbmi r0, r0, #0
+ mov pc, lr
+
+ENDPROC(__divsi3)
+ENDPROC(__aeabi_idiv)
+
+ENTRY(__modsi3)
+
+ cmp r1, #0
+ beq Ldiv0
+ rsbmi r1, r1, #0 @ loops below use unsigned.
+ movs ip, r0 @ preserve sign of dividend
+ rsbmi r0, r0, #0 @ if negative make positive
+ subs r2, r1, #1 @ compare divisor with 1
+ cmpne r0, r1 @ compare dividend with divisor
+ moveq r0, #0
+ tsthi r1, r2 @ see if divisor is power of 2
+ andeq r0, r0, r2
+ bls 10f
+
+ ARM_MOD_BODY r0, r1, r2, r3
+
+10: cmp ip, #0
+ rsbmi r0, r0, #0
+ mov pc, lr
+
+ENDPROC(__modsi3)
+
+ENTRY(__aeabi_uidivmod)
+
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_uidiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ mov pc, lr
+
+ENDPROC(__aeabi_uidivmod)
+
+ENTRY(__aeabi_idivmod)
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_idiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ mov pc, lr
+
+ENDPROC(__aeabi_idivmod)
+
+
+Ldiv0:
+ str lr, [sp, #-8]!
+ bl __div0
+ mov r0, #0 @ About as wrong as it could be.
+ ldr pc, [sp], #8
+ENDPROC(Ldiv0)
+
+#endif
diff --git a/src/arch/arm/libgcc/lshrdi3.S b/src/arch/arm/libgcc/lshrdi3.S
new file mode 100644
index 0000000..5a5809a
--- /dev/null
+++ b/src/arch/arm/libgcc/lshrdi3.S
@@ -0,0 +1,57 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+ Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA. */
+
+
+#if defined __GNUC__
+
+#include <arch/asm.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+ENTRY(__lshrdi3)
+ENTRY(__aeabi_llsr)
+
+ subs r3, r2, #32
+ rsb ip, r2, #32
+ movmi al, al, lsr r2
+ movpl al, ah, lsr r3
+ ARM( orrmi al, al, ah, lsl ip )
+ THUMB( lslmi r3, ah, ip )
+ THUMB( orrmi al, al, r3 )
+ mov ah, ah, lsr r2
+ mov pc, lr
+
+ENDPROC(__lshrdi3)
+ENDPROC(__aeabi_llsr)
+
+#endif
diff --git a/src/arch/arm/libgcc/muldi3.S b/src/arch/arm/libgcc/muldi3.S
new file mode 100644
index 0000000..f6a40a8
--- /dev/null
+++ b/src/arch/arm/libgcc/muldi3.S
@@ -0,0 +1,51 @@
+/*
+ * linux/arch/arm/lib/muldi3.S
+ *
+ * Author: Nicolas Pitre
+ * Created: Oct 19, 2005
+ * Copyright: Monta Vista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#if defined __GNUC__
+
+#include <arch/asm.h>
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+ENTRY(__muldi3)
+ENTRY(__aeabi_lmul)
+
+ mul xh, yl, xh
+ mla xh, xl, yh, xh
+ mov ip, xl, lsr #16
+ mov yh, yl, lsr #16
+ bic xl, xl, ip, lsl #16
+ bic yl, yl, yh, lsl #16
+ mla xh, yh, ip, xh
+ mul yh, xl, yh
+ mul xl, yl, xl
+ mul ip, yl, ip
+ adds xl, xl, yh, lsl #16
+ adc xh, xh, yh, lsr #16
+ adds xl, xl, ip, lsl #16
+ adc xh, xh, ip, lsr #16
+ mov pc, lr
+
+ENDPROC(__muldi3)
+ENDPROC(__aeabi_lmul)
+
+#endif
diff --git a/src/arch/arm/libgcc/ucmpdi2.S b/src/arch/arm/libgcc/ucmpdi2.S
new file mode 100644
index 0000000..01ce1b5
--- /dev/null
+++ b/src/arch/arm/libgcc/ucmpdi2.S
@@ -0,0 +1,51 @@
+/*
+ * linux/arch/arm/lib/ucmpdi2.S
+ *
+ * Author: Nicolas Pitre
+ * Created: Oct 19, 2005
+ * Copyright: Monta Vista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#if defined __GNUC__
+
+#include <arch/asm.h>
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+ENTRY(__ucmpdi2)
+
+ cmp xh, yh
+ cmpeq xl, yl
+ movlo r0, #0
+ moveq r0, #1
+ movhi r0, #2
+ mov pc, lr
+
+ENDPROC(__ucmpdi2)
+
+ENTRY(__aeabi_ulcmp)
+
+ cmp xh, yh
+ cmpeq xl, yl
+ movlo r0, #-1
+ moveq r0, #0
+ movhi r0, #1
+ mov pc, lr
+
+ENDPROC(__aeabi_ulcmp)
+
+#endif
diff --git a/src/arch/arm/libgcc/uldivmod.S b/src/arch/arm/libgcc/uldivmod.S
new file mode 100644
index 0000000..ac267d0
--- /dev/null
+++ b/src/arch/arm/libgcc/uldivmod.S
@@ -0,0 +1,258 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#include <arch/asm.h>
+
+/*
+ * A, Q = r0 + (r1 << 32)
+ * B, R = r2 + (r3 << 32)
+ * A / B = Q ... R
+ */
+
+A_0 .req r0
+A_1 .req r1
+B_0 .req r2
+B_1 .req r3
+C_0 .req r4
+C_1 .req r5
+D_0 .req r6
+D_1 .req r7
+
+Q_0 .req r0
+Q_1 .req r1
+R_0 .req r2
+R_1 .req r3
+
+ENTRY(__aeabi_uldivmod)
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ @ Test if B == 0
+ orrs ip, B_0, B_1 @ Z set -> B == 0
+ beq L_div_by_0
+ @ Test if B is power of 2: (B & (B - 1)) == 0
+ subs C_0, B_0, #1
+ sbc C_1, B_1, #0
+ tst C_0, B_0
+ tsteq B_1, C_1
+ beq L_pow2
+ @ Test if A_1 == B_1 == 0
+ orrs ip, A_1, B_1
+ beq L_div_32_32
+
+L_div_64_64:
+/* CLZ only exists in ARM architecture version 5 and above. */
+#if __COREBOOT_ARM_ARCH__ >= 5
+ mov C_0, #1
+ mov C_1, #0
+ @ D_0 = clz A
+ teq A_1, #0
+ clz D_0, A_1
+ clzeq ip, A_0
+ addeq D_0, D_0, ip
+ @ D_1 = clz B
+ teq B_1, #0
+ clz D_1, B_1
+ clzeq ip, B_0
+ addeq D_1, D_1, ip
+ @ if clz B - clz A > 0
+ subs D_0, D_1, D_0
+ bls L_done_shift
+ @ B <<= (clz B - clz A)
+ subs D_1, D_0, #32
+ rsb ip, D_0, #32
+ movmi B_1, B_1, lsl D_0
+ orrmi B_1, B_1, B_0, lsr ip
+ movpl B_1, B_0, lsl D_1
+ mov B_0, B_0, lsl D_0
+ @ C = 1 << (clz B - clz A)
+ movmi C_1, C_1, lsl D_0
+ orrmi C_1, C_1, C_0, lsr ip
+ movpl C_1, C_0, lsl D_1
+ mov C_0, C_0, lsl D_0
+L_done_shift:
+ mov D_0, #0
+ mov D_1, #0
+ @ C: current bit; D: result
+#else
+ @ C: current bit; D: result
+ mov C_0, #1
+ mov C_1, #0
+ mov D_0, #0
+ mov D_1, #0
+L_lsl_4:
+ cmp B_1, #0x10000000
+ cmpcc B_1, A_1
+ cmpeq B_0, A_0
+ bcs L_lsl_1
+ @ B <<= 4
+ mov B_1, B_1, lsl #4
+ orr B_1, B_1, B_0, lsr #28
+ mov B_0, B_0, lsl #4
+ @ C <<= 4
+ mov C_1, C_1, lsl #4
+ orr C_1, C_1, C_0, lsr #28
+ mov C_0, C_0, lsl #4
+ b L_lsl_4
+L_lsl_1:
+ cmp B_1, #0x80000000
+ cmpcc B_1, A_1
+ cmpeq B_0, A_0
+ bcs L_subtract
+ @ B <<= 1
+ mov B_1, B_1, lsl #1
+ orr B_1, B_1, B_0, lsr #31
+ mov B_0, B_0, lsl #1
+ @ C <<= 1
+ mov C_1, C_1, lsl #1
+ orr C_1, C_1, C_0, lsr #31
+ mov C_0, C_0, lsl #1
+ b L_lsl_1
+#endif
+L_subtract:
+ @ if A >= B
+ cmp A_1, B_1
+ cmpeq A_0, B_0
+ bcc L_update
+ @ A -= B
+ subs A_0, A_0, B_0
+ sbc A_1, A_1, B_1
+ @ D |= C
+ orr D_0, D_0, C_0
+ orr D_1, D_1, C_1
+L_update:
+ @ if A == 0: break
+ orrs ip, A_1, A_0
+ beq L_exit
+ @ C >>= 1
+ movs C_1, C_1, lsr #1
+ movs C_0, C_0, rrx
+ @ if C == 0: break
+ orrs ip, C_1, C_0
+ beq L_exit
+ @ B >>= 1
+ movs B_1, B_1, lsr #1
+ mov B_0, B_0, rrx
+ b L_subtract
+L_exit:
+ @ Note: A, B & Q, R are aliases
+ mov R_0, A_0
+ mov R_1, A_1
+ mov Q_0, D_0
+ mov Q_1, D_1
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+
+L_div_32_32:
+ @ Note: A_0 & r0 are aliases
+ @ Q_1 r1
+ mov r1, B_0
+ bl __aeabi_uidivmod
+ mov R_0, r1
+ mov R_1, #0
+ mov Q_1, #0
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+
+L_pow2:
+/* CLZ only exists in ARM architecture version 5 and above. */
+#if __COREBOOT_ARM_ARCH__ >= 5
+ @ Note: A, B and Q, R are aliases
+ @ R = A & (B - 1)
+ and C_0, A_0, C_0
+ and C_1, A_1, C_1
+ @ Q = A >> log2(B)
+ @ Note: B must not be 0 here!
+ clz D_0, B_0
+ add D_1, D_0, #1
+ rsbs D_0, D_0, #31
+ bpl L_1
+ clz D_0, B_1
+ rsb D_0, D_0, #31
+ mov A_0, A_1, lsr D_0
+ add D_0, D_0, #32
+L_1:
+ movpl A_0, A_0, lsr D_0
+ orrpl A_0, A_0, A_1, lsl D_1
+ mov A_1, A_1, lsr D_0
+ @ Mov back C to R
+ mov R_0, C_0
+ mov R_1, C_1
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+#else
+ @ Note: A, B and Q, R are aliases
+ @ R = A & (B - 1)
+ and C_0, A_0, C_0
+ and C_1, A_1, C_1
+ @ Q = A >> log2(B)
+ @ Note: B must not be 0 here!
+ @ Count the leading zeroes in B.
+ mov D_0, #0
+ orrs B_0, B_0, B_0
+ @ If B is greater than 1 << 31, divide A and B by 1 << 32.
+ moveq A_0, A_1
+ moveq A_1, #0
+ moveq B_0, B_1
+ @ Count the remaining leading zeroes in B.
+ movs B_1, B_0, lsl #16
+ addeq D_0, #16
+ moveq B_0, B_0, lsr #16
+ tst B_0, #0xff
+ addeq D_0, #8
+ moveq B_0, B_0, lsr #8
+ tst B_0, #0xf
+ addeq D_0, #4
+ moveq B_0, B_0, lsr #4
+ tst B_0, #0x3
+ addeq D_0, #2
+ moveq B_0, B_0, lsr #2
+ tst B_0, #0x1
+ addeq D_0, #1
+ @ Shift A to the right by the appropriate amount.
+ rsb D_1, D_0, #32
+ mov Q_0, A_0, lsr D_0
+ orr Q_0, A_1, lsl D_1
+ mov Q_1, A_1, lsr D_0
+ @ Move C to R
+ mov R_0, C_0
+ mov R_1, C_1
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+#endif
+
+L_div_by_0:
+ bl __div0
+ @ As wrong as it could be
+ mov Q_0, #0
+ mov Q_1, #0
+ mov R_0, #0
+ mov R_1, #0
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+ENDPROC(__aeabi_uldivmod)
1
0
04 Nov '14
Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6930
-gerrit
commit b9867d5ea82622136b0e20b3d5864381e54fd354
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Jan 13 13:24:30 2014 -0800
arm: Thumb ALL the things!
This patch switches every last part of Coreboot on ARM over to Thumb
mode: libpayload, the internal libgcc, and assorted assembly files. In
combination with the respective depthcharge patch, this will switch to
Thumb mode right after the entry point of the bootblock and not switch
back to ARM until the final assembly stub that jumps to the kernel.
The required changes to make this work include some new headers and
Makefile flags to handle assembly files (using the unified syntax and
the same helper macros as Linux), modifying our custom-written libgcc
code for 64-bit division to support Thumb (removing some stale old files
that were never really used for clarity), and flipping the general
CFLAGS to Thumb (some more cleanup there as well while I'm at it).
BUG=None
TEST=Snow and Nyan still boot.
Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182212
Original-Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a)
Conflicts:
payloads/libpayload/include/arm/arch/asm.h
src/arch/arm/Makefile.inc
src/arch/arm/armv7/Makefile.inc
*** There is an issue with what to do with ramstage-S-ccopts, and
*** will need to be covered in additional ARM cleanup patches.
Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
---
payloads/libpayload/arch/arm/Makefile.inc | 7 +-
payloads/libpayload/include/arm/arch/asm.h | 13 +-
src/arch/arm/Makefile.inc | 10 +-
src/arch/arm/armv7/Makefile.inc | 8 +-
src/arch/arm/armv7/bootblock.S | 23 ++--
src/arch/arm/include/arch/asm.h | 19 ++-
src/arch/arm/libgcc/bpabi.c | 214 -----------------------------
src/arch/arm/libgcc/bpabi_asm.S | 130 ------------------
src/arch/arm/libgcc/uldivmod.S | 28 ++--
src/soc/nvidia/tegra124/maincpu.S | 10 +-
10 files changed, 71 insertions(+), 391 deletions(-)
diff --git a/payloads/libpayload/arch/arm/Makefile.inc b/payloads/libpayload/arch/arm/Makefile.inc
index 0078ffe..2f8da15 100644
--- a/payloads/libpayload/arch/arm/Makefile.inc
+++ b/payloads/libpayload/arch/arm/Makefile.inc
@@ -27,7 +27,8 @@
## SUCH DAMAGE.
##
-CFLAGS += -mfloat-abi=hard -marm -mabi=aapcs-linux -march=armv7-a
+CFLAGS += -mthumb -march=armv7-a
+arm_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
head.o-y += head.S
libc-y += main.c sysinfo.c
@@ -37,3 +38,7 @@ libc-y += memcpy.S memset.S memmove.S
libc-y += exception_asm.S exception.c
libc-y += cache.c cpu.S
libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c
+
+# Add other classes here when you put assembly files into them!
+head.o-S-ccopts += $(arm_asm_flags)
+libc-S-ccopts += $(arm_asm_flags)
diff --git a/payloads/libpayload/include/arm/arch/asm.h b/payloads/libpayload/include/arm/arch/asm.h
index 2f88599..80b50d3 100644
--- a/payloads/libpayload/include/arm/arch/asm.h
+++ b/payloads/libpayload/include/arm/arch/asm.h
@@ -20,16 +20,17 @@
#ifndef __ARM_ASM_H
#define __ARM_ASM_H
-#if defined __arm__
-# define ARM(x...) x
-# define THUMB(x...)
-# define W(instr) instr
-#elif defined __thumb__
+/* __arm__ is defined regardless of Thumb mode, so need to order this right */
+#if defined __thumb2__
# define ARM(x...)
# define THUMB(x...) x
# define W(instr) instr.w
+#elif defined __thumb__
+# error You are not compiling Thumb2, this won't work!
#else
-# error Not in ARM or thumb mode!
+# define ARM(x...) x
+# define THUMB(x...)
+# define W(instr) instr
#endif
#define ALIGN .align 0
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 8044dba..95e16b5 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -66,7 +66,7 @@ $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(boo
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD_bootblock) -m armelf_linux_eabi --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/arm/bootblock.ld
else
- $(CC_bootblock) $(CFLAGS_bootblock) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) -Wl,--end-group
+ $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) -Wl,--end-group
endif
endif # CONFIG_ARCH_BOOTBLOCK_ARM
@@ -89,9 +89,9 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
$(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm/romstage.ld $(obj)/ldoptions
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
- $(LD_romstage) -nostdlib -nostartfiles --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld
+ $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld
else
- $(CC_romstage) $(CFLAGS_romstage) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group
+ $(CC_romstage) $(CFLAGS_romstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group
endif
endif # CONFIG_ARCH_ROMSTAGE_ARM
@@ -116,7 +116,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
- $(LD_ramstage) -m armelf_linux_eabi --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld
+ $(LD_ramstage) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld
else
$(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld
endif
@@ -124,7 +124,7 @@ endif
$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
- $(LD_ramstage) -m -m armelf_linux_eabi --gc-sections -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group
+ $(LD_ramstage) -nostdlib -m armelf_linux_eabi --gc-sections -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group
else
$(CC_ramstage) $(CFLAGS_ramstage) $(CPPFLAGS_ramstage) -nostdlib -Wl,--gc-sections -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) -Wl,--end-group
endif
diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc
index c46fb39..08f8e9b 100644
--- a/src/arch/arm/armv7/Makefile.inc
+++ b/src/arch/arm/armv7/Makefile.inc
@@ -19,8 +19,10 @@
##
###############################################################################
-armv7_flags = -march=armv7-a -mthumb -mthumb-interwork \
+armv7_flags = -march=armv7-a -mthumb \
-I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7
+armv7_asm_flags = $(armv7_flags) -Wa,-mthumb -Wa,-mimplicit-it=always \
+ -Wa,-mno-warn-deprecated
###############################################################################
# bootblock
@@ -58,6 +60,7 @@ romstage-y += mmu.c
CFLAGS_romstage += $(armv7_flags)
CPPFLAGS_romstage += $(armv7_flags)
+romstage-S-ccopts += $(armv7_asm_flags)
endif # CONFIG_ARCH_ROMSTAGE_ARMV7
@@ -74,6 +77,7 @@ ramstage-y += exception_asm.S
ramstage-y += mmu.c
CFLAGS_ramstage += $(armv7_flags)
-CPPFLAGS_ramstage += $(armv7_flags)
+CPPFLAGS_ramstage += $(armv7_asm_flags)
+ramstage-S-ccopts += $(armv7_asm_flags)
endif # CONFIG_ARCH_RAMSTAGE_ARMV7
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index a8d0973..4258caf 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -32,6 +32,7 @@
#include <arch/asm.h>
.section ".start", "a", %progbits
+.arm
ENTRY(_start)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
@@ -40,7 +41,11 @@ ENTRY(_start)
* causes it.
*/
msr cpsr_cxf, #0xdf
+ bl _thumb_start
+ENDPROC(_start)
+.thumb
+ENTRY(_thumb_start)
/*
* From Cortex-A Series Programmer's Guide:
* Only CPU 0 performs initialization. Other CPUs go into WFI
@@ -72,25 +77,17 @@ call_bootblock:
ldr sp, .Stack /* Set up stack pointer */
ldr r0,=0x00000000
/*
- * The current design of cpu_info places the
- * struct at the top of the stack. The number of
- * words pushed must be at least as large as that
- * struct.
+ * The current design of cpu_info places the struct at the top of the
+ * stack. Free enough space to accomodate for that, but make sure it's
+ * 8-byte aligned for ABI compliance.
*/
- push {r0-r2}
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- /*
- * Use "bl" instead of "b" even though we do not intend to return.
- * "bl" gets compiled to "blx" if we're transitioning from ARM to
- * Thumb. However, "b" will not and GCC may attempt to create a
- * wrapper which is currently broken.
- */
+ sub sp, sp, #16
bl main
wait_for_interrupt:
wfi
mov pc, lr @ back to my caller
-ENDPROC(_start)
+ENDPROC(_thumb_start)
/* we do it this way because it's a 32-bit constant and
* in some cases too far away to be loaded as just an offset
diff --git a/src/arch/arm/include/arch/asm.h b/src/arch/arm/include/arch/asm.h
index 5f3e55f..a57ce4d 100644
--- a/src/arch/arm/include/arch/asm.h
+++ b/src/arch/arm/include/arch/asm.h
@@ -20,19 +20,20 @@
#ifndef __ARM_ASM_H
#define __ARM_ASM_H
-#if defined __arm__
-# define ARM(x...) x
-# define THUMB(x...)
-# define W(instr) instr
-#elif defined __thumb__
+/* __arm__ is defined regardless of Thumb mode, so need to order this right */
+#if defined __thumb2__
# define ARM(x...)
# define THUMB(x...) x
# define W(instr) instr.w
# if __COREBOOT_ARM_ARCH__ < 7
# error thumb mode has not been tested with ARM < v7!
# endif
+#elif defined __thumb__
+# error You are not compiling Thumb2, this won't work!
#else
-# error Not in ARM or thumb mode!
+# define ARM(x...) x
+# define THUMB(x...)
+# define W(instr) instr
#endif
#define ALIGN .align 0
@@ -49,4 +50,10 @@
#define END(name) \
.size name, .-name
+/* Everything should go into the text section by default. */
+ .text
+
+/* Thumb code uses the (new) unified assembly syntax. */
+THUMB( .syntax unified )
+
#endif /* __ARM_ASM_H */
diff --git a/src/arch/arm/libgcc/bpabi.c b/src/arch/arm/libgcc/bpabi.c
deleted file mode 100644
index 8cb7ddf..0000000
--- a/src/arch/arm/libgcc/bpabi.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/* Miscellaneous BPABI functions.
-
- Copyright (C) 2003, 2004 Free Software Foundation, Inc.
- Contributed by CodeSourcery, LLC.
-
- This file is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the
- Free Software Foundation; either version 2, or (at your option) any
- later version.
-
- In addition to the permissions in the GNU General Public License, the
- Free Software Foundation gives you unlimited permission to link the
- compiled version of this file into combinations with other programs,
- and to distribute those combinations without any restriction coming
- from the use of this file. (The General Public License restrictions
- do apply in other respects; for example, they cover modification of
- the file, and distribution when not linked into a combine
- executable.)
-
- This file is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
-
-#if defined __GNUC__
-
-#include <stdint.h>
-
-uint64_t __udivmoddi4(uint64_t n, uint64_t d, uint64_t *rp);
-extern int64_t __divdi3(int64_t, int64_t);
-extern uint64_t __udivdi3(uint64_t, uint64_t);
-extern int64_t __gnu_ldivmod_helper(int64_t, int64_t, int64_t *);
-extern uint64_t __gnu_uldivmod_helper(uint64_t, uint64_t, uint64_t *);
-
-typedef union
-{
- struct {
- int32_t low;
- int32_t high;
- } s;
- int64_t ll;
-} DWunion;
-
-uint64_t
-__udivmoddi4(uint64_t n, uint64_t d, uint64_t *rp)
-{
- const DWunion nn = {.ll = n};
- const DWunion dd = {.ll = d};
- DWunion rr;
- uint32_t d0, d1, n0, n1, n2;
- uint32_t q0, q1;
- uint32_t b, bm;
-
- d0 = dd.s.low;
- d1 = dd.s.high;
- n0 = nn.s.low;
- n1 = nn.s.high;
-
- if (d1 == 0) {
- if (d0 > n1) {
- /* 0q = nn / 0D */
- udiv_qrnnd(q0, n0, n1, n0, d0);
- q1 = 0;
- /* Remainder in n0. */
- } else {
- /* qq = NN / 0d */
- if (d0 == 0)
- d0 = 1 / d0; /* Divide intentionally by zero. */
-
- udiv_qrnnd(q1, n1, 0, n1, d0);
- udiv_qrnnd(q0, n0, n1, n0, d0);
-
- /* Remainder in n0. */
- }
-
- if (rp != 0) {
- rr.s.low = n0;
- rr.s.high = 0;
- *rp = rr.ll;
- }
- } else {
- if (d1 > n1) {
- /* 00 = nn / DD */
- q0 = 0;
- q1 = 0;
-
- /* Remainder in n1n0. */
- if (rp != 0) {
- rr.s.low = n0;
- rr.s.high = n1;
- *rp = rr.ll;
- }
- } else {
- /* 0q = NN / dd */
-
- count_leading_zeros(bm, d1);
- if (bm == 0) {
- /* From (n1 >= d1) /\ (the most significant
- bit of d1 is set), conclude (the most
- significant bit of n1 is set) /\ (the
- quotient digit q0 = 0 or 1).
-
- This special case is necessary, not an
- optimization. */
-
- /* The condition on the next line takes
- advantage of that n1 >= d1 (true due to
- program flow). */
- if (n1 > d1 || n0 >= d0) {
- q0 = 1;
- sub_ddmmss(n1, n0, n1, n0, d1, d0);
- } else
- q0 = 0;
-
- q1 = 0;
-
- if (rp != 0) {
- rr.s.low = n0;
- rr.s.high = n1;
- *rp = rr.ll;
- }
- } else {
- uint32_t m1, m0;
- /* Normalize. */
-
- b = 32 - bm;
-
- d1 = (d1 << bm) | (d0 >> b);
- d0 = d0 << bm;
- n2 = n1 >> b;
- n1 = (n1 << bm) | (n0 >> b);
- n0 = n0 << bm;
-
- udiv_qrnnd(q0, n1, n2, n1, d1);
- umul_ppmm(m1, m0, q0, d0);
-
- if (m1 > n1 || (m1 == n1 && m0 > n0)) {
- q0--;
- sub_ddmmss(m1, m0, m1, m0, d1, d0);
- }
-
- q1 = 0;
-
- /* Remainder in (n1n0 - m1m0) >> bm. */
- if (rp != 0) {
- sub_ddmmss(n1, n0, n1, n0, m1, m0);
- rr.s.low = (n1 << b) | (n0 >> bm);
- rr.s.high = n1 >> bm;
- *rp = rr.ll;
- }
- }
- }
- }
-
- const DWunion ww = {{.low = q0, .high = q1}};
- return ww.ll;
-}
-
-int64_t
-__divdi3(int64_t u, int64_t v)
-{
- int32_t c = 0;
- DWunion uu = {.ll = u};
- DWunion vv = {.ll = v};
- int64_t w;
-
- if (uu.s.high < 0) {
- c = ~c;
- uu.ll = -uu.ll;
- }
- if (vv.s.high < 0) {
- c = ~c;
- vv.ll = -vv.ll;
- }
-
- w = __udivmoddi4(uu.ll, vv.ll, (uint64_t *)0);
- if (c)
- w = -w;
-
- return w;
-}
-
-int64_t
-__gnu_ldivmod_helper (int64_t a, int64_t b, int64_t *remainder)
-{
- int64_t quotient;
-
- quotient = __divdi3(a, b);
- *remainder = a - b * quotient;
- return quotient;
-}
-
-uint64_t
-__udivdi3(uint64_t n, uint64_t d)
-{
- return __udivmoddi4(n, d, (uint64_t *)0);
-}
-
-uint64_t
-__gnu_uldivmod_helper(uint64_t a, uint64_t b, uint64_t *remainder)
-{
- uint64_t quotient;
-
- quotient = __udivdi3(a, b);
- *remainder = a - b * quotient;
- return quotient;
-}
-
-#endif
diff --git a/src/arch/arm/libgcc/bpabi_asm.S b/src/arch/arm/libgcc/bpabi_asm.S
deleted file mode 100644
index 27b4a1c..0000000
--- a/src/arch/arm/libgcc/bpabi_asm.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Miscellaneous BPABI functions.
-
- Copyright (C) 2003, 2004, 2007, 2008 Free Software Foundation, Inc.
- Contributed by CodeSourcery, LLC.
-
- This file is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the
- Free Software Foundation; either version 2, or (at your option) any
- later version.
-
- In addition to the permissions in the GNU General Public License, the
- Free Software Foundation gives you unlimited permission to link the
- compiled version of this file into combinations with other programs,
- and to distribute those combinations without any restriction coming
- from the use of this file. (The General Public License restrictions
- do apply in other respects; for example, they cover modification of
- the file, and distribution when not linked into a combine
- executable.)
-
- This file is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
-
-
-#include <arch/asm.h>
-
-#ifdef __ARMEB__
-#define xxh r0
-#define xxl r1
-#define yyh r2
-#define yyl r3
-#else
-#define xxh r1
-#define xxl r0
-#define yyh r3
-#define yyl r2
-#endif
-
-#if defined __thumb2__
-
-.macro do_it cond
- it \cond
-.endm
-#define do_push push
-#define do_pop pop
-
-#else
-
-.macro do_it cond
-.endm
-#define do_push stmfd sp!,
-#define do_pop ldmfd sp!,
-
-#endif
-
-ENTRY(__aeabi_lcmp)
-
- cmp xxh, yyh
- do_it lt
- movlt r0, #-1
- do_it gt
- movgt r0, #1
- do_it ne
- movne pc, lr
- subs r0, xxl, yyl
- do_it lo
- movlo r0, #-1
- do_it hi
- movhi r0, #1
- mov pc, lr
-
-ENDPROC(__aeabi_lcmp)
-
-ENTRY(__aeabi_ulcmp)
-
- cmp xxh, yyh
- do_it lo
- movlo r0, #-1
- do_it hi
- movhi r0, #1
- do_it ne
- movne pc, lr
- cmp xxl, yyl
- do_it lo
- movlo r0, #-1
- do_it hi
- movhi r0, #1
- do_it eq
- moveq r0, #0
- mov pc, lr
-
-ENDPROC(__aeabi_ulcmp)
-
-ENTRY(__aeabi_ldivmod)
- sub sp, sp, #8
-#if defined(__thumb2__)
- mov ip, sp
- push {ip, lr}
-#else
- do_push {sp, lr}
-#endif
- bl __gnu_ldivmod_helper
- ldr lr, [sp, #4]
- add sp, sp, #8
- do_pop {r2, r3}
- mov pc, lr
-
-ENDPROC(__aeabi_ldivmod)
-
-ENTRY(__aeabi_uldivmod)
- sub sp, sp, #8
-#if defined(__thumb2__)
- mov ip, sp
- push {ip, lr}
-#else
- do_push {sp, lr}
-#endif
- bl __gnu_uldivmod_helper
- ldr lr, [sp, #4]
- add sp, sp, #8
- do_pop {r2, r3}
- mov pc, lr
-
-ENDPROC(__aeabi_uldivmod)
diff --git a/src/arch/arm/libgcc/uldivmod.S b/src/arch/arm/libgcc/uldivmod.S
index ac267d0..521a5d1 100644
--- a/src/arch/arm/libgcc/uldivmod.S
+++ b/src/arch/arm/libgcc/uldivmod.S
@@ -55,8 +55,12 @@ Q_1 .req r1
R_0 .req r2
R_1 .req r3
+THUMB(
+TMP .req r8
+)
+
ENTRY(__aeabi_uldivmod)
- stmfd sp!, {r4, r5, r6, r7, lr}
+ stmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
@ Test if B == 0
orrs ip, B_0, B_1 @ Z set -> B == 0
beq L_div_by_0
@@ -92,12 +96,16 @@ L_div_64_64:
subs D_1, D_0, #32
rsb ip, D_0, #32
movmi B_1, B_1, lsl D_0
- orrmi B_1, B_1, B_0, lsr ip
+ARM( orrmi B_1, B_1, B_0, lsr ip )
+THUMB( lsrmi TMP, B_0, ip )
+THUMB( orrmi B_1, B_1, TMP )
movpl B_1, B_0, lsl D_1
mov B_0, B_0, lsl D_0
@ C = 1 << (clz B - clz A)
movmi C_1, C_1, lsl D_0
- orrmi C_1, C_1, C_0, lsr ip
+ARM( orrmi C_1, C_1, C_0, lsr ip )
+THUMB( lsrmi TMP, C_0, ip )
+THUMB( orrmi C_1, C_1, TMP )
movpl C_1, C_0, lsl D_1
mov C_0, C_0, lsl D_0
L_done_shift:
@@ -170,7 +178,7 @@ L_exit:
mov R_1, A_1
mov Q_0, D_0
mov Q_1, D_1
- ldmfd sp!, {r4, r5, r6, r7, pc}
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
L_div_32_32:
@ Note: A_0 & r0 are aliases
@@ -180,7 +188,7 @@ L_div_32_32:
mov R_0, r1
mov R_1, #0
mov Q_1, #0
- ldmfd sp!, {r4, r5, r6, r7, pc}
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
L_pow2:
/* CLZ only exists in ARM architecture version 5 and above. */
@@ -201,12 +209,14 @@ L_pow2:
add D_0, D_0, #32
L_1:
movpl A_0, A_0, lsr D_0
- orrpl A_0, A_0, A_1, lsl D_1
+ARM( orrpl A_0, A_0, A_1, lsl D_1 )
+THUMB( lslpl TMP, A_1, D_1 )
+THUMB( orrpl A_0, A_0, TMP )
mov A_1, A_1, lsr D_0
@ Mov back C to R
mov R_0, C_0
mov R_1, C_1
- ldmfd sp!, {r4, r5, r6, r7, pc}
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
#else
@ Note: A, B and Q, R are aliases
@ R = A & (B - 1)
@@ -244,7 +254,7 @@ L_1:
@ Move C to R
mov R_0, C_0
mov R_1, C_1
- ldmfd sp!, {r4, r5, r6, r7, pc}
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
#endif
L_div_by_0:
@@ -254,5 +264,5 @@ L_div_by_0:
mov Q_1, #0
mov R_0, #0
mov R_1, #0
- ldmfd sp!, {r4, r5, r6, r7, pc}
+ ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
ENDPROC(__aeabi_uldivmod)
diff --git a/src/soc/nvidia/tegra124/maincpu.S b/src/soc/nvidia/tegra124/maincpu.S
index 7b217d8..91981ac 100644
--- a/src/soc/nvidia/tegra124/maincpu.S
+++ b/src/soc/nvidia/tegra124/maincpu.S
@@ -27,8 +27,9 @@
* SUCH DAMAGE.
*/
+#include <arch/asm.h>
+
.align 2
- .arm
.global maincpu_stack_pointer
maincpu_stack_pointer:
@@ -38,10 +39,8 @@ maincpu_stack_pointer:
maincpu_entry_point:
.word 0
- .global maincpu_setup
- .type maincpu_setup, function
- maincpu_setup:
-
+.arm
+ENTRY(maincpu_setup)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
@@ -54,3 +53,4 @@ maincpu_entry_point:
eor lr, lr
ldr r0, maincpu_entry_point
bx r0
+ENDPROC(maincpu_setup)
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