coreboot-gerrit November 2014

coreboot-gerrit@coreboot.org

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1441 discussions

Patch merged into coreboot/master: 3ec9c95 Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'
by gerrit＠coreboot.org 05 Nov '14

05 Nov '14

the following patch was just integrated into master: commit 3ec9c95d02e8c67fb05ad580b5ca7a1fd14d2b02 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:36:02 2014 +1100 Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c' Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7196 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/7196 for details. -gerrit

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New patch to review for filo: 7749f0a filo: Fix xcompile script to use reference toolchain
by Dennis Wassenberg 05 Nov '14

05 Nov '14

Dennis Wassenberg (dennis.wassenberg(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7340 -gerrit commit 7749f0a1fc1476c01527d601d6d7040017dbc805 Author: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> Date: Wed Nov 5 14:41:42 2014 +0100 filo: Fix xcompile script to use reference toolchain Corrected the directory where the xcompile script searches for the reference toolchain. Signed-off-by: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> Change-Id: Ic5d4e3f6c8c8d8669be42586716e9adcddca8e8c --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 7c1adf3..0f17444 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -41,7 +41,7 @@ touch $TMPFILE # This should be a loop over all supported architectures TARCH=i386 TWIDTH=32 -for gccprefixes in `pwd`/../../util/crossgcc/xgcc/bin/${TARCH}-elf- ${TARCH}-elf- ""; do +for gccprefixes in `pwd`/../../../../util/crossgcc/xgcc/bin/${TARCH}-elf- ${TARCH}-elf- ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi

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Patch merged into coreboot/master: 016732f pci_ops.{c, h}: Don't hide pointers behind typedefs
by gerrit＠coreboot.org 05 Nov '14

05 Nov '14

the following patch was just integrated into master: commit 016732fec9e99cafd0b1b66c0e5214f0783580f0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 29 03:04:40 2014 +1100 pci_ops.{c,h}: Don't hide pointers behind typedefs Change-Id: I7cf7c236f94314d7970b19063d73db788c8267e5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7227 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/7227 for details. -gerrit

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Patch merged into coreboot/master: 9a817ef soutbridge/*/bootblock: Use pci_dev_t over device_t typedef
by gerrit＠coreboot.org 05 Nov '14

05 Nov '14

the following patch was just integrated into master: commit 9a817ef183177d4d9ce6fc37b26e00e147d29cd1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:12:15 2014 +1100 soutbridge/*/bootblock: Use pci_dev_t over device_t typedef Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7193 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/7193 for details. -gerrit

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Patch set updated for coreboot: 6087be0 Intel Baytrail Gold2 and earlier FSP Staying Supported
by York Yang 05 Nov '14

05 Nov '14

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7335 -gerrit commit 6087be0edef8da1de17026f48d1d708306736dab Author: York Yang <york.yang(a)intel.com> Date: Tue Nov 4 17:20:46 2014 -0700 Intel Baytrail Gold2 and earlier FSP Staying Supported UPD_DATA_REGION structure has been updated to support Baytrail Gold3 FSP, but incompatible with previous FSP. Adjust the offset of those changed fields if FSP version is early than Gold3. Change-Id: Ia77431d31bed424ae25f297df893e45157a288a0 Signed-off-by: York Yang <york.yang(a)intel.com> --- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 11 +++++++++++ src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c4b781a..297ccf9 100755 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -48,6 +48,17 @@ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); + + /* adjust struct UPD_DATA_REGION content for Gold2 and earlier FSP */ + /* Gold3 FSP changes the UPD_DATA_REGION fields, adjust the struct */ + /* content in order to backward compatible with older FSP */ + /* */ + /* ISPEnable and PcdRegionTerminator are following PcdGttSize in */ + /* Gold2 and older FSP */ + if (FspInfo->ImageRevision < FSP_GOLD3_REV_ID) { + *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = UpdData->ISPEnable; + *(&(UpdData->PcdGttSize)+sizeof(UINT8)+sizeof(UINT8)) = UpdData->PcdRegionTerminator; + } } /* default to just enabling HDMI audio */ diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h old mode 100644 new mode 100755 index 1b60398..3861ac1 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -46,4 +47,7 @@ #define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ #define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ +/* Revision of the FSP binary */ +#define FSP_GOLD3_REV_ID 0x00000303 + #endif /* CHIPSET_FSP_UTIL_H */

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Patch set updated for coreboot: 3227b68 intel/fsp_baytrail: add Gold3 FSP support
by York Yang 05 Nov '14

05 Nov '14

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7334 -gerrit commit 3227b688032a42cf0768a9263ea776056f58c945 Author: York Yang <york.yang(a)intel.com> Date: Tue Nov 4 17:04:37 2014 -0700 intel/fsp_baytrail: add Gold3 FSP support Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION making platform more configurable via devicetree.cb Update the UPD_DATA_REGION structure and pass settings to FSP Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6 Signed-off-by: York Yang <york.yang(a)intel.com> --- src/soc/intel/fsp_baytrail/chip.h | 22 ++++ src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 19 ++++ src/vendorcode/intel/fsp/baytrail/include/fspvpd.h | 116 ++++++++++++--------- 3 files changed, 110 insertions(+), 47 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h old mode 100644 new mode 100755 index 7e86862..96b73ba --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +30,27 @@ struct soc_intel_fsp_baytrail_config { /* ***** UPD Configuration ***** */ + /* GFX render standby */ + uint8_t IgdRenderStandby; + #define IGD_RENDER_STANDBY_DEFAULT 0x00 + + /* Memory down data */ + uint8_t EnableMemoryDown; + uint8_t DRAMSpeed; + uint8_t DRAMType; + uint8_t DIMM0Enable; + uint8_t DIMM1Enable; + uint8_t DIMMDWidth; + uint8_t DIMMDensity; + uint8_t DIMMBusWidth; + uint8_t DIMMSides; + uint8_t DIMMtCL; + uint8_t DIMMtRPtRCD; + uint8_t DIMMtWR; + uint8_t DIMMtWTR; + uint8_t DIMMtRRD; + uint8_t DIMMtRTP; + uint8_t DIMMtFAW; /* Spd addresses */ uint8_t MrcInitSPDAddr1; diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c old mode 100644 new mode 100755 index 82f83a9..c4b781a --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -78,6 +79,24 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) dev = dev_find_slot(0, SOC_DEV_FUNC); config = dev->chip_info; + /* Populate the given memory down parameters */ + UpdData->PcdMemoryParameters.EnableMemoryDown = config->EnableMemoryDown; + UpdData->PcdMemoryParameters.DRAMSpeed = config->DRAMSpeed; + UpdData->PcdMemoryParameters.DRAMType = config->DRAMType; + UpdData->PcdMemoryParameters.DIMM0Enable = config->DIMM0Enable; + UpdData->PcdMemoryParameters.DIMM1Enable = config->DIMM1Enable; + UpdData->PcdMemoryParameters.DIMMDWidth = config->DIMMDWidth; + UpdData->PcdMemoryParameters.DIMMDensity = config->DIMMDensity; + UpdData->PcdMemoryParameters.DIMMBusWidth = config->DIMMBusWidth; + UpdData->PcdMemoryParameters.DIMMSides = config->DIMMSides; + UpdData->PcdMemoryParameters.DIMMtCL = config->DIMMtCL; + UpdData->PcdMemoryParameters.DIMMtRPtRCD = config->DIMMtRPtRCD; + UpdData->PcdMemoryParameters.DIMMtWR = config->DIMMtWR; + UpdData->PcdMemoryParameters.DIMMtWTR = config->DIMMtWTR; + UpdData->PcdMemoryParameters.DIMMtRRD = config->DIMMtRRD; + UpdData->PcdMemoryParameters.DIMMtRTP = config->DIMMtRTP; + UpdData->PcdMemoryParameters.DIMMtFAW = config->DIMMtFAW; + /* Set up default verb tables - Just HDMI audio */ UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig; diff --git a/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h old mode 100644 new mode 100755 index 1b820a8..b001cdb --- a/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -28,56 +28,78 @@ are permitted provided that the following conditions are met: **/ -/** - -This file is auto-generated, please DO NOT modify. +#ifndef __FSPVPD_H__ +#define __FSPVPD_H__ -**/ +#pragma pack(1) -#ifndef __VPDHEADER_H__ -#define __VPDHEADER_H__ +typedef struct { + UINT8 EnableMemoryDown; + UINT8 DRAMSpeed; /* DRAM Speed */ + UINT8 DRAMType; /* DRAM Type */ + UINT8 DIMM0Enable; /* DIMM 0 Enable */ + UINT8 DIMM1Enable; /* DIMM 1 Enable */ + UINT8 DIMMDWidth; /* DRAM device data width */ + UINT8 DIMMDensity; /* DRAM device data density */ + UINT8 DIMMBusWidth; /* DIMM Bus Width */ + UINT8 DIMMSides; /* Ranks Per DIMM */ + UINT8 DIMMtCL; /* tCL */ + UINT8 DIMMtRPtRCD; /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ + UINT8 DIMMtWR; /* tWR in DRAM clk */ + UINT8 DIMMtWTR; /* tWTR in DRAM clk */ + UINT8 DIMMtRRD; /* tRRD in DRAM clk */ + UINT8 DIMMtRTP; /* tRTP in DRAM clk */ + UINT8 DIMMtFAW; /* tFAW in DRAM clk */ +} MEMORY_DOWN_DATA; -#pragma pack(1) typedef struct _UPD_DATA_REGION { - UINT64 Signature; /* Offset 0x0000 */ - UINT32 RESERVED1; /* Offset 0x0008 */ - UINT8 Padding0[20]; /* Offset 0x000C */ - UINT16 PcdMrcInitTsegSize; /* Offset 0x0014 */ - UINT16 PcdMrcInitMmioSize; /* Offset 0x0016 */ - UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0018 */ - UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0019 */ - UINT8 PcdeMMCBootMode; /* Offset 0x001B */ - UINT8 PcdEnableSdio; /* Offset 0x001C */ - UINT8 PcdEnableSdcard; /* Offset 0x001D */ - UINT8 PcdEnableHsuart0; /* Offset 0x001E */ - UINT8 PcdEnableHsuart1; /* Offset 0x001F */ - UINT8 PcdEnableSpi; /* Offset 0x0020 */ - UINT8 PcdEnableLan; /* Offset 0x0021 */ - UINT8 PcdEnableSata; /* Offset 0x0023 */ - UINT8 PcdSataMode; /* Offset 0x002E */ - UINT8 PcdEnableAzalia; /* Offset 0x002F */ - UINT32 AzaliaConfigPtr; /* Offset 0x0030 */ - UINT8 PcdEnableXhci; /* Offset 0x0034 */ - UINT8 PcdEnableLpe; /* Offset 0x0029 */ - UINT8 PcdLpssSioEnablePciMode; /* Offset 0x002A */ - UINT8 PcdEnableDma0; /* Offset 0x002B */ - UINT8 PcdEnableDma1; /* Offset 0x002C */ - UINT8 PcdEnableI2C0; /* Offset 0x002D */ - UINT8 PcdEnableI2C1; /* Offset 0x002E */ - UINT8 PcdEnableI2C2; /* Offset 0x002F */ - UINT8 PcdEnableI2C3; /* Offset 0x0030 */ - UINT8 PcdEnableI2C4; /* Offset 0x0031 */ - UINT8 PcdEnableI2C5; /* Offset 0x0032 */ - UINT8 PcdEnableI2C6; /* Offset 0x0033 */ - UINT8 PcdEnablePwm0; /* Offset 0x0034 */ - UINT8 PcdEnablePwm1; /* Offset 0x0035 */ - UINT8 PcdEnableHsi; /* Offset 0x0036 */ - UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */ - UINT8 PcdApertureSize; /* Offset 0x0044 */ - UINT8 PcdGttSize; /* Offset 0x0045 */ - UINT8 ISPEnable; /* Offset 0x0046 */ - UINT16 PcdRegionTerminator; /* Offset 0x0047 */ + UINT64 Signature; /* Offset 0x0000 */ + UINT32 RESERVED1; /* Offset 0x0008 */ + UINT8 Padding0[20]; /* Offset 0x000C */ + UINT16 PcdMrcInitTsegSize; /* Offset 0x0020 */ + UINT16 PcdMrcInitMmioSize; /* Offset 0x0022 */ + UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0024 */ + UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0025 */ + UINT8 PcdeMMCBootMode; /* Offset 0x0026 */ + UINT8 PcdEnableSdio; /* Offset 0x0027 */ + UINT8 PcdEnableSdcard; /* Offset 0x0028 */ + UINT8 PcdEnableHsuart0; /* Offset 0x0029 */ + UINT8 PcdEnableHsuart1; /* Offset 0x002A */ + UINT8 PcdEnableSpi; /* Offset 0x002B */ + UINT8 PcdEnableLan; /* Offset 0x002C */ + UINT8 PcdEnableSata; /* Offset 0x002D */ + UINT8 PcdSataMode; /* Offset 0x002E */ + UINT8 PcdEnableAzalia; /* Offset 0x002F */ + UINT32 AzaliaConfigPtr; /* Offset 0x0030 */ + UINT8 PcdEnableXhci; /* Offset 0x0034 */ + UINT8 PcdEnableLpe; /* Offset 0x0035 */ + UINT8 PcdLpssSioEnablePciMode; /* Offset 0x0036 */ + UINT8 PcdEnableDma0; /* Offset 0x0037 */ + UINT8 PcdEnableDma1; /* Offset 0x0038 */ + UINT8 PcdEnableI2C0; /* Offset 0x0039 */ + UINT8 PcdEnableI2C1; /* Offset 0x003A */ + UINT8 PcdEnableI2C2; /* Offset 0x003B */ + UINT8 PcdEnableI2C3; /* Offset 0x003C */ + UINT8 PcdEnableI2C4; /* Offset 0x003D */ + UINT8 PcdEnableI2C5; /* Offset 0x003E */ + UINT8 PcdEnableI2C6; /* Offset 0x003F */ + UINT8 PcdEnablePwm0; /* Offset 0x0040 */ + UINT8 PcdEnablePwm1; /* Offset 0x0041 */ + UINT8 PcdEnableHsi; /* Offset 0x0042 */ + UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */ + UINT8 PcdApertureSize; /* Offset 0x0044 */ + UINT8 PcdGttSize; /* Offset 0x0045 */ + UINT32 SerialDebugPortAddress; /* Offset 0x0046 */ + UINT8 SerialDebugPortType; /* Offset 0x004A */ + UINT8 PcdMrcDebugMsg; /* Offset 0x004B */ + UINT8 ISPEnable; /* Offset 0x004C */ + UINT8 PcdSccEnablePciMode; /* Offset 0x004D */ + UINT8 IgdRenderStandby; /* Offset 0x004E */ + UINT8 TxeUmaEnable; /* Offset 0x004F */ + UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */ + MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */ + UINT16 PcdRegionTerminator; /* Offset 0x0100 */ } UPD_DATA_REGION; @@ -86,7 +108,7 @@ typedef struct _VPD_DATA_REGION { UINT32 PcdImageRevision; /* Offset 0x0008 */ UINT32 PcdUpdRegionOffset; /* Offset 0x000C */ UINT8 Padding0[16]; /* Offset 0x0010 */ - UINT32 RESERVED1; /* Offset 0x0020 */ + UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */ UINT8 PcdPlatformType; /* Offset 0x0024 */ UINT8 PcdEnableSecureBoot; /* Offset 0x0025 */ UINT8 PcdMemoryParameters[16]; /* Offset 0x0026 */

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Patch set updated for coreboot: 5701d4b beaglebone: use new arm bootblock infrastructure
by Alexander Couzens 05 Nov '14

05 Nov '14

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7190 -gerrit commit 5701d4b34c105f0904deae37dc03e224a899cdf5 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Fri Oct 24 23:53:55 2014 +0200 beaglebone: use new arm bootblock infrastructure 8b685398 change config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: Ifac4a18a2e380c3472f51aaa7cc7842b01a2553e Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/ti/beaglebone/Kconfig | 5 +---- src/mainboard/ti/beaglebone/Makefile.inc | 1 + src/mainboard/ti/beaglebone/bootblock.c | 2 +- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index fd465fa..57ed9bc 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_TI_AM335X select BOARD_ROMSIZE_KB_4096 + select MAINBOARD_HAS_BOOTBLOCK_INIT config MAINBOARD_DIR string @@ -40,10 +41,6 @@ config MAINBOARD_VENDOR string default "TI" -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/ti/beaglebone/bootblock.c" - config DRAM_SIZE_MB int default 256 diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc index c76cb37..71d749d 100644 --- a/src/mainboard/ti/beaglebone/Makefile.inc +++ b/src/mainboard/ti/beaglebone/Makefile.inc @@ -17,6 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +bootblock-y += bootblock.c romstage-y += romstage.c #ramstage-y += ramstage.c diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 6cc7a8c..2b22227 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -19,11 +19,11 @@ #include <arch/io.h> #include <types.h> +#include <bootblock_common.h> #include <console/uart.h> #include <console/console.h> #include <cpu/ti/am335x/pinmux.h> -void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { void *uart_clock_ctrl = NULL;

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Patch set updated for coreboot: b32f757 i82801ix: Move to implicit length patching
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7329 -gerrit commit b32f7579331e322e67af43e078ac04d0cf55485a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:21:06 2014 +0100 i82801ix: Move to implicit length patching Change-Id: I4027bc8c017901781ae56c7d3bd751bac50719f2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801ix/lpc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 664088c..dc2cfe8 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -544,16 +544,15 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { - int scopelen; memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); /* Add it to SSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } } #endif

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Patch set updated for coreboot: f0ac067 i82801gx: Move to implicit length patching
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7328 -gerrit commit f0ac0679f68111e6fb707e65fc11b6f10b69a936 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:20:56 2014 +0100 i82801gx: Move to implicit length patching Change-Id: Idba0f33d231084d02392e23026f567c30f77b316 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801gx/lpc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 10e40be..0618676 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -606,16 +606,15 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { - int scopelen; memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); /* Add it to SSDT. */ - scopelen = acpigen_write_scope("\\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } }

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Patch set updated for coreboot: 089293f lenovo/wacom: Move to implicit length patching
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7331 -gerrit commit 089293f3213a5a9e4670e6759626ebc734d3a119 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 4 21:17:30 2014 +0100 lenovo/wacom: Move to implicit length patching Change-Id: Ica8a54ab215d09a2d2de93f316e3831ae4bfe5f5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/lenovo/wacom.c | 84 +++++++++++++++++++++------------------------- 1 file changed, 38 insertions(+), 46 deletions(-) diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 33a2879..4a79e9a 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -93,84 +93,76 @@ void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, int have_dock_serial) { - int scopelen, devicelen, reslen, methodlen; + int reslen; - scopelen = acpigen_write_scope(scope); + acpigen_write_scope(scope); if (drivers_lenovo_is_wacom_present()) { /* Device op. */ - scopelen += acpigen_emit_byte(0x5b); - scopelen += acpigen_emit_byte(0x82); - devicelen = acpigen_write_len_f(); - devicelen += acpigen_emit_namestring("DTR"); + acpigen_emit_byte(0x5b); + acpigen_emit_byte(0x82); + acpigen_write_len_f(); + acpigen_emit_namestring("DTR"); - devicelen += acpigen_write_name("_HID"); - devicelen += acpigen_emit_eisaid("WACF004"); + acpigen_write_name("_HID"); + acpigen_emit_eisaid("WACF004"); - devicelen += acpigen_write_name("_CRS"); + acpigen_write_name("_CRS"); reslen = acpigen_write_resourcetemplate_header(); reslen += acpigen_write_io16(0x200, 0x200, 1, 8, 1); reslen += acpigen_write_irq((1 << 5)); - devicelen += reslen; - devicelen += acpigen_write_resourcetemplate_footer(reslen); + acpigen_write_resourcetemplate_footer(reslen); /* method op */ - devicelen += acpigen_emit_byte(0x14); - methodlen = acpigen_write_len_f(); - methodlen += acpigen_emit_namestring("_STA"); + acpigen_emit_byte(0x14); + acpigen_write_len_f(); + acpigen_emit_namestring("_STA"); /* no fnarg */ - methodlen += acpigen_emit_byte(0x00); + acpigen_emit_byte(0x00); /* return */ - methodlen += acpigen_emit_byte(0xa4); - methodlen += acpigen_write_byte(0xf); + acpigen_emit_byte(0xa4); + acpigen_write_byte(0xf); + acpigen_pop_len(); - acpigen_patch_len(methodlen); - devicelen += methodlen; - - acpigen_patch_len(devicelen - 1); - scopelen += devicelen; + acpigen_pop_len(); } if (have_dock_serial) { /* Device op. */ - scopelen += acpigen_emit_byte(0x5b); - scopelen += acpigen_emit_byte(0x82); - devicelen = acpigen_write_len_f(); - devicelen += acpigen_emit_namestring("COMA"); - - devicelen += acpigen_write_name("_HID"); - devicelen += acpigen_emit_eisaid("PNP0501"); - devicelen += acpigen_write_name("_UID"); + acpigen_emit_byte(0x5b); + acpigen_emit_byte(0x82); + acpigen_write_len_f(); + acpigen_emit_namestring("COMA"); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0501"); + acpigen_write_name("_UID"); /* Byte */ - devicelen += acpigen_write_byte(0x2); + acpigen_write_byte(0x2); - devicelen += acpigen_write_name("_CRS"); + acpigen_write_name("_CRS"); reslen = acpigen_write_resourcetemplate_header(); reslen += acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); reslen += acpigen_write_irq(1 << 4); - devicelen += reslen; - devicelen += acpigen_write_resourcetemplate_footer(reslen); + acpigen_write_resourcetemplate_footer(reslen); /* method op */ - devicelen += acpigen_emit_byte(0x14); - methodlen = acpigen_write_len_f(); - methodlen += acpigen_emit_namestring("_STA"); + acpigen_emit_byte(0x14); + acpigen_write_len_f(); + acpigen_emit_namestring("_STA"); /* no fnarg */ - methodlen += acpigen_emit_byte(0x00); + acpigen_emit_byte(0x00); /* return */ - methodlen += acpigen_emit_byte(0xa4); - methodlen += acpigen_write_byte(0xf); - acpigen_patch_len(methodlen); - - devicelen += methodlen; + acpigen_emit_byte(0xa4); + acpigen_write_byte(0xf); + acpigen_pop_len(); - acpigen_patch_len(devicelen - 1); - scopelen += devicelen; + acpigen_pop_len(); } - acpigen_patch_len(scopelen - 1); + acpigen_pop_len(); }

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coreboot-gerrit November 2014