coreboot-gerrit November 2014

coreboot-gerrit@coreboot.org

1 participants
1441 discussions

Patch set updated for coreboot: 46000c0 fsp_rangeley: Switch to per-device ACPI
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7046 -gerrit commit 46000c022badc4c88d4cbea5bcdde4e572c7c7ce Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 11 11:25:41 2014 +0200 fsp_rangeley: Switch to per-device ACPI Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/fsp_model_406dx/acpi.c | 89 +++++------ src/mainboard/intel/mohonpeak/acpi_tables.c | 177 +-------------------- src/northbridge/intel/fsp_rangeley/Kconfig | 1 + src/northbridge/intel/fsp_rangeley/acpi.c | 14 ++ src/northbridge/intel/fsp_rangeley/northbridge.c | 13 ++ src/northbridge/intel/fsp_rangeley/northbridge.h | 1 + .../intel/fsp_rangeley/acpi/globalnvs.asl | 3 +- src/southbridge/intel/fsp_rangeley/lpc.c | 27 ++++ src/southbridge/intel/fsp_rangeley/nvs.h | 1 + 9 files changed, 98 insertions(+), 228 deletions(-) diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index 24f63cd..4f883f4 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -50,47 +50,44 @@ static int get_cores_per_package(void) return cores; } -static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { struct cpu_info *info; struct cpu_driver *cpu; - int len, lenif; struct device *lapic; struct cpu_intel_model_406dx_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); if (!lapic) - return 0; + return; conf = lapic->chip_info; if (!conf) - return 0; + return; /* Find CPU map of supported C-states */ info = cpu_info(); if (!info) - return 0; + return; cpu = find_cpu_driver(info->cpu); if (!cpu || !cpu->cstates) - return 0; + return; - len = acpigen_emit_byte(0x14); /* MethodOp */ - len += acpigen_write_len_f(); /* PkgLength */ - len += acpigen_emit_namestring("_CST"); - len += acpigen_emit_byte(0x00); /* No Arguments */ + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */ /* If running on AC power */ - len += acpigen_emit_byte(0xa0); /* IfOp */ - lenif = acpigen_write_len_f(); /* PkgLength */ - lenif += acpigen_emit_namestring("PWRS"); - lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ - acpigen_patch_len(lenif - 1); - len += lenif; + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + acpigen_pop_len(); /* Else on battery power */ - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - acpigen_patch_len(len - 1); - return len; + acpigen_emit_byte(0xa4); /* ReturnOp */ + acpigen_pop_len(); } static acpi_tstate_t tss_table_fine[] = { @@ -122,31 +119,27 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -170,9 +163,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, num_entries; int ratio, power, clock, clock_max; @@ -202,16 +194,16 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + acpigen_write_PSD_package(core, cores_per_package, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = PSS_RATIO_STEP; @@ -224,13 +216,13 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -239,11 +231,11 @@ static int generate_P_state_entries(int core, int cores_per_package) ratio_turbo << 8); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); } /* First regular entry is max non-turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -259,7 +251,7 @@ static int generate_P_state_entries(int core, int cores_per_package) power = calculate_power(power_max, ratio_max, ratio); clock = ratio * RANGELEY_BCLK; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -269,15 +261,11 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); @@ -294,23 +282,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( cpuID-1, cores_per_package); /* Generate C-state tables */ - len_pr += generate_C_state_entries(); + generate_C_state_entries(); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( cpuID-1, cores_per_package); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/mainboard/intel/mohonpeak/acpi_tables.c b/src/mainboard/intel/mohonpeak/acpi_tables.c index 0349075..b49da65 100644 --- a/src/mainboard/intel/mohonpeak/acpi_tables.c +++ b/src/mainboard/intel/mohonpeak/acpi_tables.c @@ -33,14 +33,9 @@ #include <southbridge/intel/fsp_rangeley/nvs.h> #include <northbridge/intel/fsp_rangeley/northbridge.h> -extern const unsigned char AmlCode[]; -#if CONFIG_HAVE_ACPI_SLIC -unsigned long acpi_create_slic(unsigned long current); -#endif - static global_nvs_t *gnvs_; -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { gnvs_ = gnvs; memset((void *)gnvs, 0, sizeof(*gnvs)); @@ -89,173 +84,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - u32 lens, bmbound; - char pscope[] = "\\_SB.PCI0"; - - bmbound = sideband_read(B_UNIT, BMBOUND); - lens = acpigen_write_scope(pscope); - lens += acpigen_write_name_dword("BMBD", bmbound); - generate_cpu_entries(); - acpigen_patch_len(lens - 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1); - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; -#if CONFIG_HAVE_ACPI_SLIC - acpi_header_t *slic; -#endif - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - - /* Pack GNVS into the ACPI table area */ - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); - *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes - acpi_save_gnvs(current); - break; - } - } - - /* And fill it */ - acpi_create_gnvs((global_nvs_t *)current); - - /* And tell SMI about it */ -#if CONFIG_HAVE_SMI_HANDLER - smm_setup_structures((void *)current, NULL, NULL); -#endif - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - -#if CONFIG_HAVE_ACPI_SLIC - printk(BIOS_DEBUG, "ACPI: * SLIC\n"); - slic = (acpi_header_t *)current; - current += acpi_create_slic(current); - ALIGN_CURRENT; - acpi_add_table(rsdp, slic); -#endif - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "current = %lx\n", current); - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index c1353ca..2d2eda7 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_FSP_RANGELEY bool select CPU_INTEL_FSP_MODEL_406DX + select PER_DEVICE_ACPI_TABLES if NORTHBRIDGE_INTEL_FSP_RANGELEY diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 895f5b4..b2ddc88 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -30,6 +30,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <build.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include "northbridge.h" unsigned long acpi_fill_mcfg(unsigned long current) @@ -64,3 +66,15 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } + +void northbridge_acpi_fill_ssdt_generator(void) +{ + u32 bmbound; + char pscope[] = "\\_SB.PCI0"; + + bmbound = sideband_read(B_UNIT, BMBOUND); + acpigen_write_scope(pscope); + acpigen_write_name_dword("BMBD", bmbound); + acpigen_pop_len(); + generate_cpu_entries(); +} diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 07ce21f..be3a3ac 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -212,6 +212,18 @@ static void northbridge_enable(device_t dev) { } +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -231,6 +243,7 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, + .acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator, .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 855a056..abce07a 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -72,6 +72,7 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); +void northbridge_acpi_fill_ssdt_generator(void); #endif /* #ifndef __ASSEMBLER__ */ #endif /* #ifndef __ACPI__ */ diff --git a/src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl b/src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl index 21209db..c5c1a9a 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl @@ -32,7 +32,8 @@ Name(\DSEN, 1) // Display Output Switching Enable */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8576b61..9644067 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -31,8 +31,13 @@ #include <arch/acpi.h> #include <cpu/cpu.h> #include <elog.h> +#include <string.h> +#include <cbmem.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include "soc.h" #include "irq.h" +#include "nvs.h" #define NMI_OFF 0 @@ -426,6 +431,26 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void southbridge_inject_dsdt(void) +{ + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + + if (gnvs) { + memset(gnvs, 0, sizeof(*gnvs)); + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); +#if CONFIG_HAVE_SMI_HANDLER + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); +#endif + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); + } +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -435,6 +460,8 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = soc_lpc_enable_resources, .init = lpc_init, + .write_acpi_tables = acpi_write_hpet, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .enable = soc_lpc_enable, .scan_bus = scan_static_bus, .ops_pci = &pci_ops, diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h index dce23e0..6578bbf 100644 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ b/src/southbridge/intel/fsp_rangeley/nvs.h @@ -149,6 +149,7 @@ typedef struct { } __attribute__((packed)) global_nvs_t; +void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void);

1 0

Patch set updated for coreboot: 6d99100 baytrail: Switch to per-device ACPI
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7037 -gerrit commit 6d99100af4051e8d293d79b36bfc005036b489f5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 8 22:56:27 2014 +0200 baytrail: Switch to per-device ACPI Change-Id: I6a1b1daa291298c85e14f89aa47a0693837cec6f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/rambi/acpi_tables.c | 159 +---------------- src/mainboard/intel/bayleybay_fsp/acpi_tables.c | 187 +------------------- src/mainboard/intel/minnowmax/acpi_tables.c | 223 +----------------------- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/acpi.c | 53 +++--- src/soc/intel/baytrail/acpi/globalnvs.asl | 3 +- src/soc/intel/baytrail/baytrail/nvs.h | 1 + src/soc/intel/baytrail/northcluster.c | 14 ++ src/soc/intel/baytrail/southcluster.c | 31 ++++ src/soc/intel/fsp_baytrail/Kconfig | 1 + src/soc/intel/fsp_baytrail/acpi.c | 94 +++++++--- src/soc/intel/fsp_baytrail/acpi/globalnvs.asl | 3 +- src/soc/intel/fsp_baytrail/baytrail/acpi.h | 3 + src/soc/intel/fsp_baytrail/baytrail/nvs.h | 1 + src/soc/intel/fsp_baytrail/northcluster.c | 15 +- src/soc/intel/fsp_baytrail/southcluster.c | 6 + 16 files changed, 173 insertions(+), 622 deletions(-) diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 890e1df..d94b2de 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -34,9 +34,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -68,158 +66,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "current = %lx\n", current); - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c index 5f81e26..cb63df6 100644 --- a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c +++ b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c @@ -35,10 +35,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> - -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -70,185 +67,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *ssdt2; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, - facs->length); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - ALIGN_CURRENT; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, - dsdt->length); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, - fadt->header.length); - - /* - * We explicitly add these tables later on: - */ - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, - hpet->header.length); - - /* If we want to use HPET Timers Linux wants an MADT */ - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, - madt->header.length); - - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, - mcfg->header.length); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ -#if CONFIG_HAVE_SMI_HANDLER - smm_setup_structures(gnvs, NULL, NULL); -#endif - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - ssdt = (acpi_header_t *)current; - memset(ssdt, 0, sizeof(acpi_header_t)); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, - ssdt->length); - ALIGN_CURRENT; - } else { - ssdt = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); - } - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - ALIGN_CURRENT; - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c index 881c143..8e31da2 100644 --- a/src/mainboard/intel/minnowmax/acpi_tables.c +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -36,10 +36,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> - -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -62,221 +59,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *ssdt2; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, - facs->length); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - ALIGN_CURRENT; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, - dsdt->length); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, - fadt->header.length); - - /* - * We explicitly add these tables later on: - */ - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, - hpet->header.length); - - /* If we want to use HPET Timers Linux wants an MADT */ - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, - madt->header.length); - - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, - mcfg->header.length); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ -#if CONFIG_HAVE_SMI_HANDLER - smm_setup_structures(gnvs, NULL, NULL); -#endif - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - ssdt = (acpi_header_t *)current; - memset(ssdt, 0, sizeof(acpi_header_t)); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, - ssdt->length); - ALIGN_CURRENT; - } else { - ssdt = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); - } - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - ALIGN_CURRENT; - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - -#if IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) - printk(BIOS_DEBUG, "rsdp\n"); - hexdump(BIOS_DEBUG, rsdp, sizeof(acpi_rsdp_t)); - - printk(BIOS_DEBUG, "rsdt\n"); - hexdump(BIOS_DEBUG, rsdt, sizeof(acpi_rsdt_t)); - - printk(BIOS_DEBUG, "hpet\n"); - hexdump(BIOS_DEBUG, hpet, hpet->header.length); - - printk(BIOS_DEBUG, "madt\n"); - hexdump(BIOS_DEBUG, madt, madt->header.length); - - printk(BIOS_DEBUG, "mcfg\n"); - hexdump(BIOS_DEBUG, mcfg, mcfg->header.length); - - printk(BIOS_DEBUG, "dsdt\n"); - hexdump(BIOS_DEBUG, dsdt, dsdt->length); - - if (ssdt != NULL) { - printk(BIOS_DEBUG, "ssdt\n"); - hexdump(BIOS_DEBUG, ssdt, ssdt->length); - } - - if (ssdt2 != NULL) { - printk(BIOS_DEBUG, "ssdt2\n"); - hexdump(BIOS_DEBUG, ssdt2, ssdt2->length); - } - - printk(BIOS_DEBUG, "fadt\n"); - hexdump(BIOS_DEBUG, fadt, fadt->header.length); - - printk(BIOS_DEBUG, "facs\n"); - hexdump(BIOS_DEBUG, facs, facs->length); - -#endif /* IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) */ - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bc90b11..5393531 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC + select PER_DEVICE_ACPI_TABLES config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index aae0c99..9b004bd 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -295,24 +295,20 @@ static acpi_tstate_t baytrail_tss_table[] = { { 13, 125, 0, 0x12, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set NVS controlled T-state limit */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* Write TSS table for MSR access */ - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -336,9 +332,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -366,16 +361,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with NVS specified limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, 1, coord_type); + acpigen_write_PSD_package(core, 1, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = 1; @@ -388,14 +383,14 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; control_status = (ratio_turbo << 8) | vid_turbo; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -404,14 +399,14 @@ static int generate_P_state_entries(int core, int cores_per_package) control_status); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); ratio_turbo = ratio_max; vid_turbo = vid_max; } /* First regular entry is max non-turbo ratio */ control_status = (ratio_max << 8) | vid_max; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -439,7 +434,7 @@ static int generate_P_state_entries(int core, int cores_per_package) clock = (ratio * pattrs->bclk_khz) / 1000; control_status = (ratio << 8) | (vid & 0xff); - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ 10, /*lat1*/ @@ -449,15 +444,12 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) { - int len_pr, core; + int core; int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); @@ -468,23 +460,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( core, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( core, pattrs->num_cpus); /* Generate C-state tables */ - len_pr += acpigen_write_CST_package( + acpigen_write_CST_package( cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( core, pattrs->num_cpus); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index a201c03..946f123 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -30,7 +30,8 @@ Name(\PICM, 0) // IOAPIC/8259 */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index c5defac..c204042 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -70,6 +70,7 @@ typedef struct { device_nvs_t dev; } __attribute__((packed)) global_nvs_t; +void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b119e24..2807a2d 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <arch/acpi.h> #include <baytrail/iomap.h> #include <baytrail/iosf.h> @@ -131,8 +132,21 @@ static void nc_read_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + static struct device_operations nc_ops = { .read_resources = nc_read_resources, + .acpi_fill_ssdt_generator = generate_cpu_entries, .set_resources = NULL, .enable_resources = NULL, .init = NULL, diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 500a13d..277b1f8 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -41,6 +41,9 @@ #include <baytrail/ramstage.h> #include <baytrail/spi.h> #include "chip.h" +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) @@ -511,9 +514,37 @@ void southcluster_enable_dev(device_t dev) } } +static void southcluster_inject_dsdt(void) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + memset(gnvs, 0, sizeof(*gnvs)); + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); + } +} + + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .write_acpi_tables = acpi_write_hpet, .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index e9391c3..1ca19c3 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT + select PER_DEVICE_ACPI_TABLES config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb0dc87..a148bcc 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -47,6 +47,7 @@ #include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/pmc.h> +#include <cpu/cpu.h> #include <cbmem.h> #include "chip.h" @@ -402,9 +403,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -432,16 +432,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with NVS specified limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, 1, coord_type); + acpigen_write_PSD_package(core, 1, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = 1; @@ -454,14 +454,14 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; control_status = (ratio_turbo << 8) | vid_turbo; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -470,14 +470,14 @@ static int generate_P_state_entries(int core, int cores_per_package) control_status); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); ratio_turbo = ratio_max; vid_turbo = vid_max; } /* First regular entry is max non-turbo ratio */ control_status = (ratio_max << 8) | vid_max; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -505,7 +505,7 @@ static int generate_P_state_entries(int core, int cores_per_package) clock = (ratio * pattrs->bclk_khz) / 1000; control_status = (ratio << 8) | (vid & 0xff); - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ 10, /*lat1*/ @@ -515,15 +515,12 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) { - int len_pr, core; + int core; int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); @@ -534,23 +531,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( core, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( core, pattrs->num_cpus); /* Generate C-state tables */ - len_pr += acpigen_write_CST_package( + acpigen_write_CST_package( cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( core, pattrs->num_cpus); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } @@ -575,3 +571,57 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) + +unsigned long southcluster_write_acpi_tables(unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_header_t *ssdt2; + + current = acpi_write_hpet(current, rsdp); + ALIGN_CURRENT; + + ssdt2 = (acpi_header_t *)current; + memset(ssdt2, 0, sizeof(acpi_header_t)); + acpi_create_serialio_ssdt(ssdt2); + if (ssdt2->length) { + current += ssdt2->length; + acpi_add_table(rsdp, ssdt2); + printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, + ssdt2->length); + ALIGN_CURRENT; + } else { + ssdt2 = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); + } + + printk(BIOS_DEBUG, "current = %lx\n", current); + + return current; +} + +void southcluster_inject_dsdt(void) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + memset(gnvs, 0, sizeof(*gnvs)); + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl index 696390d..d2dc021 100644 --- a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl @@ -30,7 +30,8 @@ Name(\PICM, 0) // IOAPIC/8259 */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/acpi.h b/src/soc/intel/fsp_baytrail/baytrail/acpi.h index aaba61a..ea23974 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/acpi.h +++ b/src/soc/intel/fsp_baytrail/baytrail/acpi.h @@ -29,5 +29,8 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); +unsigned long southcluster_write_acpi_tables(unsigned long current, + struct acpi_rsdp *rsdp); +void southcluster_inject_dsdt(void); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvs.h b/src/soc/intel/fsp_baytrail/baytrail/nvs.h index 242f6d3..11ad72e 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/nvs.h @@ -68,6 +68,7 @@ typedef struct { device_nvs_t dev; } __attribute__((packed)) global_nvs_t; +void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..a440b9a 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -32,7 +32,7 @@ #include <cbmem.h> #include <baytrail/baytrail.h> #include <drivers/intel/fsp/fsp_util.h> - +#include <arch/acpi.h> static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; @@ -204,8 +204,21 @@ static void nc_enable(device_t dev) print_fsp_info(); } +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + static struct device_operations nc_ops = { .read_resources = nc_read_resources, + .acpi_fill_ssdt_generator = generate_cpu_entries, .set_resources = NULL, .enable_resources = NULL, .init = NULL, diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..3541482 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -40,10 +40,14 @@ #include <baytrail/irq.h> #include <baytrail/lpc.h> #include <baytrail/nvs.h> +#include <baytrail/acpi.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/ramstage.h> #include "chip.h" +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> #define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define TEST_SMM_FLASH_LOCKDOWN 0 @@ -647,6 +651,8 @@ void southcluster_enable_dev(device_t dev) static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .write_acpi_tables = southcluster_write_acpi_tables, .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev,

1 0

Patch set updated for coreboot: e99534b mainboard: Don't hide pointer behind typedef
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7139 -gerrit commit e99534b15b861ffea480e968dd1eaf38c28cfe06 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 09:54:41 2014 +1100 mainboard: Don't hide pointer behind typedef Change-Id: I4a0e4e1598e16e13b43401c7e834b292121b63ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/get_bus_conf.c | 2 +- src/mainboard/advansus/a785e-i/mainboard.c | 2 +- src/mainboard/amd/bimini_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/bimini_fam10/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/get_bus_conf.c | 2 +- src/mainboard/amd/dbm690t/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/dinar/mainboard.c | 2 +- src/mainboard/amd/dinar/mptable.c | 2 +- src/mainboard/amd/inagua/mainboard.c | 2 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/mahogany/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany_fam10/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/olivehill/mainboard.c | 2 +- src/mainboard/amd/olivehill/mptable.c | 2 +- src/mainboard/amd/olivehillplus/mainboard.c | 2 +- src/mainboard/amd/olivehillplus/mptable.c | 2 +- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/parmer/mptable.c | 2 +- src/mainboard/amd/persimmon/mainboard.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/pistachio/get_bus_conf.c | 2 +- src/mainboard/amd/pistachio/mainboard.c | 4 ++-- src/mainboard/amd/pistachio/mptable.c | 2 +- src/mainboard/amd/rumba/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 4 ++-- src/mainboard/amd/serengeti_cheetah/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 4 ++-- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/mptable.c | 4 ++-- src/mainboard/amd/south_station/mainboard.c | 2 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/mainboard/amd/thatcher/mptable.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 14 +++++++------- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/torpedo/mainboard.c | 2 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/union_station/mainboard.c | 2 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/apple/macbook21/mainboard.c | 4 ++-- src/mainboard/arima/hdama/debug.c | 4 ++-- src/mainboard/arima/hdama/mptable.c | 10 +++++----- src/mainboard/asrock/939a785gmh/get_bus_conf.c | 2 +- src/mainboard/asrock/939a785gmh/mainboard.c | 4 ++-- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/e350m1/mainboard.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asrock/imb-a180/mainboard.c | 2 +- src/mainboard/asrock/imb-a180/mptable.c | 2 +- src/mainboard/asus/a8n_e/get_bus_conf.c | 2 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/dsbf/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mptable.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/mainboard.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2n-e/get_bus_conf.c | 2 +- src/mainboard/asus/m2n-e/mainboard.c | 2 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/mainboard.c | 2 +- src/mainboard/asus/m2v/romstage.c | 4 ++-- src/mainboard/asus/m4a78-em/get_bus_conf.c | 2 +- src/mainboard/asus/m4a78-em/mainboard.c | 8 ++++---- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a785-m/get_bus_conf.c | 2 +- src/mainboard/asus/m4a785-m/mainboard.c | 10 +++++----- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m5a88-v/get_bus_conf.c | 2 +- src/mainboard/asus/m5a88-v/mainboard.c | 2 +- src/mainboard/avalue/eax-785e/get_bus_conf.c | 2 +- src/mainboard/avalue/eax-785e/mainboard.c | 2 +- src/mainboard/bachmann/ot200/mainboard.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/broadcom/blast/get_bus_conf.c | 2 +- src/mainboard/broadcom/blast/mptable.c | 4 ++-- src/mainboard/dmp/vortex86ex/mainboard.c | 2 +- src/mainboard/emulation/qemu-armv7/mainboard.c | 2 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/getac/p470/mainboard.c | 6 +++--- src/mainboard/getac/p470/romstage.c | 8 ++++---- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 2 +- src/mainboard/gigabyte/m57sli/mainboard.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 2 +- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gm/mainboard.c | 8 ++++---- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 12 ++++++------ src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma78gm/mainboard.c | 6 +++--- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/gizmosphere/gizmo/mainboard.c | 4 ++-- src/mainboard/gizmosphere/gizmo/mptable.c | 2 +- src/mainboard/google/bolt/mainboard.c | 6 +++--- src/mainboard/google/butterfly/mainboard.c | 6 +++--- src/mainboard/google/daisy/mainboard.c | 4 ++-- src/mainboard/google/falco/mainboard.c | 6 +++--- src/mainboard/google/link/mainboard.c | 6 +++--- src/mainboard/google/nyan/mainboard.c | 4 ++-- src/mainboard/google/nyan_big/mainboard.c | 4 ++-- src/mainboard/google/panther/mainboard.c | 4 ++-- src/mainboard/google/parrot/mainboard.c | 6 +++--- src/mainboard/google/peach_pit/mainboard.c | 4 ++-- src/mainboard/google/peppy/mainboard.c | 6 +++--- src/mainboard/google/rambi/mainboard.c | 6 +++--- src/mainboard/google/samus/mainboard.c | 6 +++--- src/mainboard/google/slippy/mainboard.c | 6 +++--- src/mainboard/google/storm/mainboard.c | 4 ++-- src/mainboard/google/stout/mainboard.c | 4 ++-- src/mainboard/hp/dl145_g1/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g1/mptable.c | 2 +- src/mainboard/hp/dl145_g3/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g3/mptable.c | 8 ++++---- src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 8 ++++---- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 2 +- src/mainboard/ibase/mb899/mainboard.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/ibm/e325/mptable.c | 4 ++-- src/mainboard/ibm/e326/mptable.c | 4 ++-- src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +- src/mainboard/intel/baskingridge/mainboard.c | 2 +- src/mainboard/intel/bayleybay_fsp/mainboard.c | 2 +- src/mainboard/intel/cougar_canyon2/mainboard.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/eagleheights/debug.c | 4 ++-- src/mainboard/intel/eagleheights/mptable.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/intel/jarrell/debug.c | 4 ++-- src/mainboard/intel/jarrell/mptable.c | 4 ++-- src/mainboard/intel/jarrell/romstage.c | 2 +- src/mainboard/intel/jarrell/watchdog.c | 8 ++++---- src/mainboard/intel/minnowmax/mainboard.c | 2 +- src/mainboard/intel/mohonpeak/mainboard.c | 2 +- src/mainboard/intel/truxton/mptable.c | 2 +- src/mainboard/intel/wtm2/mainboard.c | 2 +- src/mainboard/intel/xe7501devkit/mptable.c | 2 +- src/mainboard/iwave/iWRainbowG6/mainboard.c | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 4 ++-- src/mainboard/iwill/dk8_htx/mainboard.c | 2 +- src/mainboard/iwill/dk8_htx/mptable.c | 4 ++-- src/mainboard/iwill/dk8s2/mptable.c | 4 ++-- src/mainboard/iwill/dk8x/mptable.c | 4 ++-- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/get_bus_conf.c | 2 +- src/mainboard/jetway/pa78vm5/mainboard.c | 8 ++++---- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/kontron/986lcd-m/mainboard.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 6 +++--- src/mainboard/kontron/kt690/get_bus_conf.c | 2 +- src/mainboard/kontron/kt690/mainboard.c | 4 ++-- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/kontron/ktqm77/mainboard.c | 6 +++--- src/mainboard/kontron/ktqm77/romstage.c | 6 +++--- src/mainboard/lenovo/t520/mainboard.c | 4 ++-- src/mainboard/lenovo/t530/mainboard.c | 4 ++-- src/mainboard/lenovo/t60/mainboard.c | 7 ++++--- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x200/mainboard.c | 4 ++-- src/mainboard/lenovo/x201/mainboard.c | 6 +++--- src/mainboard/lenovo/x220/mainboard.c | 4 ++-- src/mainboard/lenovo/x230/mainboard.c | 4 ++-- src/mainboard/lenovo/x60/mainboard.c | 8 +++++--- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/frontrunner-af/mptable.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mptable.c | 2 +- src/mainboard/msi/ms7135/get_bus_conf.c | 2 +- src/mainboard/msi/ms7135/mptable.c | 2 +- src/mainboard/msi/ms7260/get_bus_conf.c | 2 +- src/mainboard/msi/ms7260/mainboard.c | 2 +- src/mainboard/msi/ms7260/mptable.c | 2 +- src/mainboard/msi/ms9185/get_bus_conf.c | 2 +- src/mainboard/msi/ms9185/mptable.c | 4 ++-- src/mainboard/msi/ms9282/get_bus_conf.c | 2 +- src/mainboard/msi/ms9282/mainboard.c | 2 +- src/mainboard/msi/ms9282/mptable.c | 2 +- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 2 +- src/mainboard/msi/ms9652_fam10/mainboard.c | 2 +- src/mainboard/msi/ms9652_fam10/mptable.c | 2 +- src/mainboard/newisys/khepri/mptable.c | 4 ++-- src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 2 +- src/mainboard/nvidia/l1_2pvv/mainboard.c | 2 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 8 ++++---- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/rca/rm4100/mainboard.c | 4 ++-- src/mainboard/roda/rk886ex/mainboard.c | 4 ++-- src/mainboard/roda/rk886ex/romstage.c | 8 ++++---- src/mainboard/roda/rk9/mainboard.c | 2 +- src/mainboard/roda/rk9/romstage.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 8 +++----- src/mainboard/samsung/stumpy/mainboard.c | 2 +- src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 21 +++++++++++---------- src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +- src/mainboard/sunw/ultra40/get_bus_conf.c | 2 +- src/mainboard/sunw/ultra40/mptable.c | 2 +- src/mainboard/supermicro/h8dme/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dme/mptable.c | 2 +- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qgi/mainboard.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++-- src/mainboard/supermicro/h8scm/mainboard.c | 2 +- src/mainboard/supermicro/h8scm/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 6 +++--- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/debug.c | 4 ++-- src/mainboard/supermicro/x6dai_g/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/romstage.c | 2 +- src/mainboard/supermicro/x6dai_g/watchdog.c | 2 +- src/mainboard/supermicro/x6dhe_g/debug.c | 4 ++-- src/mainboard/supermicro/x6dhe_g/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhe_g2/debug.c | 4 ++-- src/mainboard/supermicro/x6dhe_g2/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhe_g2/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g2/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhr_ig/debug.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhr_ig2/debug.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig2/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/watchdog.c | 6 +++--- src/mainboard/supermicro/x7db8/mainboard.c | 2 +- src/mainboard/technexion/tim5690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 4 ++-- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim8690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 6 +++--- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/thomson/ip1000/mainboard.c | 4 ++-- src/mainboard/tyan/s2735/mptable.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 4 ++-- src/mainboard/tyan/s2875/mptable.c | 4 ++-- src/mainboard/tyan/s2880/mptable.c | 6 +++--- src/mainboard/tyan/s2881/get_bus_conf.c | 2 +- src/mainboard/tyan/s2881/mptable.c | 2 +- src/mainboard/tyan/s2882/mptable.c | 6 +++--- src/mainboard/tyan/s2885/get_bus_conf.c | 2 +- src/mainboard/tyan/s2885/mptable.c | 2 +- src/mainboard/tyan/s2891/get_bus_conf.c | 2 +- src/mainboard/tyan/s2891/mainboard.c | 2 +- src/mainboard/tyan/s2891/mptable.c | 2 +- src/mainboard/tyan/s2892/get_bus_conf.c | 2 +- src/mainboard/tyan/s2892/mainboard.c | 2 +- src/mainboard/tyan/s2892/mptable.c | 2 +- src/mainboard/tyan/s2895/get_bus_conf.c | 2 +- src/mainboard/tyan/s2895/mainboard.c | 2 +- src/mainboard/tyan/s2895/mptable.c | 2 +- src/mainboard/tyan/s2912/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912/mptable.c | 2 +- src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912_fam10/mptable.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 6 +++--- src/mainboard/tyan/s4882/mptable.c | 6 +++--- src/mainboard/tyan/s8226/mainboard.c | 2 +- src/mainboard/tyan/s8226/mptable.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m/romstage.c | 6 +++--- src/mainboard/via/epia-m700/romstage.c | 8 ++++---- src/mainboard/via/epia-m850/mainboard.c | 2 +- src/mainboard/via/epia-n/romstage.c | 4 ++-- src/mainboard/via/epia/romstage.c | 4 ++-- src/mainboard/via/vt8454c/romstage.c | 2 +- src/mainboard/winent/mb6047/get_bus_conf.c | 2 +- src/mainboard/winent/mb6047/mainboard.c | 2 +- src/mainboard/winent/mb6047/mptable.c | 2 +- 302 files changed, 483 insertions(+), 481 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 80e1d3e..2c5757a 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 9b6450d..686e968 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in A785E-I board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index f7c55143..6b31272 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -64,7 +64,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 32c8862..cd4f50e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -100,7 +100,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -123,7 +123,7 @@ static void get_ide_dma66(void) * enable the dedicated function in bimini board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/dbm690t/get_bus_conf.c +++ b/src/mainboard/amd/dbm690t/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 43a8d91..b92426c 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 00f1a84..83171a0 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -68,7 +68,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in dinar board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 4e481f5..e796ffe 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sb700; u32 apicid_rd890; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc23007..0c57350 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -74,7 +74,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7686bd2..65f67cc 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/amd/mahogany/get_bus_conf.c +++ b/src/mainboard/amd/mahogany/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 0e542ff..e851e8f 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -97,7 +97,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index bd31846..bebf041 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 7d4514a..8f90235 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -98,7 +98,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index db4a3ff..d209582 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 6073fd4..1e58d88 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 73660e4..0ca9217 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 2ba714a..4b192c2 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in parmer board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 05da01a..7999dd8 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 58ac983..34918a8 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -151,7 +151,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 1227d89..1ae44c4 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/pistachio/get_bus_conf.c +++ b/src/mainboard/amd/pistachio/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 75f92bd..db2cbcf 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -76,7 +76,7 @@ static void set_thermal_config(void) u8 byte, byte2; u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* set adt7475 */ ADT7475_write_byte(0x40, 0x04); @@ -250,7 +250,7 @@ static void set_thermal_config(void) * enable the dedicated function in pistachio board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index 5725c78..2f6af29 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -7,7 +7,7 @@ static void init(struct device *dev) { - device_t nic = NULL; + struct device * nic = NULL; unsigned bus = 0; unsigned devfn = PCI_DEVFN(0xd, 0); int nicirq = 1; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index f5cd846..f2d7f9e 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c index b9c88f6..26f61f8 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.c +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.c @@ -5,7 +5,7 @@ #include <arch/acpigen.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 866875d..341b367 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -114,7 +114,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 48d5cc3..02dfb3c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ static u32 get_hcid(u32 i) u32 id = 0; u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; u32 devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); @@ -95,7 +95,7 @@ void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 5335cb8..3b4731b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v) if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; int jj; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 43d6a78..1be0c0a 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -77,7 +77,7 @@ static void southstation_led_init(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); southstation_led_init(); diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 834117e..e7b7ecf 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 8ddd1b6..e34b899 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index cc97866..8ebd6b4 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -46,7 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); hudson_lpc_port80(); diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 48e4c17..efea2fa 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -102,7 +102,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -127,7 +127,7 @@ static void get_ide_dma66(void) u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -157,7 +157,7 @@ static void set_gpio40_gfx(void) { u8 byte; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -212,7 +212,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -273,7 +273,7 @@ static void set_thermal_config(void) * enable the dedicated function in tilapia board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 9b52b89..f5f9c94 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) /************************************************* * enable the dedicated function in torpedo board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 477d97a..53038dd 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -186,7 +186,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 8816e8d..ca2e887 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 99527c1..c9858d8 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -41,12 +41,12 @@ int get_cst_entries(acpi_cstate_t **entries) return 0; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c index a6f0d55..d29a5b9 100644 --- a/src/mainboard/arima/hdama/debug.c +++ b/src/mainboard/arima/hdama/debug.c @@ -11,7 +11,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -50,7 +50,7 @@ static void dump_pci_device(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 6ee2704..c1a6cef 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -13,7 +13,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -48,7 +48,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) static unsigned max_apicid(void) { unsigned max; - device_t dev; + struct device * dev; max = 0; for(dev = all_devices; dev; dev = dev->next) { if (dev->path.type != DEVICE_PATH_APIC) @@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v) apicid_8131_1 = apicid_base + 1; apicid_8131_2 = apicid_base + 2; { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1)); @@ -206,7 +206,7 @@ static void *smp_write_config_table(void *v) static void reboot_if_hotswap(void) { /* Hack patch work around for hot swap enable 33mhz problem */ - device_t dev; + struct device * dev; uint32_t data; unsigned long htic; int reset; diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c +++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 58ad8b2..a8d2913 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -67,7 +67,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -95,7 +95,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 790d1da..0d174bc 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..1f554f2 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 14fa316..23b5261 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index d9ca7b7..38db63a 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -183,7 +183,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c index a55401b..22d0123 100644 --- a/src/mainboard/asus/a8n_e/get_bus_conf.c +++ b/src/mainboard/asus/a8n_e/get_bus_conf.c @@ -63,7 +63,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index a954d92..b6e1059 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..32472ee 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..74b768e 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/asus/dsbf/mainboard.c +++ b/src/mainboard/asus/dsbf/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 191eea8..ff4eb20 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index cc81819..e5d7603 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -149,7 +149,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index caa32ca..6126cb8 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -67,7 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index cd45213..2898b51 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -27,7 +27,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..4b897b1 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -88,7 +88,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c index fd7d304..c9d113d 100644 --- a/src/mainboard/asus/m2n-e/get_bus_conf.c +++ b/src/mainboard/asus/m2n-e/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c index 2c18100..7bf4639 100644 --- a/src/mainboard/asus/m2n-e/mainboard.c +++ b/src/mainboard/asus/m2n-e/mainboard.c @@ -21,7 +21,7 @@ #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c index 333ec49..69a5260 100644 --- a/src/mainboard/asus/m2n-e/mptable.c +++ b/src/mainboard/asus/m2n-e/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) struct mp_config_table *mc; unsigned int sbdn; int i, j, bus_isa; - device_t dev; + struct device * dev; struct resource *res; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index d12b77c..df73222 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -72,7 +72,7 @@ static void sio_setup(void) { u8 byte; u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ /* Subject decoding */ byte = pci_read_config8(dev, 0x7b); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..605c19d 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -107,7 +107,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index 21adac0..cbacc88 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -26,7 +26,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..74d2edc 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -91,7 +91,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); @@ -189,7 +189,7 @@ static void m2v_it8712f_gpio_init(void) static void m2v_bus_init(void) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "m2v_bus_init\n"); diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 1a2e9fc..b32ca0c 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -36,7 +36,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -61,7 +61,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -91,7 +91,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -118,7 +118,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index b1154ab..edaecab 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -100,7 +100,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -129,7 +129,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -190,7 +190,7 @@ static void set_thermal_config(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 8ee338e..1da327b 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in M5A88-V board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 6ce3469..6ee5923 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in EAX-785E board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c index d4b0b2d..ea13cef 100644 --- a/src/mainboard/bachmann/ot200/mainboard.c +++ b/src/mainboard/bachmann/ot200/mainboard.c @@ -46,7 +46,7 @@ static void init(struct device *dev) u32 chksum = 0; char block[20]; msr_t reset; - device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52); + struct device * eeprom_dev = dev_find_slot_on_smbus(1, 0x52); if (eeprom_dev == 0) { printk(BIOS_WARNING, "eeprom not found\n"); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 898ad1a..391263b 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 5de8952..f95d70a 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -50,7 +50,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d7ae6b7..9d415d2 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index 2761035..381658a 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 83a55e3..815f50e 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Enable qemu/armv7 device...\n"); } diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index a8a61c4..6d1f2b0 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -30,7 +30,7 @@ static const unsigned char qemu_i440fx_irqs[] = { 11, 10, 10, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e991b53..622ea54 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -33,7 +33,7 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 2b33ff0..1dc881a 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -62,7 +62,7 @@ static void pcie_limit_power(void) // machine. It should set the slot numbers and enable power // limitation for the PCIe slots. - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(28,0)); if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0); @@ -79,14 +79,14 @@ static void pcie_limit_power(void) } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { ec_enable(); } // mainboard_enable is executed as first thing after // enumerate_buses(). Is there no mainboard_init()? -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 3dab527..da40c55 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -105,19 +105,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pnp_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -126,7 +126,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x4e, 0x00); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index 9315cbd..c9c1950 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 0af6cf0..9e8c7bf 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index c798415..db5b685 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/gigabyte/m57sli/mainboard.c +++ b/src/mainboard/gigabyte/m57sli/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 1536823..43459bc 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index cd06069..9fe9c7f 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -35,7 +35,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -60,7 +60,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -134,7 +134,7 @@ static void set_gpio40_gfx(void) * enable the dedicated function in ma785gm board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 89b50bb..f591ebb 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ void set_pcie_reset() int is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -128,7 +128,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -183,7 +183,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -244,7 +244,7 @@ static void set_thermal_config(void) * enable the dedicated function in ma785gmt board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 49df0c2..2fd5c52 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -38,7 +38,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -51,7 +51,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -71,7 +71,7 @@ u8 is_dev3_present(void) * enable the dedicated function in board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index a9afdfb..ad8fa58 100755 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -55,7 +55,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -78,7 +78,7 @@ static void mainboard_enable(device_t dev) void mainboard_final( void *chip_info ); void mainboard_final( void *chip_info ) { - device_t ahci_dev; + struct device * ahci_dev; u32 ABAR; u8 *memptr; diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index b98598a..8301bd5 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/google/bolt/mainboard.c b/src/mainboard/google/bolt/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/bolt/mainboard.c +++ b/src/mainboard/google/bolt/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 655fc2f..c4006c6 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -194,7 +194,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { u32 search_address = 0x0; size_t search_length = -1; @@ -258,7 +258,7 @@ static void mainboard_init(device_t dev) } } -static int butterfly_onboard_smbios_data(device_t dev, int *handle, +static int butterfly_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -278,7 +278,7 @@ static int butterfly_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 0adadb6..fc9a08c 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -258,7 +258,7 @@ static void gpio_init(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { int dp_tries; struct s5p_dp_device dp_device = { @@ -322,7 +322,7 @@ static void mainboard_init(device_t dev) // gpio_info(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/falco/mainboard.c +++ b/src/mainboard/google/falco/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index ed40f8f..d1a3856 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -149,7 +149,7 @@ static int int15_handler(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ link_ec_init(); @@ -166,7 +166,7 @@ static void mainboard_init(device_t dev) } } -static int link_onboard_smbios_data(device_t dev, int *handle, +static int link_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -204,7 +204,7 @@ static int link_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 6fa8a95..d7df116 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -284,7 +284,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 4a05991..908d610 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -281,7 +281,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index 5058eca..a1bd459 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { lan_init(); } @@ -52,7 +52,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 547680e..207bcfd 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -48,13 +48,13 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ parrot_ec_init(); } -static int parrot_onboard_smbios_data(device_t dev, int *handle, +static int parrot_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -85,7 +85,7 @@ static int parrot_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1fb441d..53db9fa 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -405,7 +405,7 @@ static void sdmmc_vdd(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* we'll stick with the crummy u-boot struct for now.*/ /* doing this as an auto since the struct has to be writeable */ @@ -462,7 +462,7 @@ static void mainboard_init(device_t dev) setup_usb(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/peppy/mainboard.c +++ b/src/mainboard/google/peppy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index cd3fc48..b43928d 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -127,12 +127,12 @@ static int int15_handler(void) } #endif -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -161,7 +161,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index 7977ce3..de7f434 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -42,12 +42,12 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -112,7 +112,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0b0182f..4792ea9 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -20,11 +20,11 @@ #include <device/device.h> #include <boot/coreboot_tables.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 9bcbfe4..58d89b8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -48,7 +48,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct device *ethernet_dev = NULL; @@ -70,7 +70,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index acfa023..6a36ef7 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -51,7 +51,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index b9af38b..7e81143 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); if (dev) { diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index ba0fc88..59b35aa 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 6c71bad..6b3032b 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 099c41a..6561c94 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 86f2cc6..175cfe5 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index f858455..3384a9f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -41,7 +41,7 @@ static void pavilion_cold_boot_init(void) pavilion_m6_1035dx_ec_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index f47b9d9..d12e759 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -144,7 +144,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index a2a10a1..ba6a09e 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -31,7 +31,7 @@ // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 322907b..e8931f0 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -76,7 +76,7 @@ static void ich7_enable_lpc(void) */ static void early_superio_config_w83627ehg(void) { - device_t dev; + pnp_devfn_t dev; dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 6eb6390..50f8031 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c index f271166..d85e609 100644 --- a/src/mainboard/ibm/e326/mptable.c +++ b/src/mainboard/ibm/e326/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index 43ff9c1..9d67e2b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -53,7 +53,7 @@ u8 is_dev3_present(void) * enable the dedicated function in kino board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index a83bf7e..0cb238b 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -69,7 +69,7 @@ void main(unsigned long bist) console_init(); /* Enable COM3. */ - device_t dev = PNP_DEV(0x2e, 0x0b); + pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b); u16 port = dev >> 8; outb(0x55, port); pnp_set_logical_device(dev); diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index feae6ef..d32ca91 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -38,7 +38,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c index 0ea03d3..f0062d5 100644 --- a/src/mainboard/intel/cougar_canyon2/mainboard.c +++ b/src/mainboard/intel/cougar_canyon2/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index cc956a7..c6cf529 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -56,7 +56,7 @@ static inline void reset_system(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index e5795b6..c25b3a3 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -143,7 +143,7 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -210,7 +210,7 @@ static inline void dump_bar14(unsigned dev) static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 809feec..78dfb62 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; int bus_isa, i; uint32_t pin, route; - device_t dev; + struct device * dev; struct resource *res; unsigned long rcba; diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 220b1d7..f9f6a85 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -47,7 +47,7 @@ static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/intel/jarrell/debug.c +++ b/src/mainboard/intel/jarrell/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index 21664ce..6dcf7d7 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index f1cf4c3..29553fc 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -75,7 +75,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index 7f7a039..9722c04 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -6,7 +6,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { /* FIXME move me somewhere more appropriate */ pnp_set_logical_device(dev); @@ -20,7 +20,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -48,7 +48,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -97,7 +97,7 @@ static void disable_watchdogs(void) static void ich5_watchdog_on(void) { - device_t dev; + pci_devfn_t dev; unsigned long value, base; unsigned char byte; diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c index 3da1e23..ce9872a 100644 --- a/src/mainboard/intel/minnowmax/mainboard.c +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -25,7 +25,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c index 7559fc2..387931d 100644 --- a/src/mainboard/intel/mohonpeak/mainboard.c +++ b/src/mainboard/intel/mohonpeak/mainboard.c @@ -24,7 +24,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index 9ad6ea6..2c7eb92 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) u8 bus_pea0 = 0; u8 bus_pea1 = 0; u8 bus_aioc; - device_t dev; + struct device * dev; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index cc7eda5..65e4bcc 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -19,7 +19,7 @@ static int bus_isa; static void xe7501devkit_register_ioapics(struct mp_config_table *mc) { - device_t dev; + struct device * dev; struct resource *res; // TODO: Gack. This is REALLY ugly. diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c index dfc6636..457c88f 100644 --- a/src/mainboard/iwave/iWRainbowG6/mainboard.c +++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c @@ -22,7 +22,7 @@ #include <console/console.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index 87de022..da83738 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -36,7 +36,7 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index 8868f46..be033f5 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c index 0202b50..909e5a9 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.c +++ b/src/mainboard/iwill/dk8_htx/mainboard.c @@ -7,7 +7,7 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index ff6e582..416cd17 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -126,7 +126,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8s2/mptable.c +++ b/src/mainboard/iwill/dk8s2/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8x/mptable.c +++ b/src/mainboard/iwill/dk8x/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index a9c71c3..fe3f48c 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d67e072..92c8d70 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -153,7 +153,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 4390605..2c9606a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -116,7 +116,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 373ebb5..6da52fc 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -39,7 +39,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -52,7 +52,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -72,7 +72,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -100,7 +100,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 7cabdf1..0c7130b 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index afca796..0ae64b5 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -164,7 +164,7 @@ static void hwm_setup(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 2c12c5d..a28593f 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -78,14 +78,14 @@ static void ich7_enable_lpc(void) } /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_func_mode(device_t dev) +static void pnp_enter_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_func_mode(device_t dev) +static void pnp_exit_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -98,7 +98,7 @@ static void pnp_exit_func_mode(device_t dev) */ static void early_superio_config_w83627thg(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/kontron/kt690/get_bus_conf.c +++ b/src/mainboard/kontron/kt690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 717c399..a88a2c8 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 715ec56..6f6c2d8 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -172,7 +172,7 @@ static int int15_handler(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ @@ -181,7 +181,7 @@ static void mainboard_enable(device_t dev) unsigned disable = 0; if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); if (nic) { printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n"); nic->enabled = 0; @@ -189,7 +189,7 @@ static void mainboard_enable(device_t dev) } disable = 0; if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); if (nic) { printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n"); nic->enabled = 0; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 401314c..d1a6279 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -125,14 +125,14 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -142,7 +142,7 @@ static void superio_gpio_config(void) { int lvds_3v = 0; // 0 (5V) or 1 (3V3) int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled - device_t dev = PNP_DEV(0x2e, 0x9); + pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 387bbe0..ddd6d22 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -65,7 +65,7 @@ static void mainboard_init(device_t dev) /* mainboard_enable is executed as first thing after enumerate_buses(). */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index f8c9dae..922b424 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -69,7 +69,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 79b3da8..d960b11 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -61,10 +61,11 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + struct device * dev0; + struct device * idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); @@ -95,7 +96,7 @@ static void mainboard_init(device_t dev) ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index f11b33e..24d4ab6 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -98,7 +98,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0xa0); diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 0054064..c79b552 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -45,7 +45,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* This sneaked in here, because X200 SuperIO chip isn't really connected to anything and hence we don't init it. @@ -53,7 +53,7 @@ static void mainboard_init(device_t dev) pc_keyboard_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 5b76be2..f61bb9a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -71,7 +71,7 @@ const char *smbios_mainboard_bios_version(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -117,9 +117,9 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { - device_t dev0; + struct device * dev0; u16 pmbase; dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 00e7991..c86825e 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -49,7 +49,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -72,7 +72,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index a060015..28d7344 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -50,7 +50,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -73,7 +73,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 1d29c71..9f0cda4 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -56,9 +56,11 @@ int get_cst_entries(acpi_cstate_t **entries) return ARRAY_SIZE(cst_entries); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { - device_t dev0, idedev, sdhci_dev; + struct device * dev0; + struct device * idedev; + struct device * sdhci_dev; ec_clr_bit(0x03, 2); @@ -115,7 +117,7 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 943143a..348b5fe 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -105,7 +105,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index ee538c3..983df2c 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -163,7 +163,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 9e44a21..28ac9ba 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -130,7 +130,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c index e364892..cb2bd5d 100644 --- a/src/mainboard/msi/ms7135/get_bus_conf.c +++ b/src/mainboard/msi/ms7135/get_bus_conf.c @@ -55,7 +55,7 @@ void get_bus_conf(void) { unsigned apicid_base; - device_t dev; + struct device *dev; unsigned sbdn; int i; diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c index b43a516..0c7032f 100644 --- a/src/mainboard/msi/ms7135/mptable.c +++ b/src/mainboard/msi/ms7135/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; u32 dword; diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c index 34d3834..97b2b70 100644 --- a/src/mainboard/msi/ms7260/get_bus_conf.c +++ b/src/mainboard/msi/ms7260/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c index 492693a..d4e111f 100644 --- a/src/mainboard/msi/ms7260/mainboard.c +++ b/src/mainboard/msi/ms7260/mainboard.c @@ -23,7 +23,7 @@ #if 0 -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } #endif diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index ea003a8..a200b70 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 3a70d83..86afc47 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index b30ab73..fc00858 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c index 195ddc4..776fabb 100644 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ b/src/mainboard/msi/ms9282/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c index c7e459a..54cdc3b 100644 --- a/src/mainboard/msi/ms9282/mainboard.c +++ b/src/mainboard/msi/ms9282/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index 1764cf3..432e702 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 36ae12c..4ec04f5 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; printk(BIOS_SPEW, "get_bus_conf()\n"); diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c index 96760d6..7fc97f0 100644 --- a/src/mainboard/msi/ms9652_fam10/mainboard.c +++ b/src/mainboard/msi/ms9652_fam10/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 09a25f2..1b9b349 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c index 1d7c79e..ede913f 100644 --- a/src/mainboard/newisys/khepri/mptable.c +++ b/src/mainboard/newisys/khepri/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c index 125b564..b77a355 100644 --- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c +++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c @@ -73,7 +73,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/nvidia/l1_2pvv/mainboard.c +++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index e991efd..5cdad5b 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; @@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; @@ -128,7 +128,7 @@ static void *smp_write_config_table(void *v) //Slot PCI 32 { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); if (dev && dev->enabled) { for (i = 0; i < 4; i++) @@ -148,7 +148,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index c14e9b7..c5b51e0 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t ** entries) -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 pmbase; diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 2e3191b..421c916 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -20,12 +20,12 @@ #include <device/device.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { // TODO Switch parport LEDs again } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { // TODO Switch parport LEDs dev->ops->init = mainboard_init; diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 4c7fffa..5421d13 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -63,14 +63,14 @@ static void dump_runtime_registers(void) } #endif -static void mainboard_final(device_t dev) +static void mainboard_final(struct device * dev) { /* Enable Dummy DCC ON# for DVI */ printk(BIOS_DEBUG, "Laptop handling...\n"); outb(inb(0x60f) & ~(1 << 5), 0x60f); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { /* Configure the MultiKey controller */ // m3885_configure_multikey(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7cc1a1d..0278cdf 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -93,19 +93,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pnp_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -114,7 +114,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x2e, 0x00); diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index acf8023..39ade3f 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -44,7 +44,7 @@ static void ec_setup(void) send_ec_command(0xad); /* Set_Thml_Value */ } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { ec_setup(); /* LCD panel type is SIO GPIO40-43. diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c8b75e0..89026ac 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -88,7 +88,7 @@ static void default_superio_gpio_setup(void) GP1 GP2 GP3 GP4 fd 17 88 14 */ - const device_t sio = PNP_DEV(0x2e, 0); + const pnp_devfn_t sio = PNP_DEV(0x2e, 0); /* Enter super-io's configuration state. */ pnp_enter_conf_state(sio); diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 3bdd4d9..d53bf9e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -46,9 +46,7 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } - - -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ lumpy_ec_init(); @@ -80,7 +78,7 @@ static int lumpy_smbios_type41_irq(int *handle, unsigned long *current, } -static int lumpy_onboard_smbios_data(device_t dev, int *handle, +static int lumpy_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -101,7 +99,7 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c +++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 77be0af..219527a 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -389,7 +389,7 @@ static void pm_init( void ) { u16 word; u8 byte; - device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + struct device * sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* set SB600 GPIO 64 to GPIO with pull-up */ byte = pm2_ioread(0x42); @@ -432,7 +432,7 @@ static void set_thermal_config(void) { u8 byte, byte2; u8 cpu_pwm_conf, case_pwm_conf; - device_t sm_dev; + struct device * sm_dev; struct fan_control cpu_fan_control, case_fan_control; const char *name = NULL; @@ -614,8 +614,8 @@ static void patch_mmio_nonposted( void ) resource_t rbase, rend; u32 base, limit; struct resource *resource; - device_t dev; - device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); + struct device * dev; + struct device * k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); printk(BIOS_DEBUG,"%s ...\n", __func__); @@ -668,7 +668,7 @@ struct { unsigned int plx_present = 0; -static void update_subsystemid( device_t dev ) +static void update_subsystemid(struct device * dev) { int i; @@ -680,7 +680,7 @@ static void update_subsystemid( device_t dev ) } printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device ); for( i=0; slot[i].bus < 255; i++) { - device_t d; + struct device * d; d = dev_find_slot(slot[i].bus,slot[i].devfn); if( d ) { printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device); @@ -695,10 +695,11 @@ static void update_subsystemid( device_t dev ) * @param */ -static void detect_hw_variant( device_t dev ) +static void detect_hw_variant(struct device * dev) { - device_t nb_dev =0, dev2 = 0; + struct device * nb_dev = NULL; + struct device * dev2 = NULL; struct southbridge_amd_rs690_config *cfg; u32 lc_state, id = 0; @@ -807,7 +808,7 @@ static void smm_lock( void ) * @param the root device */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE INT15_function_extensions int15_func; @@ -833,7 +834,7 @@ static void mainboard_init(device_t dev) * enable the dedicated function in sina board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "%s %s[%x/%x] %s\n", diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index de5151d..194b5ba 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index f57719a..f716158 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; if (get_bus_conf_done == 1) return; //do it only once diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index 1ba1dcf..6259278 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index 17067ed..d53b498 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 11db23f..5a24259 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index a1de06c..71eb756 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -72,7 +72,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index 4e2d48c..5c88156 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 8f12e22..cdce2f9 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -65,7 +65,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8qgi board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 50e2b44..7a80f74 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -74,7 +74,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 4fbb4c8..79f8a5e 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 24ecb5d..ce348ba 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -115,14 +115,14 @@ static const u8 spd_addr[] = { #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c index 23b1d72..de1dead 100644 --- a/src/mainboard/supermicro/h8scm/mainboard.c +++ b/src/mainboard/supermicro/h8scm/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8scm board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 0560180..fc3a446 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -65,7 +65,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 18e1e8c..4908dcb 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -49,7 +49,7 @@ u8 is_dev3_present(void) ***/ void set_pcie_reset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); @@ -58,7 +58,7 @@ void set_pcie_reset(void) void set_pcie_dereset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); @@ -69,7 +69,7 @@ void set_pcie_dereset(void) * enable the dedicated function in h8scm board. * This function called early than sr5650_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 84593fc..864cdd1 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index 0efae77..4185a54 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* southbridge */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 0385cad..0998b02 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -70,7 +70,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing 6300ESB?"); diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c index 2fd3274..bf9f9f1 100644 --- a/src/mainboard/supermicro/x6dai_g/watchdog.c +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -8,7 +8,7 @@ static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index ab73fc7..18fe954 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 405a2bc..6e90958 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -73,7 +73,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing esb6300?"); diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c index 1d34f7d..3fab7f9 100644 --- a/src/mainboard/supermicro/x6dhe_g/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -5,7 +5,7 @@ #define ESB6300_WDBASE 0x400 #define ESB6300_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index a2b8c8d..c4d690e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 48945eb..b9e0d50 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -73,7 +73,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5r?"); diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c index 1d34f7d..3fab7f9 100644 --- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -5,7 +5,7 @@ #define ESB6300_WDBASE 0x400 #define ESB6300_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index f9165d6..935ae8c 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(2, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 08b0ccd..e78d511 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -72,7 +72,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c index a451c32..259ea79 100644 --- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -5,7 +5,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index b5ba6b1..56aec2e 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index dfe0da2..5d6d89c 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -72,7 +72,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c index a451c32..259ea79 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -5,7 +5,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/supermicro/x7db8/mainboard.c +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim5690/get_bus_conf.c +++ b/src/mainboard/technexion/tim5690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..da4ed9a 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -117,7 +117,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -222,7 +222,7 @@ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) * enable the dedicated function in tim5690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 gpio_base = IT8712F_SIMPLE_IO_BASE; #if CONFIG_VGA_ROM_RUN diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ b/src/mainboard/technexion/tim8690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 6010eb1..14811bb 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -53,7 +53,7 @@ static void enable_onboard_nic(void) { u8 byte; - device_t sm_dev; + struct device * sm_dev; printk(BIOS_INFO, "enable_onboard_nic.\n"); @@ -79,7 +79,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -140,7 +140,7 @@ static void set_thermal_config(void) * enable the dedicated function in tim8690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index 7267696..9bd4f53 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -84,13 +84,13 @@ static void flash_gpios(void) } } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { parport_gpios(); flash_gpios(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 9073728..9f65205 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 371d9a3..3145e32 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 90299a7..798ea64 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 32fc639..cbefcdb 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index 332e578..b2177a4 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -53,7 +53,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 7df5e87..d28a104 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index 6c07965..b06b49c 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -11,7 +11,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index 88706c0..dfd62b8 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -56,7 +56,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 26081c7..6413230 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index e94c608..5ff3e3b 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -60,7 +60,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index cb49434..f52a07b 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 0ead854..e59cd33 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -58,7 +58,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index 882ac69..d3dc505 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c index 11b1bc2..c6d9a08 100644 --- a/src/mainboard/tyan/s2895/get_bus_conf.c +++ b/src/mainboard/tyan/s2895/get_bus_conf.c @@ -66,7 +66,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 604df51..85f5556 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -12,7 +12,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index 20fa92c..3c4242f 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index 7727c4b..fb38d32 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 133ce43..8620cd4 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 0a3a9d8..6a9e2e9 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index e15387d..0b7ce31 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index dcc0fd8..3ec04bb 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 2); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 350b55c..3d22fd9 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 1); @@ -119,7 +119,7 @@ static void *smp_write_config_table(void *v) apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s8226/mainboard.c b/src/mainboard/tyan/s8226/mainboard.c index 9e8160a..6f094cb 100644 --- a/src/mainboard/tyan/s8226/mainboard.c +++ b/src/mainboard/tyan/s8226/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in s8226 board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 20f99cb..d3d5857 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -44,7 +44,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 3f2a0c4..2d66bbd 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -25,7 +25,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); @@ -57,7 +57,7 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; /* no need to look up 0:0.0 */ + pci_devfn_t dev = 0; /* no need to look up 0:0.0 */ unsigned char shadowreg; /* dev 0 for southbridge */ shadowreg = pci_read_config8(dev, 0x63); @@ -69,7 +69,7 @@ static void enable_shadow_ram(void) #include <cpu/intel/romstage.h> static void main(unsigned long bist) { - device_t dev; + pci_devfn_t dev; /* Enable VGA; 32MB buffer. */ pci_write_config8(0, 0xe1, 0xdd); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index b00ece1..700d13f 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -55,7 +55,7 @@ */ static int acpi_is_wakeup_early_via_vx800(void) { - device_t dev; + pci_devfn_t dev; u16 tmp, result; print_debug("In acpi_is_wakeup_early_via_vx800\n"); @@ -83,7 +83,7 @@ static int acpi_is_wakeup_early_via_vx800(void) /* All content of this function came from the cx700 port of coreboot. */ static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; #if 0 /* * Add and close this switch, since some line cause error, some @@ -378,8 +378,8 @@ void main(unsigned long bist) { u16 boot_mode; u8 rambits, Data8, Data; - device_t device; - /* device_t dev; */ + pci_devfn_t device; + /* pci_devfn_t dev; */ /* * Enable multifunction for northbridge. These 4 lines (until diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index dbe682c..146c21b 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -95,7 +95,7 @@ static int vx900_int15_handler(void) } #endif -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { (void)dev; diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 2ede8d8..f8ba755 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -58,7 +58,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; u8 reg; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -105,7 +105,7 @@ static void enable_shadow_ram(void) static void main(unsigned long bist) { unsigned long x; - device_t dev; + pci_devfn_t dev; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 1d312d7..aff85a5 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -24,7 +24,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; /* dev 0 for southbridge */ dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); @@ -60,7 +60,7 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; + pci_devfn_t dev = 0; unsigned char shadowreg; shadowreg = pci_read_config8(dev, 0x63); diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index f6d58c8..97f1858 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -39,7 +39,7 @@ static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index 5b96b05..1c7e1da 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -35,7 +35,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/winent/mb6047/mainboard.c +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index 26e79ca..afbb8b9 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -33,7 +33,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword;

1 0

Patch set updated for coreboot: 15920f8 device: Clarify correct typing of 'struct device *'
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7138 -gerrit commit 15920f8a5cd9e1b3dde292d0d70520ae7fdb701d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 13:55:04 2014 +1100 device: Clarify correct typing of 'struct device *' Disambiguate 'device_t' into 'struct device *', 'pci_devfn_t' and 'pnp_devfn_t' component types where appropriate. Change-Id: Ic4239efe0462d86694bf4ac0ec898f589b6adf1c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/agp_device.c | 6 +-- src/device/cardbus_device.c | 8 ++-- src/device/cpu_device.c | 8 ++-- src/device/device.c | 14 +++---- src/device/device_romstage.c | 2 +- src/device/device_util.c | 35 ++++++++-------- src/device/hypertransport.c | 20 +++++---- src/device/oprom/yabel/biosemu.c | 2 +- src/device/oprom/yabel/compat/functions.c | 2 +- src/device/oprom/yabel/device.c | 2 +- src/device/oprom/yabel/io.c | 2 +- src/device/pci_device.c | 22 +++++----- src/device/pci_ops.c | 2 +- src/device/pci_rom.c | 2 +- src/device/pciexp_device.c | 22 +++++----- src/device/pcix_device.c | 6 +-- src/device/pnp_device.c | 40 +++++++++--------- src/device/root_device.c | 14 +++---- src/device/smbus_ops.c | 26 ++++++------ src/include/cpu/amd/model_fxx_rev.h | 7 ++-- src/include/device/agp.h | 2 +- src/include/device/cardbus.h | 4 +- src/include/device/device.h | 69 +++++++++++++++---------------- src/include/device/pci.h | 30 +++++++------- src/include/device/pciexp.h | 2 +- src/include/device/pcix.h | 2 +- src/include/device/pnp.h | 38 ++++++++--------- src/include/device/smbus.h | 54 ++++++++++++------------ 28 files changed, 224 insertions(+), 219 deletions(-) diff --git a/src/device/agp_device.c b/src/device/agp_device.c index 550297a..fc23fe6 100644 --- a/src/device/agp_device.c +++ b/src/device/agp_device.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/agp.h> -static void agp_tune_dev(device_t dev) +static void agp_tune_dev(struct device *dev) { unsigned int cap; @@ -38,7 +38,7 @@ static void agp_tune_dev(device_t dev) unsigned int agp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max) { - device_t child; + struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); @@ -53,7 +53,7 @@ unsigned int agp_scan_bus(struct bus *bus, unsigned int min_devfn, return max; } -unsigned int agp_scan_bridge(device_t dev, unsigned int max) +unsigned int agp_scan_bridge(struct device *dev, unsigned int max) { return do_pci_scan_bridge(dev, max, agp_scan_bus); } diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index f25f96c..e32ece3 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -38,7 +38,7 @@ #define CARDBUS_IO_SIZE 4096 #define CARDBUS_MEM_SIZE (32 * 1024 * 1024) -static void cardbus_record_bridge_resource(device_t dev, resource_t moving, +static void cardbus_record_bridge_resource(struct device *dev, resource_t moving, resource_t min_size, unsigned int index, unsigned long type) { struct resource *resource; @@ -70,7 +70,7 @@ static void cardbus_record_bridge_resource(device_t dev, resource_t moving, resource->size = min_size; } -static void cardbus_size_bridge_resource(device_t dev, unsigned int index) +static void cardbus_size_bridge_resource(struct device *dev, unsigned int index) { struct resource *resource; resource_t min_size; @@ -87,7 +87,7 @@ static void cardbus_size_bridge_resource(device_t dev, unsigned int index) } } -void cardbus_read_resources(device_t dev) +void cardbus_read_resources(struct device *dev) { resource_t moving_base, moving_limit, moving; unsigned long type; @@ -153,7 +153,7 @@ void cardbus_read_resources(device_t dev) compact_resources(dev); } -void cardbus_enable_resources(device_t dev) +void cardbus_enable_resources(struct device *dev) { u16 ctrl; diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index e76b539..7152d02 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -25,7 +25,7 @@ void remap_bsp_lapic(struct bus *cpu_bus) { struct device_path cpu_path; - device_t cpu; + struct device *cpu; u32 bsp_lapic_id = lapicid(); if (bsp_lapic_id) { @@ -37,10 +37,10 @@ void remap_bsp_lapic(struct bus *cpu_bus) } } -device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) +struct device *add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) { struct device_path cpu_path; - device_t cpu; + struct device *cpu; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -61,7 +61,7 @@ device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) return cpu; } -void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread) +void set_cpu_topology(struct device *cpu, unsigned node, unsigned package, unsigned core, unsigned thread) { cpu->path.apic.node_id = node; cpu->path.apic.package_id = package; diff --git a/src/device/device.c b/src/device/device.c index e068cee..04fc725 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -114,9 +114,9 @@ uint64_t uma_memory_size = 0; * * @see device_path */ -static device_t __alloc_dev(struct bus *parent, struct device_path *path) +static struct device *__alloc_dev(struct bus *parent, struct device_path *path) { - device_t dev, child; + struct device *dev, *child; /* Find the last child of our parent. */ for (child = parent->children; child && child->sibling; /* */ ) @@ -148,9 +148,9 @@ static device_t __alloc_dev(struct bus *parent, struct device_path *path) return dev; } -device_t alloc_dev(struct bus *parent, struct device_path *path) +struct device *alloc_dev(struct bus *parent, struct device_path *path) { - device_t dev; + struct device *dev; spin_lock(&dev_lock); dev = __alloc_dev(parent, path); spin_unlock(&dev_lock); @@ -164,9 +164,9 @@ device_t alloc_dev(struct bus *parent, struct device_path *path) * @param path The relative path from the bus to the appropriate device. * @return Pointer to a device structure for the device on bus at path. */ -device_t alloc_find_dev(struct bus *parent, struct device_path *path) +struct device *alloc_find_dev(struct bus *parent, struct device_path *path) { - device_t child; + struct device *child; spin_lock(&dev_lock); child = find_dev_path(parent, path); if (!child) @@ -750,7 +750,7 @@ static void avoid_fixed_resources(struct device *dev) } } -device_t vga_pri = 0; +struct device *vga_pri = NULL; static void set_vga_bridge_bits(void) { /* diff --git a/src/device/device_romstage.c b/src/device/device_romstage.c index 987fdad..0c81d60 100644 --- a/src/device/device_romstage.c +++ b/src/device/device_romstage.c @@ -28,7 +28,7 @@ #include <device/resource.h> /** Linked list of ALL devices */ -ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root; +ROMSTAGE_CONST struct device *ROMSTAGE_CONST all_devices = &dev_root; /** * Given a PCI bus and a devfn number, find the device structure. diff --git a/src/device/device_util.c b/src/device/device_util.c index d5466cb..2bdaff3 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -37,9 +37,9 @@ * @return Pointer to a device structure for the device on bus at path * or 0/NULL if no device is found. */ -device_t find_dev_path(struct bus *parent, struct device_path *path) +struct device *find_dev_path(struct bus *parent, struct device_path *path) { - device_t child; + struct device *child; for (child = parent->children; child; child = child->sibling) { if (path_eq(path, &child->path)) break; @@ -120,9 +120,10 @@ struct device *dev_find_slot_pnp(u16 port, u16 device) * @param apic_id The Local APIC ID number. * @return Pointer to the device structure (if found), 0 otherwise. */ -device_t dev_find_lapic(unsigned apic_id) +struct device *dev_find_lapic(unsigned apic_id) { - device_t dev, result = NULL; + struct device *dev = NULL; + struct device *result = NULL; for (dev = all_devices; dev; dev = dev->next) { if (dev->path.type == DEVICE_PATH_APIC && @@ -185,7 +186,7 @@ struct device *dev_find_class(unsigned int class, struct device *from) * @param dev The device path to encode. * @return Device path encoded into lower 3 bytes of dword. */ -u32 dev_path_encode(device_t dev) +u32 dev_path_encode(struct device *dev) { u32 ret; @@ -238,7 +239,7 @@ u32 dev_path_encode(device_t dev) * Warning: This function uses a static buffer. Don't call it more than once * from the same print statement! */ -const char *dev_path(device_t dev) +const char *dev_path(struct device *dev) { static char buffer[DEVICE_PATH_MAX]; @@ -308,7 +309,7 @@ const char *dev_path(device_t dev) return buffer; } -const char *dev_name(device_t dev) +const char *dev_name(struct device *dev) { if (dev->name) return dev->name; @@ -405,7 +406,7 @@ static int allocate_more_resources(void) * @param prev TODO * @return TODO. */ -static void free_resource(device_t dev, struct resource *res, +static void free_resource(struct device *dev, struct resource *res, struct resource *prev) { if (prev) @@ -424,7 +425,7 @@ static void free_resource(device_t dev, struct resource *res, * * @param dev The device to find the resource on. */ -void compact_resources(device_t dev) +void compact_resources(struct device *dev) { struct resource *res, *next, *prev = NULL; @@ -445,7 +446,7 @@ void compact_resources(device_t dev) * @param index The index of the resource on the device. * @return The resource, if it already exists. */ -struct resource *probe_resource(device_t dev, unsigned index) +struct resource *probe_resource(struct device *dev, unsigned index) { struct resource *res; @@ -468,7 +469,7 @@ struct resource *probe_resource(device_t dev, unsigned index) * @param index The index of the resource on the device. * @return TODO. */ -struct resource *new_resource(device_t dev, unsigned index) +struct resource *new_resource(struct device *dev, unsigned index) { struct resource *resource, *tail; @@ -515,7 +516,7 @@ struct resource *new_resource(device_t dev, unsigned index) * @param index The index of the resource on the device. * return TODO. */ -struct resource *find_resource(device_t dev, unsigned index) +struct resource *find_resource(struct device *dev, unsigned index) { struct resource *resource; @@ -629,7 +630,7 @@ const char *resource_type(struct resource *resource) * @param resource The resource that was just stored. * @param comment TODO */ -void report_resource_stored(device_t dev, struct resource *resource, +void report_resource_stored(struct device *dev, struct resource *resource, const char *comment) { char buf[10]; @@ -721,7 +722,7 @@ void search_global_resources(unsigned long type_mask, unsigned long type, } } -void dev_set_enabled(device_t dev, int enable) +void dev_set_enabled(struct device *dev, int enable) { if (dev->enabled == enable) return; @@ -736,7 +737,7 @@ void dev_set_enabled(device_t dev, int enable) void disable_children(struct bus *bus) { - device_t child; + struct device *child; for (child = bus->children; child; child = child->sibling) { struct bus *link; @@ -890,7 +891,7 @@ void show_all_devs_resources(int debug_level, const char* msg) } } -void fixed_mem_resource(device_t dev, unsigned long index, +void fixed_mem_resource(struct device *dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type) { struct resource *resource; @@ -939,7 +940,7 @@ u32 find_pci_tolm(struct bus *bus) /* Count of enabled CPUs */ int dev_count_cpu(void) { - device_t cpu; + struct device *cpu; int count = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index d9ab486..030ddea 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -41,9 +41,10 @@ #include <cpu/amd/model_fxx_rev.h> #endif -static device_t ht_scan_get_devs(device_t *old_devices) +static struct device *ht_scan_get_devs(struct device * *old_devices) { - device_t first, last; + struct device *first; + struct device *last; first = *old_devices; last = first; @@ -60,7 +61,7 @@ static device_t ht_scan_get_devs(device_t *old_devices) } if (first) { - device_t child; + struct device *child; /* Unlink the chain from the list of old devices. */ *old_devices = last->sibling; @@ -81,7 +82,7 @@ static device_t ht_scan_get_devs(device_t *old_devices) } #if OPT_HT_LINK == 1 -static unsigned ht_read_freq_cap(device_t dev, unsigned pos) +static unsigned ht_read_freq_cap(struct device *dev, unsigned pos) { /* Handle bugs in valid hypertransport frequency reporting. */ unsigned freq_cap; @@ -126,7 +127,7 @@ struct ht_link { unsigned char ctrl_off, config_off, freq_off, freq_cap_off; }; -static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) +static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned pos) { #if OPT_HT_LINK == 1 static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 }; @@ -420,7 +421,10 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, * optimize link. */ unsigned int next_unitid, last_unitid, min_unitid, max_unitid; - device_t old_devices, dev, func, last_func = 0; + struct device *old_devices; + struct device *dev; + struct device *func; + struct device *last_func = NULL; struct ht_link prev; int ht_dev_num = 0; @@ -433,7 +437,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, */ unsigned int real_last_unitid = 0, end_used = 0; u8 real_last_pos = 0; - device_t real_last_dev = NULL; + struct device *real_last_dev = NULL; #endif /* Restore the hypertransport chain to it's uninitialized state. */ @@ -627,7 +631,7 @@ end_of_chain: * a problem in devicetree.cb. */ if (old_devices) { - device_t left; + struct device *left; for (left = old_devices; left; left = left->sibling) printk(BIOS_DEBUG, "%s\n", dev_path(left)); diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index d27a5f1..86197a8 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -62,7 +62,7 @@ mainboard_interrupt_handlers(int interrupt, yabel_handleIntFunc func) * will look for an ExpansionROM BAR and use the code from there. */ u32 -biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_addr) +biosemu(u8 *biosmem, u32 biosmem_size, struct device *dev, unsigned long rom_addr) { u8 *rom_image; int i = 0; diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index 27d0413..a132946 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -35,7 +35,7 @@ u8* vmem = NULL; extern u8 *biosmem; -void run_bios(struct device * dev, unsigned long addr) +void run_bios(struct device *dev, unsigned long addr) { biosmem = vmem; diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 2f41847..37e6020 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -407,7 +407,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr) } u8 -biosemu_dev_init(struct device * device) +biosemu_dev_init(struct device *device) { u8 rval = 0; //init bios_device struct diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 08189a9..2d38ad7 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -390,7 +390,7 @@ u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size) { u32 rval = 0xFFFFFFFF; - struct device * dev; + struct device *dev; if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { // PCI Configuration Mechanism 1 step 1 // write to 0xCF8, sets bus, device, function and Config Space offset diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 8351e9c..e82cb5c 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -157,7 +157,7 @@ unsigned pci_find_next_capability(struct device *dev, unsigned cap, * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. * @return The next matching capability. */ -unsigned pci_find_capability(device_t dev, unsigned cap) +unsigned pci_find_capability(struct device *dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } @@ -761,7 +761,7 @@ struct device_operations default_pci_ops_bus = { * @param dev Pointer to the device structure of the bridge. * @return Appropriate bridge operations. */ -static struct device_operations *get_pci_bridge_ops(device_t dev) +static struct device_operations *get_pci_bridge_ops(struct device *dev) { #if CONFIG_PCIX_PLUGIN_SUPPORT unsigned int pcixpos; @@ -959,7 +959,7 @@ static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn) * @param devfn A device/function number to look at. * @return The device structure for the device (if found), NULL otherwise. */ -device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) +struct device *pci_probe_dev(struct device * dev, struct bus *bus, unsigned devfn) { u32 id, class; u8 hdr_type; @@ -1066,7 +1066,7 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) * @param sdev Simple device model identifier, created with PCI_DEV(). * @return Non-zero if bus:dev.fn of device matches. */ -unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev) +unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) { return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); @@ -1146,7 +1146,7 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, * There's probably a problem in devicetree.cb. */ if (old_devices) { - device_t left; + struct device *left; printk(BIOS_WARNING, "PCI: Left over static devices:\n"); for (left = old_devices; left; left = left->sibling) printk(BIOS_WARNING, "%s\n", dev_path(left)); @@ -1280,7 +1280,7 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) * @param max The highest bus number assigned up to now. * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); return max; @@ -1326,10 +1326,10 @@ const char *pin_to_str(int pin) * @return The interrupt pin number (1 - 4) that 'dev' will * trigger when generating an interrupt */ -static int swizzle_irq_pins(device_t dev, device_t *parent_bridge) +static int swizzle_irq_pins(struct device *dev, struct device * *parent_bridge) { - device_t parent; /* Our current device's parent device */ - device_t child; /* The child device of the parent */ + struct device *parent; /* Our current device's parent device */ + struct device *child; /* The child device of the parent */ uint8_t parent_bus = 0; /* Parent Bus number */ uint16_t parent_devfn = 0; /* Parent Device and Function number */ uint16_t child_devfn = 0; /* Child Device and Function number */ @@ -1394,7 +1394,7 @@ static int swizzle_irq_pins(device_t dev, device_t *parent_bridge) * Errors: -1 is returned if the device is not enabled * -2 is returned if a parent bridge could not be found. */ -int get_pci_irq_pins(device_t dev, device_t *parent_bdg) +int get_pci_irq_pins(struct device *dev, struct device * *parent_bdg) { uint8_t bus = 0; /* The bus this device is on */ uint16_t devfn = 0; /* This device's device and function numbers */ @@ -1456,7 +1456,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]) { unsigned int funct; - device_t pdev; + struct device *pdev; u8 line, irq; /* Each slot may contain up to eight functions. */ diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 6ddb493..73b4242 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -25,7 +25,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -const struct pci_bus_operations *pci_bus_default_ops(device_t dev) +const struct pci_bus_operations *pci_bus_default_ops(struct device *dev) { #if CONFIG_MMCONF_SUPPORT_DEFAULT return &pci_ops_mmconf; diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 1bdccf0..b7fdde6 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -155,7 +155,7 @@ struct rom_header *pci_rom_load(struct device *dev, */ if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { #if !CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; /* Primary VGA device (device.c). */ + extern struct device *vga_pri; /* Primary VGA device (device.c). */ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ #endif if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 87aea67..a38da40 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -30,7 +30,7 @@ * Re-train a PCIe link */ #define PCIE_TRAIN_RETRY 10000 -static int pciexp_retrain_link(device_t dev, unsigned cap) +static int pciexp_retrain_link(struct device *dev, unsigned cap) { unsigned try = PCIE_TRAIN_RETRY; u16 lnk; @@ -57,8 +57,8 @@ static int pciexp_retrain_link(device_t dev, unsigned cap) * and enable Common Clock Configuration if possible. If CCC is * enabled the link must be retrained. */ -static void pciexp_enable_common_clock(device_t root, unsigned root_cap, - device_t endp, unsigned endp_cap) +static void pciexp_enable_common_clock(struct device *root, unsigned root_cap, + struct device *endp, unsigned endp_cap) { u16 root_scc, endp_scc, lnkctl; @@ -96,8 +96,8 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap, * by checking both root port and endpoint and returning * the highest latency value. */ -static int pciexp_aspm_latency(device_t root, unsigned root_cap, - device_t endp, unsigned endp_cap, +static int pciexp_aspm_latency(struct device *root, unsigned root_cap, + struct device *endp, unsigned endp_cap, enum aspm_type type) { int root_lat = 0, endp_lat = 0; @@ -139,8 +139,8 @@ static int pciexp_aspm_latency(device_t root, unsigned root_cap, * 2 = L1 Enabled * 3 = L0s and L1 Enabled */ -static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, - device_t endp, unsigned endp_cap) +static enum aspm_type pciexp_enable_aspm(struct device *root, unsigned root_cap, + struct device *endp, unsigned endp_cap) { const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; enum aspm_type apmc = PCIE_ASPM_NONE; @@ -182,9 +182,9 @@ static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, } #endif /* CONFIG_PCIEXP_ASPM */ -static void pciexp_tune_dev(device_t dev) +static void pciexp_tune_dev(struct device *dev) { - device_t root = dev->bus->dev; + struct device *root = dev->bus->dev; unsigned int root_cap, cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); @@ -216,7 +216,7 @@ static void pciexp_tune_dev(device_t dev) unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max) { - device_t child; + struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); @@ -230,7 +230,7 @@ unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, return max; } -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) +unsigned int pciexp_scan_bridge(struct device *dev, unsigned int max) { return do_pci_scan_bridge(dev, max, pciexp_scan_bus); } diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index a20c3bf..59355b5 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pcix.h> -static void pcix_tune_dev(device_t dev) +static void pcix_tune_dev(struct device *dev) { u32 status; u16 orig_cmd, cmd; @@ -65,7 +65,7 @@ static void pcix_tune_dev(device_t dev) static void pcix_tune_bus(struct bus *bus) { - device_t child; + struct device *child; for (child = bus->children; child; child = child->sibling) pcix_tune_dev(child); @@ -112,7 +112,7 @@ const char *pcix_speed(u16 sstatus) return result; } -unsigned int pcix_scan_bridge(device_t dev, unsigned int max) +unsigned int pcix_scan_bridge(struct device *dev, unsigned int max) { unsigned int pos; u16 sstatus; diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index e4aa4d3..d49b7a9 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -32,13 +32,13 @@ /* PNP config mode wrappers */ -void pnp_enter_conf_mode(device_t dev) +void pnp_enter_conf_mode(struct device *dev) { if (dev->ops->ops_pnp_mode) dev->ops->ops_pnp_mode->enter_conf_mode(dev); } -void pnp_exit_conf_mode(device_t dev) +void pnp_exit_conf_mode(struct device *dev) { if (dev->ops->ops_pnp_mode) dev->ops->ops_pnp_mode->exit_conf_mode(dev); @@ -46,24 +46,24 @@ void pnp_exit_conf_mode(device_t dev) /* PNP fundamental operations */ -void pnp_write_config(device_t dev, u8 reg, u8 value) +void pnp_write_config(struct device *dev, u8 reg, u8 value) { outb(reg, dev->path.pnp.port); outb(value, dev->path.pnp.port + 1); } -u8 pnp_read_config(device_t dev, u8 reg) +u8 pnp_read_config(struct device *dev, u8 reg) { outb(reg, dev->path.pnp.port); return inb(dev->path.pnp.port + 1); } -void pnp_set_logical_device(device_t dev) +void pnp_set_logical_device(struct device *dev) { pnp_write_config(dev, 0x07, dev->path.pnp.device & 0xff); } -void pnp_set_enable(device_t dev, int enable) +void pnp_set_enable(struct device *dev, int enable) { u8 tmp, bitpos; @@ -80,7 +80,7 @@ void pnp_set_enable(device_t dev, int enable) pnp_write_config(dev, 0x30, tmp); } -int pnp_read_enable(device_t dev) +int pnp_read_enable(struct device *dev) { u8 tmp, bitpos; @@ -92,20 +92,20 @@ int pnp_read_enable(device_t dev) return !!(tmp & (1 << bitpos)); } -void pnp_set_iobase(device_t dev, u8 index, u16 iobase) +void pnp_set_iobase(struct device *dev, u8 index, u16 iobase) { /* Index == 0x60 or 0x62. */ pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); pnp_write_config(dev, index + 1, iobase & 0xff); } -void pnp_set_irq(device_t dev, u8 index, u8 irq) +void pnp_set_irq(struct device *dev, u8 index, u8 irq) { /* Index == 0x70 or 0x72. */ pnp_write_config(dev, index, irq); } -void pnp_set_drq(device_t dev, u8 index, u8 drq) +void pnp_set_drq(struct device *dev, u8 index, u8 drq) { /* Index == 0x74. */ pnp_write_config(dev, index, drq & 0xff); @@ -113,12 +113,12 @@ void pnp_set_drq(device_t dev, u8 index, u8 drq) /* PNP device operations */ -void pnp_read_resources(device_t dev) +void pnp_read_resources(struct device *dev) { return; } -static void pnp_set_resource(device_t dev, struct resource *resource) +static void pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " @@ -144,7 +144,7 @@ static void pnp_set_resource(device_t dev, struct resource *resource) report_resource_stored(dev, resource, ""); } -void pnp_set_resources(device_t dev) +void pnp_set_resources(struct device *dev) { struct resource *res; @@ -160,7 +160,7 @@ void pnp_set_resources(device_t dev) pnp_exit_conf_mode(dev); } -void pnp_enable_resources(device_t dev) +void pnp_enable_resources(struct device *dev) { pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); @@ -168,7 +168,7 @@ void pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -void pnp_enable(device_t dev) +void pnp_enable(struct device *dev) { if (!dev->enabled) { pnp_enter_conf_mode(dev); @@ -178,7 +178,7 @@ void pnp_enable(device_t dev) } } -void pnp_alt_enable(device_t dev) +void pnp_alt_enable(struct device *dev) { pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); @@ -195,7 +195,7 @@ struct device_operations pnp_ops = { /* PNP chip operations */ -static void pnp_get_ioresource(device_t dev, u8 index, struct io_info *info) +static void pnp_get_ioresource(struct device *dev, u8 index, struct io_info *info) { struct resource *resource; unsigned moving, gran, step; @@ -246,7 +246,7 @@ static void pnp_get_ioresource(device_t dev, u8 index, struct io_info *info) resource->size = 1 << gran; } -static void get_resources(device_t dev, struct pnp_info *info) +static void get_resources(struct device *dev, struct pnp_info *info) { struct resource *resource; @@ -312,11 +312,11 @@ static void get_resources(device_t dev, struct pnp_info *info) } } -void pnp_enable_devices(device_t base_dev, struct device_operations *ops, +void pnp_enable_devices(struct device *base_dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info) { struct device_path path; - device_t dev; + struct device *dev; int i; path.type = DEVICE_PATH_PNP; diff --git a/src/device/root_device.c b/src/device/root_device.c index 49fa711..fb32151 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -35,7 +35,7 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * * @param root Pointer to the device structure for the system root device. */ -static void root_dev_read_resources(device_t root) +static void root_dev_read_resources(struct device *root) { printk(BIOS_ERR, "%s should never be called.\n", __func__); } @@ -48,7 +48,7 @@ static void root_dev_read_resources(device_t root) * * @param root Pointer to the device structure for the system root device. */ -static void root_dev_set_resources(device_t root) +static void root_dev_set_resources(struct device *root) { printk(BIOS_ERR, "%s should never be called.\n", __func__); } @@ -76,9 +76,9 @@ static void root_dev_set_resources(device_t root) * @return The largest bus number used. */ static int smbus_max = 0; -unsigned int scan_static_bus(device_t bus, unsigned int max) +unsigned int scan_static_bus(struct device *bus, unsigned int max) { - device_t child; + struct device *child; struct bus *link; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); @@ -121,7 +121,7 @@ unsigned int scan_static_bus(device_t bus, unsigned int max) return max; } -static void root_dev_enable_resources(device_t dev) +static void root_dev_enable_resources(struct device *dev) { } @@ -134,12 +134,12 @@ static void root_dev_enable_resources(device_t dev) * @param max The current bus number scanned so far, usually 0x00. * @return The largest bus number used. */ -static unsigned int root_dev_scan_bus(device_t root, unsigned int max) +static unsigned int root_dev_scan_bus(struct device *root, unsigned int max) { return scan_static_bus(root, max); } -static void root_dev_init(device_t root) +static void root_dev_init(struct device *root) { } diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c index 41b31ed..547d144 100644 --- a/src/device/smbus_ops.c +++ b/src/device/smbus_ops.c @@ -25,7 +25,7 @@ #include <device/path.h> #include <device/smbus.h> -struct bus *get_pbus_smbus(device_t dev) +struct bus *get_pbus_smbus(struct device *dev) { struct bus *pbus = dev->bus; @@ -51,7 +51,7 @@ struct bus *get_pbus_smbus(device_t dev) * * @param dev TODO. */ -int smbus_set_link(device_t dev) +int smbus_set_link(struct device *dev) { struct bus *pbus_a[4]; // 4 level mux only. Enough? struct bus *pbus = dev->bus; @@ -87,70 +87,70 @@ int smbus_set_link(device_t dev) } -int smbus_quick_read(device_t dev) +int smbus_quick_read(struct device *dev) { CHECK_PRESENCE(quick_read); return ops_smbus_bus(get_pbus_smbus(dev))->quick_read(dev); } -int smbus_quick_write(device_t dev) +int smbus_quick_write(struct device *dev) { CHECK_PRESENCE(quick_write); return ops_smbus_bus(get_pbus_smbus(dev))->quick_write(dev); } -int smbus_recv_byte(device_t dev) +int smbus_recv_byte(struct device *dev) { CHECK_PRESENCE(recv_byte); return ops_smbus_bus(get_pbus_smbus(dev))->recv_byte(dev); } -int smbus_send_byte(device_t dev, u8 byte) +int smbus_send_byte(struct device *dev, u8 byte) { CHECK_PRESENCE(send_byte); return ops_smbus_bus(get_pbus_smbus(dev))->send_byte(dev, byte); } -int smbus_read_byte(device_t dev, u8 addr) +int smbus_read_byte(struct device *dev, u8 addr) { CHECK_PRESENCE(read_byte); return ops_smbus_bus(get_pbus_smbus(dev))->read_byte(dev, addr); } -int smbus_write_byte(device_t dev, u8 addr, u8 val) +int smbus_write_byte(struct device *dev, u8 addr, u8 val) { CHECK_PRESENCE(write_byte); return ops_smbus_bus(get_pbus_smbus(dev))->write_byte(dev, addr, val); } -int smbus_read_word(device_t dev, u8 addr) +int smbus_read_word(struct device *dev, u8 addr) { CHECK_PRESENCE(read_word); return ops_smbus_bus(get_pbus_smbus(dev))->read_word(dev, addr); } -int smbus_write_word(device_t dev, u8 addr, u16 val) +int smbus_write_word(struct device *dev, u8 addr, u16 val) { CHECK_PRESENCE(write_word); return ops_smbus_bus(get_pbus_smbus(dev))->write_word(dev, addr, val); } -int smbus_process_call(device_t dev, u8 cmd, u16 data) +int smbus_process_call(struct device *dev, u8 cmd, u16 data) { CHECK_PRESENCE(process_call); return ops_smbus_bus(get_pbus_smbus(dev))->process_call(dev, cmd, data); } -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer) +int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer) { CHECK_PRESENCE(block_read); @@ -158,7 +158,7 @@ int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer) bytes, buffer); } -int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer) +int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer) { CHECK_PRESENCE(block_write); diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 1e85596..c3ef4e9 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -1,4 +1,5 @@ #include <arch/cpu.h> +#include <arch/io.h> int init_processor_name(void); @@ -59,7 +60,7 @@ static int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,2); val_old = pci_read_config32(dev, 0x80); val = val_old; @@ -101,7 +102,7 @@ static inline int is_cpu_pre_f2(void) static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; @@ -109,7 +110,7 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff0f) < 0x40f02; diff --git a/src/include/device/agp.h b/src/include/device/agp.h index be2b833..b3791fe 100644 --- a/src/include/device/agp.h +++ b/src/include/device/agp.h @@ -7,7 +7,7 @@ unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); -unsigned int agp_scan_bridge(device_t dev, unsigned int max); +unsigned int agp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_agp_ops_bus; diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h index 45ae24f..4443c15 100644 --- a/src/include/device/cardbus.h +++ b/src/include/device/cardbus.h @@ -5,8 +5,8 @@ #include <device/device.h> -void cardbus_read_resources(device_t dev); -void cardbus_enable_resources(device_t dev); +void cardbus_read_resources(struct device *dev); +void cardbus_enable_resources(struct device *dev); extern struct device_operations default_cardbus_ops_bus; diff --git a/src/include/device/device.h b/src/include/device/device.h index c67205c..fe8dbed 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -41,19 +41,19 @@ struct smbios_type11; struct acpi_rsdp; struct device_operations { - void (*read_resources)(device_t dev); - void (*set_resources)(device_t dev); - void (*enable_resources)(device_t dev); - void (*init)(device_t dev); - void (*final)(device_t dev); - unsigned int (*scan_bus)(device_t bus, unsigned int _max); - void (*enable)(device_t dev); - void (*disable)(device_t dev); - void (*set_link)(device_t dev, unsigned int link); + void (*read_resources)(struct device *dev); + void (*set_resources)(struct device *dev); + void (*enable_resources)(struct device *dev); + void (*init)(struct device *dev); + void (*final)(struct device *dev); + unsigned int (*scan_bus)(struct device *bus, unsigned int _max); + void (*enable)(struct device *dev); + void (*disable)(struct device *dev); + void (*set_link)(struct device *dev, unsigned int link); void (*reset_bus)(struct bus *bus); #if CONFIG_GENERATE_SMBIOS_TABLES - int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); - void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); + int (*get_smbios_data)(struct device *dev, int *handle, unsigned long *current); + void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); @@ -62,7 +62,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); + const struct pci_bus_operations * (*ops_pci_bus)(struct device *dev); const struct pnp_mode_ops *ops_pnp_mode; }; @@ -76,9 +76,8 @@ static inline void device_noop(struct device *dev) {} struct bus { - - ROMSTAGE_CONST struct device * dev; /* This bridge device */ - ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct device *dev; /* This bridge device */ + ROMSTAGE_CONST struct device *children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ @@ -98,7 +97,7 @@ struct pci_irq_info { unsigned int ioapic_irq_pin; unsigned int ioapic_src_pin; unsigned int ioapic_dst_id; - unsigned int ioapic_flags; + unsigned int ioapic_flags; }; struct device { @@ -159,7 +158,7 @@ extern uint64_t uma_memory_size; #endif /* Generic device interface functions */ -device_t alloc_dev(struct bus *parent, struct device_path *path); +struct device *alloc_dev(struct bus *parent, struct device_path *path); void dev_initialize_chips(void); void dev_enumerate(void); void dev_configure(void); @@ -175,30 +174,30 @@ unsigned int scan_bus(struct device *bus, unsigned int _max); void assign_resources(struct bus *bus); void enumerate_static_device(void); void enumerate_static_devices(void); -const char *dev_name(device_t dev); -const char *dev_path(device_t dev); -u32 dev_path_encode(device_t dev); +const char *dev_name(struct device *dev); +const char *dev_path(struct device *dev); +u32 dev_path_encode(struct device *dev); const char *bus_path(struct bus *bus); -void dev_set_enabled(device_t dev, int enable); +void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); /* Option ROM helper functions */ void run_bios(struct device *dev, unsigned long addr); /* Helper functions */ -device_t find_dev_path(struct bus *parent, struct device_path *path); -device_t alloc_find_dev(struct bus *parent, struct device_path *path); -device_t dev_find_device (u16 vendor, u16 device, device_t from); -device_t dev_find_class (unsigned int class, device_t from); -device_t dev_find_slot (unsigned int bus, unsigned int devfn); -device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); -device_t dev_find_slot_pnp(u16 port, u16 device); -device_t dev_find_lapic(unsigned apic_id); +struct device *find_dev_path(struct bus *parent, struct device_path *path); +struct device *alloc_find_dev(struct bus *parent, struct device_path *path); +struct device *dev_find_device (u16 vendor, u16 device, struct device *from); +struct device *dev_find_class (unsigned int class, struct device *from); +struct device *dev_find_slot (unsigned int bus, unsigned int devfn); +struct device *dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +struct device *dev_find_slot_pnp(u16 port, u16 device); +struct device *dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); void remap_bsp_lapic(struct bus *cpu_bus); -device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); -void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread); +struct device *add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); +void set_cpu_topology(struct device *cpu, unsigned node, unsigned package, unsigned core, unsigned thread); #define amd_cpu_topology(cpu, node, core) \ set_cpu_topology(cpu, node, 0, core, 0) @@ -207,7 +206,7 @@ void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned co set_cpu_topology(cpu, 0, package, core, thread) /* Debug functions */ -void print_resource_tree(struct device * root, int debug_level, +void print_resource_tree(struct device *root, int debug_level, const char *msg); void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum); void show_devs_subtree(struct device *root, int debug_level, const char *msg); @@ -226,9 +225,9 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); -unsigned int scan_static_bus(device_t bus, unsigned int _max); +unsigned int scan_static_bus(struct device *bus, unsigned int _max); -void fixed_mem_resource(device_t dev, unsigned long index, +void fixed_mem_resource(struct device *dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); @@ -257,7 +256,7 @@ u32 find_pci_tolm(struct bus *bus); ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); -ROMSTAGE_CONST struct device *dev_find_next_pci_device( +ROMSTAGE_CONST struct device * dev_find_next_pci_device( ROMSTAGE_CONST struct device *previous_dev); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 0670da4..3688322 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -32,7 +32,7 @@ /* Common pci operations without a standard interface */ struct pci_operations { /* set the Subsystem IDs for the PCI device */ - void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device); + void (*set_subsystem)(struct device *dev, unsigned vendor, unsigned device); }; /* Common pci bus operations */ @@ -62,35 +62,35 @@ extern struct pci_driver epci_drivers[]; extern struct device_operations default_pci_ops_dev; extern struct device_operations default_pci_ops_bus; -void pci_dev_read_resources(device_t dev); -void pci_bus_read_resources(device_t dev); -void pci_dev_set_resources(device_t dev); -void pci_dev_enable_resources(device_t dev); -void pci_bus_enable_resources(device_t dev); +void pci_dev_read_resources(struct device *dev); +void pci_bus_read_resources(struct device *dev); +void pci_dev_set_resources(struct device *dev); +void pci_dev_enable_resources(struct device *dev); +void pci_bus_enable_resources(struct device *dev); void pci_bus_reset(struct bus *bus); -device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); -unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, +struct device *pci_probe_dev(struct device *dev, struct bus *bus, unsigned devfn); +unsigned int do_pci_scan_bridge(struct device *bus, unsigned int max, unsigned int (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max)); -unsigned int pci_scan_bridge(device_t bus, unsigned int max); +unsigned int pci_scan_bridge(struct device *bus, unsigned int max); unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); struct resource *pci_get_resource(struct device *dev, unsigned long index); -void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); +void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); -unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev); +unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev); const char * pin_to_str(int pin); -int get_pci_irq_pins(device_t dev, device_t *parent_bdg); +int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -static inline const struct pci_operations *ops_pci(device_t dev) +static inline const struct pci_operations *ops_pci(struct device *dev) { const struct pci_operations *pops; pops = 0; @@ -106,8 +106,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); #else /* !__PRE_RAM__ */ -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); -unsigned pci_find_capability(device_t dev, unsigned cap); +unsigned pci_find_next_capability(struct device *dev, unsigned cap, unsigned last); +unsigned pci_find_capability(struct device *dev, unsigned cap); #endif /* __PRE_RAM__ */ void pci_early_bridge_init(void); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 87a5002..c7ff4f5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -11,7 +11,7 @@ enum aspm_type { unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); +unsigned int pciexp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 4ffab5b..8cc83df 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -4,7 +4,7 @@ unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pcix_scan_bridge(device_t dev, unsigned int max); +unsigned int pcix_scan_bridge(struct device *dev, unsigned int max); const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index d0d6fa3..9290056 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -9,21 +9,21 @@ #ifndef __SIMPLE_DEVICE__ /* Primitive PNP resource manipulation */ -void pnp_write_config(device_t dev, u8 reg, u8 value); -u8 pnp_read_config(device_t dev, u8 reg); -void pnp_set_logical_device(device_t dev); -void pnp_set_enable(device_t dev, int enable); -int pnp_read_enable(device_t dev); -void pnp_set_iobase(device_t dev, u8 index, u16 iobase); -void pnp_set_irq(device_t dev, u8 index, u8 irq); -void pnp_set_drq(device_t dev, u8 index, u8 drq); +void pnp_write_config(struct device *dev, u8 reg, u8 value); +u8 pnp_read_config(struct device *dev, u8 reg); +void pnp_set_logical_device(struct device *dev); +void pnp_set_enable(struct device *dev, int enable); +int pnp_read_enable(struct device *dev); +void pnp_set_iobase(struct device *dev, u8 index, u16 iobase); +void pnp_set_irq(struct device *dev, u8 index, u8 irq); +void pnp_set_drq(struct device *dev, u8 index, u8 drq); /* PNP device operations */ -void pnp_read_resources(device_t dev); -void pnp_set_resources(device_t dev); -void pnp_enable_resources(device_t dev); -void pnp_enable(device_t dev); -void pnp_alt_enable(device_t dev); +void pnp_read_resources(struct device *dev); +void pnp_set_resources(struct device *dev); +void pnp_enable_resources(struct device *dev); +void pnp_enable(struct device *dev); +void pnp_alt_enable(struct device *dev); extern struct device_operations pnp_ops; @@ -52,16 +52,16 @@ struct pnp_info { #define PNP_MSC10 0x1000 struct io_info io0, io1, io2, io3; }; -struct resource *pnp_get_resource(device_t dev, unsigned index); +struct resource *pnp_get_resource(struct device *dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); struct pnp_mode_ops { - void (*enter_conf_mode)(device_t dev); - void (*exit_conf_mode)(device_t dev); + void (*enter_conf_mode)(struct device *dev); + void (*exit_conf_mode)(struct device *dev); }; -void pnp_enter_conf_mode(device_t dev); -void pnp_exit_conf_mode(device_t dev); +void pnp_enter_conf_mode(struct device *dev); +void pnp_exit_conf_mode(struct device *dev); #endif /* ! __SIMPLE_DEVICE__ */ -#endif /* DEVICE_PNP_H */ +#endif /*devICE_PNP_H */ diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 073d7e2..7002459 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -8,17 +8,17 @@ /* Common SMBus bus operations */ struct smbus_bus_operations { - int (*quick_read) (device_t dev); - int (*quick_write) (device_t dev); - int (*recv_byte) (device_t dev); - int (*send_byte) (device_t dev, u8 value); - int (*read_byte) (device_t dev, u8 addr); - int (*write_byte) (device_t dev, u8 addr, u8 value); - int (*read_word) (device_t dev, u8 addr); - int (*write_word) (device_t dev, u8 addr, u16 value); - int (*process_call)(device_t dev, u8 cmd, u16 data); - int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer); - int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer); + int (*quick_read) (struct device *dev); + int (*quick_write) (struct device *dev); + int (*recv_byte) (struct device *dev); + int (*send_byte) (struct device *dev, u8 value); + int (*read_byte) (struct device *dev, u8 addr); + int (*write_byte) (struct device *dev, u8 addr, u8 value); + int (*read_word) (struct device *dev, u8 addr); + int (*write_word) (struct device *dev, u8 addr, u16 value); + int (*process_call)(struct device *dev, u8 cmd, u16 data); + int (*block_read) (struct device *dev, u8 cmd, u8 bytes, u8 *buffer); + int (*block_write) (struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); }; static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) @@ -32,19 +32,19 @@ static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) return bops; } -struct bus *get_pbus_smbus(device_t dev); -int smbus_set_link(device_t dev); - -int smbus_quick_read(device_t dev); -int smbus_quick_write(device_t dev); -int smbus_recv_byte(device_t dev); -int smbus_send_byte(device_t dev, u8 byte); -int smbus_read_byte(device_t dev, u8 addr); -int smbus_write_byte(device_t dev, u8 addr, u8 val); -int smbus_read_word(device_t dev, u8 addr); -int smbus_write_word(device_t dev, u8 addr, u16 val); -int smbus_process_call(device_t dev, u8 cmd, u16 data); -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); -int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); - -#endif /* DEVICE_SMBUS_H */ +struct bus *get_pbus_smbus(struct device *dev); +int smbus_set_link(struct device *dev); + +int smbus_quick_read(struct device *dev); +int smbus_quick_write(struct device *dev); +int smbus_recv_byte(struct device *dev); +int smbus_send_byte(struct device *dev, u8 byte); +int smbus_read_byte(struct device *dev, u8 addr); +int smbus_write_byte(struct device *dev, u8 addr, u8 val); +int smbus_read_word(struct device *dev, u8 addr); +int smbus_write_word(struct device *dev, u8 addr, u16 val); +int smbus_process_call(struct device *dev, u8 cmd, u16 data); +int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); + +#endif /*devICE_SMBUS_H */

1 0

Patch set updated for coreboot: 9d5ea38 southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 9d5ea389ffdb7dcf40dc3d8c0fff267d1e773125 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/via/vt8231/early_serial.c | 2 +- src/southbridge/via/vt82c686/early_serial.c | 4 ++-- 31 files changed, 96 insertions(+), 96 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..ce22d34 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..86e4f89 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..5cf1376 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device * dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..ddcb44c 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..e5783e7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + struct device * dev; ich9_spi_regs *ich9_spi; uint16_t hsfs; diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..c4e8a1c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + struct device * dev; uint32_t ids; uint16_t vendor_id, device_id; diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..a48401f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device * dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device * dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device * dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device * dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..ebf2a01 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device * dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device * dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device * dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c index a0aec65..8c500b9 100644 --- a/src/southbridge/via/vt8231/early_serial.c +++ b/src/southbridge/via/vt8231/early_serial.c @@ -33,7 +33,7 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) static void enable_vt8231_serial(void) { uint8_t c; - device_t dev; + pnp_devfn_t dev; post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 55742a7..9cdf943 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -48,10 +48,10 @@ static void vt82c686_sio_write(uint8_t index, uint8_t value) * @param dev TODO * @param iobase TODO */ -static void vt82c686_enable_serial(device_t dev, unsigned iobase) +static void vt82c686_enable_serial(pnp_devfn_t dev, unsigned iobase) { uint8_t reg; - device_t sbdev; + pnp_devfn_t sbdev; /* TODO: Use info from 'dev' and 'iobase'. */ /* TODO: Only enable one serial port (depending on config) or both? */

1 0

Patch set updated for coreboot: afc817c soc: Don't hide pointers behind typedefs
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7277 -gerrit commit afc817c1f1097bfbcebcb0b1b4036397a27de919 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 23:00:45 2014 +1100 soc: Don't hide pointers behind typedefs Change-Id: I05bb3b09cd1059cf43905a310f5c1ba04ed32336 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/baytrail/chip.c | 6 ++--- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 4 ++-- src/soc/intel/baytrail/emmc.c | 2 +- src/soc/intel/baytrail/gfx.c | 14 +++++------ src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/lpe.c | 12 +++++----- src/soc/intel/baytrail/lpss.c | 10 ++++---- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 14 +++++------ src/soc/intel/baytrail/pmutil.c | 8 +++---- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/sata.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/sd.c | 2 +- src/soc/intel/baytrail/smihandler.c | 2 +- src/soc/intel/baytrail/southcluster.c | 24 +++++++++---------- src/soc/intel/baytrail/spi.c | 6 ++--- src/soc/intel/baytrail/xhci.c | 6 ++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/broadwell/me.h | 2 +- src/soc/intel/broadwell/broadwell/pch.h | 2 +- src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++-- src/soc/intel/broadwell/broadwell/xhci.h | 2 +- src/soc/intel/broadwell/chip.c | 6 ++--- src/soc/intel/broadwell/cpu.c | 6 ++--- src/soc/intel/broadwell/ehci.c | 2 +- src/soc/intel/broadwell/lpc.c | 18 +++++++-------- src/soc/intel/broadwell/me.c | 24 +++++++++---------- src/soc/intel/broadwell/pch.c | 6 ++--- src/soc/intel/broadwell/pcie.c | 32 +++++++++++++------------- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/smbus.c | 8 +++---- src/soc/intel/broadwell/smihandler.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 6 ++--- src/soc/intel/broadwell/spi.c | 2 +- src/soc/intel/broadwell/systemagent.c | 22 +++++++++--------- src/soc/intel/broadwell/xhci.c | 8 +++---- src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/fsp_baytrail/chip.c | 8 +++---- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +++---- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 2 +- src/soc/intel/fsp_baytrail/smihandler.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++----------- src/soc/intel/fsp_baytrail/spi.c | 6 ++--- src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/soc.c | 6 ++--- src/soc/samsung/exynos5250/cpu.c | 8 +++---- src/soc/samsung/exynos5420/cpu.c | 8 +++---- 55 files changed, 191 insertions(+), 191 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index a8b5fdc..4a7b536 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -26,16 +26,16 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); +void southcluster_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 7a5b9c2..a29bef2 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -26,7 +26,7 @@ #include <baytrail/ramstage.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -49,7 +49,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -77,7 +77,7 @@ struct chip_operations soc_intel_baytrail_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e8f95ae..a5106dd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -78,7 +78,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -121,7 +121,7 @@ void baytrail_init_cpus(device_t dev) restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..accfed2 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = { REG_SCRIPT_END }; -static void usb2_phy_init(device_t dev) +static void usb2_phy_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev) reg_script_run(usb2_phy_script); } -static void ehci_init(device_t dev) +static void ehci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..74bdb4b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; -static void emmc_init(device_t dev) +static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 9d4768f..a47152d 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -38,7 +38,7 @@ * Lock Power Context Base Register to point to a 24KB block * of memory in GSM. Power context save data is stored here. */ -static void gfx_lock_pcbase(device_t dev) +static void gfx_lock_pcbase(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, @@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } -static void gfx_pre_vbios_init(device_t dev) +static void gfx_pre_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) +static void gfx_pm_init(struct device *dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); gfx_run_script(dev, gfx_init_script); @@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev) gfx_lock_pcbase(dev); } -static void gfx_post_vbios_init(device_t dev) +static void gfx_post_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void gfx_panel_setup(device_t dev) +static void gfx_panel_setup(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { @@ -340,7 +340,7 @@ static void gfx_panel_setup(device_t dev) } } -static void gfx_init(device_t dev) +static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..5733b95 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = { 0x20671f58, }; -static void hda_init(device_t dev) +static void hda_init(struct device *dev) { struct resource *res; int codec_mask; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..b6fb7c2 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -45,7 +45,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) { struct resource *res; @@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index) *field = res->base; } -static void lpe_enable_acpi_mode(device_t dev) +static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev) reg_script_run_on_dev(dev, ops); } -static void setup_codec_clock(device_t dev) +static void setup_codec_clock(struct device *dev) { uint32_t reg; int clk_reg; @@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } -static void lpe_stash_firmware_info(device_t dev) +static void lpe_stash_firmware_info(struct device *dev) { struct resource *res; struct resource *mmio; @@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev) } } -static void lpe_init(device_t dev) +static void lpe_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -161,7 +161,7 @@ static void lpe_init(device_t dev) lpe_enable_acpi_mode(dev); } -static void lpe_read_resources(device_t dev) +static void lpe_read_resources(struct device *dev) { pci_dev_read_resources(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..c548370 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -33,7 +33,7 @@ #include "chip.h" -static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, @@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; @@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(device_t dev) +static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { @@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev) } } -static void lpss_init(device_t dev) +static void lpss_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; int iosf_reg, nvs_index; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b119e24..2d4f20b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 4498f43..e530498 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -34,12 +34,12 @@ static int pll_en_off; static uint32_t strpfusecfg; -static inline int root_port_offset(device_t dev) +static inline int root_port_offset(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn); } -static inline int is_first_port(device_t dev) +static inline int is_first_port(struct device *dev) { return root_port_offset(dev) == PCIE_PORT1_FUNC; } @@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void byt_pcie_init(struct device *dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), @@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = { REG_SCRIPT_END, }; -static void check_port_enabled(device_t dev) +static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; @@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev) } } -static void check_device_present(device_t dev) +static void check_device_present(struct device *dev) { /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -172,7 +172,7 @@ static void check_device_present(device_t dev) } } -static void byt_pcie_enable(device_t dev) +static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did) { uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..935253c 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline pci_devfn_t get_pcu_dev(void) { return pcu_dev; } @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..10f7ff2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -78,7 +78,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8c..3c69985 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -159,7 +159,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { config_t *config = dev->chip_info; u8 reg8; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..e2bd1dd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -87,7 +87,7 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..6068e61 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -34,7 +34,7 @@ #define CAP_OVERRIDE_HIGH 0xa4 # define USE_CAP_OVERRIDES (1 << 31) -static void sd_init(device_t dev) +static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 22b60c4..94e6d81 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 500a13d..d3d284d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -43,12 +43,12 @@ #include "chip.h" static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; @@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -154,7 +154,7 @@ static void sc_rtc_init(void) * or configuration. This is definitely a hack, but it helps the kernel * along. */ -static void com1_configure_resume(device_t dev) +static void com1_configure_resume(struct device *dev) { const uint16_t port = 0x3f8; @@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev) outb(3, port + UART8250_LCR); } -static void sc_init(device_t dev) +static void sc_init(struct device *dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; @@ -224,7 +224,7 @@ static void sc_init(device_t dev) */ /* Set bit in function disble register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -362,7 +362,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8677b61..112b878 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -290,13 +290,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is stage dependent typed */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..3f3ed91 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = { }; /* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) +static void xhci_reset_port_usb3(struct device *dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ @@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port) } /* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) +static void xhci_route_all(struct device *dev) { static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ @@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev) } } -static void xhci_init(device_t dev) +static void xhci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f4cac7b..3259308 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package) static int generate_C_state_entries(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index ddecaf8..f3021ee 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -465,7 +465,7 @@ typedef struct { } __attribute__ ((packed)) mbp_plat_time; typedef struct { - u32 device_type : 2; + u32 struct device *ype : 2; u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data; diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index e677215..c58b695 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -47,6 +47,6 @@ int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h index 685de14..d66e8cc 100644 --- a/src/soc/intel/broadwell/broadwell/ramstage.h +++ b/src/soc/intel/broadwell/broadwell/ramstage.h @@ -24,8 +24,8 @@ #include <chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(device_t dev); -void broadwell_pch_enable_dev(device_t dev); +void broadwell_init_cpus(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h index 3f4fb4e..a5536fc 100644 --- a/src/soc/intel/broadwell/broadwell/xhci.h +++ b/src/soc/intel/broadwell/broadwell/xhci.h @@ -55,7 +55,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 2a12820..ef19e8e 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -24,7 +24,7 @@ #include <broadwell/ramstage.h> #include <chip.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -43,7 +43,7 @@ static struct device_operations cpu_bus_ops = { .init = &broadwell_init_cpus, }; -static void broadwell_enable(device_t dev) +static void broadwell_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -65,7 +65,7 @@ struct chip_operations soc_intel_broadwell_ops = { .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 58f81fc..416fe3c 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -444,7 +444,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; msr_t msr; @@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void cpu_core_init(device_t cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void broadwell_init_cpus(device_t dev) +void broadwell_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; int num_threads; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index a59d3c8..30f4acd 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -28,7 +28,7 @@ #include <broadwell/ehci.h> #include <broadwell/pch.h> -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { u8 access_cntl; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 4b21326..270316c 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u16 reg16; const char *state; @@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev) RCBA32_OR(0x3a6c, 0x00000001); } -static void pch_cg_init(device_t dev) +static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; @@ -420,7 +420,7 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 15bcc34..19bc754 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); /* MMIO base address for MEI interface */ static u32 mei_base_address; -void intel_me_mbp_clear(device_t dev); +void intel_me_mbp_clear(struct device *dev); #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +static void intel_me_mbp_give_up(struct device *dev) { struct mei_csr csr; @@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev) * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +void intel_me_mbp_clear(struct device *dev) { int count; struct me_hfs2 hfs2; @@ -568,7 +568,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(void) { - device_t dev = PCH_DEV_ME; + struct device *dev = PCH_DEV_ME; struct me_hfs hfs; u32 reg32; @@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev) } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { config_t *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -829,7 +829,7 @@ static void intel_me_init(device_t dev) */ } -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ @@ -882,7 +882,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 82390a4..e681620 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id) #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev) } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c..08e4863 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -32,8 +32,8 @@ #include <broadwell/rcba.h> #include <chip.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or); +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or); /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -52,23 +52,23 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[NUM_ROOT_PORTS]; + struct device *ports[NUM_ROOT_PORTS]; }; static struct root_port_config rpc; -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void) int enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -244,7 +244,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -297,7 +297,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; @@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 8214a8a..2517fef 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -52,7 +52,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + struct device *dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e8d1fbe..24a8ebe 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -221,7 +221,7 @@ static void sata_init(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index a1dbdfe..c214510 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -31,7 +31,7 @@ #include <broadwell/ramstage.h> #include <broadwell/smbus.h> -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_BASE_ADDRESS; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 6acd07c..49cf774 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index bd1fc26..9ba6a00 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; int num_cpus; msr_t msr; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 353323a..6095cf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -286,7 +286,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; + struct device *dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi; pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 2b3ce41..d940e33 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -37,7 +37,7 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -184,7 +184,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } -static void systemagent_read_resources(device_t dev) +static void systemagent_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) +static void systemagent_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 89e1139..9530422 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -27,7 +27,7 @@ #include <broadwell/xhci.h> #ifdef __SMM__ -static u32 usb_xhci_mem_base(device_t dev) +static u32 usb_xhci_mem_base(struct device *dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(struct device *dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(struct device *dev, int all) { u32 status, port_disabled; int timeout, port; @@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ) { u16 reg16; u32 reg32; diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a2377..d991d34 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -57,7 +57,7 @@ void rangeley_early_initialization(void); int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); +void soc_enable(struct device *dev); /* debugging functions */ void print_pci_devices(void); diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h index 095f09c..c1114df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -25,10 +25,10 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void southcluster_enable_dev(struct device *dev); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 732d1dc..5b54874 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -25,12 +25,12 @@ #include <drivers/intel/fsp/fsp_util.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -58,7 +58,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", dev_name(dev), dev->path.type); @@ -98,7 +98,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { .final = &finalize_chip, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 6f1e9c4..5c6375e 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev) } } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..010063e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 bmbound, bsmmrrl; int index = 0; @@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void nc_enable(device_t dev) +static void nc_enable(struct device *dev) { print_fsp_info(); } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..55abb4d 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -76,7 +76,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2225964..50b6ef4 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..307b006 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -51,12 +51,12 @@ typedef struct soc_intel_fsp_baytrail_config config_t; static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { #ifndef CONFIG_VIRTUAL_ROM_SIZE #error CONFIG_VIRTUAL_ROM_SIZE must be set. @@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -255,7 +255,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void sc_pirq_init(device_t dev) +static void sc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -409,7 +409,7 @@ static void sc_init(struct device *dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -534,7 +534,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4feb502..295e203 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -288,13 +288,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is type-dependent on stage */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 48ffbda..895fd89 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -567,7 +567,7 @@ struct disp_ctl_win { u32 out_h; /* Height of output window in pixels */ }; -void display_startup(device_t dev); +void display_startup(struct device *dev); void dp_bringup(u32 winb_addr); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 00dfbb6..9cc0cf0 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -234,7 +234,7 @@ uint32_t fb_base_mb(void) /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ -void display_startup(device_t dev) +void display_startup(struct device *dev) { u32 val; int i; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 8ad1aa9..5d95110 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -29,7 +29,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(device_t dev) +static void soc_enable(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -39,7 +39,7 @@ static void soc_enable(device_t dev) mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { display_startup(dev); printk(BIOS_INFO, "CPU: Tegra124\n"); @@ -53,7 +53,7 @@ static struct device_operations soc_ops = { .scan_bus = 0, }; -static void enable_tegra124_dev(device_t dev) +static void enable_tegra124_dev(struct device *dev) { dev->ops = &soc_ops; } diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 60fa55a..639a45a 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -59,7 +59,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5250_config *conf = dev->chip_info; @@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -123,7 +123,7 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); @@ -137,7 +137,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_exynos5250_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index c904636..1f4d739 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -73,7 +73,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5420_config *conf = dev->chip_info; @@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index) } } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -154,7 +154,7 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / 1000000); @@ -168,7 +168,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5420_dev(device_t dev) +static void enable_exynos5420_dev(struct device *dev) { dev->ops = &cpu_ops; }

1 0

Patch set updated for coreboot: 34483e8 mainboard/packardbell/ms2290: Missing romstage header
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7235 -gerrit commit 34483e8b72a44e04a734a1658e1706ae9dcfcee0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 29 07:56:04 2014 +1100 mainboard/packardbell/ms2290: Missing romstage header cpu/intel/romstage.h is needed so the the main() has a prototype in freestanding. Change-Id: I5e6afef82a4f63ab42927725adf3881084a1e25c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/packardbell/ms2290/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index c4a278e..d33a9ba 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -38,6 +38,7 @@ #include <timestamp.h> #include <arch/acpi.h> #include <cbmem.h> +#include <cpu/intel/romstage.h> #include "arch/early_variables.h" #include "southbridge/intel/ibexpeak/pch.h"

1 0

Patch set updated for coreboot: ac3988c gigabyte/ga-b75m-d3h: Add new Intel mainboard
by Damien Zammit 05 Nov '14

05 Nov '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7341 -gerrit commit ac3988cd1366f463860e29c5cf9edde4f896aa5f Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Oct 23 22:06:38 2014 +1100 gigabyte/ga-b75m-d3h: Add new Intel mainboard This is based on LENOVO X230 port. Board boots to linux via SATA or USB. All USB ports are working. NB: This patch depends on WIP 3 common FADT patches 7201, 7200, 7199 and automatic interrupt handling patch 7130 Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/Kconfig | 3 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 83 ++++ src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 21 + src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl | 1 + .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 28 ++ .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 73 ++++ .../gigabyte/ga-b75m-d3h/acpi/superio.asl | 24 ++ .../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 65 ++++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl | 1 + src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 83 ++++ src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt | 6 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.default | 9 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 152 ++++++++ src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 139 +++++++ src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 24 ++ src/mainboard/gigabyte/ga-b75m-d3h/gpio.c | 433 +++++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 8 + src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 110 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c | 109 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/onboard.h | 25 ++ src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 209 ++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 30 ++ 22 files changed, 1636 insertions(+) diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index ff96a17..c46b979 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" config BOARD_GIGABYTE_GA_6BXE bool "GA-6BXE" +config BOARD_GIGABYTE_GA_B75M_D3H + bool "GA-B75M-D3H" config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_MA785GMT @@ -41,6 +43,7 @@ endchoice source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" +source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" source "src/mainboard/gigabyte/ma785gm/Kconfig" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig new file mode 100644 index 0000000..8e65d94 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -0,0 +1,83 @@ +if BOARD_GIGABYTE_GA_B75M_D3H + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select INTEL_INT15 + select VGA + #select INTEL_EDID + #select MAINBOARD_HAS_NATIVE_VGA_INIT + #select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + #select IVYBRIDGE_LVDS + select UDELAY_TSC + select EARLY_CBMEM_INIT + select SERIRQ_CONTINUOUS_MODE + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-b75m-d3h + +config MAINBOARD_PART_NUMBER + string + default "GA-B75M-D3H" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086.0162" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00600000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x004fffff" + +# UNCOMMENT BELOW WHEN YOU BUILD WITH REAL ME IMAGE +#config IFD_GBE_SECTION +# string +# default "0x00fff000:0x00000fff" + +endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc new file mode 100644 index 0000000..a2efadd --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl new file mode 100644 index 0000000..09cff9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl new file mode 100644 index 0000000..1448aeb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl new file mode 100644 index 0000000..753fc29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl new file mode 100644 index 0000000..f71611a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c new file mode 100644 index 0000000..73b1c11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt new file mode 100644 index 0000000..312f6ef --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default new file mode 100644 index 0000000..21d75e5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default @@ -0,0 +1,9 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout new file mode 100644 index 0000000..7c8af49 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -0,0 +1,152 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb new file mode 100644 index 0000000..4a7845e --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -0,0 +1,139 @@ +chip northbridge/intel/sandybridge + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + register "gpu_dp_d_hotplug" = "0x06" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gfx.link_frequency_270_mhz" = "1" + register "gpu_pch_backlight" = "0x06100610" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_up_delay" = "300" + register "gpu_panel_power_down_delay" = "300" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.lvds_num_lanes" = "4" + register "gpu_cpu_backlight" = "0x1155" + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + register "pstate_coord_type" = "0xfe" + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + end + end + + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on # host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on # vga controller + subsystemid 0x1458 0xd000 + end + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + + # GPI routing + register "alt_gp_smi_en" = "0x0000" + + #register "gpi1_routing" = "2" + #register "gpi8_routing" = "2" + register "gen1_dec" = "0x003c0a01" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "pcie_port_coalesce" = "1" + register "p_cnt_throttling_supported" = "0" + register "docking_supported" = "0" + #register "gen1_dec" = "0x7c1601" + #register "gen2_dec" = "0x0c15e1" + #register "gen4_dec" = "0x0c06a1" + register "sata_port_map" = "0x3f" + register "c2_latency" = "0x0065" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 14.0 off # USB 3.0 Controller + subsystemid 0x1458 0x5007 + end + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + device pci 00.0 on # PCI device 10ec:8168 + subsystemid 0x1458 0xe000 + end + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge (ethernet here) + device pci 1f.0 on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 9 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0 + io 0x62 = 0xa00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.a off end # IR + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMBus + subsystemid 0x1458 0x5001 + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl new file mode 100644 index 0000000..84a889a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -0,0 +1,24 @@ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c new file mode 100644 index 0000000..791d7c7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c @@ -0,0 +1,433 @@ +#include "southbridge/intel/bd82x6x/gpio.h" +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_NATIVE, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_NATIVE, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_NATIVE, + .gpio28 = GPIO_MODE_NATIVE, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_OUTPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c new file mode 100644 index 0000000..253ec08 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -0,0 +1,8 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c new file mode 100644 index 0000000..045d699 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> +#include <build.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + + + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; + + pc_keyboard_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c new file mode 100644 index 0000000..9f8a29f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h new file mode 100644 index 0000000..f8b9141 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_ONBOARD_H +#define GAB75MD3H_ONBOARD_H + +#include <arch/smp/mpspec.h> + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c new file mode 100644 index 0000000..4bba88d --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_BASE 0x2e +#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +static void it8728f_b75md3h_disable_reboot(device_t dev) +{ + /* GPIO SIO settings */ + ite_reg_write(dev, 0xEF, 0x7E); // magic + + ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(dev, 0xe9, 0x27); // bus select disable + ite_reg_write(dev, 0xf0, 0x10); // ? + ite_reg_write(dev, 0xf1, 0x42); // ? + ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} + +void rcba_config(void) +{ +/* + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); + + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x3500) = 0x2000035f; + RCBA32(0x3504) = 0x2000035f; + RCBA32(0x3508) = 0x2000035f; + RCBA32(0x350c) = 0x2000035f; + RCBA32(0x3510) = 0x2000035f; + RCBA32(0x3514) = 0x2000035f; + RCBA32(0x3518) = 0x2000035f; + RCBA32(0x351c) = 0x2000035f; + RCBA32(0x3520) = 0x2000035f; + RCBA32(0x3524) = 0x2000035f; + RCBA32(0x3528) = 0x2000035f; + RCBA32(0x352c) = 0x2000035f; + RCBA32(0x3530) = 0x2000035f; + RCBA32(0x3534) = 0x2000035f; + RCBA32(0x3560) = 0x024c8001; + RCBA32(0x3564) = 0x000024a3; + RCBA32(0x3568) = 0x00040002; + RCBA32(0x356c) = 0x01000050; + RCBA32(0x3570) = 0x02000662; + RCBA32(0x3574) = 0x18000f9f; + RCBA32(0x3578) = 0x1800ff4f; + RCBA32(0x357c) = 0x0001d530; + RCBA32(0x35a0) = 0xc0300c03; + RCBA32(0x35a4) = 0x00241803; + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + outw (0x0000, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; +// RCBA32(0x3418) = 0x1fee1fe1; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +*/ + /* Disable unused devices (board specific) */ + RCBA32(0x3414) = 0x00000020; + RCBA32(FD) = 0x17ee1fe1; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + * FDD Port3F0h-3F5h and Port3F7h + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_b75md3h_disable_reboot(SUPERIO_GPIO); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); +} + +#if 0 +static void dmi_config(void) +{ + DMIBAR32(0x0218) = 0x06aa0b0c; + DMIBAR32(0x021c) = 0x0b0d0b0d; + DMIBAR32(0x0300) = 0x0011028d; + DMIBAR32(0x0304) = 0x002102cd; + DMIBAR32(0x030c) = 0x007d004b; + DMIBAR32(0x0310) = 0x007e004c; + DMIBAR32(0x0318) = 0x002304ad; + DMIBAR32(0x031c) = 0x003304ed; + DMIBAR32(0x03b8) = 0x005c05a4; + DMIBAR32(0x03bc) = 0x006c05e4; + DMIBAR32(0x0530) = 0x41d3b000; + DMIBAR32(0x0534) = 0x00019f80; + DMIBAR32(0x0ba4) = 0x0000000d; + DMIBAR32(0x0d80) = 0x1c9cfc0b; + DMIBAR32(0x0e1c) = 0x20000000; + DMIBAR32(0x0e2c) = 0x20000000; +} +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h new file mode 100644 index 0000000..ed08c8a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_THERMAL_H +#define GAB75MD3H_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif

1 0

Patch set updated for coreboot: c5bfd0c gigabyte/ga-b75m-d3h: Add new Intel mainboard
by Damien Zammit 05 Nov '14

05 Nov '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7341 -gerrit commit c5bfd0c49f6b91108473ac2e88588c3dbeec7a8c Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Oct 23 22:06:38 2014 +1100 gigabyte/ga-b75m-d3h: Add new Intel mainboard This is based on LENOVO X230 port. Board boots to linux via SATA or USB. All USB ports are working. NB: This patch depends on WIP 3 common FADT patches 7201, 7200, 7199 and automatic interrupt handling patch 7130 Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/Kconfig | 3 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 75 ++++ src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 21 + src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl | 1 + .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 28 ++ .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 73 ++++ .../gigabyte/ga-b75m-d3h/acpi/superio.asl | 24 ++ .../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 65 ++++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl | 1 + src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 83 ++++ src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt | 6 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.default | 9 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 152 ++++++++ src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 87 +++++ src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 54 +++ src/mainboard/gigabyte/ga-b75m-d3h/gpio.c | 433 +++++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 8 + src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 110 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c | 109 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/onboard.h | 25 ++ src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 208 ++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 30 ++ 22 files changed, 1605 insertions(+) diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index ff96a17..c46b979 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" config BOARD_GIGABYTE_GA_6BXE bool "GA-6BXE" +config BOARD_GIGABYTE_GA_B75M_D3H + bool "GA-B75M-D3H" config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_MA785GMT @@ -41,6 +43,7 @@ endchoice source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" +source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" source "src/mainboard/gigabyte/ma785gm/Kconfig" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig new file mode 100644 index 0000000..416cfdb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -0,0 +1,75 @@ +if BOARD_GIGABYTE_GA_B75M_D3H + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select INTEL_INT15 + select VGA + #select INTEL_EDID + #select MAINBOARD_HAS_NATIVE_VGA_INIT + #select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + #select IVYBRIDGE_LVDS + select UDELAY_TSC + select EARLY_CBMEM_INIT + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-b75m-d3h + +config MAINBOARD_PART_NUMBER + string + default "GA-B75M-D3H" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +# No need to override the chipset VGA_BIOS_ID. +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00600000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x004fffff" + +# UNCOMMENT BELOW WHEN YOU BUILD WITH REAL ME IMAGE +#config IFD_GBE_SECTION +# string +# default "0x00fff000:0x00000fff" + +endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc new file mode 100644 index 0000000..a2efadd --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl new file mode 100644 index 0000000..09cff9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl new file mode 100644 index 0000000..1448aeb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl new file mode 100644 index 0000000..753fc29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl new file mode 100644 index 0000000..f71611a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c new file mode 100644 index 0000000..73b1c11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt new file mode 100644 index 0000000..312f6ef --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default new file mode 100644 index 0000000..21d75e5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default @@ -0,0 +1,9 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout new file mode 100644 index 0000000..7c8af49 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -0,0 +1,152 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb new file mode 100644 index 0000000..68f8bf6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -0,0 +1,87 @@ +chip northbridge/intel/sandybridge + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + end + end + + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + + # GPI routing + register "alt_gp_smi_en" = "0x0000" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + register "gen1_dec" = "0x003c0a01" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 14.0 off end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on end # PCI bridge (ethernet here) + device pci 1f.0 on # ISA/LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 9 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0 + io 0x62 = 0xa00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.a off end # IR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl new file mode 100644 index 0000000..3209963 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c new file mode 100644 index 0000000..791d7c7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c @@ -0,0 +1,433 @@ +#include "southbridge/intel/bd82x6x/gpio.h" +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_NATIVE, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_NATIVE, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_NATIVE, + .gpio28 = GPIO_MODE_NATIVE, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_OUTPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c new file mode 100644 index 0000000..253ec08 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -0,0 +1,8 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c new file mode 100644 index 0000000..045d699 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> +#include <build.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + + + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; + + pc_keyboard_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c new file mode 100644 index 0000000..9f8a29f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h new file mode 100644 index 0000000..f8b9141 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_ONBOARD_H +#define GAB75MD3H_ONBOARD_H + +#include <arch/smp/mpspec.h> + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c new file mode 100644 index 0000000..5c83c44 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_BASE 0x2e +#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +static void it8728f_b75md3h_disable_reboot(device_t dev) +{ + /* GPIO SIO settings */ + ite_reg_write(dev, 0xEF, 0x7E); // magic + + ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(dev, 0xe9, 0x27); // bus select disable + ite_reg_write(dev, 0xf0, 0x10); // ? + ite_reg_write(dev, 0xf1, 0x42); // ? + ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} + +void rcba_config(void) +{ +/* + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); + + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x3500) = 0x2000035f; + RCBA32(0x3504) = 0x2000035f; + RCBA32(0x3508) = 0x2000035f; + RCBA32(0x350c) = 0x2000035f; + RCBA32(0x3510) = 0x2000035f; + RCBA32(0x3514) = 0x2000035f; + RCBA32(0x3518) = 0x2000035f; + RCBA32(0x351c) = 0x2000035f; + RCBA32(0x3520) = 0x2000035f; + RCBA32(0x3524) = 0x2000035f; + RCBA32(0x3528) = 0x2000035f; + RCBA32(0x352c) = 0x2000035f; + RCBA32(0x3530) = 0x2000035f; + RCBA32(0x3534) = 0x2000035f; + RCBA32(0x3560) = 0x024c8001; + RCBA32(0x3564) = 0x000024a3; + RCBA32(0x3568) = 0x00040002; + RCBA32(0x356c) = 0x01000050; + RCBA32(0x3570) = 0x02000662; + RCBA32(0x3574) = 0x18000f9f; + RCBA32(0x3578) = 0x1800ff4f; + RCBA32(0x357c) = 0x0001d530; + RCBA32(0x35a0) = 0xc0300c03; + RCBA32(0x35a4) = 0x00241803; + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + outw (0x0000, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; +// RCBA32(0x3418) = 0x1fee1fe1; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +*/ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17ee1fe1; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + * FDD Port3F0h-3F5h and Port3F7h + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_b75md3h_disable_reboot(SUPERIO_GPIO); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); +} + +#if 0 +static void dmi_config(void) +{ + DMIBAR32(0x0218) = 0x06aa0b0c; + DMIBAR32(0x021c) = 0x0b0d0b0d; + DMIBAR32(0x0300) = 0x0011028d; + DMIBAR32(0x0304) = 0x002102cd; + DMIBAR32(0x030c) = 0x007d004b; + DMIBAR32(0x0310) = 0x007e004c; + DMIBAR32(0x0318) = 0x002304ad; + DMIBAR32(0x031c) = 0x003304ed; + DMIBAR32(0x03b8) = 0x005c05a4; + DMIBAR32(0x03bc) = 0x006c05e4; + DMIBAR32(0x0530) = 0x41d3b000; + DMIBAR32(0x0534) = 0x00019f80; + DMIBAR32(0x0ba4) = 0x0000000d; + DMIBAR32(0x0d80) = 0x1c9cfc0b; + DMIBAR32(0x0e1c) = 0x20000000; + DMIBAR32(0x0e2c) = 0x20000000; +} +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h new file mode 100644 index 0000000..ed08c8a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_THERMAL_H +#define GAB75MD3H_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif

1 0

New patch to review for coreboot: 5407416 gigabyte/ga-b75m-d3h: Add new Intel mainboard
by Damien Zammit 05 Nov '14

05 Nov '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7341 -gerrit commit 5407416061ebb1b5f4149962d6499a78e805b5d6 Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Oct 23 22:06:38 2014 +1100 gigabyte/ga-b75m-d3h: Add new Intel mainboard This is based on LENOVO X230 port. Board boots to linux via SATA or USB. All USB ports are working. NB: This patch depends on WIP 3 common FADT patches 7201, 7200, 7199 and automatic interrupt handling patch 7130 Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/Kconfig | 3 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 75 ++++ src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 21 + src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl | 1 + .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 28 ++ .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 73 ++++ .../gigabyte/ga-b75m-d3h/acpi/superio.asl | 24 ++ .../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 65 ++++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl | 1 + src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 83 ++++ src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt | 6 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.default | 9 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 152 ++++++++ src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 87 +++++ src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 54 +++ src/mainboard/gigabyte/ga-b75m-d3h/gpio.c | 433 +++++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 8 + src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 110 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c | 109 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/onboard.h | 25 ++ src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 208 ++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 30 ++ 22 files changed, 1605 insertions(+) diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index ff96a17..c46b979 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" config BOARD_GIGABYTE_GA_6BXE bool "GA-6BXE" +config BOARD_GIGABYTE_GA_B75M_D3H + bool "GA-B75M-D3H" config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_MA785GMT @@ -41,6 +43,7 @@ endchoice source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" +source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" source "src/mainboard/gigabyte/ma785gm/Kconfig" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig new file mode 100644 index 0000000..85e9ec2 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -0,0 +1,75 @@ +if BOARD_GIGABYTE_GA_B75M_D3H + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select INTEL_INT15 + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS + select UDELAY_TSC + select EARLY_CBMEM_INIT + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-b75m-d3h + +config MAINBOARD_PART_NUMBER + string + default "GA-B75M-D3H" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +# No need to override the chipset VGA_BIOS_ID. +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00600000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x004fffff" + +# UNCOMMENT BELOW WHEN YOU BUILD WITH REAL ME IMAGE +#config IFD_GBE_SECTION +# string +# default "0x00fff000:0x00000fff" + +endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc new file mode 100644 index 0000000..a2efadd --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl new file mode 100644 index 0000000..09cff9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl new file mode 100644 index 0000000..1448aeb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl new file mode 100644 index 0000000..753fc29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl new file mode 100644 index 0000000..f71611a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c new file mode 100644 index 0000000..73b1c11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt new file mode 100644 index 0000000..312f6ef --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default new file mode 100644 index 0000000..21d75e5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default @@ -0,0 +1,9 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout new file mode 100644 index 0000000..7c8af49 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -0,0 +1,152 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb new file mode 100644 index 0000000..68f8bf6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -0,0 +1,87 @@ +chip northbridge/intel/sandybridge + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + end + end + + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + + # GPI routing + register "alt_gp_smi_en" = "0x0000" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + register "gen1_dec" = "0x003c0a01" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 14.0 off end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on end # PCI bridge (ethernet here) + device pci 1f.0 on # ISA/LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 9 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0 + io 0x62 = 0xa00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.a off end # IR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl new file mode 100644 index 0000000..3209963 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c new file mode 100644 index 0000000..791d7c7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c @@ -0,0 +1,433 @@ +#include "southbridge/intel/bd82x6x/gpio.h" +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_NATIVE, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_NATIVE, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_NATIVE, + .gpio28 = GPIO_MODE_NATIVE, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_OUTPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c new file mode 100644 index 0000000..253ec08 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -0,0 +1,8 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c new file mode 100644 index 0000000..045d699 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> +#include <build.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + + + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; + + pc_keyboard_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c new file mode 100644 index 0000000..9f8a29f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h new file mode 100644 index 0000000..f8b9141 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_ONBOARD_H +#define GAB75MD3H_ONBOARD_H + +#include <arch/smp/mpspec.h> + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c new file mode 100644 index 0000000..5c83c44 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_BASE 0x2e +#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +static void it8728f_b75md3h_disable_reboot(device_t dev) +{ + /* GPIO SIO settings */ + ite_reg_write(dev, 0xEF, 0x7E); // magic + + ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(dev, 0xe9, 0x27); // bus select disable + ite_reg_write(dev, 0xf0, 0x10); // ? + ite_reg_write(dev, 0xf1, 0x42); // ? + ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} + +void rcba_config(void) +{ +/* + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); + + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x3500) = 0x2000035f; + RCBA32(0x3504) = 0x2000035f; + RCBA32(0x3508) = 0x2000035f; + RCBA32(0x350c) = 0x2000035f; + RCBA32(0x3510) = 0x2000035f; + RCBA32(0x3514) = 0x2000035f; + RCBA32(0x3518) = 0x2000035f; + RCBA32(0x351c) = 0x2000035f; + RCBA32(0x3520) = 0x2000035f; + RCBA32(0x3524) = 0x2000035f; + RCBA32(0x3528) = 0x2000035f; + RCBA32(0x352c) = 0x2000035f; + RCBA32(0x3530) = 0x2000035f; + RCBA32(0x3534) = 0x2000035f; + RCBA32(0x3560) = 0x024c8001; + RCBA32(0x3564) = 0x000024a3; + RCBA32(0x3568) = 0x00040002; + RCBA32(0x356c) = 0x01000050; + RCBA32(0x3570) = 0x02000662; + RCBA32(0x3574) = 0x18000f9f; + RCBA32(0x3578) = 0x1800ff4f; + RCBA32(0x357c) = 0x0001d530; + RCBA32(0x35a0) = 0xc0300c03; + RCBA32(0x35a4) = 0x00241803; + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + outw (0x0000, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; +// RCBA32(0x3418) = 0x1fee1fe1; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +*/ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17ee1fe1; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + * FDD Port3F0h-3F5h and Port3F7h + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_b75md3h_disable_reboot(SUPERIO_GPIO); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); +} + +#if 0 +static void dmi_config(void) +{ + DMIBAR32(0x0218) = 0x06aa0b0c; + DMIBAR32(0x021c) = 0x0b0d0b0d; + DMIBAR32(0x0300) = 0x0011028d; + DMIBAR32(0x0304) = 0x002102cd; + DMIBAR32(0x030c) = 0x007d004b; + DMIBAR32(0x0310) = 0x007e004c; + DMIBAR32(0x0318) = 0x002304ad; + DMIBAR32(0x031c) = 0x003304ed; + DMIBAR32(0x03b8) = 0x005c05a4; + DMIBAR32(0x03bc) = 0x006c05e4; + DMIBAR32(0x0530) = 0x41d3b000; + DMIBAR32(0x0534) = 0x00019f80; + DMIBAR32(0x0ba4) = 0x0000000d; + DMIBAR32(0x0d80) = 0x1c9cfc0b; + DMIBAR32(0x0e1c) = 0x20000000; + DMIBAR32(0x0e2c) = 0x20000000; +} +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h new file mode 100644 index 0000000..ed08c8a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_THERMAL_H +#define GAB75MD3H_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2014