coreboot-gerrit November 2014

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New patch to review for coreboot: 8240f58 northbridge: DEVICE_NOOP some stub function callbacks
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7344 -gerrit commit 8240f58f36f1daf99af2c77e0122c8eea7b8d054 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Nov 6 08:57:40 2014 +1100 northbridge: DEVICE_NOOP some stub function callbacks Reduces loc and makes NOP's explicit. Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family14/northbridge.c | 12 ++---------- src/northbridge/amd/agesa/family15/northbridge.c | 12 ++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 12 ++---------- src/northbridge/amd/amdfam10/northbridge.c | 6 +----- 4 files changed, 7 insertions(+), 35 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index d7a352b..f8464c8 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -779,14 +779,6 @@ static void domain_enable_resources(struct device *dev) /* Bus related code */ -static void cpu_bus_read_resources(struct device *dev) -{ -} - -static void cpu_bus_set_resources(struct device *dev) -{ -} - static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus = dev->link_list; @@ -846,8 +838,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = NULL, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 2d69939..2b0b8b8 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1092,17 +1092,9 @@ static void cpu_bus_init(struct device *dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device *dev) -{ -} - -static void cpu_bus_set_resources(struct device *dev) -{ -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 1fccec1..5c650f3 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1054,17 +1054,9 @@ static void cpu_bus_init(struct device *dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device *dev) -{ -} - -static void cpu_bus_set_resources(struct device *dev) -{ -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 779a0d6..e49deec 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1412,10 +1412,6 @@ static void cpu_bus_init(struct device *dev) } -static void cpu_bus_read_resources(struct device *dev) -{ -} - static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -1426,7 +1422,7 @@ static void cpu_bus_set_resources(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, + .read_resources = DEVICE_NOOP, .set_resources = cpu_bus_set_resources, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init,

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New patch to review for coreboot: 03738db northbridge: style fix
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7343 -gerrit commit 03738db65170b1f854eb6c6be9505d01b31e7994 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Nov 6 08:51:13 2014 +1100 northbridge: style fix Change-Id: Ib3de17b3b1b8149f5d10ce203f128345394d11d1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/00730F01/northbridge.c | 70 +++++++++---------- src/northbridge/amd/agesa/family10/northbridge.c | 80 +++++++++++----------- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 50 +++++++------- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 54 +++++++-------- src/northbridge/amd/agesa/family15/northbridge.c | 72 +++++++++---------- src/northbridge/amd/agesa/family15tn/iommu.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 66 +++++++++--------- src/northbridge/amd/agesa/family16kb/northbridge.c | 70 +++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 72 +++++++++---------- src/northbridge/amd/amdk8/northbridge.c | 64 ++++++++--------- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 12 ++-- src/northbridge/amd/gx2/northbridge.c | 12 ++-- src/northbridge/amd/lx/northbridge.c | 12 ++-- src/northbridge/dmp/vortex86ex/northbridge.c | 6 +- src/northbridge/intel/e7501/northbridge.c | 6 +- src/northbridge/intel/e7505/northbridge.c | 8 +-- src/northbridge/intel/e7520/northbridge.c | 16 ++--- src/northbridge/intel/e7525/northbridge.c | 16 ++--- src/northbridge/intel/fsp_rangeley/northbridge.c | 20 +++--- .../intel/fsp_sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/gm45/northbridge.c | 12 ++-- src/northbridge/intel/haswell/northbridge.c | 30 ++++---- src/northbridge/intel/i3100/northbridge.c | 18 ++--- src/northbridge/intel/i440bx/northbridge.c | 8 +-- src/northbridge/intel/i440lx/northbridge.c | 8 +-- src/northbridge/intel/i5000/northbridge.c | 14 ++-- src/northbridge/intel/i82810/northbridge.c | 8 +-- src/northbridge/intel/i82830/northbridge.c | 8 +-- src/northbridge/intel/i855/northbridge.c | 8 +-- src/northbridge/intel/i945/northbridge.c | 14 ++-- src/northbridge/intel/nehalem/northbridge.c | 14 ++-- src/northbridge/intel/sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/sch/northbridge.c | 14 ++-- src/northbridge/rdc/r8610/northbridge.c | 6 +- src/northbridge/via/cn400/northbridge.c | 16 ++--- src/northbridge/via/cn700/northbridge.c | 10 +-- src/northbridge/via/cx700/northbridge.c | 8 +-- src/northbridge/via/vt8601/northbridge.c | 8 +-- src/northbridge/via/vt8623/northbridge.c | 14 ++-- src/northbridge/via/vx800/northbridge.c | 8 +-- src/northbridge/via/vx900/northbridge.c | 14 ++-- 44 files changed, 504 insertions(+), 504 deletions(-) diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c index 06fe3f6..7769b03 100644 --- a/src/northbridge/amd/agesa/00730F01/northbridge.c +++ b/src/northbridge/amd/agesa/00730F01/northbridge.c @@ -58,15 +58,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(struct device * dev) +static u32 amdfam16_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -287,7 +287,7 @@ static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -329,7 +329,7 @@ static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void read_resources(struct device * dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -342,7 +342,7 @@ static void read_resources(struct device * dev) } } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -393,7 +393,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -402,7 +402,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -422,7 +422,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(struct device * dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -449,11 +449,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(struct device * dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -499,7 +499,7 @@ struct chip_operations northbridge_amd_agesa_00730F01_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -512,7 +512,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -559,7 +559,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -663,7 +663,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -840,13 +840,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -882,12 +882,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -983,7 +983,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1068,7 +1068,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1076,12 +1076,12 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1092,7 +1092,7 @@ static void cpu_bus_read_resources(struct device * dev) #endif } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index bc4a25d..543966e 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -52,10 +52,10 @@ typedef struct dram_base_mask { struct amdfam10_sysconf_t sysconf; -static struct device * __f0_dev[NODE_NUMS]; -static struct device * __f1_dev[NODE_NUMS]; -static struct device * __f2_dev[NODE_NUMS]; -static struct device * __f4_dev[NODE_NUMS]; +static struct device *__f0_dev[NODE_NUMS]; +static struct device *__f1_dev[NODE_NUMS]; +static struct device *__f2_dev[NODE_NUMS]; +static struct device *__f4_dev[NODE_NUMS]; static unsigned fx_devs = 0; #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 @@ -64,7 +64,7 @@ static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; @@ -96,7 +96,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - struct device * dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -149,7 +149,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, #endif #if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(struct device * dev, u32 segbusn, u32 nodes, +static u32 check_segn(struct device *dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -249,7 +249,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, sysconf.mmio_addr_num = index+1; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -318,7 +318,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - struct device * dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first @@ -357,7 +357,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi #endif } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -407,7 +407,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -415,7 +415,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(struct device * dev) +static u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 unsigned busn; @@ -442,7 +442,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -450,7 +450,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -470,7 +470,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -505,7 +505,7 @@ static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -541,7 +541,7 @@ static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -600,7 +600,7 @@ static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(struct device * dev) +static void amdfam10_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -612,7 +612,7 @@ static void amdfam10_read_resources(struct device * dev) } } -static void amdfam10_set_resource(struct device * dev, struct resource *resource, +static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -667,7 +667,7 @@ static void amdfam10_set_resource(struct device * dev, struct resource *resource * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -676,7 +676,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -696,7 +696,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(struct device * dev) +static void amdfam10_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -723,12 +723,12 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0xff; nodeid = amdfam10_nodeid(dev); @@ -770,7 +770,7 @@ struct chip_operations northbridge_amd_agesa_family10_ops = { }; -static void amdfam10_domain_read_resources(struct device * dev) +static void amdfam10_domain_read_resources(struct device *dev) { unsigned reg; @@ -783,7 +783,7 @@ static void amdfam10_domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -829,7 +829,7 @@ static void amdfam10_domain_read_resources(struct device * dev) #endif } -static void amdfam10_domain_enable_resources(struct device * dev) +static void amdfam10_domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); @@ -904,7 +904,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void amdfam10_domain_set_resources(struct device * dev) +static void amdfam10_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1071,7 +1071,7 @@ static void amdfam10_domain_set_resources(struct device * dev) } } -static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1102,7 +1102,7 @@ static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) */ get_fx_devs(); for (i = 0; i < fx_devs; i++) { - struct device * f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1132,7 +1132,7 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1150,7 +1150,7 @@ static void sysconf_init(struct device * dev) // first node sysconf.bsp_apicid = lapicid(); } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1186,12 +1186,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int nodes; @@ -1282,7 +1282,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1363,7 +1363,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1371,12 +1371,12 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1387,7 +1387,7 @@ static void cpu_bus_read_resources(struct device * dev) #endif } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 116a466..aa7eb69 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - struct device * dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - struct device * dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 7d1b118..ca357ef 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,14 +41,14 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static struct device * __f0_dev[FX_DEVS]; -static struct device * __f1_dev[FX_DEVS]; -static struct device * __f2_dev[FX_DEVS]; -static struct device * __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs=0; -struct device * get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -89,7 +89,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -98,7 +98,7 @@ static void f1_write_config32(unsigned reg, u32 value) } -static u32 amdfam12_nodeid(struct device * dev) +static u32 amdfam12_nodeid(struct device *dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -108,7 +108,7 @@ static u32 amdfam12_nodeid(struct device * dev) #include "amdfam12_conf.c" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -137,7 +137,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -158,7 +158,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam12_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 result, reg; @@ -182,7 +182,7 @@ static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam12_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -218,7 +218,7 @@ static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u } -static void amdfam12_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam12_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -343,7 +343,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void read_resources(struct device * dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void read_resources(struct device * dev) } -static void set_resource(struct device * dev, struct resource *resource, +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -412,10 +412,10 @@ static void set_resource(struct device * dev, struct resource *resource, #if CONFIG_CONSOLE_VGA_MULTI -extern struct device * vga_pri; // the primary vga device, defined in device.c +extern struct device *vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -447,7 +447,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) } -static void set_resources(struct device * dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -503,7 +503,7 @@ static void setup_uma_memory(void) /* Domain/Root Complex related code */ -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -518,7 +518,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -581,7 +581,7 @@ static void domain_read_resources(struct device * dev) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -765,7 +765,7 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -783,7 +783,7 @@ static void domain_enable_resources(struct device * dev) /* Bus related code */ -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -797,7 +797,7 @@ static void cpu_bus_read_resources(struct device * dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -809,7 +809,7 @@ static void cpu_bus_set_resources(struct device * dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index b72b21b..b5fd94d 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - struct device * dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - struct device * dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index de1465b..d7a352b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -44,13 +44,13 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static struct device * __f0_dev[FX_DEVS]; -static struct device * __f1_dev[FX_DEVS]; -static struct device * __f2_dev[FX_DEVS]; -static struct device * __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs = 0; -struct device * get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -88,7 +88,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -96,14 +96,14 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam14_nodeid(struct device * dev) +static u32 amdfam14_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #include "amdfam14_conf.c" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -119,7 +119,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -127,7 +127,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -146,7 +146,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodeid, +static struct resource *amdfam14_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -173,7 +173,7 @@ static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, +static struct resource *amdfam14_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -208,7 +208,7 @@ static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, return resource; } -static void amdfam14_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam14_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void nb_read_resources(struct device * dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(struct device * dev) #endif } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -409,10 +409,10 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod } #if CONFIG_CONSOLE_VGA_MULTI -extern struct device * vga_pri; // the primary vga device, defined in device.c +extern struct device *vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -444,7 +444,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void nb_set_resources(struct device * dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -477,7 +477,7 @@ static void nb_set_resources(struct device * dev) /* Domain/Root Complex related code */ -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -492,7 +492,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -566,7 +566,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -757,7 +757,7 @@ static void domain_set_resources(struct device * dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { #if CONFIG_AMD_SB_CIMX if (!acpi_is_wakeup_s3()) { @@ -779,18 +779,18 @@ static void domain_enable_resources(struct device * dev) /* Bus related code */ -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus = dev->link_list; - struct device * cpu; + struct device *cpu; int apic_id, cores_found; /* There is only one node for fam14, but there may be multiple cores. */ @@ -809,7 +809,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c7a141f..2d69939 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -57,16 +57,16 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(struct device * dev) +static u32 amdfam15_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -288,7 +288,7 @@ static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u } -static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void nb_read_resources(struct device * dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(struct device * dev) } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -412,7 +412,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -422,7 +422,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -443,7 +443,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) } -static void nb_set_resources(struct device * dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -476,11 +476,11 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(struct device * dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { @@ -526,7 +526,7 @@ struct chip_operations northbridge_amd_agesa_family15_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -540,7 +540,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -588,7 +588,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); @@ -681,7 +681,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -860,13 +860,13 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -902,12 +902,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -987,7 +987,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1079,7 +1079,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1087,16 +1087,16 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { } @@ -1136,7 +1136,7 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { }; /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(struct device *dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); return max; diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 5b3529b..396ba02 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <lib.h> -static void iommu_read_resources(struct device * dev) +static void iommu_read_resources(struct device *dev) { struct resource *res; @@ -39,7 +39,7 @@ static void iommu_read_resources(struct device * dev) res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(struct device * dev) +static void iommu_set_resources(struct device *dev) { struct resource *res; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 5f0cafc..1fccec1 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(struct device * dev) +static u32 amdfam15_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void nb_read_resources(struct device * dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -354,7 +354,7 @@ static void nb_read_resources(struct device * dev) #endif } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -405,7 +405,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -414,7 +414,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -434,7 +434,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void nb_set_resources(struct device * dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -494,7 +494,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -507,7 +507,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -554,7 +554,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -647,7 +647,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -824,13 +824,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -866,12 +866,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -951,7 +951,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1041,7 +1041,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1049,16 +1049,16 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cc79da3..f91bbbb 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(struct device * dev) +static u32 amdfam16_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void read_resources(struct device * dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -341,7 +341,7 @@ static void read_resources(struct device * dev) } } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -392,7 +392,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -401,7 +401,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -421,7 +421,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(struct device * dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -448,11 +448,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(struct device * dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -498,7 +498,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -511,7 +511,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -558,7 +558,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -653,7 +653,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -830,13 +830,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -872,12 +872,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -957,7 +957,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1047,7 +1047,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1055,12 +1055,12 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1071,7 +1071,7 @@ static void cpu_bus_read_resources(struct device * dev) #endif } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8b87abc..779a0d6 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -53,13 +53,13 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS -static struct device * __f0_dev[FX_DEVS]; -static struct device * __f1_dev[FX_DEVS]; -static struct device * __f2_dev[FX_DEVS]; -static struct device * __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs=0; -struct device * get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if((CONFIG_CDB + nodeid) < 32) { @@ -102,7 +102,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(struct device * dev) +static u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 unsigned busn; @@ -139,7 +139,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdfam10_scan_chain(struct device *dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -152,7 +152,7 @@ static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link u32 max_bus; u32 min_bus; u32 is_sublink1 = (link_num>3); - struct device * devx; + struct device *devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -284,7 +284,7 @@ static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link return max; } -static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -327,7 +327,7 @@ static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -335,7 +335,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -355,7 +355,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -389,7 +389,7 @@ static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -425,7 +425,7 @@ static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u } -static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -484,7 +484,7 @@ static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(struct device * dev) +static void amdfam10_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -496,7 +496,7 @@ static void amdfam10_read_resources(struct device * dev) } } -static void amdfam10_set_resource(struct device * dev, struct resource *resource, +static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -551,7 +551,7 @@ static void amdfam10_set_resource(struct device * dev, struct resource *resource * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -580,7 +580,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(struct device * dev) +static void amdfam10_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -629,7 +629,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { .enable_dev = 0, }; -static void amdfam10_domain_read_resources(struct device * dev) +static void amdfam10_domain_read_resources(struct device *dev) { unsigned reg; @@ -642,7 +642,7 @@ static void amdfam10_domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -767,7 +767,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - struct device * dev; + struct device *dev; struct dram_base_mask_t d; u32 sel_m; u32 sel_hi_en; @@ -871,7 +871,7 @@ static void setup_uma_memory(void) #endif } -static void amdfam10_domain_set_resources(struct device * dev) +static void amdfam10_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1087,7 +1087,7 @@ static void amdfam10_domain_set_resources(struct device * dev) } } -static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1118,7 +1118,7 @@ static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1146,7 +1146,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1188,7 +1188,7 @@ static void sysconf_init(struct device * dev) // first node #endif } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1224,12 +1224,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int nodes; @@ -1324,7 +1324,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < nodes; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1394,7 +1394,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) } } #endif - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1402,7 +1402,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX @@ -1412,11 +1412,11 @@ static void cpu_bus_init(struct device * dev) } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 816d9e4..e14f706 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -40,8 +40,8 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 -static struct device * __f0_dev[MAX_FX_DEVS]; -static struct device * __f1_dev[MAX_FX_DEVS]; +static struct device *__f0_dev[MAX_FX_DEVS]; +static struct device *__f1_dev[MAX_FX_DEVS]; static unsigned fx_devs=0; static void get_fx_devs(void) @@ -71,7 +71,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -79,12 +79,12 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdk8_nodeid(struct device * dev) +static u32 amdk8_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdk8_scan_chain(struct device *dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u return max; } -static unsigned amdk8_scan_chains(struct device * dev, unsigned max) +static unsigned amdk8_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -271,7 +271,7 @@ static unsigned amdk8_scan_chains(struct device * dev, unsigned max) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -279,7 +279,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -299,7 +299,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned link, +static unsigned amdk8_find_reg(struct device *dev, unsigned nodeid, unsigned link, unsigned min, unsigned max) { unsigned resource; @@ -327,17 +327,17 @@ static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned li return resource; } -static unsigned amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8); } -static unsigned amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_mempair(struct device *dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8); } -static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -376,9 +376,9 @@ static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned } } -static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid); +static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid); -static void amdk8_read_resources(struct device * dev) +static void amdk8_read_resources(struct device *dev) { unsigned nodeid; struct bus *link; @@ -391,7 +391,7 @@ static void amdk8_read_resources(struct device * dev) amdk8_create_vga_resource(dev, nodeid); } -static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device *dev, struct resource *resource, unsigned nodeid) { struct bus *link; resource_t rbase, rend; @@ -488,7 +488,7 @@ static void amdk8_set_resource(struct device * dev, struct resource *resource, u report_resource_stored(dev, resource, buf); } -static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid) { struct resource *resource; struct bus *link; @@ -498,7 +498,7 @@ static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -529,7 +529,7 @@ static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) IORESOURCE_ASSIGNED; } -static void amdk8_set_resources(struct device * dev) +static void amdk8_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -638,7 +638,7 @@ struct chip_operations northbridge_amd_amdk8_ops = { .enable_dev = 0, }; -static void amdk8_domain_read_resources(struct device * dev) +static void amdk8_domain_read_resources(struct device *dev) { unsigned reg; @@ -651,7 +651,7 @@ static void amdk8_domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; nodeid = limit & 7; reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; @@ -765,7 +765,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - struct device * dev; + struct device *dev; u32 base, limit; u32 hoist; u32 hole_sizek; @@ -810,7 +810,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; u32 carry_over; - struct device * dev; + struct device *dev; u32 base, limit; u32 basek; u32 hoist; @@ -904,7 +904,7 @@ static void setup_uma_memory(void) #endif } -static void amdk8_domain_set_resources(struct device * dev) +static void amdk8_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1121,7 +1121,7 @@ static void amdk8_domain_set_resources(struct device * dev) } -static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) +static u32 amdk8_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1136,7 +1136,7 @@ static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1164,7 +1164,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1200,10 +1200,10 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; int bsp_apicid; int i,j; unsigned nb_cfg_54; @@ -1258,7 +1258,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < sysconf.nodes; i++) { - struct device * cpu_dev; + struct device *cpu_dev; /* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1267,7 +1267,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) * ensure all of the cpu's pci devices are found. */ int local_j; - struct device * dev_f0; + struct device *dev_f0; for(local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); @@ -1334,7 +1334,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) } } - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1342,7 +1342,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { #if CONFIG_WAIT_BEFORE_CPUS_INIT cpus_ready_for_init(); diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 09cdce5..937095b 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -66,7 +66,7 @@ void nb_Late_Post_Init(void) LibSystemApiCall(AmdLatePostInit, &gConfig); } -static void rd890_enable(struct device * dev) +static void rd890_enable(struct device *dev) { u32 address = 0; u32 devfn; diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index d960406..25add9f 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -14,7 +14,7 @@ /* */ -static void optimize_xbus(struct device * dev) +static void optimize_xbus(struct device *dev) { /* Optimise X-Bus performance */ pci_write_config8(dev, 0x40, 0x1e); @@ -31,13 +31,13 @@ static void optimize_xbus(struct device * dev) * this region? **/ -static void enable_shadow(struct device * dev) +static void enable_shadow(struct device *dev) { write32(GX_BASE+BC_XMAP_2, 0x77777777); write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); @@ -65,9 +65,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -126,7 +126,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e7a37f1..50f72ce 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -213,12 +213,12 @@ int sizeram(void) return sizem; } -static void enable_shadow(struct device * dev) +static void enable_shadow(struct device *dev) { } -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); @@ -273,11 +273,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { int idx; u32 tomk; - struct device * mc_dev; + struct device *mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -296,7 +296,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void pci_domain_enable(struct device * dev) +static void pci_domain_enable(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -318,7 +318,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 9a75fc4..f7971c3 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -291,11 +291,11 @@ int sizeram(void) return sizem; } -static void enable_shadow(struct device * dev) +static void enable_shadow(struct device *dev) { } -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { //msr_t msr; @@ -372,11 +372,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { int idx; u32 tomk; - struct device * mc_dev; + struct device *mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -395,7 +395,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void pci_domain_enable(struct device * dev) +static void pci_domain_enable(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -422,7 +422,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index e193168..03c52cd 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -30,7 +30,7 @@ #define SPI_BASE 0xfc00 -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. @@ -75,9 +75,9 @@ static void set_cmos_memory_size(unsigned long sizek) * don't touch it. */ } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 407df57..e3bdb42 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -20,9 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -110,7 +110,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 0f6a1ce..417b5b7 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -16,9 +16,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -97,7 +97,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -117,7 +117,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 42c2f84..143fd7c 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static u32 e7520_domain_scan_bus(struct device * dev, u32 max) +static u32 e7520_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -122,7 +122,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -134,7 +134,7 @@ static void mc_read_resources(struct device * dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -145,7 +145,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -170,7 +170,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x3590, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -184,7 +184,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index b6cb7fc..b011fc9 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -106,7 +106,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static u32 e7525_domain_scan_bus(struct device * dev, u32 max) +static u32 e7525_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -121,7 +121,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -133,7 +133,7 @@ static void mc_read_resources(struct device * dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -144,7 +144,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -169,7 +169,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x359e, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -183,7 +183,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 04cb5d9..47b98ba 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -112,7 +112,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (struct device * dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -123,7 +123,7 @@ static void finalize_dev (struct device * dev) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); } -static void mc_add_dram_resources(struct device * dev) +static void mc_add_dram_resources(struct device *dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -168,7 +168,7 @@ static void mc_add_dram_resources(struct device * dev) index = add_fixed_resources(dev, index); } -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -177,7 +177,7 @@ static void mc_read_resources(struct device * dev) mc_add_dram_resources(dev); } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { /* * Assign memory resources for PCI devices @@ -187,13 +187,13 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -208,7 +208,7 @@ static void northbridge_init(struct device *dev) { } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { } @@ -258,7 +258,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -271,7 +271,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index e6f1fec..01d60fb 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -68,7 +68,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -121,7 +121,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -261,7 +261,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -283,7 +283,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -297,7 +297,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -322,7 +322,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -375,7 +375,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -388,7 +388,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index b7737aa..9f2d409 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -46,7 +46,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - struct device * dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; @@ -73,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) return 0; } -static void mch_domain_read_resources(struct device * dev) +static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0, usable_tomk; @@ -170,7 +170,7 @@ static void mch_domain_read_resources(struct device * dev) } } -static void mch_domain_set_resources(struct device * dev) +static void mch_domain_set_resources(struct device *dev) { struct resource *resource; int i; @@ -185,7 +185,7 @@ static void mch_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void mch_domain_init(struct device * dev) +static void mch_domain_init(struct device *dev) { u32 reg32; @@ -207,7 +207,7 @@ static struct device_operations pci_domain_ops = { }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -221,7 +221,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 1cd6ac0..35ceb68 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,7 +39,7 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -69,7 +69,7 @@ static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 return 0; } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +106,7 @@ static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -126,7 +126,7 @@ static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(struct device * dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -146,7 +146,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(struct device * dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -203,7 +203,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(struct device * dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(struct device * dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(struct device * dev, uint64_t *values) } } -static void mc_report_map_entries(struct device * dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -291,7 +291,7 @@ static void mc_report_map_entries(struct device * dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(struct device * dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -383,7 +383,7 @@ static void mc_add_dram_resources(struct device * dev) #endif } -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -395,7 +395,7 @@ static void mc_read_resources(struct device * dev) mc_add_dram_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -433,7 +433,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; @@ -480,7 +480,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { bsp_init_and_start_aps(dev->link_list); } @@ -493,7 +493,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 8f30486..ee448a7 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -39,9 +39,9 @@ static u32 max_bus; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -132,7 +132,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static u32 i3100_domain_scan_bus(struct device * dev, u32 max) +static u32 i3100_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -159,7 +159,7 @@ static void mc_read_resources(struct device * dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -170,7 +170,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -180,7 +180,7 @@ static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned d unsigned long acpi_fill_mcfg(unsigned long current) { - struct device * dev; + struct device *dev; u64 mmcfg; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = PCI_DEVICE_ID_INTEL_3100_MC, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -233,7 +233,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 866a778..bbda583 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -12,7 +12,7 @@ #include "northbridge.h" #include "i440bx.h" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -32,9 +32,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -static void i440bx_domain_set_resources(struct device * dev) +static void i440bx_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -81,7 +81,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 4070c7a..5c96eca 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -38,7 +38,7 @@ * Maciej */ -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -58,9 +58,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -static void i440lx_domain_set_resources(struct device * dev) +static void i440lx_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 30517bb..49ceff8 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <cbmem.h> -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -40,15 +40,15 @@ static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned d } } -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0; - struct device * dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); - struct device * dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + struct device *dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + struct device *dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); pci_dev_read_resources(dev); @@ -139,7 +139,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = nb_ids, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -151,7 +151,7 @@ static struct device_operations cpu_bus_ops = { .init = cpu_bus_init, .scan_bus = 0, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -165,7 +165,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 5925e63..fba09fc 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -32,7 +32,7 @@ #include "northbridge.h" #include "i82810.h" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -69,9 +69,9 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -136,7 +136,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index a317613..5bb5ac3 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -30,7 +30,7 @@ #include <string.h> #include "i82830.h" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -50,9 +50,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -103,7 +103,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index ff3ca5b..4daacfe 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -32,7 +32,7 @@ #include <cpu/x86/cache.h> #include <cpu/cpu.h> -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -52,9 +52,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); @@ -119,7 +119,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 494253f..2baf935 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -81,7 +81,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { uint32_t pci_tolm; uint8_t tolud, reg8; @@ -185,7 +185,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -207,7 +207,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -221,7 +221,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,7 +274,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x27a0, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -287,7 +287,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index ea14c12..d9c6723 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -96,7 +96,7 @@ static void add_fixed_resources(struct device *dev, int index) #endif } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { uint32_t tseg_base; uint64_t TOUUD; @@ -165,13 +165,13 @@ static void mc_read_resources(struct device * dev) add_fixed_resources(dev, 10); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { /* And call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -283,7 +283,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -324,7 +324,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -337,7 +337,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ab28093..4ed1db6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -66,7 +66,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -132,7 +132,7 @@ static void add_fixed_resources(struct device *dev, int index) bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -266,7 +266,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -288,7 +288,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -302,7 +302,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -412,7 +412,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -471,7 +471,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -484,7 +484,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index e2cc496..7ecdbc4 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { u32 pci_tolm; u8 reg8; @@ -200,7 +200,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -226,7 +226,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -239,7 +239,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -292,7 +292,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x8100, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -305,7 +305,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 5ca0ab3..f85756c 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -33,7 +33,7 @@ static unsigned long get_memory_size(void) { - struct device * nb_dev; + struct device *nb_dev; u8 size; nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, @@ -42,7 +42,7 @@ static unsigned long get_memory_size(void) return (2 * 1024) << size; } -static void cpu_pci_domain_set_resources(struct device * dev) +static void cpu_pci_domain_set_resources(struct device *dev) { u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; @@ -92,7 +92,7 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current) return len; } -static int rdc_get_smbios_data(struct device * dev, int *handle, unsigned long *current) +static int rdc_get_smbios_data(struct device *dev, int *handle, unsigned long *current) { int len; len = rdc_get_smbios_data16(*handle, current); diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index dc64991..1ecd2cf 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn400.h" -static void memctrl_init(struct device * dev) +static void memctrl_init(struct device *dev) { - struct device * vlink_dev; + struct device *vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; int i, j; @@ -140,7 +140,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; -static void cn400_domain_read_resources(struct device * dev) +static void cn400_domain_read_resources(struct device *dev) { struct resource *resource; @@ -162,7 +162,7 @@ static void cn400_domain_read_resources(struct device * dev) } #ifdef UNUSED_CODE -static void ram_reservation(struct device * dev, unsigned long index, +static void ram_reservation(struct device *dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +177,9 @@ static void ram_reservation(struct device * dev, unsigned long index, } #endif -static void cn400_domain_set_resources(struct device * dev) +static void cn400_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +219,7 @@ static void cn400_domain_set_resources(struct device * dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); } -static unsigned int cn400_domain_scan_bus(struct device * dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device *dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__); @@ -236,7 +236,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index c1bd74c..6c21b72 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn700.h" -static void memctrl_init(struct device * dev) +static void memctrl_init(struct device *dev) { - struct device * vlink_dev; + struct device *vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg; @@ -97,11 +97,11 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -156,7 +156,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index bb8caf9..3dc5bc4 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -31,9 +31,9 @@ #include <cbmem.h> #include <arch/acpi.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; @@ -82,7 +82,7 @@ static void pci_domain_set_resources(struct device * dev) unsigned long acpi_fill_mcfg(unsigned long current) { - struct device * dev; + struct device *dev; u64 mmcfg; dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 @@ -112,7 +112,7 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = acpi_write_hpet, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 2565b1d..6f2ad3d 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -17,7 +17,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -44,12 +44,12 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -102,7 +102,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 0b5030b..01f4432 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -19,9 +19,9 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { - struct device * fb_dev; + struct device *fb_dev; unsigned long fb; unsigned char c; @@ -58,7 +58,7 @@ static void northbridge_init(struct device * dev) } } -static void nullfunc(struct device * dev) +static void nullfunc(struct device *dev) { /* Nothing to do */ } @@ -76,7 +76,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8623, }; -static void agp_init(struct device * dev) +static void agp_init(struct device *dev) { printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n"); @@ -103,10 +103,10 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); @@ -162,7 +162,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index e0fb06f..52da40c 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -37,7 +37,7 @@ /* !!FIXME!! I declared this to fix the build. */ u8 acpi_sleep_type = 0; -static void memctrl_init(struct device * dev) +static void memctrl_init(struct device *dev) { /* set VGA in uma_ram_setting.c, not in this function. @@ -71,13 +71,13 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; u8 reg; @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 7047a04..fe3e3ba 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -60,7 +60,7 @@ uint64_t get_uma_memory_base(void) return uma_memory_base; } -static u64 vx900_get_top_of_ram(struct device * mcu) +static u64 vx900_get_top_of_ram(struct device *mcu) { u16 reg16; /* The last valid DRAM address is computed by the MCU @@ -97,7 +97,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) * * @return The new top of memory. */ -static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) +static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm) { size_t i; u8 reg8, start8, end8, start, end; @@ -216,7 +216,7 @@ static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) return newtor; } -static void vx900_set_resources(struct device * dev) +static void vx900_set_resources(struct device *dev) { u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk; @@ -228,7 +228,7 @@ static void vx900_set_resources(struct device * dev) "========================================\n"); int idx = 10; - struct device * mcu = dev_find_device(PCI_VENDOR_ID_VIA, + struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); if (!mcu) { @@ -286,7 +286,7 @@ static void vx900_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void vx900_read_resources(struct device * dev) +static void vx900_read_resources(struct device *dev) { /* Our fixed resources start at 0 */ int idx = 0; @@ -317,7 +317,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -330,7 +330,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) {

1 0

Patch set updated for coreboot: 1efb673 mainboard: Don't hide pointer behind typedef
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7139 -gerrit commit 1efb673c0a5b63e38b41cff49317a6081073b352 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 09:54:41 2014 +1100 mainboard: Don't hide pointer behind typedef Change-Id: I4a0e4e1598e16e13b43401c7e834b292121b63ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/get_bus_conf.c | 2 +- src/mainboard/advansus/a785e-i/mainboard.c | 2 +- src/mainboard/amd/bimini_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/bimini_fam10/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/get_bus_conf.c | 2 +- src/mainboard/amd/dbm690t/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/dinar/mainboard.c | 2 +- src/mainboard/amd/dinar/mptable.c | 2 +- src/mainboard/amd/inagua/mainboard.c | 2 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/mahogany/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany_fam10/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/olivehill/mainboard.c | 2 +- src/mainboard/amd/olivehill/mptable.c | 2 +- src/mainboard/amd/olivehillplus/mainboard.c | 2 +- src/mainboard/amd/olivehillplus/mptable.c | 2 +- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/parmer/mptable.c | 2 +- src/mainboard/amd/persimmon/mainboard.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/pistachio/get_bus_conf.c | 2 +- src/mainboard/amd/pistachio/mainboard.c | 4 ++-- src/mainboard/amd/pistachio/mptable.c | 2 +- src/mainboard/amd/rumba/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 4 ++-- src/mainboard/amd/serengeti_cheetah/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 4 ++-- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/mptable.c | 4 ++-- src/mainboard/amd/south_station/mainboard.c | 2 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/mainboard/amd/thatcher/mptable.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 14 +++++++------- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/torpedo/mainboard.c | 2 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/union_station/mainboard.c | 2 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/apple/macbook21/mainboard.c | 4 ++-- src/mainboard/arima/hdama/debug.c | 4 ++-- src/mainboard/arima/hdama/mptable.c | 10 +++++----- src/mainboard/asrock/939a785gmh/get_bus_conf.c | 2 +- src/mainboard/asrock/939a785gmh/mainboard.c | 4 ++-- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/e350m1/mainboard.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asrock/imb-a180/mainboard.c | 2 +- src/mainboard/asrock/imb-a180/mptable.c | 2 +- src/mainboard/asus/a8n_e/get_bus_conf.c | 2 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/dsbf/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mptable.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/mainboard.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2n-e/get_bus_conf.c | 2 +- src/mainboard/asus/m2n-e/mainboard.c | 2 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/mainboard.c | 2 +- src/mainboard/asus/m2v/romstage.c | 4 ++-- src/mainboard/asus/m4a78-em/get_bus_conf.c | 2 +- src/mainboard/asus/m4a78-em/mainboard.c | 8 ++++---- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a785-m/get_bus_conf.c | 2 +- src/mainboard/asus/m4a785-m/mainboard.c | 10 +++++----- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m5a88-v/get_bus_conf.c | 2 +- src/mainboard/asus/m5a88-v/mainboard.c | 2 +- src/mainboard/avalue/eax-785e/get_bus_conf.c | 2 +- src/mainboard/avalue/eax-785e/mainboard.c | 2 +- src/mainboard/bachmann/ot200/mainboard.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/broadcom/blast/get_bus_conf.c | 2 +- src/mainboard/broadcom/blast/mptable.c | 4 ++-- src/mainboard/dmp/vortex86ex/mainboard.c | 2 +- src/mainboard/emulation/qemu-armv7/mainboard.c | 2 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/getac/p470/mainboard.c | 6 +++--- src/mainboard/getac/p470/romstage.c | 8 ++++---- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 2 +- src/mainboard/gigabyte/m57sli/mainboard.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 2 +- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gm/mainboard.c | 8 ++++---- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 12 ++++++------ src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma78gm/mainboard.c | 6 +++--- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/gizmosphere/gizmo/mainboard.c | 4 ++-- src/mainboard/gizmosphere/gizmo/mptable.c | 2 +- src/mainboard/google/bolt/mainboard.c | 6 +++--- src/mainboard/google/butterfly/mainboard.c | 6 +++--- src/mainboard/google/daisy/mainboard.c | 4 ++-- src/mainboard/google/falco/mainboard.c | 6 +++--- src/mainboard/google/link/mainboard.c | 6 +++--- src/mainboard/google/nyan/mainboard.c | 4 ++-- src/mainboard/google/nyan_big/mainboard.c | 4 ++-- src/mainboard/google/panther/mainboard.c | 4 ++-- src/mainboard/google/parrot/mainboard.c | 6 +++--- src/mainboard/google/peach_pit/mainboard.c | 4 ++-- src/mainboard/google/peppy/mainboard.c | 6 +++--- src/mainboard/google/rambi/mainboard.c | 6 +++--- src/mainboard/google/samus/mainboard.c | 6 +++--- src/mainboard/google/slippy/mainboard.c | 6 +++--- src/mainboard/google/storm/mainboard.c | 4 ++-- src/mainboard/google/stout/mainboard.c | 4 ++-- src/mainboard/hp/dl145_g1/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g1/mptable.c | 2 +- src/mainboard/hp/dl145_g3/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g3/mptable.c | 8 ++++---- src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 8 ++++---- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 2 +- src/mainboard/ibase/mb899/mainboard.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/ibm/e325/mptable.c | 4 ++-- src/mainboard/ibm/e326/mptable.c | 4 ++-- src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +- src/mainboard/intel/baskingridge/mainboard.c | 2 +- src/mainboard/intel/bayleybay_fsp/mainboard.c | 2 +- src/mainboard/intel/cougar_canyon2/mainboard.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/eagleheights/debug.c | 4 ++-- src/mainboard/intel/eagleheights/mptable.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/intel/jarrell/debug.c | 4 ++-- src/mainboard/intel/jarrell/mptable.c | 4 ++-- src/mainboard/intel/jarrell/romstage.c | 2 +- src/mainboard/intel/jarrell/watchdog.c | 8 ++++---- src/mainboard/intel/minnowmax/mainboard.c | 2 +- src/mainboard/intel/mohonpeak/mainboard.c | 2 +- src/mainboard/intel/truxton/mptable.c | 2 +- src/mainboard/intel/wtm2/mainboard.c | 2 +- src/mainboard/intel/xe7501devkit/mptable.c | 2 +- src/mainboard/iwave/iWRainbowG6/mainboard.c | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 4 ++-- src/mainboard/iwill/dk8_htx/mainboard.c | 2 +- src/mainboard/iwill/dk8_htx/mptable.c | 4 ++-- src/mainboard/iwill/dk8s2/mptable.c | 4 ++-- src/mainboard/iwill/dk8x/mptable.c | 4 ++-- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/get_bus_conf.c | 2 +- src/mainboard/jetway/pa78vm5/mainboard.c | 8 ++++---- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/kontron/986lcd-m/mainboard.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 6 +++--- src/mainboard/kontron/kt690/get_bus_conf.c | 2 +- src/mainboard/kontron/kt690/mainboard.c | 4 ++-- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/kontron/ktqm77/mainboard.c | 6 +++--- src/mainboard/kontron/ktqm77/romstage.c | 6 +++--- src/mainboard/lenovo/t520/mainboard.c | 4 ++-- src/mainboard/lenovo/t530/mainboard.c | 4 ++-- src/mainboard/lenovo/t60/mainboard.c | 7 ++++--- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x200/mainboard.c | 4 ++-- src/mainboard/lenovo/x201/mainboard.c | 6 +++--- src/mainboard/lenovo/x220/mainboard.c | 4 ++-- src/mainboard/lenovo/x230/mainboard.c | 4 ++-- src/mainboard/lenovo/x60/mainboard.c | 8 +++++--- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/frontrunner-af/mptable.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mptable.c | 2 +- src/mainboard/msi/ms7135/get_bus_conf.c | 2 +- src/mainboard/msi/ms7135/mptable.c | 2 +- src/mainboard/msi/ms7260/get_bus_conf.c | 2 +- src/mainboard/msi/ms7260/mainboard.c | 2 +- src/mainboard/msi/ms7260/mptable.c | 2 +- src/mainboard/msi/ms9185/get_bus_conf.c | 2 +- src/mainboard/msi/ms9185/mptable.c | 4 ++-- src/mainboard/msi/ms9282/get_bus_conf.c | 2 +- src/mainboard/msi/ms9282/mainboard.c | 2 +- src/mainboard/msi/ms9282/mptable.c | 2 +- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 2 +- src/mainboard/msi/ms9652_fam10/mainboard.c | 2 +- src/mainboard/msi/ms9652_fam10/mptable.c | 2 +- src/mainboard/newisys/khepri/mptable.c | 4 ++-- src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 2 +- src/mainboard/nvidia/l1_2pvv/mainboard.c | 2 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 8 ++++---- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/rca/rm4100/mainboard.c | 4 ++-- src/mainboard/roda/rk886ex/mainboard.c | 4 ++-- src/mainboard/roda/rk886ex/romstage.c | 8 ++++---- src/mainboard/roda/rk9/mainboard.c | 2 +- src/mainboard/roda/rk9/romstage.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 8 +++----- src/mainboard/samsung/stumpy/mainboard.c | 2 +- src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 21 +++++++++++---------- src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +- src/mainboard/sunw/ultra40/get_bus_conf.c | 2 +- src/mainboard/sunw/ultra40/mptable.c | 2 +- src/mainboard/supermicro/h8dme/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dme/mptable.c | 2 +- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qgi/mainboard.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++-- src/mainboard/supermicro/h8scm/mainboard.c | 2 +- src/mainboard/supermicro/h8scm/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 6 +++--- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/debug.c | 4 ++-- src/mainboard/supermicro/x6dai_g/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/romstage.c | 2 +- src/mainboard/supermicro/x6dai_g/watchdog.c | 2 +- src/mainboard/supermicro/x6dhe_g/debug.c | 4 ++-- src/mainboard/supermicro/x6dhe_g/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhe_g2/debug.c | 4 ++-- src/mainboard/supermicro/x6dhe_g2/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhe_g2/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g2/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhr_ig/debug.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhr_ig2/debug.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig2/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/watchdog.c | 6 +++--- src/mainboard/supermicro/x7db8/mainboard.c | 2 +- src/mainboard/technexion/tim5690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 4 ++-- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim8690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 6 +++--- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/thomson/ip1000/mainboard.c | 4 ++-- src/mainboard/tyan/s2735/mptable.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 4 ++-- src/mainboard/tyan/s2875/mptable.c | 4 ++-- src/mainboard/tyan/s2880/mptable.c | 6 +++--- src/mainboard/tyan/s2881/get_bus_conf.c | 2 +- src/mainboard/tyan/s2881/mptable.c | 2 +- src/mainboard/tyan/s2882/mptable.c | 6 +++--- src/mainboard/tyan/s2885/get_bus_conf.c | 2 +- src/mainboard/tyan/s2885/mptable.c | 2 +- src/mainboard/tyan/s2891/get_bus_conf.c | 2 +- src/mainboard/tyan/s2891/mainboard.c | 2 +- src/mainboard/tyan/s2891/mptable.c | 2 +- src/mainboard/tyan/s2892/get_bus_conf.c | 2 +- src/mainboard/tyan/s2892/mainboard.c | 2 +- src/mainboard/tyan/s2892/mptable.c | 2 +- src/mainboard/tyan/s2895/get_bus_conf.c | 2 +- src/mainboard/tyan/s2895/mainboard.c | 2 +- src/mainboard/tyan/s2895/mptable.c | 2 +- src/mainboard/tyan/s2912/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912/mptable.c | 2 +- src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912_fam10/mptable.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 6 +++--- src/mainboard/tyan/s4882/mptable.c | 6 +++--- src/mainboard/tyan/s8226/mainboard.c | 2 +- src/mainboard/tyan/s8226/mptable.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m/romstage.c | 6 +++--- src/mainboard/via/epia-m700/romstage.c | 8 ++++---- src/mainboard/via/epia-m850/mainboard.c | 2 +- src/mainboard/via/epia-n/romstage.c | 4 ++-- src/mainboard/via/epia/romstage.c | 4 ++-- src/mainboard/via/vt8454c/romstage.c | 2 +- src/mainboard/winent/mb6047/get_bus_conf.c | 2 +- src/mainboard/winent/mb6047/mainboard.c | 2 +- src/mainboard/winent/mb6047/mptable.c | 2 +- 302 files changed, 483 insertions(+), 481 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 80e1d3e..2c5757a 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 9b6450d..686e968 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in A785E-I board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index f7c55143..6b31272 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -64,7 +64,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 32c8862..cd4f50e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -100,7 +100,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -123,7 +123,7 @@ static void get_ide_dma66(void) * enable the dedicated function in bimini board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/dbm690t/get_bus_conf.c +++ b/src/mainboard/amd/dbm690t/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 43a8d91..b92426c 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 00f1a84..83171a0 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -68,7 +68,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in dinar board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 4e481f5..e796ffe 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sb700; u32 apicid_rd890; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc23007..0c57350 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -74,7 +74,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7686bd2..65f67cc 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/amd/mahogany/get_bus_conf.c +++ b/src/mainboard/amd/mahogany/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 0e542ff..e851e8f 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -97,7 +97,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index bd31846..bebf041 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 7d4514a..8f90235 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -98,7 +98,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index db4a3ff..d209582 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 6073fd4..1e58d88 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 73660e4..0ca9217 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 2ba714a..4b192c2 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in parmer board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 05da01a..7999dd8 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 58ac983..34918a8 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -151,7 +151,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 1227d89..1ae44c4 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/pistachio/get_bus_conf.c +++ b/src/mainboard/amd/pistachio/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 75f92bd..db2cbcf 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -76,7 +76,7 @@ static void set_thermal_config(void) u8 byte, byte2; u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* set adt7475 */ ADT7475_write_byte(0x40, 0x04); @@ -250,7 +250,7 @@ static void set_thermal_config(void) * enable the dedicated function in pistachio board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index 5725c78..2f6af29 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -7,7 +7,7 @@ static void init(struct device *dev) { - device_t nic = NULL; + struct device * nic = NULL; unsigned bus = 0; unsigned devfn = PCI_DEVFN(0xd, 0); int nicirq = 1; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index f5cd846..f2d7f9e 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c index b9c88f6..26f61f8 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.c +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.c @@ -5,7 +5,7 @@ #include <arch/acpigen.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 866875d..341b367 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -114,7 +114,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 48d5cc3..02dfb3c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ static u32 get_hcid(u32 i) u32 id = 0; u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; u32 devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); @@ -95,7 +95,7 @@ void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 5335cb8..3b4731b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v) if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; int jj; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 43d6a78..1be0c0a 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -77,7 +77,7 @@ static void southstation_led_init(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); southstation_led_init(); diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 834117e..e7b7ecf 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 8ddd1b6..e34b899 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index cc97866..8ebd6b4 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -46,7 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); hudson_lpc_port80(); diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 48e4c17..efea2fa 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -102,7 +102,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -127,7 +127,7 @@ static void get_ide_dma66(void) u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -157,7 +157,7 @@ static void set_gpio40_gfx(void) { u8 byte; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -212,7 +212,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -273,7 +273,7 @@ static void set_thermal_config(void) * enable the dedicated function in tilapia board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 9b52b89..f5f9c94 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) /************************************************* * enable the dedicated function in torpedo board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 477d97a..53038dd 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -186,7 +186,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 8816e8d..ca2e887 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 99527c1..c9858d8 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -41,12 +41,12 @@ int get_cst_entries(acpi_cstate_t **entries) return 0; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c index a6f0d55..d29a5b9 100644 --- a/src/mainboard/arima/hdama/debug.c +++ b/src/mainboard/arima/hdama/debug.c @@ -11,7 +11,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -50,7 +50,7 @@ static void dump_pci_device(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 6ee2704..c1a6cef 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -13,7 +13,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -48,7 +48,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) static unsigned max_apicid(void) { unsigned max; - device_t dev; + struct device * dev; max = 0; for(dev = all_devices; dev; dev = dev->next) { if (dev->path.type != DEVICE_PATH_APIC) @@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v) apicid_8131_1 = apicid_base + 1; apicid_8131_2 = apicid_base + 2; { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1)); @@ -206,7 +206,7 @@ static void *smp_write_config_table(void *v) static void reboot_if_hotswap(void) { /* Hack patch work around for hot swap enable 33mhz problem */ - device_t dev; + struct device * dev; uint32_t data; unsigned long htic; int reset; diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c +++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 58ad8b2..a8d2913 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -67,7 +67,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -95,7 +95,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 790d1da..0d174bc 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..1f554f2 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 14fa316..23b5261 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index d9ca7b7..38db63a 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -183,7 +183,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c index a55401b..22d0123 100644 --- a/src/mainboard/asus/a8n_e/get_bus_conf.c +++ b/src/mainboard/asus/a8n_e/get_bus_conf.c @@ -63,7 +63,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index a954d92..b6e1059 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..32472ee 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..74b768e 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/asus/dsbf/mainboard.c +++ b/src/mainboard/asus/dsbf/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 191eea8..ff4eb20 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index cc81819..e5d7603 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -149,7 +149,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index caa32ca..6126cb8 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -67,7 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index cd45213..2898b51 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -27,7 +27,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..4b897b1 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -88,7 +88,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c index fd7d304..c9d113d 100644 --- a/src/mainboard/asus/m2n-e/get_bus_conf.c +++ b/src/mainboard/asus/m2n-e/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c index 2c18100..7bf4639 100644 --- a/src/mainboard/asus/m2n-e/mainboard.c +++ b/src/mainboard/asus/m2n-e/mainboard.c @@ -21,7 +21,7 @@ #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c index 333ec49..69a5260 100644 --- a/src/mainboard/asus/m2n-e/mptable.c +++ b/src/mainboard/asus/m2n-e/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) struct mp_config_table *mc; unsigned int sbdn; int i, j, bus_isa; - device_t dev; + struct device * dev; struct resource *res; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index d12b77c..df73222 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -72,7 +72,7 @@ static void sio_setup(void) { u8 byte; u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ /* Subject decoding */ byte = pci_read_config8(dev, 0x7b); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..605c19d 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -107,7 +107,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index 21adac0..cbacc88 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -26,7 +26,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..74d2edc 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -91,7 +91,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); @@ -189,7 +189,7 @@ static void m2v_it8712f_gpio_init(void) static void m2v_bus_init(void) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "m2v_bus_init\n"); diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 1a2e9fc..b32ca0c 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -36,7 +36,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -61,7 +61,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -91,7 +91,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -118,7 +118,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index b1154ab..edaecab 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -100,7 +100,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -129,7 +129,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -190,7 +190,7 @@ static void set_thermal_config(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 8ee338e..1da327b 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in M5A88-V board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 6ce3469..6ee5923 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in EAX-785E board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c index d4b0b2d..ea13cef 100644 --- a/src/mainboard/bachmann/ot200/mainboard.c +++ b/src/mainboard/bachmann/ot200/mainboard.c @@ -46,7 +46,7 @@ static void init(struct device *dev) u32 chksum = 0; char block[20]; msr_t reset; - device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52); + struct device * eeprom_dev = dev_find_slot_on_smbus(1, 0x52); if (eeprom_dev == 0) { printk(BIOS_WARNING, "eeprom not found\n"); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 898ad1a..391263b 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 5de8952..f95d70a 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -50,7 +50,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d7ae6b7..9d415d2 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index 2761035..381658a 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 83a55e3..815f50e 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Enable qemu/armv7 device...\n"); } diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index a8a61c4..6d1f2b0 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -30,7 +30,7 @@ static const unsigned char qemu_i440fx_irqs[] = { 11, 10, 10, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e991b53..622ea54 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -33,7 +33,7 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 2b33ff0..1dc881a 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -62,7 +62,7 @@ static void pcie_limit_power(void) // machine. It should set the slot numbers and enable power // limitation for the PCIe slots. - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(28,0)); if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0); @@ -79,14 +79,14 @@ static void pcie_limit_power(void) } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { ec_enable(); } // mainboard_enable is executed as first thing after // enumerate_buses(). Is there no mainboard_init()? -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 3dab527..da40c55 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -105,19 +105,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pnp_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -126,7 +126,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x4e, 0x00); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index 9315cbd..c9c1950 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 0af6cf0..9e8c7bf 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index c798415..db5b685 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/gigabyte/m57sli/mainboard.c +++ b/src/mainboard/gigabyte/m57sli/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 1536823..43459bc 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index cd06069..9fe9c7f 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -35,7 +35,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -60,7 +60,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -134,7 +134,7 @@ static void set_gpio40_gfx(void) * enable the dedicated function in ma785gm board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 89b50bb..f591ebb 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ void set_pcie_reset() int is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -128,7 +128,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -183,7 +183,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -244,7 +244,7 @@ static void set_thermal_config(void) * enable the dedicated function in ma785gmt board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 49df0c2..2fd5c52 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -38,7 +38,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -51,7 +51,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -71,7 +71,7 @@ u8 is_dev3_present(void) * enable the dedicated function in board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index a9afdfb..ad8fa58 100755 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -55,7 +55,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -78,7 +78,7 @@ static void mainboard_enable(device_t dev) void mainboard_final( void *chip_info ); void mainboard_final( void *chip_info ) { - device_t ahci_dev; + struct device * ahci_dev; u32 ABAR; u8 *memptr; diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index b98598a..8301bd5 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/google/bolt/mainboard.c b/src/mainboard/google/bolt/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/bolt/mainboard.c +++ b/src/mainboard/google/bolt/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 655fc2f..c4006c6 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -194,7 +194,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { u32 search_address = 0x0; size_t search_length = -1; @@ -258,7 +258,7 @@ static void mainboard_init(device_t dev) } } -static int butterfly_onboard_smbios_data(device_t dev, int *handle, +static int butterfly_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -278,7 +278,7 @@ static int butterfly_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 0adadb6..fc9a08c 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -258,7 +258,7 @@ static void gpio_init(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { int dp_tries; struct s5p_dp_device dp_device = { @@ -322,7 +322,7 @@ static void mainboard_init(device_t dev) // gpio_info(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/falco/mainboard.c +++ b/src/mainboard/google/falco/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index ed40f8f..d1a3856 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -149,7 +149,7 @@ static int int15_handler(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ link_ec_init(); @@ -166,7 +166,7 @@ static void mainboard_init(device_t dev) } } -static int link_onboard_smbios_data(device_t dev, int *handle, +static int link_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -204,7 +204,7 @@ static int link_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 6fa8a95..d7df116 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -284,7 +284,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 4a05991..908d610 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -281,7 +281,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index 5058eca..a1bd459 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { lan_init(); } @@ -52,7 +52,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 547680e..207bcfd 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -48,13 +48,13 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ parrot_ec_init(); } -static int parrot_onboard_smbios_data(device_t dev, int *handle, +static int parrot_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -85,7 +85,7 @@ static int parrot_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1fb441d..53db9fa 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -405,7 +405,7 @@ static void sdmmc_vdd(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* we'll stick with the crummy u-boot struct for now.*/ /* doing this as an auto since the struct has to be writeable */ @@ -462,7 +462,7 @@ static void mainboard_init(device_t dev) setup_usb(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/peppy/mainboard.c +++ b/src/mainboard/google/peppy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index cd3fc48..b43928d 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -127,12 +127,12 @@ static int int15_handler(void) } #endif -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -161,7 +161,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index 7977ce3..de7f434 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -42,12 +42,12 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -112,7 +112,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0b0182f..4792ea9 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -20,11 +20,11 @@ #include <device/device.h> #include <boot/coreboot_tables.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 9bcbfe4..58d89b8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -48,7 +48,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct device *ethernet_dev = NULL; @@ -70,7 +70,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index acfa023..6a36ef7 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -51,7 +51,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index b9af38b..7e81143 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); if (dev) { diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index ba0fc88..59b35aa 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 6c71bad..6b3032b 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 099c41a..6561c94 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 86f2cc6..175cfe5 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index f858455..3384a9f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -41,7 +41,7 @@ static void pavilion_cold_boot_init(void) pavilion_m6_1035dx_ec_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index f47b9d9..d12e759 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -144,7 +144,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index a2a10a1..ba6a09e 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -31,7 +31,7 @@ // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 322907b..e8931f0 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -76,7 +76,7 @@ static void ich7_enable_lpc(void) */ static void early_superio_config_w83627ehg(void) { - device_t dev; + pnp_devfn_t dev; dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 6eb6390..50f8031 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c index f271166..d85e609 100644 --- a/src/mainboard/ibm/e326/mptable.c +++ b/src/mainboard/ibm/e326/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index 43ff9c1..9d67e2b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -53,7 +53,7 @@ u8 is_dev3_present(void) * enable the dedicated function in kino board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index a83bf7e..0cb238b 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -69,7 +69,7 @@ void main(unsigned long bist) console_init(); /* Enable COM3. */ - device_t dev = PNP_DEV(0x2e, 0x0b); + pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b); u16 port = dev >> 8; outb(0x55, port); pnp_set_logical_device(dev); diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index feae6ef..d32ca91 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -38,7 +38,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c index 0ea03d3..f0062d5 100644 --- a/src/mainboard/intel/cougar_canyon2/mainboard.c +++ b/src/mainboard/intel/cougar_canyon2/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index cc956a7..c6cf529 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -56,7 +56,7 @@ static inline void reset_system(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index e5795b6..c25b3a3 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -143,7 +143,7 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -210,7 +210,7 @@ static inline void dump_bar14(unsigned dev) static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 809feec..78dfb62 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; int bus_isa, i; uint32_t pin, route; - device_t dev; + struct device * dev; struct resource *res; unsigned long rcba; diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 220b1d7..f9f6a85 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -47,7 +47,7 @@ static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/intel/jarrell/debug.c +++ b/src/mainboard/intel/jarrell/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index 21664ce..6dcf7d7 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index f1cf4c3..29553fc 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -75,7 +75,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index 7f7a039..9722c04 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -6,7 +6,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { /* FIXME move me somewhere more appropriate */ pnp_set_logical_device(dev); @@ -20,7 +20,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -48,7 +48,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -97,7 +97,7 @@ static void disable_watchdogs(void) static void ich5_watchdog_on(void) { - device_t dev; + pci_devfn_t dev; unsigned long value, base; unsigned char byte; diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c index 3da1e23..ce9872a 100644 --- a/src/mainboard/intel/minnowmax/mainboard.c +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -25,7 +25,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c index 7559fc2..387931d 100644 --- a/src/mainboard/intel/mohonpeak/mainboard.c +++ b/src/mainboard/intel/mohonpeak/mainboard.c @@ -24,7 +24,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index 9ad6ea6..2c7eb92 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) u8 bus_pea0 = 0; u8 bus_pea1 = 0; u8 bus_aioc; - device_t dev; + struct device * dev; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index cc7eda5..65e4bcc 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -19,7 +19,7 @@ static int bus_isa; static void xe7501devkit_register_ioapics(struct mp_config_table *mc) { - device_t dev; + struct device * dev; struct resource *res; // TODO: Gack. This is REALLY ugly. diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c index dfc6636..457c88f 100644 --- a/src/mainboard/iwave/iWRainbowG6/mainboard.c +++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c @@ -22,7 +22,7 @@ #include <console/console.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index 87de022..da83738 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -36,7 +36,7 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index 8868f46..be033f5 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c index 0202b50..909e5a9 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.c +++ b/src/mainboard/iwill/dk8_htx/mainboard.c @@ -7,7 +7,7 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index ff6e582..416cd17 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -126,7 +126,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8s2/mptable.c +++ b/src/mainboard/iwill/dk8s2/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8x/mptable.c +++ b/src/mainboard/iwill/dk8x/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index a9c71c3..fe3f48c 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d67e072..92c8d70 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -153,7 +153,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 4390605..2c9606a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -116,7 +116,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 373ebb5..6da52fc 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -39,7 +39,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -52,7 +52,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -72,7 +72,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -100,7 +100,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 7cabdf1..0c7130b 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index afca796..0ae64b5 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -164,7 +164,7 @@ static void hwm_setup(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 2c12c5d..a28593f 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -78,14 +78,14 @@ static void ich7_enable_lpc(void) } /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_func_mode(device_t dev) +static void pnp_enter_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_func_mode(device_t dev) +static void pnp_exit_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -98,7 +98,7 @@ static void pnp_exit_func_mode(device_t dev) */ static void early_superio_config_w83627thg(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/kontron/kt690/get_bus_conf.c +++ b/src/mainboard/kontron/kt690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 717c399..a88a2c8 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 715ec56..6f6c2d8 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -172,7 +172,7 @@ static int int15_handler(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ @@ -181,7 +181,7 @@ static void mainboard_enable(device_t dev) unsigned disable = 0; if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); if (nic) { printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n"); nic->enabled = 0; @@ -189,7 +189,7 @@ static void mainboard_enable(device_t dev) } disable = 0; if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); if (nic) { printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n"); nic->enabled = 0; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 401314c..d1a6279 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -125,14 +125,14 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -142,7 +142,7 @@ static void superio_gpio_config(void) { int lvds_3v = 0; // 0 (5V) or 1 (3V3) int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled - device_t dev = PNP_DEV(0x2e, 0x9); + pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 387bbe0..ddd6d22 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -65,7 +65,7 @@ static void mainboard_init(device_t dev) /* mainboard_enable is executed as first thing after enumerate_buses(). */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index f8c9dae..922b424 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -69,7 +69,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 79b3da8..d960b11 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -61,10 +61,11 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + struct device * dev0; + struct device * idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); @@ -95,7 +96,7 @@ static void mainboard_init(device_t dev) ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index f11b33e..24d4ab6 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -98,7 +98,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0xa0); diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 0054064..c79b552 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -45,7 +45,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* This sneaked in here, because X200 SuperIO chip isn't really connected to anything and hence we don't init it. @@ -53,7 +53,7 @@ static void mainboard_init(device_t dev) pc_keyboard_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 5b76be2..f61bb9a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -71,7 +71,7 @@ const char *smbios_mainboard_bios_version(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -117,9 +117,9 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { - device_t dev0; + struct device * dev0; u16 pmbase; dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 00e7991..c86825e 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -49,7 +49,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -72,7 +72,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index a060015..28d7344 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -50,7 +50,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -73,7 +73,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 1d29c71..9f0cda4 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -56,9 +56,11 @@ int get_cst_entries(acpi_cstate_t **entries) return ARRAY_SIZE(cst_entries); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { - device_t dev0, idedev, sdhci_dev; + struct device * dev0; + struct device * idedev; + struct device * sdhci_dev; ec_clr_bit(0x03, 2); @@ -115,7 +117,7 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 943143a..348b5fe 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -105,7 +105,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index ee538c3..983df2c 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -163,7 +163,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 9e44a21..28ac9ba 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -130,7 +130,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c index e364892..cb2bd5d 100644 --- a/src/mainboard/msi/ms7135/get_bus_conf.c +++ b/src/mainboard/msi/ms7135/get_bus_conf.c @@ -55,7 +55,7 @@ void get_bus_conf(void) { unsigned apicid_base; - device_t dev; + struct device *dev; unsigned sbdn; int i; diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c index b43a516..0c7032f 100644 --- a/src/mainboard/msi/ms7135/mptable.c +++ b/src/mainboard/msi/ms7135/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; u32 dword; diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c index 34d3834..97b2b70 100644 --- a/src/mainboard/msi/ms7260/get_bus_conf.c +++ b/src/mainboard/msi/ms7260/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c index 492693a..d4e111f 100644 --- a/src/mainboard/msi/ms7260/mainboard.c +++ b/src/mainboard/msi/ms7260/mainboard.c @@ -23,7 +23,7 @@ #if 0 -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } #endif diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index ea003a8..a200b70 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 3a70d83..86afc47 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index b30ab73..fc00858 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c index 195ddc4..776fabb 100644 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ b/src/mainboard/msi/ms9282/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c index c7e459a..54cdc3b 100644 --- a/src/mainboard/msi/ms9282/mainboard.c +++ b/src/mainboard/msi/ms9282/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index 1764cf3..432e702 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 36ae12c..4ec04f5 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; printk(BIOS_SPEW, "get_bus_conf()\n"); diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c index 96760d6..7fc97f0 100644 --- a/src/mainboard/msi/ms9652_fam10/mainboard.c +++ b/src/mainboard/msi/ms9652_fam10/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 09a25f2..1b9b349 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c index 1d7c79e..ede913f 100644 --- a/src/mainboard/newisys/khepri/mptable.c +++ b/src/mainboard/newisys/khepri/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c index 125b564..b77a355 100644 --- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c +++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c @@ -73,7 +73,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/nvidia/l1_2pvv/mainboard.c +++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index e991efd..5cdad5b 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; @@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; @@ -128,7 +128,7 @@ static void *smp_write_config_table(void *v) //Slot PCI 32 { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); if (dev && dev->enabled) { for (i = 0; i < 4; i++) @@ -148,7 +148,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index c14e9b7..c5b51e0 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t ** entries) -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 pmbase; diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 2e3191b..421c916 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -20,12 +20,12 @@ #include <device/device.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { // TODO Switch parport LEDs again } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { // TODO Switch parport LEDs dev->ops->init = mainboard_init; diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 4c7fffa..5421d13 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -63,14 +63,14 @@ static void dump_runtime_registers(void) } #endif -static void mainboard_final(device_t dev) +static void mainboard_final(struct device * dev) { /* Enable Dummy DCC ON# for DVI */ printk(BIOS_DEBUG, "Laptop handling...\n"); outb(inb(0x60f) & ~(1 << 5), 0x60f); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { /* Configure the MultiKey controller */ // m3885_configure_multikey(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7cc1a1d..0278cdf 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -93,19 +93,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pnp_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -114,7 +114,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x2e, 0x00); diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index acf8023..39ade3f 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -44,7 +44,7 @@ static void ec_setup(void) send_ec_command(0xad); /* Set_Thml_Value */ } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { ec_setup(); /* LCD panel type is SIO GPIO40-43. diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c8b75e0..89026ac 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -88,7 +88,7 @@ static void default_superio_gpio_setup(void) GP1 GP2 GP3 GP4 fd 17 88 14 */ - const device_t sio = PNP_DEV(0x2e, 0); + const pnp_devfn_t sio = PNP_DEV(0x2e, 0); /* Enter super-io's configuration state. */ pnp_enter_conf_state(sio); diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 3bdd4d9..d53bf9e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -46,9 +46,7 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } - - -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ lumpy_ec_init(); @@ -80,7 +78,7 @@ static int lumpy_smbios_type41_irq(int *handle, unsigned long *current, } -static int lumpy_onboard_smbios_data(device_t dev, int *handle, +static int lumpy_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -101,7 +99,7 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c +++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 77be0af..219527a 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -389,7 +389,7 @@ static void pm_init( void ) { u16 word; u8 byte; - device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + struct device * sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* set SB600 GPIO 64 to GPIO with pull-up */ byte = pm2_ioread(0x42); @@ -432,7 +432,7 @@ static void set_thermal_config(void) { u8 byte, byte2; u8 cpu_pwm_conf, case_pwm_conf; - device_t sm_dev; + struct device * sm_dev; struct fan_control cpu_fan_control, case_fan_control; const char *name = NULL; @@ -614,8 +614,8 @@ static void patch_mmio_nonposted( void ) resource_t rbase, rend; u32 base, limit; struct resource *resource; - device_t dev; - device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); + struct device * dev; + struct device * k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); printk(BIOS_DEBUG,"%s ...\n", __func__); @@ -668,7 +668,7 @@ struct { unsigned int plx_present = 0; -static void update_subsystemid( device_t dev ) +static void update_subsystemid(struct device * dev) { int i; @@ -680,7 +680,7 @@ static void update_subsystemid( device_t dev ) } printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device ); for( i=0; slot[i].bus < 255; i++) { - device_t d; + struct device * d; d = dev_find_slot(slot[i].bus,slot[i].devfn); if( d ) { printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device); @@ -695,10 +695,11 @@ static void update_subsystemid( device_t dev ) * @param */ -static void detect_hw_variant( device_t dev ) +static void detect_hw_variant(struct device * dev) { - device_t nb_dev =0, dev2 = 0; + struct device * nb_dev = NULL; + struct device * dev2 = NULL; struct southbridge_amd_rs690_config *cfg; u32 lc_state, id = 0; @@ -807,7 +808,7 @@ static void smm_lock( void ) * @param the root device */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE INT15_function_extensions int15_func; @@ -833,7 +834,7 @@ static void mainboard_init(device_t dev) * enable the dedicated function in sina board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "%s %s[%x/%x] %s\n", diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index de5151d..194b5ba 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index f57719a..f716158 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; if (get_bus_conf_done == 1) return; //do it only once diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index 1ba1dcf..6259278 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index 17067ed..d53b498 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 11db23f..5a24259 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index a1de06c..71eb756 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -72,7 +72,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index 4e2d48c..5c88156 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 8f12e22..cdce2f9 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -65,7 +65,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8qgi board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 50e2b44..7a80f74 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -74,7 +74,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 4fbb4c8..79f8a5e 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 24ecb5d..ce348ba 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -115,14 +115,14 @@ static const u8 spd_addr[] = { #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c index 23b1d72..de1dead 100644 --- a/src/mainboard/supermicro/h8scm/mainboard.c +++ b/src/mainboard/supermicro/h8scm/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8scm board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 0560180..fc3a446 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -65,7 +65,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 18e1e8c..4908dcb 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -49,7 +49,7 @@ u8 is_dev3_present(void) ***/ void set_pcie_reset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); @@ -58,7 +58,7 @@ void set_pcie_reset(void) void set_pcie_dereset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); @@ -69,7 +69,7 @@ void set_pcie_dereset(void) * enable the dedicated function in h8scm board. * This function called early than sr5650_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 84593fc..864cdd1 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index 0efae77..4185a54 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* southbridge */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 0385cad..0998b02 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -70,7 +70,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing 6300ESB?"); diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c index 2fd3274..bf9f9f1 100644 --- a/src/mainboard/supermicro/x6dai_g/watchdog.c +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -8,7 +8,7 @@ static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index ab73fc7..18fe954 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 405a2bc..6e90958 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -73,7 +73,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing esb6300?"); diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c index 1d34f7d..3fab7f9 100644 --- a/src/mainboard/supermicro/x6dhe_g/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -5,7 +5,7 @@ #define ESB6300_WDBASE 0x400 #define ESB6300_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index a2b8c8d..c4d690e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 48945eb..b9e0d50 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -73,7 +73,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5r?"); diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c index 1d34f7d..3fab7f9 100644 --- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -5,7 +5,7 @@ #define ESB6300_WDBASE 0x400 #define ESB6300_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index f9165d6..935ae8c 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(2, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 08b0ccd..e78d511 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -72,7 +72,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c index a451c32..259ea79 100644 --- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -5,7 +5,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index 93199d7..5ea10d2 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -121,7 +121,7 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -188,7 +188,7 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index b5ba6b1..56aec2e 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index dfe0da2..5d6d89c 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -72,7 +72,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c index a451c32..259ea79 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -5,7 +5,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/supermicro/x7db8/mainboard.c +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim5690/get_bus_conf.c +++ b/src/mainboard/technexion/tim5690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..da4ed9a 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -117,7 +117,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -222,7 +222,7 @@ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) * enable the dedicated function in tim5690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 gpio_base = IT8712F_SIMPLE_IO_BASE; #if CONFIG_VGA_ROM_RUN diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ b/src/mainboard/technexion/tim8690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 6010eb1..14811bb 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -53,7 +53,7 @@ static void enable_onboard_nic(void) { u8 byte; - device_t sm_dev; + struct device * sm_dev; printk(BIOS_INFO, "enable_onboard_nic.\n"); @@ -79,7 +79,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -140,7 +140,7 @@ static void set_thermal_config(void) * enable the dedicated function in tim8690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index 7267696..9bd4f53 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -84,13 +84,13 @@ static void flash_gpios(void) } } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { parport_gpios(); flash_gpios(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 9073728..9f65205 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 371d9a3..3145e32 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 90299a7..798ea64 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 32fc639..cbefcdb 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index 332e578..b2177a4 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -53,7 +53,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 7df5e87..d28a104 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index 6c07965..b06b49c 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -11,7 +11,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index 88706c0..dfd62b8 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -56,7 +56,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 26081c7..6413230 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index e94c608..5ff3e3b 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -60,7 +60,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index cb49434..f52a07b 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 0ead854..e59cd33 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -58,7 +58,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index 882ac69..d3dc505 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c index 11b1bc2..c6d9a08 100644 --- a/src/mainboard/tyan/s2895/get_bus_conf.c +++ b/src/mainboard/tyan/s2895/get_bus_conf.c @@ -66,7 +66,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 604df51..85f5556 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -12,7 +12,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index 20fa92c..3c4242f 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index 7727c4b..fb38d32 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 133ce43..8620cd4 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 0a3a9d8..6a9e2e9 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index e15387d..0b7ce31 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index dcc0fd8..3ec04bb 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 2); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 350b55c..3d22fd9 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 1); @@ -119,7 +119,7 @@ static void *smp_write_config_table(void *v) apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s8226/mainboard.c b/src/mainboard/tyan/s8226/mainboard.c index 9e8160a..6f094cb 100644 --- a/src/mainboard/tyan/s8226/mainboard.c +++ b/src/mainboard/tyan/s8226/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in s8226 board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 20f99cb..d3d5857 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -44,7 +44,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 3f2a0c4..2d66bbd 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -25,7 +25,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); @@ -57,7 +57,7 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; /* no need to look up 0:0.0 */ + pci_devfn_t dev = 0; /* no need to look up 0:0.0 */ unsigned char shadowreg; /* dev 0 for southbridge */ shadowreg = pci_read_config8(dev, 0x63); @@ -69,7 +69,7 @@ static void enable_shadow_ram(void) #include <cpu/intel/romstage.h> static void main(unsigned long bist) { - device_t dev; + pci_devfn_t dev; /* Enable VGA; 32MB buffer. */ pci_write_config8(0, 0xe1, 0xdd); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index b00ece1..700d13f 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -55,7 +55,7 @@ */ static int acpi_is_wakeup_early_via_vx800(void) { - device_t dev; + pci_devfn_t dev; u16 tmp, result; print_debug("In acpi_is_wakeup_early_via_vx800\n"); @@ -83,7 +83,7 @@ static int acpi_is_wakeup_early_via_vx800(void) /* All content of this function came from the cx700 port of coreboot. */ static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; #if 0 /* * Add and close this switch, since some line cause error, some @@ -378,8 +378,8 @@ void main(unsigned long bist) { u16 boot_mode; u8 rambits, Data8, Data; - device_t device; - /* device_t dev; */ + pci_devfn_t device; + /* pci_devfn_t dev; */ /* * Enable multifunction for northbridge. These 4 lines (until diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index dbe682c..146c21b 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -95,7 +95,7 @@ static int vx900_int15_handler(void) } #endif -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { (void)dev; diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 2ede8d8..f8ba755 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -58,7 +58,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; u8 reg; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -105,7 +105,7 @@ static void enable_shadow_ram(void) static void main(unsigned long bist) { unsigned long x; - device_t dev; + pci_devfn_t dev; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 1d312d7..aff85a5 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -24,7 +24,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; /* dev 0 for southbridge */ dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); @@ -60,7 +60,7 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; + pci_devfn_t dev = 0; unsigned char shadowreg; shadowreg = pci_read_config8(dev, 0x63); diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index f6d58c8..97f1858 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -39,7 +39,7 @@ static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index 5b96b05..1c7e1da 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -35,7 +35,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/winent/mb6047/mainboard.c +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index 26e79ca..afbb8b9 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -33,7 +33,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword;

1 0

Patch set updated for coreboot: 38c1427 southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 38c1427d159803bd1778fa3b43bdcb3949f3072d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb600/sata.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/amd/sb700/sata.c | 2 +- src/southbridge/amd/sb800/sata.c | 2 +- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/intel/bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/bd82x6x/sata.c | 4 ++-- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/esb6300/sata.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/fsp_bd82x6x/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/intel/i3100/sata.c | 2 +- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801ix/sata.c | 6 +++--- src/southbridge/intel/ibexpeak/me.c | 14 +++++++------- src/southbridge/intel/ibexpeak/sata.c | 4 ++-- src/southbridge/intel/lynxpoint/sata.c | 4 ++-- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/sis/sis966/sata.c | 2 +- src/southbridge/via/vt8231/early_serial.c | 2 +- src/southbridge/via/vt8237r/sata.c | 2 +- src/southbridge/via/vt82c686/early_serial.c | 4 ++-- 48 files changed, 138 insertions(+), 138 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..ce22d34 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..86e4f89 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index a17aab8..b965bb9 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -70,7 +70,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb600_config *conf; conf = dev->chip_info; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index c0e3c0f..1a7410b 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -86,7 +86,7 @@ static void sata_init(struct device *dev) u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 5ac6144..c592298 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -89,7 +89,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb800_config *conf; conf = dev->chip_info; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..5cf1376 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device * dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..d2b908e 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 44c7273..a316ea0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -548,7 +548,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -615,7 +615,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -645,7 +645,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -692,14 +692,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -741,7 +741,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index cb5699e..897470b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -211,7 +211,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -236,7 +236,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..e5783e7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + struct device * dev; ich9_spi_regs *ich9_spi; uint16_t hsfs; diff --git a/src/southbridge/intel/esb6300/sata.c b/src/southbridge/intel/esb6300/sata.c index b08f0ed..cc11006 100644 --- a/src/southbridge/intel/esb6300/sata.c +++ b/src/southbridge/intel/esb6300/sata.c @@ -42,7 +42,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); } -static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void esb6300_sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* This value is also visible in usb1, usb2 and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 2282378..ddec118 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -119,7 +119,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -547,7 +547,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -614,7 +614,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -644,7 +644,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -691,14 +691,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -740,7 +740,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 591bdbc..cbbb76b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -82,11 +82,11 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index f672e4c..dcaa230 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -95,11 +95,11 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..c4e8a1c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + struct device * dev; uint32_t ids; uint16_t vendor_id, device_id; diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index 0740440..6f4ebf9 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -111,7 +111,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index ea29986..e0794d6 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -188,7 +188,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, reg32); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 10c8a2b..2054d5d 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -212,7 +212,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg); if (is_mobile && config->sata_traffic_monitor) { - const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct device *lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); @@ -228,7 +228,7 @@ static void sata_init(struct device *const dev) sata_program_indexed(dev, is_mobile); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ const config_t *const config = dev->chip_info; @@ -255,7 +255,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 99920f5..0a5b20f 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -430,7 +430,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -497,7 +497,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -527,7 +527,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -574,14 +574,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -616,7 +616,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 5f3c4d3..cee66c5 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -212,7 +212,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -237,7 +237,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 43a99c8..0812fe5 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -305,7 +305,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x300, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -326,7 +326,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..a48401f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device * dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device * dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device * dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device * dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..ebf2a01 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device * dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device * dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device * dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 3f8c28f..1f942aa 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -171,7 +171,7 @@ for (i=0;i<10;i++){ } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c index a0aec65..8c500b9 100644 --- a/src/southbridge/via/vt8231/early_serial.c +++ b/src/southbridge/via/vt8231/early_serial.c @@ -33,7 +33,7 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) static void enable_vt8231_serial(void) { uint8_t c; - device_t dev; + pnp_devfn_t dev; post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c index 606c33e..0246d54 100644 --- a/src/southbridge/via/vt8237r/sata.c +++ b/src/southbridge/via/vt8237r/sata.c @@ -96,7 +96,7 @@ static void sata_ii_init(struct device *dev) } -static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0xd4, vendor); pci_write_config16(dev, 0xd6, device); diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 55742a7..9cdf943 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -48,10 +48,10 @@ static void vt82c686_sio_write(uint8_t index, uint8_t value) * @param dev TODO * @param iobase TODO */ -static void vt82c686_enable_serial(device_t dev, unsigned iobase) +static void vt82c686_enable_serial(pnp_devfn_t dev, unsigned iobase) { uint8_t reg; - device_t sbdev; + pnp_devfn_t sbdev; /* TODO: Use info from 'dev' and 'iobase'. */ /* TODO: Only enable one serial port (depending on config) or both? */

1 0

Patch set updated for coreboot: 1338a84 northbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7166 -gerrit commit 1338a84d7133d5388ca9976b675e40b63b2f849e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 22 22:03:49 2014 +1100 northbridge: Don't hide pointers behind typedefs Change-Id: Ib2c373695820e71a6e41e4f173d2615ee5838f28 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 10 +-- src/northbridge/amd/agesa/00730F01/northbridge.c | 70 +++++++++---------- src/northbridge/amd/agesa/family10/northbridge.c | 80 +++++++++++----------- src/northbridge/amd/agesa/family10/reset_test.h | 4 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 50 +++++++------- src/northbridge/amd/agesa/family12/northbridge.h | 2 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 54 +++++++-------- src/northbridge/amd/agesa/family14/northbridge.h | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 72 +++++++++---------- src/northbridge/amd/agesa/family15/northbridge.h | 2 +- src/northbridge/amd/agesa/family15tn/iommu.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 66 +++++++++--------- src/northbridge/amd/agesa/family16kb/northbridge.c | 70 +++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 73 ++++++++++---------- src/northbridge/amd/amdk8/northbridge.c | 64 ++++++++--------- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 12 ++-- src/northbridge/amd/gx2/northbridge.c | 12 ++-- src/northbridge/amd/lx/northbridge.c | 12 ++-- src/northbridge/dmp/vortex86ex/northbridge.c | 6 +- src/northbridge/intel/e7501/northbridge.c | 6 +- src/northbridge/intel/e7505/northbridge.c | 8 +-- src/northbridge/intel/e7520/northbridge.c | 16 ++--- src/northbridge/intel/e7525/northbridge.c | 16 ++--- src/northbridge/intel/fsp_rangeley/northbridge.c | 20 +++--- .../intel/fsp_sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/gm45/northbridge.c | 12 ++-- src/northbridge/intel/haswell/northbridge.c | 30 ++++---- src/northbridge/intel/i3100/northbridge.c | 18 ++--- src/northbridge/intel/i440bx/northbridge.c | 8 +-- src/northbridge/intel/i440lx/northbridge.c | 8 +-- src/northbridge/intel/i5000/northbridge.c | 14 ++-- src/northbridge/intel/i82810/northbridge.c | 8 +-- src/northbridge/intel/i82830/northbridge.c | 8 +-- src/northbridge/intel/i855/northbridge.c | 8 +-- src/northbridge/intel/i945/northbridge.c | 14 ++-- src/northbridge/intel/nehalem/northbridge.c | 14 ++-- src/northbridge/intel/sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/sch/northbridge.c | 14 ++-- src/northbridge/rdc/r8610/northbridge.c | 6 +- src/northbridge/via/cn400/northbridge.c | 16 ++--- src/northbridge/via/cn700/northbridge.c | 10 +-- src/northbridge/via/cx700/northbridge.c | 8 +-- src/northbridge/via/vt8601/northbridge.c | 8 +-- src/northbridge/via/vt8623/northbridge.c | 14 ++-- src/northbridge/via/vx800/northbridge.c | 8 +-- src/northbridge/via/vx900/northbridge.c | 14 ++-- src/northbridge/via/vx900/sata.c | 16 ++--- 50 files changed, 523 insertions(+), 522 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 2714052..b1967de 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -46,7 +46,7 @@ static void qemu_reserve_ports(struct device *dev, unsigned int idx, IORESOURCE_ASSIGNED; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -213,7 +213,7 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * return len; } -static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int qemu_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = qemu_get_smbios_data16(*handle, current); @@ -234,15 +234,15 @@ static struct device_operations pci_domain_ops = { #endif }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +static unsigned int cpu_bus_scan(struct device * bus, unsigned int max) { int max_cpus = fw_cfg_max_cpus(); - device_t cpu; + struct device * cpu; int i; if (max_cpus < 0) diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c index 03433af..06fe3f6 100644 --- a/src/northbridge/amd/agesa/00730F01/northbridge.c +++ b/src/northbridge/amd/agesa/00730F01/northbridge.c @@ -58,15 +58,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -287,7 +287,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -329,7 +329,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -342,7 +342,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -402,7 +402,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -449,11 +449,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -499,7 +499,7 @@ struct chip_operations northbridge_amd_agesa_00730F01_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -512,7 +512,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -559,7 +559,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -663,7 +663,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -840,13 +840,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -882,12 +882,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -983,7 +983,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1068,7 +1068,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1076,12 +1076,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1092,7 +1092,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b1f0890..bc4a25d 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -52,10 +52,10 @@ typedef struct dram_base_mask { struct amdfam10_sysconf_t sysconf; -static device_t __f0_dev[NODE_NUMS]; -static device_t __f1_dev[NODE_NUMS]; -static device_t __f2_dev[NODE_NUMS]; -static device_t __f4_dev[NODE_NUMS]; +static struct device * __f0_dev[NODE_NUMS]; +static struct device * __f1_dev[NODE_NUMS]; +static struct device * __f2_dev[NODE_NUMS]; +static struct device * __f4_dev[NODE_NUMS]; static unsigned fx_devs = 0; #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 @@ -64,7 +64,7 @@ static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; @@ -96,7 +96,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -149,7 +149,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, #endif #if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, +static u32 check_segn(struct device * dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -249,7 +249,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, sysconf.mmio_addr_num = index+1; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -318,7 +318,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first @@ -357,7 +357,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi #endif } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -407,7 +407,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -415,7 +415,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -442,7 +442,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -450,7 +450,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -470,7 +470,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -505,7 +505,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -541,7 +541,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -600,7 +600,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -612,7 +612,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -667,7 +667,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -676,7 +676,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -696,7 +696,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -723,12 +723,12 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0xff; nodeid = amdfam10_nodeid(dev); @@ -770,7 +770,7 @@ struct chip_operations northbridge_amd_agesa_family10_ops = { }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg; @@ -783,7 +783,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -829,7 +829,7 @@ static void amdfam10_domain_read_resources(device_t dev) #endif } -static void amdfam10_domain_enable_resources(device_t dev) +static void amdfam10_domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); @@ -904,7 +904,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1071,7 +1071,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1102,7 +1102,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1132,7 +1132,7 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1150,7 +1150,7 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1186,12 +1186,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1282,7 +1282,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1363,7 +1363,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1371,12 +1371,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1387,7 +1387,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 8c8d9a0..a38cde8 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -33,7 +33,7 @@ static inline u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -42,7 +42,7 @@ static inline u32 warm_reset_detect(u8 nodeid) static inline void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 00ff641..116a466 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 94de010..7d1b118 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,14 +41,14 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -89,7 +89,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -98,7 +98,7 @@ static void f1_write_config32(unsigned reg, u32 value) } -static u32 amdfam12_nodeid(device_t dev) +static u32 amdfam12_nodeid(struct device * dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -108,7 +108,7 @@ static u32 amdfam12_nodeid(device_t dev) #include "amdfam12_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -137,7 +137,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -158,7 +158,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 result, reg; @@ -182,7 +182,7 @@ static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -218,7 +218,7 @@ static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam12_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -343,7 +343,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -412,10 +412,10 @@ static void set_resource(device_t dev, struct resource *resource, #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -447,7 +447,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -503,7 +503,7 @@ static void setup_uma_memory(void) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -518,7 +518,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -581,7 +581,7 @@ static void domain_read_resources(device_t dev) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -765,7 +765,7 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -783,7 +783,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -797,7 +797,7 @@ static void cpu_bus_read_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -809,7 +809,7 @@ static void cpu_bus_set_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h index 4edb525..c3fc171 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.h +++ b/src/northbridge/amd/agesa/family12/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */ diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index c255213..b72b21b 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 57502e9..de1465b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -44,13 +44,13 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs = 0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -88,7 +88,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -96,14 +96,14 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam14_nodeid(device_t dev) +static u32 amdfam14_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #include "amdfam14_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -119,7 +119,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -127,7 +127,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -146,7 +146,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, +static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -173,7 +173,7 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, return resource; } -static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, +static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -208,7 +208,7 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, return resource; } -static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam14_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -409,10 +409,10 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) } #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -444,7 +444,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -477,7 +477,7 @@ static void nb_set_resources(device_t dev) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -492,7 +492,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -566,7 +566,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -757,7 +757,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { #if CONFIG_AMD_SB_CIMX if (!acpi_is_wakeup_s3()) { @@ -779,18 +779,18 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus = dev->link_list; - device_t cpu; + struct device * cpu; int apic_id, cores_found; /* There is only one node for fam14, but there may be multiple cores. */ @@ -809,7 +809,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h index 474e74c..6046137 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.h +++ b/src/northbridge/amd/agesa/family14/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */ diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index ce9785e..c7a141f 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -57,16 +57,16 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -288,7 +288,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -412,7 +412,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -443,7 +443,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -476,11 +476,11 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { @@ -526,7 +526,7 @@ struct chip_operations northbridge_amd_agesa_family15_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -588,7 +588,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); @@ -681,7 +681,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -860,13 +860,13 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -902,12 +902,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -987,7 +987,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1079,7 +1079,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1087,16 +1087,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } @@ -1136,7 +1136,7 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { }; /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); return max; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h index 99fdcae..3a90964 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.h +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -22,6 +22,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max); +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max); #endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 3765f20..5b3529b 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <lib.h> -static void iommu_read_resources(device_t dev) +static void iommu_read_resources(struct device * dev) { struct resource *res; @@ -39,7 +39,7 @@ static void iommu_read_resources(device_t dev) res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(device_t dev) +static void iommu_set_resources(struct device * dev) { struct resource *res; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d77897d..5f0cafc 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -354,7 +354,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -405,7 +405,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -414,7 +414,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -434,7 +434,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -494,7 +494,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -507,7 +507,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -554,7 +554,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -647,7 +647,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -824,13 +824,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -866,12 +866,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -951,7 +951,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1041,7 +1041,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1049,16 +1049,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d47a00d..cc79da3 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -341,7 +341,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -392,7 +392,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -401,7 +401,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -421,7 +421,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -448,11 +448,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -498,7 +498,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -511,7 +511,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -558,7 +558,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -653,7 +653,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -830,13 +830,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -872,12 +872,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -957,7 +957,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1047,7 +1047,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1055,12 +1055,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1071,7 +1071,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 76ffc5d..8b87abc 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -53,13 +53,13 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if((CONFIG_CDB + nodeid) < 32) { @@ -102,7 +102,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -139,7 +139,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -152,7 +152,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l u32 max_bus; u32 min_bus; u32 is_sublink1 = (link_num>3); - device_t devx; + struct device * devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -284,7 +284,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l return max; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -327,7 +327,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -335,7 +335,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -355,7 +355,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -389,7 +389,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -425,7 +425,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -484,7 +484,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -496,7 +496,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -551,7 +551,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -580,7 +580,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -629,7 +629,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { .enable_dev = 0, }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg; @@ -642,7 +642,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -767,7 +767,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; struct dram_base_mask_t d; u32 sel_m; u32 sel_hi_en; @@ -871,7 +871,7 @@ static void setup_uma_memory(void) #endif } -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1087,7 +1087,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1118,7 +1118,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1146,7 +1146,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1188,7 +1188,7 @@ static void sysconf_init(device_t dev) // first node #endif } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1224,12 +1224,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1324,7 +1324,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1394,7 +1394,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } #endif - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1402,7 +1402,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX @@ -1411,11 +1411,12 @@ static void cpu_bus_init(device_t dev) #endif } -static void cpu_bus_read_resources(device_t dev) + +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a91a499..816d9e4 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -40,8 +40,8 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 -static device_t __f0_dev[MAX_FX_DEVS]; -static device_t __f1_dev[MAX_FX_DEVS]; +static struct device * __f0_dev[MAX_FX_DEVS]; +static struct device * __f1_dev[MAX_FX_DEVS]; static unsigned fx_devs=0; static void get_fx_devs(void) @@ -71,7 +71,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -79,12 +79,12 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdk8_nodeid(device_t dev) +static u32 amdk8_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link return max; } -static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static unsigned amdk8_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -271,7 +271,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -279,7 +279,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -299,7 +299,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, +static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned link, unsigned min, unsigned max) { unsigned resource; @@ -327,17 +327,17 @@ static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, return resource; } -static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8); } -static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8); } -static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -376,9 +376,9 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) } } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid); +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid); -static void amdk8_read_resources(device_t dev) +static void amdk8_read_resources(struct device * dev) { unsigned nodeid; struct bus *link; @@ -391,7 +391,7 @@ static void amdk8_read_resources(device_t dev) amdk8_create_vga_resource(dev, nodeid); } -static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) { struct bus *link; resource_t rbase, rend; @@ -488,7 +488,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned report_resource_stored(dev, resource, buf); } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) { struct resource *resource; struct bus *link; @@ -498,7 +498,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -529,7 +529,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) IORESOURCE_ASSIGNED; } -static void amdk8_set_resources(device_t dev) +static void amdk8_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -638,7 +638,7 @@ struct chip_operations northbridge_amd_amdk8_ops = { .enable_dev = 0, }; -static void amdk8_domain_read_resources(device_t dev) +static void amdk8_domain_read_resources(struct device * dev) { unsigned reg; @@ -651,7 +651,7 @@ static void amdk8_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; nodeid = limit & 7; reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; @@ -765,7 +765,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; u32 base, limit; u32 hoist; u32 hole_sizek; @@ -810,7 +810,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; u32 carry_over; - device_t dev; + struct device * dev; u32 base, limit; u32 basek; u32 hoist; @@ -904,7 +904,7 @@ static void setup_uma_memory(void) #endif } -static void amdk8_domain_set_resources(device_t dev) +static void amdk8_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1121,7 +1121,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1136,7 +1136,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1164,7 +1164,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1200,10 +1200,10 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; int bsp_apicid; int i,j; unsigned nb_cfg_54; @@ -1258,7 +1258,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < sysconf.nodes; i++) { - device_t cpu_dev; + struct device * cpu_dev; /* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1267,7 +1267,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * ensure all of the cpu's pci devices are found. */ int local_j; - device_t dev_f0; + struct device * dev_f0; for(local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); @@ -1334,7 +1334,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1342,7 +1342,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { #if CONFIG_WAIT_BEFORE_CPUS_INIT cpus_ready_for_init(); diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index fa23344..09cdce5 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -66,7 +66,7 @@ void nb_Late_Post_Init(void) LibSystemApiCall(AmdLatePostInit, &gConfig); } -static void rd890_enable(device_t dev) +static void rd890_enable(struct device * dev) { u32 address = 0; u32 devfn; diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index bcb6e56..d960406 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -14,7 +14,7 @@ /* */ -static void optimize_xbus(device_t dev) +static void optimize_xbus(struct device * dev) { /* Optimise X-Bus performance */ pci_write_config8(dev, 0x40, 0x1e); @@ -31,13 +31,13 @@ static void optimize_xbus(device_t dev) * this region? **/ -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { write32(GX_BASE+BC_XMAP_2, 0x77777777); write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); @@ -65,9 +65,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -126,7 +126,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..e7a37f1 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -213,12 +213,12 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); @@ -273,11 +273,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -296,7 +296,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -318,7 +318,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..9a75fc4 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -291,11 +291,11 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { //msr_t msr; @@ -372,11 +372,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -395,7 +395,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -422,7 +422,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index fcebed8..e193168 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -30,7 +30,7 @@ #define SPI_BASE 0xfc00 -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. @@ -75,9 +75,9 @@ static void set_cmos_memory_size(unsigned long sizek) * don't touch it. */ } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 64bf840..407df57 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -20,9 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -110,7 +110,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023..0f6a1ce 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -16,9 +16,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -97,7 +97,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -117,7 +117,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 6e0379e..42c2f84 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7520_domain_scan_bus(device_t dev, u32 max) +static u32 e7520_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -122,7 +122,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -134,7 +134,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -145,7 +145,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -170,7 +170,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x3590, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -184,7 +184,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 68fdc74..b6cb7fc 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -106,7 +106,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7525_domain_scan_bus(device_t dev, u32 max) +static u32 e7525_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -121,7 +121,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -133,7 +133,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -144,7 +144,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -169,7 +169,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x359e, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -183,7 +183,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 07ce21f..04cb5d9 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -112,7 +112,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device * dev) { /* * Notify FSP for PostPciEnumeration. @@ -123,7 +123,7 @@ static void finalize_dev (device_t dev) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -168,7 +168,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -177,7 +177,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * Assign memory resources for PCI devices @@ -187,13 +187,13 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -208,7 +208,7 @@ static void northbridge_init(struct device *dev) { } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { } @@ -258,7 +258,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -271,7 +271,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index da27b25..e6f1fec 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -68,7 +68,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -121,7 +121,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -261,7 +261,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -283,7 +283,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -297,7 +297,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -322,7 +322,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -375,7 +375,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -388,7 +388,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 716ee62..b7737aa 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -46,7 +46,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; @@ -73,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) return 0; } -static void mch_domain_read_resources(device_t dev) +static void mch_domain_read_resources(struct device * dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0, usable_tomk; @@ -170,7 +170,7 @@ static void mch_domain_read_resources(device_t dev) } } -static void mch_domain_set_resources(device_t dev) +static void mch_domain_set_resources(struct device * dev) { struct resource *resource; int i; @@ -185,7 +185,7 @@ static void mch_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mch_domain_init(device_t dev) +static void mch_domain_init(struct device * dev) { u32 reg32; @@ -207,7 +207,7 @@ static struct device_operations pci_domain_ops = { }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -221,7 +221,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..1cd6ac0 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,7 +39,7 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -69,7 +69,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +106,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -126,7 +126,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device * dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -146,7 +146,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device * dev) { int i; @@ -203,7 +203,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device * dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -291,7 +291,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -383,7 +383,7 @@ static void mc_add_dram_resources(device_t dev) #endif } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -395,7 +395,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -433,7 +433,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; @@ -480,7 +480,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { bsp_init_and_start_aps(dev->link_list); } @@ -493,7 +493,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 2cf5ae1..8f30486 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -39,9 +39,9 @@ static u32 max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 i3100_domain_scan_bus(device_t dev, u32 max) +static u32 i3100_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -159,7 +159,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -170,7 +170,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -180,7 +180,7 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = PCI_DEVICE_ID_INTEL_3100_MC, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -233,7 +233,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 12ff37b..866a778 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -12,7 +12,7 @@ #include "northbridge.h" #include "i440bx.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -32,9 +32,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -static void i440bx_domain_set_resources(device_t dev) +static void i440bx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -81,7 +81,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 60e62c1..4070c7a 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -38,7 +38,7 @@ * Maciej */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -58,9 +58,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -static void i440lx_domain_set_resources(device_t dev) +static void i440lx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index a9b3560..30517bb 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <cbmem.h> -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -40,15 +40,15 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0; - device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); - device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + struct device * dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + struct device * dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); pci_dev_read_resources(dev); @@ -139,7 +139,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = nb_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -151,7 +151,7 @@ static struct device_operations cpu_bus_ops = { .init = cpu_bus_init, .scan_bus = 0, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -165,7 +165,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index ce0dc20..5925e63 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -32,7 +32,7 @@ #include "northbridge.h" #include "i82810.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -69,9 +69,9 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -136,7 +136,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4898aaf..a317613 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -30,7 +30,7 @@ #include <string.h> #include "i82830.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -50,9 +50,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -103,7 +103,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index fce7d57..ff3ca5b 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -32,7 +32,7 @@ #include <cpu/x86/cache.h> #include <cpu/cpu.h> -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -52,9 +52,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); @@ -119,7 +119,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 91c5c82..494253f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -81,7 +81,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint32_t pci_tolm; uint8_t tolud, reg8; @@ -185,7 +185,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -207,7 +207,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -221,7 +221,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,7 +274,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x27a0, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -287,7 +287,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..ea14c12 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -96,7 +96,7 @@ static void add_fixed_resources(struct device *dev, int index) #endif } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { uint32_t tseg_base; uint64_t TOUUD; @@ -165,13 +165,13 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* And call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -283,7 +283,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -324,7 +324,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -337,7 +337,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..ab28093 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -66,7 +66,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -132,7 +132,7 @@ static void add_fixed_resources(struct device *dev, int index) bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -266,7 +266,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -288,7 +288,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -302,7 +302,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -412,7 +412,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -471,7 +471,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -484,7 +484,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..e2cc496 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { u32 pci_tolm; u8 reg8; @@ -200,7 +200,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -226,7 +226,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -239,7 +239,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -292,7 +292,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x8100, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -305,7 +305,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index d69c4f6..5ca0ab3 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -33,7 +33,7 @@ static unsigned long get_memory_size(void) { - device_t nb_dev; + struct device * nb_dev; u8 size; nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, @@ -42,7 +42,7 @@ static unsigned long get_memory_size(void) return (2 * 1024) << size; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; @@ -92,7 +92,7 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current) return len; } -static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int rdc_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = rdc_get_smbios_data16(*handle, current); diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index b797179..dc64991 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn400.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; int i, j; @@ -140,7 +140,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; -static void cn400_domain_read_resources(device_t dev) +static void cn400_domain_read_resources(struct device * dev) { struct resource *resource; @@ -162,7 +162,7 @@ static void cn400_domain_read_resources(device_t dev) } #ifdef UNUSED_CODE -static void ram_reservation(device_t dev, unsigned long index, +static void ram_reservation(struct device * dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +177,9 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif -static void cn400_domain_set_resources(device_t dev) +static void cn400_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +219,7 @@ static void cn400_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); } -static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device * dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__); @@ -236,7 +236,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 506bdd1..c1bd74c 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn700.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg; @@ -97,11 +97,11 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -156,7 +156,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index cc9dabd..bb8caf9 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -31,9 +31,9 @@ #include <cbmem.h> #include <arch/acpi.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; @@ -82,7 +82,7 @@ static void pci_domain_set_resources(device_t dev) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg; dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 @@ -112,7 +112,7 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = acpi_write_hpet, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 1887491..2565b1d 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -17,7 +17,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -44,12 +44,12 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -102,7 +102,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 546db4c..0b5030b 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -19,9 +19,9 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { - device_t fb_dev; + struct device * fb_dev; unsigned long fb; unsigned char c; @@ -58,7 +58,7 @@ static void northbridge_init(device_t dev) } } -static void nullfunc(device_t dev) +static void nullfunc(struct device * dev) { /* Nothing to do */ } @@ -76,7 +76,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8623, }; -static void agp_init(device_t dev) +static void agp_init(struct device * dev) { printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n"); @@ -103,10 +103,10 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); @@ -162,7 +162,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index fad0c2f..e0fb06f 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -37,7 +37,7 @@ /* !!FIXME!! I declared this to fix the build. */ u8 acpi_sleep_type = 0; -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { /* set VGA in uma_ram_setting.c, not in this function. @@ -71,13 +71,13 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; u8 reg; @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index f9c225d..7047a04 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -60,7 +60,7 @@ uint64_t get_uma_memory_base(void) return uma_memory_base; } -static u64 vx900_get_top_of_ram(device_t mcu) +static u64 vx900_get_top_of_ram(struct device * mcu) { u16 reg16; /* The last valid DRAM address is computed by the MCU @@ -97,7 +97,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) * * @return The new top of memory. */ -static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) +static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) { size_t i; u8 reg8, start8, end8, start, end; @@ -216,7 +216,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) return newtor; } -static void vx900_set_resources(device_t dev) +static void vx900_set_resources(struct device * dev) { u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk; @@ -228,7 +228,7 @@ static void vx900_set_resources(device_t dev) "========================================\n"); int idx = 10; - const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + struct device * mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); if (!mcu) { @@ -286,7 +286,7 @@ static void vx900_set_resources(device_t dev) assign_resources(dev->link_list); } -static void vx900_read_resources(device_t dev) +static void vx900_read_resources(struct device * dev) { /* Our fixed resources start at 0 */ int idx = 0; @@ -317,7 +317,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -330,7 +330,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 63295e5..4a7ae6d 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -74,7 +74,7 @@ static void vx900_print_sata_errors(u32 flags) print_debug("\tUNRECOGNIZED FIS type\n"); } -static void vx900_dbg_sata_errors(device_t dev) +static void vx900_dbg_sata_errors(struct device *dev) { /* Port 0 */ if (pci_read_config8(dev, 0xa0) & (1 << 0)) { @@ -103,7 +103,7 @@ static sata_phy_config reference_ephy = { 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static u32 sata_phy_read32(device_t dev, u8 index) +static u32 sata_phy_read32(struct device *dev, u8 index) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -115,7 +115,7 @@ static u32 sata_phy_read32(device_t dev, u8 index) return pci_read_config32(dev, 0x64); } -static void sata_phy_write32(device_t dev, u8 index, u32 val) +static void sata_phy_write32(struct device *dev, u8 index, u32 val) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -127,7 +127,7 @@ static void sata_phy_write32(device_t dev, u8 index, u32 val) pci_write_config32(dev, 0x64, val); } -static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -136,7 +136,7 @@ static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) } } -static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -181,7 +181,7 @@ static void vx900_sata_dump_phy_config(sata_phy_config cfg) * Our only option is to operate in IDE mode. We choose native IDE so that we * can freely assign an IRQ, and are not forced to use IRQ14 */ -static void vx900_native_ide_mode(device_t dev) +static void vx900_native_ide_mode(struct device *dev) { /* Disable subclass write protect */ pci_mod_config8(dev, 0x45, 1 << 7, 0); @@ -193,7 +193,7 @@ static void vx900_native_ide_mode(device_t dev) pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); } -static void vx900_sata_init(device_t dev) +static void vx900_sata_init(struct device *dev) { /* Enable SATA primary channel IO access */ pci_mod_config8(dev, 0x40, 0, 1 << 1); @@ -261,7 +261,7 @@ static void vx900_sata_init(device_t dev) vx900_dbg_sata_errors(dev); } -static void vx900_sata_read_resources(device_t dev) +static void vx900_sata_read_resources(struct device *dev) { pci_dev_read_resources(dev); }

1 0

Patch set updated for coreboot: 9d2b76b macbook21: Move SB-specific early init to separate file
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7085 -gerrit commit 9d2b76ba2941e0be3a507810083ce7d8180a4b61 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 23:07:24 2014 +0200 macbook21: Move SB-specific early init to separate file Change-Id: I5995dd0c43a541c352af279a373bc783f51176a9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/Makefile.inc | 1 + src/mainboard/apple/macbook21/early_mainboard.h | 3 + src/mainboard/apple/macbook21/early_southbridge.c | 253 ++++++++++++++++++++++ src/mainboard/apple/macbook21/romstage.c | 231 +------------------- 4 files changed, 258 insertions(+), 230 deletions(-) diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc new file mode 100644 index 0000000..7b421c4 --- /dev/null +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -0,0 +1 @@ +romstage-y += early_southbridge.c \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/early_mainboard.h b/src/mainboard/apple/macbook21/early_mainboard.h new file mode 100644 index 0000000..6c9dbe9 --- /dev/null +++ b/src/mainboard/apple/macbook21/early_mainboard.h @@ -0,0 +1,3 @@ +void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); diff --git a/src/mainboard/apple/macbook21/early_southbridge.c b/src/mainboard/apple/macbook21/early_southbridge.c new file mode 100644 index 0000000..7e7b5a9 --- /dev/null +++ b/src/mainboard/apple/macbook21/early_southbridge.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "early_mainboard.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + + /* X60 GPIO: + * 1: HDD_PRESENCE# + * 6: Unknown (Pulled high by R215 to VCC3B) + * 7: BDC_PRESENCE# + * 8: H8_WAKE# + * 9: RTC_BAT_IN# + * 10: Unknown (Pulled high by R700 to VCC3M) + * 12: H8SCI# + * 13: SLICE_ON_3M# + * 14: Unknown (Pulled high by R321 to VCC3) + * 15: Unknown (Pulled high by R258 to VCC3) + * 19: Unknown (Pulled low by R594) + * 21: Unknown (Pulled high by R145 to VCC3) + * 22: FWH_WP# + * 25: MDC_KILL# + * 33: HDD_PRESENCE_2# + * 35: CLKREQ_SATA# + * 36: PLANARID0 + * 37: PLANARID1 + * 38: PLANARID2 + * 39: PLANARID3 + * 48: FWH_TBL# + */ + + outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // I/O Decode Ranges + // X60: 0x0210 == 00000010 00010000 + // Macbook21: 0x0010 == 00000000 00010000 + // Bit 9:8 LPT Decode Range. This field determines which range to + // decode for the LPT Port. + // 00 = 378h 37Fh and 778h 77Fh + // 10 = 3BCh 3BEh and 7BCh 7BEh + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + + // LPC_EN--LPC I/F Enables Register + // X60: 0x1f0d == 00011111 00001101 + // Macbook21: 0x3807 == 00111000 00000111 + // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh + // to the LPC interface. This range is used for + // Super I/O devices. + // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 62h and 66h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 60h and 64h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 208h to 20Fh + // to the LPC interface. This range is used for a gameport. + // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 200h to 207h + // to the LPC interface. This range is used for a gameport. + // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable + // 0 = Disable. + // 1 = Enables the decoding of the FDD range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 12). + // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable + // 0 = Disable. + // 1 = Enables the decoding of the LPT range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 9:8). + // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMB range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 6:4). + // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMA range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 3:2). + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); + + /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ + // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 + // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 + // Bit 31:24 Reserved. + // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any + // bit position indicates that any value in the corresponding + // address bit in a received cycle will be treated as a + // match. The corresponding bit in the Address field, below, + // is ignored. The mask is only provided for the lower 6 bits + // of the DWord address, allowing for decoding blocks up to + // 256 bytes in size. + // Bit 17:16 Reserved. + // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This + // address is aligned on a 128-byte boundary, and must have + // address lines 31:16 as 0. NOTE: The Intel ICH7 does not + // provide decode down to the word or byte level. + // Bit 1 Reserved. + // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. + // 0 = Disable. + // 1 = Enable the GEN1 I/O range to be forwarded to the LPC + // I/F + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); + + /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ + // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 + // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); + + /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ + // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 + // Macbook21: 0x0000 0x0000 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); + + /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ + // X60: 0x0000 0x0000 + // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); +} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable unused devices */ + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; + RCBA32(0x3418) |= (1 << 0); // Required. + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + // RCBA32(0x1e84) = 0x00020001; + // RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} + +void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index d82569b..50a4dd6 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -26,241 +26,13 @@ #include <string.h> #include <arch/io.h> #include <device/pci_def.h> -#include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> -#include <cbmem.h> #include <timestamp.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" - -void setup_ich7_gpios(void) -{ - printk(BIOS_DEBUG, " GPIOS..."); - - /* X60 GPIO: - * 1: HDD_PRESENCE# - * 6: Unknown (Pulled high by R215 to VCC3B) - * 7: BDC_PRESENCE# - * 8: H8_WAKE# - * 9: RTC_BAT_IN# - * 10: Unknown (Pulled high by R700 to VCC3M) - * 12: H8SCI# - * 13: SLICE_ON_3M# - * 14: Unknown (Pulled high by R321 to VCC3) - * 15: Unknown (Pulled high by R258 to VCC3) - * 19: Unknown (Pulled low by R594) - * 21: Unknown (Pulled high by R145 to VCC3) - * 22: FWH_WP# - * 25: MDC_KILL# - * 33: HDD_PRESENCE_2# - * 35: CLKREQ_SATA# - * 36: PLANARID0 - * 37: PLANARID1 - * 38: PLANARID2 - * 39: PLANARID3 - * 48: FWH_TBL# - */ - - outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ -} - -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - - // I/O Decode Ranges - // X60: 0x0210 == 00000010 00010000 - // Macbook21: 0x0010 == 00000000 00010000 - // Bit 9:8 LPT Decode Range. This field determines which range to - // decode for the LPT Port. - // 00 = 378h 37Fh and 778h 77Fh - // 10 = 3BCh 3BEh and 7BCh 7BEh - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - - // LPC_EN--LPC I/F Enables Register - // X60: 0x1f0d == 00011111 00001101 - // Macbook21: 0x3807 == 00111000 00000111 - // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh - // to the LPC interface. This range is used for - // Super I/O devices. - // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 62h and 66h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 60h and 64h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 208h to 20Fh - // to the LPC interface. This range is used for a gameport. - // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 200h to 207h - // to the LPC interface. This range is used for a gameport. - // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable - // 0 = Disable. - // 1 = Enables the decoding of the FDD range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 12). - // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable - // 0 = Disable. - // 1 = Enables the decoding of the LPT range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 9:8). - // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMB range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 6:4). - // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMA range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 3:2). - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); - - /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ - // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 - // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 - // Bit 31:24 Reserved. - // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any - // bit position indicates that any value in the corresponding - // address bit in a received cycle will be treated as a - // match. The corresponding bit in the Address field, below, - // is ignored. The mask is only provided for the lower 6 bits - // of the DWord address, allowing for decoding blocks up to - // 256 bytes in size. - // Bit 17:16 Reserved. - // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This - // address is aligned on a 128-byte boundary, and must have - // address lines 31:16 as 0. NOTE: The Intel ICH7 does not - // provide decode down to the word or byte level. - // Bit 1 Reserved. - // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. - // 0 = Disable. - // 1 = Enable the GEN1 I/O range to be forwarded to the LPC - // I/F - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); - - /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ - // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 - // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); - - /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ - // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 - // Macbook21: 0x0000 0x0000 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); - - /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ - // X60: 0x0000 0x0000 - // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); -} - -static void rcba_config(void) -{ - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* V1CAP Virtual Channel 1 Resource Capability */ - RCBA32(0x001c) = 0x03128010; - - /* Disable unused devices */ - RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; - RCBA32(0x3418) |= (1 << 0); // Required. - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - // RCBA32(0x1e84) = 0x00020001; - // RCBA32(0x1e80) = 0x0000fe01; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; -} - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA32(0x3418) |= (1 << 0); - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} +#include "early_mainboard.h" void main(unsigned long bist) { @@ -327,5 +99,4 @@ void main(unsigned long bist) i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); - }

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Patch set updated for coreboot: e2194c0 sandy/ivy/nehalem: Remerge interrupt handling
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7130 -gerrit commit e2194c0a2829a415e17f1c7a75281a97f4dcab06 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 19 10:13:14 2014 +0200 sandy/ivy/nehalem: Remerge interrupt handling On those chipsets the pins are just a legacy concept. Real interrupts are messages on corresponding busses or some internal logic of chipset. Hence interrupt routing isn't anymore board-specific (dependent on layout) but depends only on configuration. Rather than attempting to sync real config, ACPI and legacy descriptors, just use the same interrupt routing per chipset covering all possible devices. Interrupt balancing may suffer from such merge but: a) Doesn't seem to be the case of this map on current systems b) Almost all OS use MSI nowadays bypassing this stuff completely c) If we want a good balancing we need to take into account that e.g. wlan card may be placed in a different slot and so would require complicated balancing on runtime. It's difficult to maintain with almost no benefit. Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/acpi_tables.c | 18 ----- src/mainboard/google/butterfly/devicetree.cb | 9 --- src/mainboard/google/butterfly/romstage.c | 42 +---------- src/mainboard/google/link/acpi_tables.c | 18 ----- src/mainboard/google/link/devicetree.cb | 9 --- src/mainboard/google/link/romstage.c | 39 +--------- src/mainboard/google/parrot/acpi_tables.c | 18 ----- src/mainboard/google/parrot/devicetree.cb | 9 --- src/mainboard/google/parrot/romstage.c | 43 +---------- src/mainboard/google/stout/acpi_tables.c | 18 ----- src/mainboard/google/stout/devicetree.cb | 9 --- src/mainboard/google/stout/romstage.c | 43 +---------- src/mainboard/intel/cougar_canyon2/devicetree.cb | 9 --- src/mainboard/intel/emeraldlake2/acpi_tables.c | 18 ----- src/mainboard/intel/emeraldlake2/devicetree.cb | 9 --- src/mainboard/intel/emeraldlake2/romstage.c | 38 +--------- src/mainboard/kontron/ktqm77/acpi_tables.c | 18 ----- src/mainboard/kontron/ktqm77/devicetree.cb | 9 --- src/mainboard/kontron/ktqm77/romstage.c | 58 +-------------- .../lenovo/t520/acpi/sandybridge_pci_irqs.asl | 64 ---------------- src/mainboard/lenovo/t520/acpi_tables.c | 18 ----- src/mainboard/lenovo/t520/devicetree.cb | 9 --- src/mainboard/lenovo/t520/romstage.c | 42 ----------- .../lenovo/t530/acpi/sandybridge_pci_irqs.asl | 64 ---------------- src/mainboard/lenovo/t530/acpi_tables.c | 18 ----- src/mainboard/lenovo/t530/devicetree.cb | 9 --- src/mainboard/lenovo/t530/romstage.c | 42 ----------- .../lenovo/x201/acpi/nehalem_pci_irqs.asl | 86 ---------------------- src/mainboard/lenovo/x201/acpi_tables.c | 36 --------- src/mainboard/lenovo/x201/devicetree.cb | 9 --- src/mainboard/lenovo/x201/romstage.c | 40 +--------- src/mainboard/lenovo/x220/acpi_tables.c | 18 ----- src/mainboard/lenovo/x220/devicetree.cb | 9 --- src/mainboard/lenovo/x220/romstage.c | 42 ----------- .../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 64 ---------------- src/mainboard/lenovo/x230/acpi_tables.c | 18 ----- src/mainboard/lenovo/x230/devicetree.cb | 9 --- src/mainboard/lenovo/x230/romstage.c | 42 ----------- .../packardbell/ms2290/acpi/nehalem_pci_irqs.asl | 86 ---------------------- src/mainboard/packardbell/ms2290/acpi_tables.c | 36 --------- src/mainboard/packardbell/ms2290/devicetree.cb | 9 --- src/mainboard/packardbell/ms2290/romstage.c | 41 ++--------- src/mainboard/samsung/lumpy/acpi_tables.c | 18 ----- src/mainboard/samsung/lumpy/devicetree.cb | 9 --- src/mainboard/samsung/lumpy/romstage.c | 36 +-------- src/mainboard/samsung/stumpy/acpi_tables.c | 18 ----- src/mainboard/samsung/stumpy/devicetree.cb | 9 --- src/mainboard/samsung/stumpy/romstage.c | 38 +--------- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 63 +++++++++++++++- .../intel/sandybridge/acpi/hostbridge.asl | 51 ++++++++++++- .../intel/sandybridge/romstage_native.c | 1 + src/southbridge/intel/bd82x6x/Makefile.inc | 3 + src/southbridge/intel/bd82x6x/chip.h | 13 ---- src/southbridge/intel/bd82x6x/early_rcba.c | 69 +++++++++++++++++ src/southbridge/intel/bd82x6x/lpc.c | 27 ++++--- src/southbridge/intel/bd82x6x/madt.c | 45 +++++++++++ src/southbridge/intel/bd82x6x/pch.h | 2 + src/southbridge/intel/ibexpeak/Makefile.inc | 2 + src/southbridge/intel/ibexpeak/early_rcba.c | 61 +++++++++++++++ src/southbridge/intel/ibexpeak/lpc.c | 27 ++++--- src/southbridge/intel/ibexpeak/madt.c | 68 +++++++++++++++++ src/southbridge/intel/ibexpeak/pch.h | 1 + 62 files changed, 405 insertions(+), 1401 deletions(-) diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index dcaf384..cabc052 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -75,24 +75,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index daafeff..ed0d8d1 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -39,15 +39,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 6b7613a..80c0742 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -62,47 +62,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index 14baad2..d1d4fcb 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -83,24 +83,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->lids = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 15aa432..5333dfc 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -42,15 +42,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 8236e20..f90d7e7 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -78,44 +78,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P3IP WLAN INTA -> PIRQB - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * TRACKPAD -> PIRQE (Edge Triggered) - * TOUCHSCREEN -> PIRQG (Edge Triggered) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index e4e1797..0041c98 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -74,24 +74,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->lids = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 2da7a53..a4baafd 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -41,15 +41,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x8b" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ce42b41..c25b419 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -62,48 +62,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQB - * D28IP_P3IP ETH0 INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQE - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * - * Trackpad DVT PIRQA (16) - * Trackpad DVT PIRQE (20) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 504ae64..23c47f9 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -80,24 +80,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->xhci = XHCI_MODE; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 97e2c09..4ac89f6 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -40,15 +40,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 728d74d..6290e03 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -68,48 +68,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D20IP_XHCI XHCI INTA -> PIRQD (MSI) - * D26IP_E2P EHCI #2 INTA -> PIRQF - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQD - * D28IP_P3IP Card Reader INTB -> PIRQE - * D28IP_P6IP LAN INTC -> PIRQB - * D29IP_E1P EHCI #1 INTA -> PIRQD - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); - DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index 42b1535..c386853 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -32,15 +32,6 @@ chip northbridge/intel/fsp_sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - register "sata_port_map" = "0x3f" register "c2_latency" = "1" diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 3d95586..f17e1f4 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -92,24 +92,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 75643f4..e5a8ea0 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -32,15 +32,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 220b1d7..d50093e 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -73,43 +73,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index 0d90403..d2d70e9 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -63,24 +63,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index fb18057..855fd5c 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -27,15 +27,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8b" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x8b" - register "pirqf_routing" = "0x8b" - register "pirqg_routing" = "0x8b" - register "pirqh_routing" = "0x8b" - # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 401314c..bfe7715 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -59,63 +59,7 @@ static void rcba_config(void) { u32 reg32; - /* - * D31IP_TTIP THRT INTC -> PIRQC - * D31IP_SIP2 SATA2 NOINT - * D31IP_SMIP SMBUS INTC -> PIRQC - * D31IP_SIP SATA INTB -> PIRQD (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQH - * D28IP_P8IP Slot? INTD -> PIRQD - * D28IP_P7IP PCIEx1 INTC -> PIRQC - * D28IP_P6IP 1394 INTB -> PIRQB (MSI) - * D28IP_P5IP GbEPHY INTA -> PIRQA - * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) - * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) - * D28IP_P2IP Slot? INTB -> PIRQB - * D28IP_P1IP Slot? INTA -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * D26IP_E2P EHCI2 INTA -> PIRQA - * D25IP_LIP ETH0 INTA -> PIRQE (MSI) - * D22IP_KTIP MEI NOINT - * D22IP_IDERIP MEI NOINT - * D22IP_MEI2IP MEI NOINT - * D22IP_MEI1IP MEI NOINT - * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) - * GFX INTA -> PIRQA (MSI) - * PEGx16 INTA -> PIRQA - * INTB -> PIRQB - * INTC -> PIRQC - * INTD -> PIRQD - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | - (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) | - (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (INTA << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); - DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); - DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); - DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index b4b81a2..0000000 --- a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P2IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P4IP EXC INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P5IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index d347e82..486e8d2 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 83be0c7..f7866a8 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -60,48 +60,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQB - * D28IP_P4IP EXC INTB -> PIRQF - * D28IP_P5IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) | - (INTC << D28IP_P5IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1ee51fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6c1c695..0000000 --- a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 397bb9f..c1cbca2 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 115f83b..0a49ed0 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -47,48 +47,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl deleted file mode 100644 index 3e9e1b3..0000000 --- a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing. - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0001ffff, 0, 0, 0x10 }, - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x0003ffff, 0, 0, 0x10 }, - Package() { 0x0016ffff, 0, 0, 0x10 }, // ME - Package() { 0x0016ffff, 1, 0, 0x11 }, // ME - Package() { 0x0016ffff, 2, 0, 0x12 }, // ME - Package() { 0x0016ffff, 3, 0, 0x13 }, // ME - Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet - Package() { 0x001affff, 0, 0, 0x14 }, // USB - Package() { 0x001affff, 1, 0, 0x15 }, // USB - Package() { 0x001affff, 2, 0, 0x16 }, // USB - Package() { 0x001affff, 3, 0, 0x17 }, // USB - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x11 }, // SATA - Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS - }) - } Else { - Return (Package() { - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME - Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME - Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB - Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus - }) - } -} diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index b8979f4..85eabc7 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -48,42 +48,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 1, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, - MP_IRQ_POLARITY_DEFAULT | - MP_IRQ_TRIGGER_DEFAULT); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_LEVEL); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 2, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 3, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { /* Not implemented */ diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 3005077..d467e92 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -93,15 +93,6 @@ chip northbridge/intel/nehalem subsystemid 0x17aa 0x215a end chip southbridge/intel/ibexpeak - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2c3dfd1..e58f5f6 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -75,41 +75,9 @@ static void pch_enable_lpc(void) static void rcba_config(void) { + southbridge_configure_default_intmap(); + static const u32 rcba_dump3[] = { - /* 30fc */ 0x00000000, - /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, - /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, - /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, - /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, - /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, - /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, - /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -179,8 +147,8 @@ static void rcba_config(void) }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x30fc); + RCBA32(4 * i + 0x3310) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3310); } } diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 3edbb87..c3b8ad9 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index ba48fac..d9c8aa0 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -57,48 +57,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1fe41fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6c1c695..0000000 --- a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 256586b..f2fed1f 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 2c39741..0bb137e 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -60,48 +60,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl deleted file mode 100644 index 1f782c8..0000000 --- a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing. - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0001ffff, 0, 0, 0x10 }, - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x0003ffff, 0, 0, 0x10 }, - Package() { 0x0016ffff, 0, 0, 0x10 }, // ME - Package() { 0x0016ffff, 1, 0, 0x11 }, // ME - Package() { 0x0016ffff, 2, 0, 0x12 }, // ME - Package() { 0x0016ffff, 3, 0, 0x13 }, // ME - Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet - Package() { 0x001affff, 0, 0, 0x14 }, // USB - Package() { 0x001affff, 1, 0, 0x15 }, // USB - Package() { 0x001affff, 2, 0, 0x16 }, // USB - Package() { 0x001affff, 3, 0, 0x17 }, // USB - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x10 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x11 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x12 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x13 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x11 }, // SATA - Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS - }) - } Else { - Return (Package() { - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME - Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME - Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB - Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus - }) - } -} diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index b8979f4..85eabc7 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -48,42 +48,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 1, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, - MP_IRQ_POLARITY_DEFAULT | - MP_IRQ_TRIGGER_DEFAULT); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_LEVEL); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 2, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 3, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { /* Not implemented */ diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 19f6c9c..2f4bce1 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -54,15 +54,6 @@ chip northbridge/intel/nehalem subsystemid 0x1025 0x0379 end chip southbridge/intel/ibexpeak - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index d33a9ba..ca96c87 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -70,41 +70,9 @@ static void pch_enable_lpc(void) static void rcba_config(void) { + southbridge_configure_default_intmap(); + static const u32 rcba_dump3[] = { - /* 30fc */ 0x00000000, - /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, - /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, - /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, - /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, - /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, - /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, - /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -173,9 +141,10 @@ static void rcba_config(void) /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, }; unsigned i; + for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x30fc); + RCBA32(4 * i + 0x3310) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3310); } } diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 24a0efd..6d8517c 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -93,24 +93,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index f1df610..9b0fc40 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -42,15 +42,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index cf2973d..6595f0d 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -75,41 +75,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQB - * D31IP_SIP SATA INTA -> PIRQA (MSI) - * D31IP_SMIP SMBUS INTC -> PIRQH - * D31IP_TTIP THRT INTB -> PIRQG - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * - * LIGHTSENSOR -> PIRQE (Edge Triggered) - * TRACKPAD -> PIRQF (Edge Triggered) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + southbridge_configure_default_intmap(); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 2d24822..dc2197a 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -93,24 +93,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 618d1e0..60b112b 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -33,15 +33,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 625903d..2c651ae 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -87,43 +87,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index e826bd6..ee5d1c9 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -344,5 +344,64 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/nehalem_pci_irqs.asl" +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x0003ffff, 0, 0, 0x10 }, + Package() { 0x0016ffff, 0, 0, 0x10 }, // ME + Package() { 0x0016ffff, 1, 0, 0x11 }, // ME + Package() { 0x0016ffff, 2, 0, 0x12 }, // ME + Package() { 0x0016ffff, 3, 0, 0x13 }, // ME + Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet + Package() { 0x001affff, 0, 0, 0x14 }, // USB + Package() { 0x001affff, 1, 0, 0x15 }, // USB + Package() { 0x001affff, 2, 0, 0x16 }, // USB + Package() { 0x001affff, 3, 0, 0x17 }, // USB + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x11 }, // SATA + Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME + Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME + Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME + Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB + Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus + }) + } +} diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 690c072..4025a0f 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -379,5 +379,52 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/sandybridge_pci_irqs.asl" +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // XHCI 0:14.0 (ivy only) + Package() { 0x0014ffff, 0, 0, 19 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // XHCI 0:14.0 (ivy only) + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 67c64d7..902d66d 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -91,6 +91,7 @@ void main(unsigned long bist) timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); + southbridge_configure_default_intmap(); rcba_config(); post_code(0x3d); diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 3d33edc..07c5c24 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -50,12 +50,15 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_smbus.c me_status.c gpio.c romstage-y += reset.c romstage-y += early_spi.c early_pch.c +romstage-y += early_rcba.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c +ramstage-y += madt.c + ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index e5da531..1256129 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -22,19 +22,6 @@ struct southbridge_intel_bd82x6x_config { /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - - /** * GPI Routing configuration * * Only the lower two bits have a meaning: diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c new file mode 100644 index 0000000..114b174 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "pch.h" +#include "northbridge/intel/sandybridge/sandybridge.h" + +void +southbridge_configure_default_intmap(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP SLOT1 INTA -> PIRQB + * D28IP_P2IP SLOT2 INTB -> PIRQF + * D28IP_P3IP SLOT3 INTC -> PIRQD + * D28IP_P5IP SLOT5 INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + + */ + + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); +} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c165ecc..20f20ae 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -106,18 +106,17 @@ static void pch_enable_serial_irqs(struct device *dev) static void pch_pirq_init(device_t dev) { device_t irq_dev; - /* Get the chip configuration */ - config_t *config = dev->chip_info; + u8 pirq_routing[8] = { 0x8b, 0x8a, 0x8b, 0x8b, 0x80, 0x80, 0x80, 0x80 }; - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq_routing[0]); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing[1]); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing[2]); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing[3]); - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQE_ROUT, pirq_routing[4]); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing[5]); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing[6]); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing[7]); /* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. @@ -132,10 +131,10 @@ static void pch_pirq_init(device_t dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; + case 1: /* INTA# */ int_line = pirq_routing[0]; break; + case 2: /* INTB# */ int_line = pirq_routing[1]; break; + case 3: /* INTC# */ int_line = pirq_routing[2]; break; + case 4: /* INTD# */ int_line = pirq_routing[3]; break; } if (!int_line) diff --git a/src/southbridge/intel/bd82x6x/madt.c b/src/southbridge/intel/bd82x6x/madt.c new file mode 100644 index 0000000..45b652b --- /dev/null +++ b/src/southbridge/intel/bd82x6x/madt.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 9b84c67..8147559 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,6 +75,8 @@ void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); +void +southbridge_configure_default_intmap(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void); diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 24cbe45..c264993 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += ../common/spi.c +ramstage-y += madt.c smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c @@ -49,6 +50,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c romstage-y += ../bd82x6x/reset.c +romstage-y += early_rcba.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c diff --git a/src/southbridge/intel/ibexpeak/early_rcba.c b/src/southbridge/intel/ibexpeak/early_rcba.c new file mode 100644 index 0000000..5218ca7 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_rcba.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "pch.h" +#include "northbridge/intel/nehalem/nehalem.h" + +void +southbridge_configure_default_intmap(void) +{ + RCBA32(0x30fc) = 0; + (void)RCBA32(0x30fc); + + RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | + (INTA << D31IP_SMIP) | (INTB << D31IP_SIP) | (INTD << 16); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = 0x40043210 | (INTD << D29IP_E1P); + + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | + (INTA << D28IP_P5IP); + + RCBA32(D27IP) = (INTB << D27IP_ZIP); + RCBA32(D26IP) = (INTD << D26IP_E2P) | 0x30003210; + RCBA32(D25IP) = (INTA << D25IP_LIP); + RCBA32(0x311c) = 0x00000002; + RCBA32(0x3120) = 0x00000000; + RCBA32(D22IP) = (INTA << D22IP_MEI1IP) | (INTB << D22IP_MEI2IP) | (INTC << D22IP_IDERIP) | (INTB << D22IP_KTIP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQH, PIRQA, PIRQB, PIRQD); + DIR_ROUTE(D29IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D28IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQA, PIRQA); + DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQE, PIRQA, PIRQA, PIRQA); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0300; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); +} diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f0ebbc9..da609da 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -105,18 +105,17 @@ static void pch_enable_serial_irqs(struct device *dev) static void pch_pirq_init(device_t dev) { device_t irq_dev; - /* Get the chip configuration */ - config_t *config = dev->chip_info; + u8 pirq_routing[8] = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b }; - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq_routing[0]); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing[1]); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing[2]); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing[3]); - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQE_ROUT, pirq_routing[4]); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing[5]); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing[6]); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing[7]); /* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. @@ -131,10 +130,10 @@ static void pch_pirq_init(device_t dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; + case 1: /* INTA# */ int_line = pirq_routing[0]; break; + case 2: /* INTB# */ int_line = pirq_routing[1]; break; + case 3: /* INTC# */ int_line = pirq_routing[2]; break; + case 4: /* INTD# */ int_line = pirq_routing[3]; break; } if (!int_line) diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c new file mode 100644 index 0000000..69a7b4b --- /dev/null +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 1, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, + MP_IRQ_POLARITY_DEFAULT | + MP_IRQ_TRIGGER_DEFAULT); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_LEVEL); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 2, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 3, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + return current; +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index df125f0..bd94689 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -79,6 +79,7 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); +void southbridge_configure_default_intmap(void); #endif #endif

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Patch set updated for coreboot: 787acec autoport: Experimental stuff
by Vladimir Serbinenko 05 Nov '14

05 Nov '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7131 -gerrit commit 787acec01f823d7ed741ff001487bc6e1d02ea6e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 21:51:47 2014 +0200 autoport: Experimental stuff Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/azalia.go | 54 +++++ util/autoport/bd82x6x.go | 293 +++++++++++++++++++++++ util/autoport/hardcoded.go | 407 ++++++++++++++++++++++++++++++++ util/autoport/i82801gx.go | 265 +++++++++++++++++++++ util/autoport/i945.go | 81 +++++++ util/autoport/log_maker.go | 77 +++++++ util/autoport/log_reader.go | 264 +++++++++++++++++++++ util/autoport/main.go | 537 +++++++++++++++++++++++++++++++++++++++++++ util/autoport/rce823.go | 39 ++++ util/autoport/root.go | 29 +++ util/autoport/sandybridge.go | 112 +++++++++ 11 files changed, 2158 insertions(+) diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go new file mode 100644 index 0000000..97e3449 --- /dev/null +++ b/util/autoport/azalia.go @@ -0,0 +1,54 @@ +package main + +import ( + "fmt" +) + +type azalia struct { +} + +func (i azalia) Scan(ctx Context, addr PCIDevData) { + az := Create(ctx, "hda_verb.c") + defer az.Close() + + az.WriteString( + `#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +`) + + for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { + fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n", + codec.VendorID, codec.Name) + fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n", + codec.SubsystemID) + fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n", + len(codec.PinConfig)+1) + fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n") + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + codec.CodecNo, codec.SubsystemID) + + for nid, val := range codec.PinConfig { + fmt.Fprintf(az, "\n\t/* NID 0x%02x: Subsystem ID. */\n", nid) + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + codec.CodecNo, nid, val) + } + } + + az.WriteString( + `}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; +`) + + PutPCIDev(addr, "Audio controller") +} + +func init() { + /* I82801GX/I945 */ + RegisterPCI(0x8086, 0x27d8, azalia{}) + /* C216/ivybridge */ + RegisterPCI(0x8086, 0x1e20, azalia{}) +} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go new file mode 100644 index 0000000..247524c --- /dev/null +++ b/util/autoport/bd82x6x.go @@ -0,0 +1,293 @@ +package main + +import ( + "fmt" + "os" +) + +type bd82x6x struct { + variant string +} + +func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } +} + +func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMstageFile("gpio.c", "") + + gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h" +`) + + adresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := adresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`static const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true + /* FIMXE: move */ + KconfigBool["HAVE_SMI_HANDLER"] = true + KconfigInt["IRQ_SLOT_COUNT"] = 18 + /* FIXME: hardcoded */ + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + /* FIXME: hardcoded */ + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + /* FIXME: hardcoded */ + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + pcieHotplugMap := "{ " + + for port := 0; port < 7; port++ { + if b.IsPCIeHotplug(ctx, port) { + pcieHotplugMap += "1, " + } else { + pcieHotplugMap += "0, " + } + } + + if b.IsPCIeHotplug(ctx, 7) { + pcieHotplugMap += "1 }" + } else { + pcieHotplugMap += "0 }" + } + + cur := DevTreeNode{ + Chip: "southbridge/intel/bd82x6x", + Comment: "Intel Series 6 Cougar Point PCH", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "alt_gp_smi_en": "0x0000", + "gpi1_routing": "2", + "gpi8_routing": "2", + "sata_interface_speed_support": "0x3", + "gen1_dec": "0x7c1601", + "gen2_dec": "0x0c15e1", + "gen4_dec": "0x0c06a1", + "pcie_port_coalesce": "1", + "pcie_hotplug_map": pcieHotplugMap, + + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c2_latency": FormatHexLE16(FADT[96:98]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMstageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ +`) + /* FIXME: Make sure that all regions are properly reserved. */ + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI32Simple(sb, addr, 0x84) + RestorePCI32Simple(sb, addr, 0x88) + RestorePCI32Simple(sb, addr, 0x8c) + RestorePCI32Simple(sb, addr, 0x90) + + RestorePCI16Simple(sb, addr, 0x80) + + RestorePCI32Simple(sb, addr, 0xac) + + sb.WriteString(`} + +void rcba_config(void) +{ + /* Disable devices. */ +`) + RestoreRCBA32(sb, inteltool, 0x3414) + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString("\n}\n") + + sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") + + currentMap := map[uint32]int{ + 0x20000153: 0, + 0x20000f57: 1, + 0x2000055b: 2, + 0x20000f51: 3, + 0x2000094a: 4, + } + + for port := 0; port < 14; port++ { + var pinmask uint32 + OCPin := -1 + if port < 8 { + pinmask = inteltool.RCBA[0x35a0] + } else { + pinmask = inteltool.RCBA[0x35a4] + } + for pin := 0; pin < 4; pin++ { + if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 { + OCPin = pin + if port >= 8 { + OCPin += 4 + } + } + } + fmt.Fprintf(sb, "{ %d, %d, %d }\n", + (inteltool.RCBA[0x359c]>>port)&1, + currentMap[inteltool.RCBA[0x3500+4*port]], + OCPin) + } + sb.WriteString("};\n") + + /* FIXME: hardcoded. */ + sb.WriteString(`void mainboard_get_spd(spd_raw_data *spd) { + read_spd (&spd[0], 0x50); + read_spd (&spd[2], 0x51); +} +`) + +} + +func init() { + RegisterPCI(0x8086, 0x1e55, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e31, GenericPCI{}) + RegisterPCI(0x8086, 0x1e26, GenericPCI{}) + RegisterPCI(0x8086, 0x1e2d, GenericPCI{}) + RegisterPCI(0x8086, 0x1e3a, GenericPCI{}) + RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1e10, GenericPCI{}) + RegisterPCI(0x8086, 0x1e12, GenericPCI{}) + RegisterPCI(0x8086, 0x1e14, GenericPCI{}) + RegisterPCI(0x8086, 0x1e03, GenericPCI{}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/hardcoded.go b/util/autoport/hardcoded.go new file mode 100644 index 0000000..584ddd8 --- /dev/null +++ b/util/autoport/hardcoded.go @@ -0,0 +1,407 @@ +package main + +func Hardcoded(ctx Context) { + ai := Create(ctx, "acpi/ich7_pci_irqs.asl") + defer ai.Close() + + /* FIXME: hardcoded. */ + ai.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} +`) + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + /* FIXME: hardcoded. */ + ap.WriteString( + `Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Scope(\_SB) +{ + Method(_INI, 0) + { + \GOS() + } +} +`) + sh := Create(ctx, "smihandler.c") + defer sh.Close() + + /* FIXME: hardcoded. */ + sh.WriteString( + ` +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + case APM_CNT_ACPI_DISABLE: + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + default: + break; + } + return 0; +} +`) + mb := Create(ctx, "mainboard.c") + defer mb.Close() + + /* FIXME: hardcoded. */ + mb.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <drivers/intel/gma/int15.h> +#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} + +static void mainboard_init(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; +`) + + em := Create(ctx, "early_mainboard.h") + defer em.Close() + + /* FIXME: hardcoded. */ + em.WriteString( + `void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); +`) + + rs := Create(ctx, "romstage.c") + defer rs.Close() + + /* FIXME: hardcoded. */ + rs.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <cpu/x86/lapic.h> +#include <timestamp.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "early_mainboard.h" + +void main(unsigned long bist) +{ + int s3resume = 0; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + while (1) + asm("hlt"); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); + + timestamp_add_now(TS_END_ROMSTAGE); +} +`) + + at := Create(ctx, "acpi_tables.c") + defer at.Close() + + /* FIXME: hardcoded. */ + at.WriteString( + `#include <stdint.h> +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} +`) + + av := Create(ctx, "acpi/video.asl") + defer av.Close() + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() +} diff --git a/util/autoport/i82801gx.go b/util/autoport/i82801gx.go new file mode 100644 index 0000000..82db040 --- /dev/null +++ b/util/autoport/i82801gx.go @@ -0,0 +1,265 @@ +package main + +import ( + "fmt" + "os" +) + +type i82801gx struct { +} + +func (i i82801gx) writeGPIO(ctx Context, sb *os.File, inteltool InteltoolData, addr uint16, name string) { + fmt.Fprintf(sb, " outl(0x%08x, DEFAULT_GPIOBASE + %s);\n", + inteltool.GPIO[addr], name) +} + +func (i i82801gx) Scan(ctx Context, addr PCIDevData) { + + /* FIXME: Move to southbbridge. */ + KconfigBool["HAVE_MP_TABLE"] = true + + KconfigBool["SOUTHBRIDGE_INTEL_I82801GX"] = true + KconfigInt["IRQ_SLOT_COUNT"] = 18 + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMstageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "early_mainboard.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + +`) + inteltool := ctx.InfoSource.GetInteltool() + i.writeGPIO(ctx, sb, inteltool, 0x0, "GPIO_USE_SEL") + i.writeGPIO(ctx, sb, inteltool, 0x4, "GP_IO_SEL") + i.writeGPIO(ctx, sb, inteltool, 0xc, "GP_LVL") + i.writeGPIO(ctx, sb, inteltool, 0x18, "GPO_BLINK") + i.writeGPIO(ctx, sb, inteltool, 0x2c, "GPI_INV") + i.writeGPIO(ctx, sb, inteltool, 0x30, "GPIO_USE_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x34, "GP_IO_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x38, "GP_LVL2") + + sb.WriteString(`} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // Enable address decodes + /* FIXME: Make sure that all regions are properly reserved. */ +`) + + /* FIXME: Make sure that all regions are properly reserved. */ + RestorePCI16Simple(sb, addr, 0x80) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI16Simple(sb, addr, 0x84) + RestorePCI16Simple(sb, addr, 0x86) + RestorePCI16Simple(sb, addr, 0x88) + RestorePCI16Simple(sb, addr, 0x8a) + RestorePCI16Simple(sb, addr, 0x8c) + RestorePCI16Simple(sb, addr, 0x8e) + RestorePCI16Simple(sb, addr, 0x90) + RestorePCI16Simple(sb, addr, 0x92) + + /* Just use the same interrupt map for all boards: just registers have to match ACPI. */ + sb.WriteString(`} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable devices. */ +`) + + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString(` + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} +`) + + /* FIXME: does this one need adjustments? */ + sb.WriteString(`void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +`) + + Hardcoded(ctx) + + ioapic := DevTreeNode{ + Chip: "drivers/generic/ioapic", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "have_isa_interrupts": "1", + "irq_on_fsb": "1", + "enable_virtual_wire": "0", + "base": "0xfec00000", + }, + Children: []DevTreeNode{ + { + Chip: "ioapic", + Dev: 2, + }, + }, + } + + PutPCIChip(addr, ioapic) + + ideConfig := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 1}].ConfigDump[0x54] + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/i82801gx", + Comment: "Southbridge", + MissingParent: "southbridge", + Registers: map[string]string{ + /* FIXME: should be a CMOS config */ + "sata_ahci": "0x1", + /* FIXME: hardcoded. */ + "gpi1_routing": "2", + "gpi7_routing": "2", + "gpe0_en": "0x11000006", + "alt_gp_smi_en": "0x1000", + + "sata_ports_implemented": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0xf), + "ide_enable_primary": fmt.Sprintf("%d", (ideConfig>>1)&1), + "ide_enable_secondary": fmt.Sprintf("%d", (ideConfig>>3)&1), + "c4onc3_enable": fmt.Sprintf("%d", ((addr.ConfigDump[0xa0] >> 7) & 1)), + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c3_latency": FormatHexLE16(FADT[98:100]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 1}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 2}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 3}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 7}, writeEmpty: true, additionalComment: "USB EHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 1}, writeEmpty: true, additionalComment: "IDE Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + }, + } + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x00}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x07}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1b}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1c}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x11, 0x10, 0x12, 0x13}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1d}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x17, 0x13, 0x12, 0x10}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1e}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0x14, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1f}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x12, 0x13, 0, 0x10}} + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/ich7.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x27b9, i82801gx{}) + RegisterPCI(0x8086, 0x27c8, GenericPCI{}) + RegisterPCI(0x8086, 0x27c9, GenericPCI{}) + RegisterPCI(0x8086, 0x27ca, GenericPCI{}) + RegisterPCI(0x8086, 0x27cb, GenericPCI{}) + RegisterPCI(0x8086, 0x27cc, GenericPCI{}) + + RegisterPCI(0x8086, 0x27d0, GenericPCI{}) + RegisterPCI(0x8086, 0x27d2, GenericPCI{}) + RegisterPCI(0x8086, 0x27d4, GenericPCI{}) + RegisterPCI(0x8086, 0x27d6, GenericPCI{}) + + RegisterPCI(0x8086, 0x2448, GenericPCI{}) + + RegisterPCI(0x8086, 0x27c5, GenericPCI{}) + RegisterPCI(0x8086, 0x27c4, GenericPCI{}) + RegisterPCI(0x8086, 0x27df, GenericPCI{}) + RegisterPCI(0x8086, 0x27da, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/i945.go b/util/autoport/i945.go new file mode 100644 index 0000000..6ddfac9 --- /dev/null +++ b/util/autoport/i945.go @@ -0,0 +1,81 @@ +package main + +type i945mc struct { +} + +func (i i945mc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/i945", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_hotplug": "0x00000220", + "gpu_lvds_use_spread_spectrum_clock": "1", + "gpu_lvds_is_dual_channel": "0", + "gpu_backlight": "0x1280128", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_mFCPGA478", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + }, + }, + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool["VGA"] = true + KconfigBool["MAINBOARD_DO_EDID"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_MFCPGA478"] = true + KconfigBool["NORTHBRIDGE_INTEL_I945"] = true + KconfigBool["CHANNEL_XOR_RANDOMIZATION"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigHex["DCACHE_RAM_BASE"] = 0xffdf8000 + KconfigHex["DCACHE_RAM_SIZE"] = 0x8000 + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 2 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_6dx/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/i945/acpi/i945.asl", + }) + + /* FIXME: when adding new i945 variants change this. */ + KconfigBool["NORTHBRIDGE_INTEL_SUBTYPE_I945GM"] = true +} + +func init() { + RegisterPCI(0x8086, 0x27a0, i945mc{}) + RegisterPCI(0x8086, 0x27ac, i945mc{}) + RegisterPCI(0x8086, 0x27a2, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27ae, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27a6, GenericPCI{Comment: "display controller"}) +} diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go new file mode 100644 index 0000000..f172520 --- /dev/null +++ b/util/autoport/log_maker.go @@ -0,0 +1,77 @@ +package main + +import ( + "io" + "io/ioutil" + "log" + "os" + "os/exec" + "strings" +) + +func RunAndSave(output string, name string, arg ...string) { + cmd := exec.Command(name, arg...) + + f, err := os.Create(output) + if err != nil { + log.Fatal(err) + } + + cmd.Stdout = f + cmd.Stderr = f + + err = cmd.Start() + if err != nil { + log.Fatal(err) + } + cmd.Wait() +} + +func MakeLogs(outDir string) { + os.MkdirAll(outDir, 0700) + RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") + RunAndSave(outDir+"/dmidecode.log", "dmidecode") + RunAndSave(outDir+"/acpidump.log", "acpidump") + /* FIXME */ + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a") + + SysDir := "/sys/class/sound/card0/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/card0/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + /* + l.InputDirectory + "/inteltool.log" + */ +} diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go new file mode 100644 index 0000000..4e89cf2 --- /dev/null +++ b/util/autoport/log_reader.go @@ -0,0 +1,264 @@ +package main + +import ( + "bufio" + "flag" + "fmt" + "log" + "os" + "strconv" + "strings" +) + +type LogDevReader struct { + InputDirectory string + ACPITables map[string][]byte +} + +func isXDigit(x uint8) bool { + if x >= '0' && x <= '9' { + return true + } + if x >= 'a' && x <= 'f' { + return true + } + if x >= 'A' && x <= 'F' { + return true + } + return false +} + +type HexLine struct { + length uint + values [16]byte + start uint +} + +func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) { + hex.start = 0 + line = strings.Trim(line, " ") + fmt.Sscanf(line, "%x:", &hex.start) + ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start, + &hex.values[0], &hex.values[1], &hex.values[2], + &hex.values[3], &hex.values[4], &hex.values[5], + &hex.values[6], &hex.values[7], &hex.values[8], + &hex.values[9], &hex.values[10], &hex.values[11], + &hex.values[12], &hex.values[13], &hex.values[14], + &hex.values[15]) + hex.length = uint(ll - 1) + return +} + +func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte { + hex := l.ReadHexLine(inp) + if hex.start+hex.length > uint(len(target)) { + target = target[0 : hex.start+hex.length] + } + copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length]) + return target +} + +func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { + if l.ACPITables != nil { + return l.ACPITables + } + l.ACPITables = Tables + + file, err := os.Open(l.InputDirectory + "/acpidump.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + Tables = map[string][]byte{} + + curTable := "" + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) >= 6 && line[5] == '@': + curTable = line[0:4] + Tables[curTable] = make([]byte, 0, 100000) + case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':': + Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) { + file, err := os.Open(l.InputDirectory + "/lspci.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + PCIList = []PCIDevData{} + + for scanner.Scan() { + line := scanner.Text() + switch { + case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + cur := PCIDevData{} + fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) + lc := strings.LastIndex(line, ":") + li := strings.LastIndex(line[0:lc], "[") + if li < 0 { + continue + } + ven := 0 + dev := 0 + fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) + cur.PCIDevID = uint16(dev) + cur.PCIVenID = uint16(ven) + cur.ConfigDump = make([]byte, 0x100, 0x1000) + PCIList = append(PCIList, cur) + case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': + start := 0 + fmt.Sscanf(line, "%x:", &start) + cur := &PCIList[len(PCIList)-1] + cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetInteltool() (ret InteltoolData) { + file, err := os.Open(l.InputDirectory + "/inteltool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + ret.GPIO = map[uint16]uint32{} + ret.RCBA = map[uint16]uint32{} + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.RCBA[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "gpiobase"): + addr, value := 0, 0 + fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value) + ret.GPIO[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "============="): + paragraph = strings.Trim(line, "= ") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetDMI() (ret DMIData) { + file, err := os.Open(l.InputDirectory + "/dmidecode.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + for scanner.Scan() { + line := scanner.Text() + if !strings.HasPrefix(line, "\t") { + paragraph = strings.TrimSpace(line) + continue + } + idx := strings.Index(line, ":") + if idx < 0 { + continue + } + name := strings.TrimSpace(line[0:idx]) + value := strings.TrimSpace(line[idx+1:]) + switch paragraph + ":" + name { + case "System Information:Manufacturer": + ret.Vendor = value + case "System Information:Product Name": + ret.Model = value + case "System Information:Version": + ret.Version = value + case "Chassis Information:Type": + ret.IsLaptop = (value == "Notebook" || value == "Laptop") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) { + for codecno := 0; codecno < 10; codecno++ { + cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}} + codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer codec.Close() + pin, err := os.Open(l.InputDirectory + "/pin_hwC0D" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer pin.Close() + + scanner := bufio.NewScanner(codec) + for scanner.Scan() { + line := scanner.Text() + if strings.HasPrefix(line, "Codec:") { + fmt.Sscanf(line, "Codec: %s", &cur.Name) + continue + } + if strings.HasPrefix(line, "Vendor Id:") { + fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID) + continue + } + if strings.HasPrefix(line, "Subsystem Id:") { + fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID) + continue + } + } + + scanner = bufio.NewScanner(pin) + for scanner.Scan() { + line := scanner.Text() + addr := 0 + val := uint32(0) + fmt.Sscanf(line, "0x%x 0x%x", &addr, &val) + cur.PinConfig[addr] = val + } + ret = append(ret, cur) + } + return +} + +var FlagLogInput = flag.String("input_log", ".", "Input log directory") +var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs") + +func MakeLogReader() *LogDevReader { + if *FlagLogMkLogs { + MakeLogs(*FlagLogInput) + } + return &LogDevReader{InputDirectory: *FlagLogInput} +} diff --git a/util/autoport/main.go b/util/autoport/main.go new file mode 100644 index 0000000..67f40e5 --- /dev/null +++ b/util/autoport/main.go @@ -0,0 +1,537 @@ +/* This is just an experiment. Full automatic porting + is probably not possible but a lot can be automated. */ +package main + +import ( + "flag" + "fmt" + "log" + "os" + "strings" +) + +type PCIAddr struct { + Bus int + Dev int + Func int +} + +type PCIDevData struct { + PCIAddr + PCIVenID uint16 + PCIDevID uint16 + ConfigDump []uint8 +} + +type PCIDevice interface { + Scan(ctx Context, addr PCIDevData) +} + +type InteltoolData struct { + GPIO map[uint16]uint32 + RCBA map[uint16]uint32 +} + +type DMIData struct { + Vendor string + Model string + Version string + IsLaptop bool +} + +type AzaliaCodec struct { + Name string + VendorID uint32 + SubsystemID uint32 + CodecNo int + PinConfig map[int]uint32 +} + +type DevReader interface { + GetPCIList() []PCIDevData + GetDMI() DMIData + GetInteltool() InteltoolData + GetAzaliaCodecs() []AzaliaCodec + GetACPI() map[string][]byte +} + +var ROMStageFiles map[string]string = map[string]string{} +var RAMStageFiles map[string]string = map[string]string{} + +type Context struct { + MoboID string + KconfigName string + Vendor string + Model string + BaseDirectory string + InfoSource DevReader +} + +type IOAPICIRQ struct { + APICID int + IRQNO [4]int +} + +var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} +var KconfigBool map[string]bool = map[string]bool{} +var KconfigString map[string]string = map[string]string{} +var KconfigStringUnquoted map[string]string = map[string]string{} +var KconfigHex map[string]uint32 = map[string]uint32{} +var KconfigInt map[string]int = map[string]int{} + +func FormatHexLE16(inp []byte) string { + return fmt.Sprintf("0x%04x", uint16(inp[0])|(uint16(inp[1])<<8)) +} + +func FormatBool(inp bool) string { + if inp { + return "1" + } else { + return "0" + } +} + +func sanitize(inp string) string { + result := strings.ToLower(inp) + result = strings.Replace(result, " ", "_", -1) + result = strings.Replace(result, ",", "_", -1) + for strings.HasSuffix(result, ".") { + result = result[0 : len(result)-1] + } + return result +} + +func AddROMstageFile(Name string, Condition string) { + ROMStageFiles[Name] = Condition +} + +func AddRAMstageFile(Name string, Condition string) { + RAMStageFiles[Name] = Condition +} + +var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory") + +func writeMF(mf *os.File, files map[string]string, category string) { + for file, condition := range files { + if condition == "" { + fmt.Fprintf(mf, "%s-y += %s\n", category, file) + } else { + fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, + condition, file) + } + } +} + +func Create(ctx Context, name string) *os.File { + li := strings.LastIndex(name, "/") + if li > 0 { + os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700) + } + mf, err := os.Create(ctx.BaseDirectory + "/" + name) + if err != nil { + log.Fatal(err) + } + return mf +} + +func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) { + fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) +} + +type PCISlot struct { + PCIAddr + additionalComment string + writeEmpty bool +} + +type DevTreeNode struct { + Bus int + Dev int + Func int + Disabled bool + Registers map[string]string + Children []DevTreeNode + PCISlots []PCISlot + PCIController bool + ChildPCIBus int + MissingParent string + SubVendor uint16 + SubSystem uint16 + Chip string + Comment string +} + +var DevTree DevTreeNode +var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{} +var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} +var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} + +func Offset(dt *os.File, offset int) { + for i := 0; i < offset; i++ { + fmt.Fprintf(dt, "\t") + } +} + +func MatchDev(dev *DevTreeNode) { + for idx := range dev.Children { + MatchDev(&dev.Children[idx]) + } + + for _, slot := range dev.PCISlots { + slotChip, ok := unmatchedPCIChips[slot.PCIAddr] + + if !ok { + continue + } + + if slot.additionalComment != "" && slotChip.Comment != "" { + slotChip.Comment = slot.additionalComment + " " + slotChip.Comment + } else { + slotChip.Comment = slot.additionalComment + slotChip.Comment + } + + delete(unmatchedPCIChips, slot.PCIAddr) + MatchDev(&slotChip) + dev.Children = append(dev.Children, slotChip) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIChips { + if slot.Bus == dev.ChildPCIBus { + delete(unmatchedPCIChips, slot) + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + } + } + } + + for _, slot := range dev.PCISlots { + slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] + if !ok { + if slot.writeEmpty { + dev.Children = append(dev.Children, + DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: slot.Bus, + Dev: slot.Dev, + Func: slot.Func, + Comment: slot.additionalComment, + Disabled: true, + }, + ) + } + continue + } + + if slot.additionalComment != "" && slotDev.Comment != "" { + slotDev.Comment = slot.additionalComment + " " + slotDev.Comment + } else { + slotDev.Comment = slot.additionalComment + slotDev.Comment + } + + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot.PCIAddr) + } + + if dev.MissingParent != "" { + for _, child := range MissingChildren[dev.MissingParent] { + MatchDev(&child) + dev.Children = append(dev.Children, child) + } + delete(MissingChildren, dev.MissingParent) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIDevices { + if slot.Bus == dev.ChildPCIBus { + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot) + } + } + } +} + +func writeOn(dt *os.File, dev DevTreeNode) { + if dev.Disabled { + fmt.Fprintf(dt, "off") + } else { + fmt.Fprintf(dt, "on") + } +} + +func WriteDev(dt *os.File, offset int, dev DevTreeNode) { + Offset(dt, offset) + switch dev.Chip { + case "cpu_cluster", "lapic", "domain", "ioapic": + fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + case "pci": + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + writeOn(dt, dev) + default: + fmt.Fprintf(dt, "chip %s", dev.Chip) + } + if dev.Comment != "" { + fmt.Fprintf(dt, " # %s", dev.Comment) + } + fmt.Fprintf(dt, "\n") + if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem) + } + + ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}] + if dev.Chip == "pci" && ok { + for pin, irq := range ioapic.IRQNO { + if irq != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq) + } + } + } + + for reg, val := range dev.Registers { + Offset(dt, offset+1) + fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val) + } + + for _, child := range dev.Children { + WriteDev(dt, offset+1, child) + } + + Offset(dt, offset) + fmt.Fprintf(dt, "end\n") +} + +func PutChip(domain string, cur DevTreeNode) { + MissingChildren[domain] = append(MissingChildren[domain], cur) +} + +func PutPCIChip(addr PCIDevData, cur DevTreeNode) { + unmatchedPCIChips[addr.PCIAddr] = cur +} + +func PutPCIDevParent(addr PCIDevData, comment string, parent string) { + cur := DevTreeNode{ + Registers: map[string]string{}, + SubVendor: uint16(addr.ConfigDump[0x2c]) | (uint16(addr.ConfigDump[0x2d]) << 8), + SubSystem: uint16(addr.ConfigDump[0x2e]) | (uint16(addr.ConfigDump[0x2f]) << 8), + Chip: "pci", + Bus: addr.Bus, + Dev: addr.Dev, + Func: addr.Func, + MissingParent: parent, + Comment: comment, + } + if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 { + cur.PCIController = true + cur.ChildPCIBus = int(addr.ConfigDump[0x19]) + } + unmatchedPCIDevices[addr.PCIAddr] = cur +} + +func PutPCIDev(addr PCIDevData, comment string) { + PutPCIDevParent(addr, comment, "") +} + +type GenericPCI struct { + Comment string + Bus0Subdiv string + MissingParent string +} + +type GenericVGA struct { + GenericPCI +} + +type DSDTInclude struct { + Comment string + File string +} + +var DSDTIncludes []DSDTInclude +var DSDTPCI0Includes []DSDTInclude + +func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { + KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x.%04x", + addr.PCIVenID, + addr.PCIDevID) + KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom", + addr.PCIVenID, + addr.PCIDevID) + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func main() { + flag.Parse() + + ctx := Context{} + + ctx.InfoSource = MakeLogReader() + + dmi := ctx.InfoSource.GetDMI() + + ctx.Vendor = dmi.Vendor + + if dmi.Vendor == "LENOVO" { + ctx.Model = dmi.Version + } else { + ctx.Model = dmi.Model + } + + if dmi.IsLaptop { + KconfigBool["SYSTEM_TYPE_LAPTOP"] = true + } + ctx.MoboID = sanitize(ctx.Vendor) + "/" + sanitize(ctx.Model) + ctx.KconfigName = "BOARD_" + strings.ToUpper(sanitize(ctx.Vendor)+"_"+sanitize(ctx.Model)) + ctx.BaseDirectory = *FlagOutDir + "/src/mainboard/" + ctx.MoboID + KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model + + /* Only x86 currently. */ + KconfigBool["ARCH_X86"] = true + + /* FIXME: hardcoded. */ + KconfigBool["BOARD_ROMSIZE_KB_2048"] = true + + os.MkdirAll(ctx.BaseDirectory, 0700) + + ScanRoot(ctx) + + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 { + mf := Create(ctx, "Makefile.inc") + defer mf.Close() + writeMF(mf, ROMStageFiles, "romstage") + } + + devtree := Create(ctx, "devicetree.cb") + defer devtree.Close() + + MatchDev(&DevTree) + WriteDev(devtree, 0, DevTree) + + bi := Create(ctx, "board_info.txt") + defer bi.Close() + + if dmi.IsLaptop { + bi.WriteString("Category: laptop") + } else { + /* FIXME: other categories. */ + bi.WriteString("Category: desktop") + } + + /* FIXME: flash chip. */ + + kc := Create(ctx, "Kconfig") + defer kc.Close() + + fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName) + + fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n") + for name, val := range KconfigBool { + if val { + fmt.Fprintf(kc, "\tselect %s\n", name) + } + } + + for name, val := range KconfigBool { + if !val { + fmt.Fprintf(kc, ` +config %s + string + default n +`, name) + } + } + + for name, val := range KconfigStringUnquoted { + fmt.Fprintf(kc, ` +config %s + string + default %s +`, name, val) + } + + for name, val := range KconfigString { + fmt.Fprintf(kc, ` +config %s + string + default "%s" +`, name, val) + } + + for name, val := range KconfigHex { + fmt.Fprintf(kc, ` +config %s + hex + default 0x%x +`, name, val) + } + + for name, val := range KconfigInt { + fmt.Fprintf(kc, ` +config %s + int + default %d +`, name, val) + } + + fmt.Fprintf(kc, "endif\n") + + dsdt := Create(ctx, "dsdt.asl") + defer dsdt.Close() + + dsdt.WriteString( + `DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" +`) + + for _, x := range DSDTIncludes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File) + } + + dsdt.WriteString(` + Scope (\_SB) { + Device (PCI0) + { +`) + /* FIXME: use scoping at another level. */ + for _, x := range DSDTPCI0Includes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + } + dsdt.WriteString( + ` } + } +} +`) + +} diff --git a/util/autoport/rce823.go b/util/autoport/rce823.go new file mode 100644 index 0000000..07002f5 --- /dev/null +++ b/util/autoport/rce823.go @@ -0,0 +1,39 @@ +package main + +import "fmt" + +type rce823 struct { + variant string +} + +func (r rce823) Scan(ctx Context, addr PCIDevData) { + if addr.Dev == 0 && addr.Func == 0 { + cur := DevTreeNode{ + Chip: "drivers/ricoh/rce822", + Comment: "Ricoh cardreader", + Registers: map[string]string{ + + "sdwppol": fmt.Sprintf("%d", (addr.ConfigDump[0xfb]&2)>>1), + "disable_mask": fmt.Sprintf("0x%x", addr.ConfigDump[0xcb]), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 0}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 1}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 2}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 3}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 4}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 5}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 6}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 7}, writeEmpty: false}, + }, + } + PutPCIChip(addr, cur) + } + PutPCIDev(addr, "Ricoh SD card reader") + +} + +func init() { + RegisterPCI(0x1180, 0xe822, rce823{}) + RegisterPCI(0x1180, 0xe823, rce823{}) +} diff --git a/util/autoport/root.go b/util/autoport/root.go new file mode 100644 index 0000000..60b5ccd --- /dev/null +++ b/util/autoport/root.go @@ -0,0 +1,29 @@ +package main + +import "fmt" + +var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{} +var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{} + +func ScanRoot(ctx Context) { + for _, pciDev := range ctx.InfoSource.GetPCIList() { + PCIMap[pciDev.PCIAddr] = pciDev + } + for _, pciDev := range ctx.InfoSource.GetPCIList() { + vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID) + + dev, ok := supportedPCIDevices[vendevid] + if !ok { + fmt.Printf("Unsupported PCI device %04x:%04x\n", + pciDev.PCIVenID, pciDev.PCIDevID) + dev = GenericPCI{Comment: fmt.Sprintf("Unsupported PCI device %04x:%04x", + pciDev.PCIVenID, pciDev.PCIDevID)} + } + dev.Scan(ctx, pciDev) + } +} + +func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) { + vendevid := (uint32(DevID) << 16) | uint32(VenID) + supportedPCIDevices[vendevid] = dev +} diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go new file mode 100644 index 0000000..a6b9c1e --- /dev/null +++ b/util/autoport/sandybridge.go @@ -0,0 +1,112 @@ +package main + +type sandybridgemc struct { + variant string +} + +func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/sandybridge", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_dp_d_hotplug": "0x06", + "gpu_panel_port_select": "0", + "gpu_panel_power_cycle_delay": "5", + "gpu_panel_power_up_delay": "300", + "gpu_panel_power_down_delay": "300", + "gpu_panel_power_backlight_on_delay": "2000", + "gpu_panel_power_backlight_off_delay": "2000", + "gfx.use_spread_spectrum_clock": "1", + "gfx.lvds_dual_channel": "0", + "gfx.link_frequency_270_mhz": "1", + "gfx.lvds_num_lanes": "4", + "gpu_cpu_backlight": "0x1155", + "gpu_pch_backlight": "0x06100610", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_rPGA989", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + + { + Chip: "cpu/intel/model_206ax", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "pstate_coord_type": "0xfe", + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + }, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool[i.variant+"BRIDGE_LVDS"] = true + + KconfigBool["VGA"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true + KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigBool["HAVE_IFD_BIN"] = false + KconfigBool["HAVE_ME_BIN"] = false + + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_206ax/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"}) + RegisterPCI(0x8086, 0x0166, GenericVGA{GenericPCI{Comment: "VGA controller"}}) +}

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New patch to review for coreboot: 89d5c74 inteltool: Fix message in case of multiple LPC controllers
by Mathias Krause 05 Nov '14

05 Nov '14

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7342 -gerrit commit 89d5c74e6c9b652a763f95e8e955be8d0430bc96 Author: Mathias Krause <minipli(a)googlemail.com> Date: Wed Nov 5 21:27:01 2014 +0100 inteltool: Fix message in case of multiple LPC controllers If we find multiple LPC controllers, we want to tell the user that we'll ignore all but the first. However, we use 'dev' in the message (the current device found) instead of 'sb' (the one we want to use). Fix the message by using 'sb' and break the loop right away in this case. It's sufficient to tell the user once which LPC controller we'll use. Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- util/inteltool/inteltool.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 5e320e2..9775aeb 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -338,13 +338,14 @@ int main(int argc, char *argv[]) pci_fill_info(dev, PCI_FILL_CLASS); /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */ if (dev->device_class == 0x0601) { /* ISA/LPC bridge */ - if (sb == NULL) + if (sb == NULL) { sb = dev; - else + } else { fprintf(stderr, "Multiple devices with class ID" " 0x0601, using %02x%02x:%02x.%02x\n", - dev->domain, dev->bus, dev->dev, - dev->func); + sb->domain, sb->bus, sb->dev, sb->func); + break; + } } }

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Patch merged into coreboot/master: 5e1d34b mainboard/packardbell/ms2290: Missing romstage header
by gerrit＠coreboot.org 05 Nov '14

05 Nov '14

the following patch was just integrated into master: commit 5e1d34b19a6ad9c65f7c7833df3791707d5d9905 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 29 07:56:04 2014 +1100 mainboard/packardbell/ms2290: Missing romstage header cpu/intel/romstage.h is needed so the the main() has a prototype in freestanding. Change-Id: I5e6afef82a4f63ab42927725adf3881084a1e25c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7235 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7235 for details. -gerrit

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coreboot-gerrit November 2014