coreboot-gerrit November 2014

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Patch set updated for coreboot: 3df841b southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 3df841b2e952905a80d9fff8ed573da938c56a5b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/cx700/lpc.c | 8 ++++---- src/northbridge/via/vx800/lpc.c | 6 +++--- src/northbridge/via/vx900/lpc.c | 14 +++++++------- src/southbridge/amd/agesa/hudson/lpc.c | 12 ++++++------ src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb700/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb700/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/cimx/sb800/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb800/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/cimx/sb900/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb900/lpc.h | 6 +++--- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb600/lpc.c | 12 ++++++------ src/southbridge/amd/sb600/sata.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/amd/sb700/lpc.c | 12 ++++++------ src/southbridge/amd/sb700/sata.c | 2 +- src/southbridge/amd/sb800/lpc.c | 12 ++++++------ src/southbridge/amd/sb800/sata.c | 2 +- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/intel/bd82x6x/lpc.c | 18 +++++++++--------- src/southbridge/intel/bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/bd82x6x/sata.c | 4 ++-- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/esb6300/lpc.c | 22 +++++++++++----------- src/southbridge/intel/esb6300/sata.c | 2 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/fsp_bd82x6x/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_rangeley/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/intel/i3100/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i3100/sata.c | 2 +- src/southbridge/intel/i82801ax/lpc.c | 10 +++++----- src/southbridge/intel/i82801bx/lpc.c | 10 +++++----- src/southbridge/intel/i82801cx/lpc.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 10 +++++----- src/southbridge/intel/i82801ex/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i82801gx/lpc.c | 16 ++++++++-------- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 14 +++++++------- src/southbridge/intel/i82801ix/sata.c | 8 ++++---- src/southbridge/intel/ibexpeak/lpc.c | 18 +++++++++--------- src/southbridge/intel/ibexpeak/me.c | 14 +++++++------- src/southbridge/intel/ibexpeak/sata.c | 4 ++-- src/southbridge/intel/lynxpoint/lpc.c | 26 +++++++++++++------------- src/southbridge/intel/lynxpoint/sata.c | 4 ++-- src/southbridge/intel/sch/lpc.c | 8 ++++---- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/sis/sis966/lpc.c | 18 +++++++++--------- src/southbridge/sis/sis966/sata.c | 2 +- src/southbridge/via/vt8231/early_serial.c | 2 +- src/southbridge/via/vt8231/lpc.c | 2 +- src/southbridge/via/vt8235/lpc.c | 6 +++--- src/southbridge/via/vt8237r/lpc.c | 8 ++++---- src/southbridge/via/vt8237r/sata.c | 2 +- src/southbridge/via/vt82c686/early_serial.c | 4 ++-- 81 files changed, 329 insertions(+), 329 deletions(-) diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 1e6d2ce..db810d2 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -80,7 +80,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -232,7 +232,7 @@ static void cx700_set_lpc_registers(struct device *dev) } -static void cx700_read_resources(device_t dev) +static void cx700_read_resources(struct device *dev) { struct resource *res; @@ -254,7 +254,7 @@ static void cx700_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void cx700_set_resources(device_t dev) +static void cx700_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); @@ -262,7 +262,7 @@ static void cx700_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void cx700_enable_resources(device_t dev) +static void cx700_enable_resources(struct device *dev) { /* Enable SuperIO decoding */ pci_dev_enable_resources(dev); diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index c2a8a1d..ca9bfc2 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -103,7 +103,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); } -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ @@ -300,7 +300,7 @@ static void vx800_sb_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vx800_read_resources(device_t dev) +static void vx800_read_resources(struct device *dev) { struct resource *resource; @@ -313,7 +313,7 @@ static void vx800_read_resources(device_t dev) resource->base = 0x2e; } -static void vx800_set_resources(device_t dev) +static void vx800_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index ac5e4c8..f22cee5 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -50,7 +50,7 @@ * it will work, but perhaps this should be more configurable. */ -static void vx900_lpc_misc_stuff(device_t dev) +static void vx900_lpc_misc_stuff(struct device *dev) { char extint; u8 val; @@ -74,7 +74,7 @@ static void vx900_lpc_misc_stuff(device_t dev) } } -static void vx900_lpc_dma_setup(device_t dev) +static void vx900_lpc_dma_setup(struct device *dev) { /* These are the steps recommended by VIA in order to get DMA running */ @@ -107,12 +107,12 @@ static void vx900_lpc_dma_setup(device_t dev) * We are assuming this is called before the drivers/generic/ioapic code, * which should be the case if devicetree.cb is set up properly. */ -static void vx900_lpc_ioapic_setup(device_t dev) +static void vx900_lpc_ioapic_setup(struct device *dev) { /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb * If it's not, then the generic ioapic driver will not set it up * correctly, and the MP table will not be correctly generated */ - device_t ioapic; + struct device *ioapic; for (ioapic = dev->next; ioapic; ioapic = ioapic->next) { if (ioapic->path.type == DEVICE_PATH_IOAPIC) break; @@ -154,7 +154,7 @@ static void vx900_lpc_ioapic_setup(device_t dev) pci_mod_config8(dev, 0x58, 0, 1 << 6); } -static void vx900_lpc_interrupt_stuff(device_t dev) +static void vx900_lpc_interrupt_stuff(struct device *dev) { /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports * And enable I/O recovery time */ @@ -180,7 +180,7 @@ static void vx900_lpc_interrupt_stuff(device_t dev) vx900_lpc_ioapic_setup(dev); } -static void vx900_lpc_init(device_t dev) +static void vx900_lpc_init(struct device *dev) { vx900_lpc_interrupt_stuff(dev); vx900_lpc_misc_stuff(dev); @@ -204,7 +204,7 @@ static const struct pci_driver lpc_driver __pci_driver = { #if CONFIG_PIRQ_ROUTE void pirq_assign_irqs(const u8 * pirq) { - device_t lpc; + struct device *lpc; lpc = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_LPC, 0); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 1f60bc4..3b0c90d 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -31,11 +31,11 @@ #include <arch/ioapic.h> #include "hudson.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -80,7 +80,7 @@ static void lpc_init(device_t dev) cmos_init(0); } -static void hudson_lpc_read_resources(device_t dev) +static void hudson_lpc_read_resources(struct device *dev) { struct resource *res; @@ -128,7 +128,7 @@ static void hudson_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void hudson_lpc_enable_childrens_resources(device_t dev) +static void hudson_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -168,7 +168,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) reg_var[0] = pci_read_config16(dev, 0x64); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -307,7 +307,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void hudson_lpc_enable_resources(device_t dev) +static void hudson_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); hudson_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..ce22d34 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 718b40b..d8fb2e7 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -86,7 +86,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void amd8111_lpc_read_resources(device_t dev) +static void amd8111_lpc_read_resources(struct device *dev) { struct resource *res; @@ -112,7 +112,7 @@ static void amd8111_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 5d05762..3b4a40a 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -38,7 +38,7 @@ void backup_top_of_ram(uint64_t ramtop) } } -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -92,7 +92,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -104,7 +104,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h index b30f247..7d1874f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.h +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 519e3c1..4663c9f 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include <cbmem.h> -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -80,7 +80,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -92,7 +92,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 8a657d8..032db06 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..86e4f89 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index ce1be11..5a56b49 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -23,7 +23,7 @@ #include <arch/ioapic.h> -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -77,7 +77,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -89,7 +89,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h index 66f3ccd..fe2f84b 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ b/src/southbridge/amd/cimx/sb900/lpc.h @@ -24,8 +24,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index d8e63b5..1a1fab7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -33,11 +33,11 @@ #include <cpu/amd/powernow.h> #include "sb600.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -66,7 +66,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); } -static void sb600_lpc_read_resources(device_t dev) +static void sb600_lpc_read_resources(struct device *dev) { struct resource *res; @@ -102,7 +102,7 @@ static void sb600_lpc_read_resources(device_t dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb600_lpc_enable_childrens_resources(device_t dev) +static void sb600_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -114,7 +114,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -213,7 +213,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb600_lpc_enable_resources(device_t dev) +static void sb600_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb600_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index a17aab8..b965bb9 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -70,7 +70,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb600_config *conf; conf = dev->chip_info; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 173de83..c266402 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -40,11 +40,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -104,7 +104,7 @@ void backup_top_of_ram(uint64_t ramtop) } } -static void sb700_lpc_read_resources(device_t dev) +static void sb700_lpc_read_resources(struct device *dev) { struct resource *res; @@ -151,7 +151,7 @@ static void sb700_lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -static void sb700_lpc_enable_childrens_resources(device_t dev) +static void sb700_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -163,7 +163,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -262,7 +262,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb700_lpc_enable_resources(device_t dev) +static void sb700_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb700_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index c0e3c0f..1a7410b 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -86,7 +86,7 @@ static void sata_init(struct device *dev) u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 7a4dd83..143e717 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -28,11 +28,11 @@ #include <arch/io.h> #include "sb800.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); } -static void sb800_lpc_read_resources(device_t dev) +static void sb800_lpc_read_resources(struct device *dev) { struct resource *res; @@ -118,7 +118,7 @@ static void sb800_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb800_lpc_enable_childrens_resources(device_t dev) +static void sb800_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -130,7 +130,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -229,7 +229,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb800_lpc_enable_resources(device_t dev) +static void sb800_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb800_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 5ac6144..c592298 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -89,7 +89,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb800_config *conf; conf = dev->chip_info; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..35173d3 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device *dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..d2b908e 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0e3a4f6..04f38d1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -393,7 +393,7 @@ static void enable_hpet(void) RCBA32(HPTC) = reg32; } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -581,7 +581,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -645,13 +645,13 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -660,7 +660,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 44c7273..a316ea0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -548,7 +548,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -615,7 +615,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -645,7 +645,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -692,14 +692,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -741,7 +741,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index cb5699e..897470b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -211,7 +211,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -236,7 +236,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..e5783e7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + struct device * dev; ich9_spi_regs *ich9_spi; uint16_t hsfs; diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index b5b77ef..b2dcd06 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -24,7 +24,7 @@ #endif #define SERIRQ_CNTL 0x64 -static void esb6300_enable_serial_irqs(device_t dev) +static void esb6300_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -32,14 +32,14 @@ static void esb6300_enable_serial_irqs(device_t dev) } #define PCI_DMA_CFG 0x90 -static void esb6300_pci_dma_cfg(device_t dev) +static void esb6300_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } #define LPC_EN 0xe6 -static void esb6300_enable_lpc(device_t dev) +static void esb6300_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -48,7 +48,7 @@ static void esb6300_enable_lpc(device_t dev) typedef struct southbridge_intel_esb6300_config config_t; static void set_esb6300_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; @@ -81,7 +81,7 @@ static void set_esb6300_gpio_use_sel( } static void set_esb6300_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; @@ -114,7 +114,7 @@ static void set_esb6300_gpio_direction( } static void set_esb6300_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -154,7 +154,7 @@ static void set_esb6300_gpio_level( } static void set_esb6300_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv; @@ -176,7 +176,7 @@ static void set_esb6300_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void esb6300_pirq_init(device_t dev) +static void esb6300_pirq_init(struct device *dev) { config_t *config; @@ -192,7 +192,7 @@ static void esb6300_pirq_init(device_t dev) } -static void esb6300_gpio_init(device_t dev) +static void esb6300_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -303,7 +303,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); } -static void esb6300_lpc_read_resources(device_t dev) +static void esb6300_lpc_read_resources(struct device *dev) { struct resource *res; @@ -335,7 +335,7 @@ static void esb6300_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void esb6300_lpc_enable_resources(device_t dev) +static void esb6300_lpc_enable_resources(struct device *dev) { uint8_t acpi_cntl, gpio_cntl; diff --git a/src/southbridge/intel/esb6300/sata.c b/src/southbridge/intel/esb6300/sata.c index b08f0ed..cc11006 100644 --- a/src/southbridge/intel/esb6300/sata.c +++ b/src/southbridge/intel/esb6300/sata.c @@ -42,7 +42,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); } -static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void esb6300_sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* This value is also visible in usb1, usb2 and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..edd5dc7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -116,9 +116,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -158,7 +158,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -187,7 +187,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -547,7 +547,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -608,18 +608,18 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 2282378..ddec118 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -119,7 +119,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -547,7 +547,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -614,7 +614,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -644,7 +644,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -691,14 +691,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -740,7 +740,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 591bdbc..cbbb76b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -82,11 +82,11 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8576b61..9b1df7a 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -113,8 +113,8 @@ static void soc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -197,7 +197,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void soc_pirq_init(device_t dev) +static void soc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -242,7 +242,7 @@ static void soc_pirq_init(device_t dev) write_pci_config_irqs(); } -static void soc_power_options(device_t dev) +static void soc_power_options(struct device *dev) { u8 reg8; u16 pmbase; @@ -344,7 +344,7 @@ static void lpc_init(struct device *dev) soc_disable_smm_only_flashing(dev); } -static void soc_lpc_read_resources(device_t dev) +static void soc_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -405,17 +405,17 @@ static void soc_lpc_read_resources(device_t dev) } } -static void soc_lpc_enable_resources(device_t dev) +static void soc_lpc_enable_resources(struct device *dev) { return pci_dev_enable_resources(dev); } -static void soc_lpc_enable(device_t dev) +static void soc_lpc_enable(struct device *dev) { soc_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index f672e4c..dcaa230 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -95,11 +95,11 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..c4e8a1c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + struct device * dev; uint32_t ids; uint16_t vendor_id, device_id; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index ba74f30..6cfec63 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void i3100_enable_serial_irqs(device_t dev) +static void i3100_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -62,7 +62,7 @@ static void i3100_enable_serial_irqs(device_t dev) typedef struct southbridge_intel_i3100_config config_t; static void set_i3100_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_use_sel, gpio_use_sel2; int i; @@ -95,7 +95,7 @@ static void set_i3100_gpio_use_sel( } static void set_i3100_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_io_sel, gpio_io_sel2; int i; @@ -128,7 +128,7 @@ static void set_i3100_gpio_direction( } static void set_i3100_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_lvl, gpio_lvl2; u32 gpio_blink; @@ -172,7 +172,7 @@ static void set_i3100_gpio_level( } static void set_i3100_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_inv; int i; @@ -196,9 +196,9 @@ static void set_i3100_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void i3100_pirq_init(device_t dev) +static void i3100_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config; /* Get the chip configuration */ @@ -245,7 +245,7 @@ static void i3100_pirq_init(device_t dev) } -static void i3100_power_options(device_t dev) { +static void i3100_power_options(struct device *dev) { u8 reg8; u16 reg16; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; @@ -308,7 +308,7 @@ static void i3100_power_options(device_t dev) { // i82801gx_gpi_routing(dev); } -static void i3100_gpio_init(device_t dev) +static void i3100_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -384,7 +384,7 @@ static void lpc_init(struct device *dev) i8259_configure_irq_trigger(9, 1); } -static void i3100_lpc_read_resources(device_t dev) +static void i3100_lpc_read_resources(struct device *dev) { struct resource *res; @@ -424,7 +424,7 @@ static void i3100_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM; } -static void i3100_lpc_enable_resources(device_t dev) +static void i3100_lpc_enable_resources(struct device *dev) { u8 acpi_cntl, gpio_cntl; diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index 0740440..6f4ebf9 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -111,7 +111,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 11519c1..c96ac00 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -122,7 +122,7 @@ static void i82801ax_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801ax_pirq_init(device_t dev) +static void i82801ax_pirq_init(struct device *dev) { u8 reg8; config_t *config = dev->chip_info; @@ -140,7 +140,7 @@ static void i82801ax_pirq_init(device_t dev) pci_write_config8(dev, PIRQD_ROUT, reg8); } -static void i82801ax_power_options(device_t dev) +static void i82801ax_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -170,7 +170,7 @@ static void i82801ax_power_options(device_t dev) } } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); pci_write_config8(dev, GPIO_CNTL, GPIO_EN); @@ -211,7 +211,7 @@ static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801ax_lpc_decode_en(device_t dev) +static void i82801ax_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -255,7 +255,7 @@ static void lpc_init(struct device *dev) i82801ax_lpc_decode_en(dev); } -static void i82801ax_lpc_read_resources(device_t dev) +static void i82801ax_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 278d65c..3bd6570 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -123,7 +123,7 @@ static void i82801bx_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801bx_pirq_init(struct device *dev, uint16_t ich_model) { u8 reg8; config_t *config = dev->chip_info; @@ -154,7 +154,7 @@ static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) pci_write_config8(dev, PIRQH_ROUT, reg8); } -static void i82801bx_power_options(device_t dev) +static void i82801bx_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -184,7 +184,7 @@ static void i82801bx_power_options(device_t dev) } } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); @@ -226,7 +226,7 @@ static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801bx_lpc_decode_en(struct device *dev, uint16_t ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -273,7 +273,7 @@ static void lpc_init(struct device *dev) i82801bx_lpc_decode_en(dev, ich_model); } -static void i82801bx_lpc_read_resources(device_t dev) +static void i82801bx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f6c33b7..9978842 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -199,7 +199,7 @@ static void lpc_init(struct device *dev) i82801cx_1f0_misc(dev); } -static void i82801cx_lpc_read_resources(device_t dev) +static void i82801cx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1b23fad..c5821c6 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -85,7 +85,7 @@ static void i82801dx_enable_serial_irqs(struct device *dev) (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -static void i82801dx_pirq_init(device_t dev) +static void i82801dx_pirq_init(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -100,7 +100,7 @@ static void i82801dx_pirq_init(device_t dev) pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); } -static void i82801dx_power_options(device_t dev) +static void i82801dx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -179,7 +179,7 @@ static void i82801dx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* This should be done in romstage.c already */ pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); @@ -221,7 +221,7 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(device_t dev) +static void i82801dx_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -305,7 +305,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801dx_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 1823e65..7703d14 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -61,7 +61,7 @@ static void i82801ex_general_cntl(struct device *dev) } #define SERIRQ_CNTL 0x64 -static void i82801ex_enable_serial_irqs(device_t dev) +static void i82801ex_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -69,14 +69,14 @@ static void i82801ex_enable_serial_irqs(device_t dev) } #define PCI_DMA_CFG 0x90 -static void i82801ex_pci_dma_cfg(device_t dev) +static void i82801ex_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } #define LPC_EN 0xe6 -static void i82801ex_enable_lpc(device_t dev) +static void i82801ex_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -85,7 +85,7 @@ static void i82801ex_enable_lpc(device_t dev) typedef struct southbridge_intel_i82801ex_config config_t; static void set_i82801ex_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; int i; @@ -114,7 +114,7 @@ static void set_i82801ex_gpio_use_sel( } static void set_i82801ex_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; int i; @@ -143,7 +143,7 @@ static void set_i82801ex_gpio_direction( } static void set_i82801ex_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -178,7 +178,7 @@ static void set_i82801ex_gpio_level( } static void set_i82801ex_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv; int i; @@ -198,7 +198,7 @@ static void set_i82801ex_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void i82801ex_pirq_init(device_t dev) +static void i82801ex_pirq_init(struct device *dev) { config_t *config; @@ -214,7 +214,7 @@ static void i82801ex_pirq_init(device_t dev) } -static void i82801ex_gpio_init(device_t dev) +static void i82801ex_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -319,7 +319,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801ex_lpc_read_resources(device_t dev) +static void i82801ex_lpc_read_resources(struct device *dev) { struct resource *res; @@ -351,7 +351,7 @@ static void i82801ex_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void i82801ex_lpc_enable_resources(device_t dev) +static void i82801ex_lpc_enable_resources(struct device *dev) { /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3b6b71a..021884d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -90,9 +90,9 @@ static void i82801gx_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801gx_pirq_init(device_t dev) +static void i82801gx_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -132,7 +132,7 @@ static void i82801gx_pirq_init(device_t dev) } } -static void i82801gx_gpi_routing(device_t dev) +static void i82801gx_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -161,7 +161,7 @@ static void i82801gx_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void i82801gx_power_options(device_t dev) +static void i82801gx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -265,7 +265,7 @@ static void i82801gx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void i82801gx_configure_cstates(device_t dev) +static void i82801gx_configure_cstates(struct device *dev) { u8 reg8; @@ -457,7 +457,7 @@ static void lpc_init(struct device *dev) void acpi_fill_fadt(acpi_fadt_t * fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -575,7 +575,7 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) } } -static void i82801gx_lpc_read_resources(device_t dev) +static void i82801gx_lpc_read_resources(struct device *dev) { struct resource *res; @@ -601,7 +601,7 @@ static void i82801gx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index ea29986..e0794d6 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -188,7 +188,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, reg32); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 664088c..b4ded0f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -92,9 +92,9 @@ static void i82801ix_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801ix_pirq_init(device_t dev) +static void i82801ix_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -134,7 +134,7 @@ static void i82801ix_pirq_init(device_t dev) } } -static void i82801ix_gpi_routing(device_t dev) +static void i82801ix_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -163,7 +163,7 @@ static void i82801ix_gpi_routing(device_t dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } -static void i82801ix_power_options(device_t dev) +static void i82801ix_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -295,7 +295,7 @@ static void i82801ix_power_options(device_t dev) outl(reg32, pmbase + 0x10); } -static void i82801ix_configure_cstates(device_t dev) +static void i82801ix_configure_cstates(struct device *dev) { u8 reg8; @@ -471,7 +471,7 @@ static void lpc_init(struct device *dev) #endif } -static void i82801ix_lpc_read_resources(device_t dev) +static void i82801ix_lpc_read_resources(struct device *dev) { /* * I/O Resources @@ -527,7 +527,7 @@ static void i82801ix_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 10c8a2b..0fcf7bd 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -141,7 +141,7 @@ static void sata_program_indexed(struct device *const dev, const int is_mobile) pci_write_config32(dev, D31F2_SDAT, reg32); } -static void sata_init(struct device *const dev) +static void sata_init(struct device *dev) { u16 reg16; @@ -212,7 +212,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg); if (is_mobile && config->sata_traffic_monitor) { - const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct device *lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); @@ -228,7 +228,7 @@ static void sata_init(struct device *const dev) sata_program_indexed(dev, is_mobile); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ const config_t *const config = dev->chip_info; @@ -255,7 +255,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a833a3d..31b8389 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -400,7 +400,7 @@ static void enable_hpet(void) write32(0xfed00010, read32(0xfed00010) | 1); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -578,7 +578,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -639,13 +639,13 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -654,7 +654,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 99920f5..0a5b20f 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -430,7 +430,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -497,7 +497,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -527,7 +527,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -574,14 +574,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -616,7 +616,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 5f3c4d3..cee66c5 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -212,7 +212,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -237,7 +237,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a202424..6adc8a5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -107,9 +107,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -149,7 +149,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -178,7 +178,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16; @@ -416,7 +416,7 @@ static void enable_hpet(void) reg32 = RCBA32(HPTC); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ u32 reg32; @@ -441,7 +441,7 @@ static void enable_clock_gating(device_t dev) RCBA32_OR(0x38c0, 0x7); // SPI Dynamic } -static void enable_lp_clock_gating(device_t dev) +static void enable_lp_clock_gating(struct device *dev) { /* LynxPoint LP */ u32 reg32; @@ -591,7 +591,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -653,7 +653,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -666,7 +666,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -679,7 +679,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -704,7 +704,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; @@ -723,7 +723,7 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -732,7 +732,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 43a99c8..0812fe5 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -305,7 +305,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x300, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -326,7 +326,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index 7d209b1..beaf090 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -76,9 +76,9 @@ typedef struct southbridge_intel_sch_config config_t; #define PIRQG 0x0B #define PIRQH 0x0C -static void sch_pirq_init(device_t dev) +static void sch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -151,7 +151,7 @@ static void lpc_init(struct device *dev) sch_fixups(dev); } -static void sch_lpc_read_resources(device_t dev) +static void sch_lpc_read_resources(struct device *dev) { struct resource *res; @@ -177,7 +177,7 @@ static void sch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..d62075f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device *dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device *dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device *dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device *dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..a2a3b22 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device *dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device *dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device *dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0e11c6f..55a5e43 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -56,7 +56,7 @@ #undef SLAVE_INIT -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device *dev) { uint8_t byte; uint32_t ioapic_base; @@ -71,13 +71,13 @@ static void lpc_common_init(device_t dev) } #ifdef SLAVE_INIT -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); } #endif -static void lpc_usb_legacy_init(device_t dev) +static void lpc_usb_legacy_init(struct device *dev) { uint16_t acpi_base; @@ -87,7 +87,7 @@ static void lpc_usb_legacy_init(device_t dev) outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba); } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { uint8_t byte; uint8_t byte_old; @@ -156,7 +156,7 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "LPC_INIT <--------\n"); } -static void sis966_lpc_read_resources(device_t dev) +static void sis966_lpc_read_resources(struct device *dev) { struct resource *res; @@ -187,7 +187,7 @@ static void sis966_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void sis966_lpc_enable_childrens_resources(device_t dev) +static void sis966_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg, reg_var[4]; @@ -197,7 +197,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -238,13 +238,13 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) } -static void sis966_lpc_enable_resources(device_t dev) +static void sis966_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sis966_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 3f8c28f..1f942aa 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -171,7 +171,7 @@ for (i=0;i<10;i++){ } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c index a0aec65..8c500b9 100644 --- a/src/southbridge/via/vt8231/early_serial.c +++ b/src/southbridge/via/vt8231/early_serial.c @@ -33,7 +33,7 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) static void enable_vt8231_serial(void) { uint8_t c; - device_t dev; + pnp_devfn_t dev; post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c index c6b74fd..862b1ad 100644 --- a/src/southbridge/via/vt8231/lpc.c +++ b/src/southbridge/via/vt8231/lpc.c @@ -124,7 +124,7 @@ static void vt8231_init(struct device *dev) cmos_init(0); } -static void vt8231_read_resources(device_t dev) +static void vt8231_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c index 2c78481..396b647 100644 --- a/src/southbridge/via/vt8235/lpc.c +++ b/src/southbridge/via/vt8235/lpc.c @@ -104,7 +104,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { // Set gen config 0 pci_write_config8(dev, 0x80, 0x20); @@ -214,7 +214,7 @@ static void vt8235_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vt8235_read_resources(device_t dev) +static void vt8235_read_resources(struct device *dev) { struct resource *res; @@ -232,7 +232,7 @@ static void vt8235_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vt8235_set_resources(device_t dev) +static void vt8235_set_resources(struct device *dev) { //struct resource *resource; //resource = find_resource(dev,1); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 9e8f6f6..70b6120 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -66,7 +66,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT - device_t pdev; + struct device *pdev; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -148,7 +148,7 @@ static void pci_routing_fixup(struct device *dev) * This avoids having to handle any System Management Interrupts (SMIs). */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; struct southbridge_via_vt8237r_config *cfg; @@ -568,7 +568,7 @@ static void vt8237_common_init(struct device *dev) cmos_init(0); } -static void vt8237r_read_resources(device_t dev) +static void vt8237r_read_resources(struct device *dev) { struct resource *res; @@ -640,7 +640,7 @@ static void southbridge_init_common(struct device *dev) } -static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0x70, vendor); pci_write_config16(dev, 0x72, device); diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c index 606c33e..0246d54 100644 --- a/src/southbridge/via/vt8237r/sata.c +++ b/src/southbridge/via/vt8237r/sata.c @@ -96,7 +96,7 @@ static void sata_ii_init(struct device *dev) } -static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0xd4, vendor); pci_write_config16(dev, 0xd6, device); diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 55742a7..9cdf943 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -48,10 +48,10 @@ static void vt82c686_sio_write(uint8_t index, uint8_t value) * @param dev TODO * @param iobase TODO */ -static void vt82c686_enable_serial(device_t dev, unsigned iobase) +static void vt82c686_enable_serial(pnp_devfn_t dev, unsigned iobase) { uint8_t reg; - device_t sbdev; + pnp_devfn_t sbdev; /* TODO: Use info from 'dev' and 'iobase'. */ /* TODO: Only enable one serial port (depending on config) or both? */

1 0

Patch set updated for coreboot: 3438aeb northbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7166 -gerrit commit 3438aeb36b5c7359e347114fdaa37ac23bd1ed12 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 22 22:03:49 2014 +1100 northbridge: Don't hide pointers behind typedefs Change-Id: Ib2c373695820e71a6e41e4f173d2615ee5838f28 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 10 +-- src/northbridge/amd/agesa/00730F01/northbridge.c | 70 +++++++++---------- src/northbridge/amd/agesa/family10/northbridge.c | 80 +++++++++++----------- src/northbridge/amd/agesa/family10/reset_test.h | 4 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 50 +++++++------- src/northbridge/amd/agesa/family12/northbridge.h | 2 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 54 +++++++-------- src/northbridge/amd/agesa/family14/northbridge.h | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 72 +++++++++---------- src/northbridge/amd/agesa/family15/northbridge.h | 2 +- src/northbridge/amd/agesa/family15tn/iommu.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 66 +++++++++--------- src/northbridge/amd/agesa/family16kb/northbridge.c | 70 +++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 73 ++++++++++---------- src/northbridge/amd/amdk8/northbridge.c | 64 ++++++++--------- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 12 ++-- src/northbridge/amd/gx2/northbridge.c | 12 ++-- src/northbridge/amd/lx/northbridge.c | 12 ++-- src/northbridge/dmp/vortex86ex/northbridge.c | 6 +- src/northbridge/intel/e7501/northbridge.c | 6 +- src/northbridge/intel/e7505/northbridge.c | 8 +-- src/northbridge/intel/e7520/northbridge.c | 16 ++--- src/northbridge/intel/e7525/northbridge.c | 16 ++--- src/northbridge/intel/fsp_rangeley/northbridge.c | 20 +++--- .../intel/fsp_sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/gm45/northbridge.c | 12 ++-- src/northbridge/intel/haswell/northbridge.c | 30 ++++---- src/northbridge/intel/i3100/northbridge.c | 18 ++--- src/northbridge/intel/i440bx/northbridge.c | 8 +-- src/northbridge/intel/i440lx/northbridge.c | 8 +-- src/northbridge/intel/i5000/northbridge.c | 14 ++-- src/northbridge/intel/i82810/northbridge.c | 8 +-- src/northbridge/intel/i82830/northbridge.c | 8 +-- src/northbridge/intel/i855/northbridge.c | 8 +-- src/northbridge/intel/i945/northbridge.c | 14 ++-- src/northbridge/intel/nehalem/northbridge.c | 14 ++-- src/northbridge/intel/sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/sch/northbridge.c | 14 ++-- src/northbridge/rdc/r8610/northbridge.c | 6 +- src/northbridge/via/cn400/northbridge.c | 16 ++--- src/northbridge/via/cn700/northbridge.c | 10 +-- src/northbridge/via/cx700/northbridge.c | 8 +-- src/northbridge/via/vt8601/northbridge.c | 8 +-- src/northbridge/via/vt8623/northbridge.c | 14 ++-- src/northbridge/via/vx800/northbridge.c | 8 +-- src/northbridge/via/vx900/northbridge.c | 14 ++-- src/northbridge/via/vx900/sata.c | 16 ++--- 50 files changed, 523 insertions(+), 522 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 2714052..b1967de 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -46,7 +46,7 @@ static void qemu_reserve_ports(struct device *dev, unsigned int idx, IORESOURCE_ASSIGNED; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -213,7 +213,7 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * return len; } -static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int qemu_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = qemu_get_smbios_data16(*handle, current); @@ -234,15 +234,15 @@ static struct device_operations pci_domain_ops = { #endif }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +static unsigned int cpu_bus_scan(struct device * bus, unsigned int max) { int max_cpus = fw_cfg_max_cpus(); - device_t cpu; + struct device * cpu; int i; if (max_cpus < 0) diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c index 03433af..7769b03 100644 --- a/src/northbridge/amd/agesa/00730F01/northbridge.c +++ b/src/northbridge/amd/agesa/00730F01/northbridge.c @@ -58,15 +58,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -287,7 +287,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -329,7 +329,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -342,7 +342,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -402,7 +402,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -449,11 +449,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -499,7 +499,7 @@ struct chip_operations northbridge_amd_agesa_00730F01_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -512,7 +512,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -559,7 +559,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -663,7 +663,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -840,13 +840,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -882,12 +882,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -983,7 +983,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1068,7 +1068,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1076,12 +1076,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1092,7 +1092,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b1f0890..543966e 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -52,10 +52,10 @@ typedef struct dram_base_mask { struct amdfam10_sysconf_t sysconf; -static device_t __f0_dev[NODE_NUMS]; -static device_t __f1_dev[NODE_NUMS]; -static device_t __f2_dev[NODE_NUMS]; -static device_t __f4_dev[NODE_NUMS]; +static struct device *__f0_dev[NODE_NUMS]; +static struct device *__f1_dev[NODE_NUMS]; +static struct device *__f2_dev[NODE_NUMS]; +static struct device *__f4_dev[NODE_NUMS]; static unsigned fx_devs = 0; #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 @@ -64,7 +64,7 @@ static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; @@ -96,7 +96,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -149,7 +149,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, #endif #if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, +static u32 check_segn(struct device *dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -249,7 +249,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, sysconf.mmio_addr_num = index+1; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -318,7 +318,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first @@ -357,7 +357,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi #endif } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -407,7 +407,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -415,7 +415,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 unsigned busn; @@ -442,7 +442,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -450,7 +450,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -470,7 +470,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -505,7 +505,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -541,7 +541,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -600,7 +600,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -612,7 +612,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -667,7 +667,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -676,7 +676,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -696,7 +696,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -723,12 +723,12 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; - device_t io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0xff; nodeid = amdfam10_nodeid(dev); @@ -770,7 +770,7 @@ struct chip_operations northbridge_amd_agesa_family10_ops = { }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device *dev) { unsigned reg; @@ -783,7 +783,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -829,7 +829,7 @@ static void amdfam10_domain_read_resources(device_t dev) #endif } -static void amdfam10_domain_enable_resources(device_t dev) +static void amdfam10_domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); @@ -904,7 +904,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1071,7 +1071,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1102,7 +1102,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1132,7 +1132,7 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1150,7 +1150,7 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1186,12 +1186,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int nodes; @@ -1282,7 +1282,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1363,7 +1363,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1371,12 +1371,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1387,7 +1387,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 8c8d9a0..a38cde8 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -33,7 +33,7 @@ static inline u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -42,7 +42,7 @@ static inline u32 warm_reset_detect(u8 nodeid) static inline void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 00ff641..aa7eb69 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 94de010..ca357ef 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,14 +41,14 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -89,7 +89,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -98,7 +98,7 @@ static void f1_write_config32(unsigned reg, u32 value) } -static u32 amdfam12_nodeid(device_t dev) +static u32 amdfam12_nodeid(struct device *dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -108,7 +108,7 @@ static u32 amdfam12_nodeid(device_t dev) #include "amdfam12_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -137,7 +137,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -158,7 +158,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam12_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 result, reg; @@ -182,7 +182,7 @@ static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam12_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -218,7 +218,7 @@ static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam12_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -343,7 +343,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void read_resources(device_t dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -412,10 +412,10 @@ static void set_resource(device_t dev, struct resource *resource, #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device *vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -447,7 +447,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void set_resources(device_t dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -503,7 +503,7 @@ static void setup_uma_memory(void) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -518,7 +518,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -581,7 +581,7 @@ static void domain_read_resources(device_t dev) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -765,7 +765,7 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -783,7 +783,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -797,7 +797,7 @@ static void cpu_bus_read_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -809,7 +809,7 @@ static void cpu_bus_set_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h index 4edb525..c3fc171 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.h +++ b/src/northbridge/amd/agesa/family12/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */ diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index c255213..b5fd94d 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 57502e9..d7a352b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -44,13 +44,13 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs = 0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -88,7 +88,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -96,14 +96,14 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam14_nodeid(device_t dev) +static u32 amdfam14_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #include "amdfam14_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -119,7 +119,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -127,7 +127,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -146,7 +146,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, +static struct resource *amdfam14_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -173,7 +173,7 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, return resource; } -static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, +static struct resource *amdfam14_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -208,7 +208,7 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, return resource; } -static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam14_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -409,10 +409,10 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) } #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device *vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -444,7 +444,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -477,7 +477,7 @@ static void nb_set_resources(device_t dev) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -492,7 +492,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -566,7 +566,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -757,7 +757,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { #if CONFIG_AMD_SB_CIMX if (!acpi_is_wakeup_s3()) { @@ -779,18 +779,18 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus = dev->link_list; - device_t cpu; + struct device *cpu; int apic_id, cores_found; /* There is only one node for fam14, but there may be multiple cores. */ @@ -809,7 +809,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h index 474e74c..6046137 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.h +++ b/src/northbridge/amd/agesa/family14/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */ diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index ce9785e..2d69939 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -57,16 +57,16 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -288,7 +288,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -412,7 +412,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -443,7 +443,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -476,11 +476,11 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { @@ -526,7 +526,7 @@ struct chip_operations northbridge_amd_agesa_family15_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -588,7 +588,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); @@ -681,7 +681,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -860,13 +860,13 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -902,12 +902,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -987,7 +987,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1079,7 +1079,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1087,16 +1087,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { } @@ -1136,7 +1136,7 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { }; /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(struct device *dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); return max; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h index 99fdcae..3a90964 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.h +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -22,6 +22,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max); +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max); #endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 3765f20..396ba02 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <lib.h> -static void iommu_read_resources(device_t dev) +static void iommu_read_resources(struct device *dev) { struct resource *res; @@ -39,7 +39,7 @@ static void iommu_read_resources(device_t dev) res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(device_t dev) +static void iommu_set_resources(struct device *dev) { struct resource *res; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d77897d..1fccec1 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -354,7 +354,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -405,7 +405,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -414,7 +414,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -434,7 +434,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -494,7 +494,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -507,7 +507,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -554,7 +554,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -647,7 +647,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -824,13 +824,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -866,12 +866,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -951,7 +951,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1041,7 +1041,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1049,16 +1049,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d47a00d..f91bbbb 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -341,7 +341,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -392,7 +392,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -401,7 +401,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -421,7 +421,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -448,11 +448,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -498,7 +498,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -511,7 +511,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -558,7 +558,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -653,7 +653,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -830,13 +830,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -872,12 +872,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -957,7 +957,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1047,7 +1047,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1055,12 +1055,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1071,7 +1071,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 76ffc5d..779a0d6 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -53,13 +53,13 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if((CONFIG_CDB + nodeid) < 32) { @@ -102,7 +102,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 unsigned busn; @@ -139,7 +139,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdfam10_scan_chain(struct device *dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -152,7 +152,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l u32 max_bus; u32 min_bus; u32 is_sublink1 = (link_num>3); - device_t devx; + struct device *devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -284,7 +284,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l return max; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -327,7 +327,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -335,7 +335,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -355,7 +355,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -389,7 +389,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -425,7 +425,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -484,7 +484,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -496,7 +496,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -551,7 +551,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -580,7 +580,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -629,7 +629,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { .enable_dev = 0, }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device *dev) { unsigned reg; @@ -642,7 +642,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -767,7 +767,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device *dev; struct dram_base_mask_t d; u32 sel_m; u32 sel_hi_en; @@ -871,7 +871,7 @@ static void setup_uma_memory(void) #endif } -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1087,7 +1087,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1118,7 +1118,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1146,7 +1146,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device *dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1188,7 +1188,7 @@ static void sysconf_init(device_t dev) // first node #endif } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1224,12 +1224,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device *pci_domain; #endif int i,j; int nodes; @@ -1324,7 +1324,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1394,7 +1394,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } #endif - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1402,7 +1402,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX @@ -1411,11 +1411,12 @@ static void cpu_bus_init(device_t dev) #endif } -static void cpu_bus_read_resources(device_t dev) + +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a91a499..e14f706 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -40,8 +40,8 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 -static device_t __f0_dev[MAX_FX_DEVS]; -static device_t __f1_dev[MAX_FX_DEVS]; +static struct device *__f0_dev[MAX_FX_DEVS]; +static struct device *__f1_dev[MAX_FX_DEVS]; static unsigned fx_devs=0; static void get_fx_devs(void) @@ -71,7 +71,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -79,12 +79,12 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdk8_nodeid(device_t dev) +static u32 amdk8_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdk8_scan_chain(struct device *dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link return max; } -static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static unsigned amdk8_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -271,7 +271,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -279,7 +279,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -299,7 +299,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, +static unsigned amdk8_find_reg(struct device *dev, unsigned nodeid, unsigned link, unsigned min, unsigned max) { unsigned resource; @@ -327,17 +327,17 @@ static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, return resource; } -static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8); } -static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_mempair(struct device *dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8); } -static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -376,9 +376,9 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) } } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid); +static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid); -static void amdk8_read_resources(device_t dev) +static void amdk8_read_resources(struct device *dev) { unsigned nodeid; struct bus *link; @@ -391,7 +391,7 @@ static void amdk8_read_resources(device_t dev) amdk8_create_vga_resource(dev, nodeid); } -static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device *dev, struct resource *resource, unsigned nodeid) { struct bus *link; resource_t rbase, rend; @@ -488,7 +488,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned report_resource_stored(dev, resource, buf); } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid) { struct resource *resource; struct bus *link; @@ -498,7 +498,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -529,7 +529,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) IORESOURCE_ASSIGNED; } -static void amdk8_set_resources(device_t dev) +static void amdk8_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -638,7 +638,7 @@ struct chip_operations northbridge_amd_amdk8_ops = { .enable_dev = 0, }; -static void amdk8_domain_read_resources(device_t dev) +static void amdk8_domain_read_resources(struct device *dev) { unsigned reg; @@ -651,7 +651,7 @@ static void amdk8_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device *reg_dev; nodeid = limit & 7; reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; @@ -765,7 +765,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device *dev; u32 base, limit; u32 hoist; u32 hole_sizek; @@ -810,7 +810,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; u32 carry_over; - device_t dev; + struct device *dev; u32 base, limit; u32 basek; u32 hoist; @@ -904,7 +904,7 @@ static void setup_uma_memory(void) #endif } -static void amdk8_domain_set_resources(device_t dev) +static void amdk8_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1121,7 +1121,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static u32 amdk8_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1136,7 +1136,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1164,7 +1164,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1200,10 +1200,10 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device *dev_mc; int bsp_apicid; int i,j; unsigned nb_cfg_54; @@ -1258,7 +1258,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < sysconf.nodes; i++) { - device_t cpu_dev; + struct device *cpu_dev; /* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1267,7 +1267,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * ensure all of the cpu's pci devices are found. */ int local_j; - device_t dev_f0; + struct device *dev_f0; for(local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); @@ -1334,7 +1334,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1342,7 +1342,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { #if CONFIG_WAIT_BEFORE_CPUS_INIT cpus_ready_for_init(); diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index fa23344..937095b 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -66,7 +66,7 @@ void nb_Late_Post_Init(void) LibSystemApiCall(AmdLatePostInit, &gConfig); } -static void rd890_enable(device_t dev) +static void rd890_enable(struct device *dev) { u32 address = 0; u32 devfn; diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index bcb6e56..25add9f 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -14,7 +14,7 @@ /* */ -static void optimize_xbus(device_t dev) +static void optimize_xbus(struct device *dev) { /* Optimise X-Bus performance */ pci_write_config8(dev, 0x40, 0x1e); @@ -31,13 +31,13 @@ static void optimize_xbus(device_t dev) * this region? **/ -static void enable_shadow(device_t dev) +static void enable_shadow(struct device *dev) { write32(GX_BASE+BC_XMAP_2, 0x77777777); write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); @@ -65,9 +65,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -126,7 +126,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..50f72ce 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -213,12 +213,12 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device *dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); @@ -273,11 +273,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { int idx; u32 tomk; - device_t mc_dev; + struct device *mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -296,7 +296,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -318,7 +318,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..f7971c3 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -291,11 +291,11 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device *dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { //msr_t msr; @@ -372,11 +372,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { int idx; u32 tomk; - device_t mc_dev; + struct device *mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -395,7 +395,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -422,7 +422,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index fcebed8..03c52cd 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -30,7 +30,7 @@ #define SPI_BASE 0xfc00 -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. @@ -75,9 +75,9 @@ static void set_cmos_memory_size(unsigned long sizek) * don't touch it. */ } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 64bf840..e3bdb42 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -20,9 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -110,7 +110,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023..417b5b7 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -16,9 +16,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -97,7 +97,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -117,7 +117,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 6e0379e..143fd7c 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7520_domain_scan_bus(device_t dev, u32 max) +static u32 e7520_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -122,7 +122,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -134,7 +134,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -145,7 +145,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -170,7 +170,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x3590, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -184,7 +184,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 68fdc74..b011fc9 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -106,7 +106,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7525_domain_scan_bus(device_t dev, u32 max) +static u32 e7525_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -121,7 +121,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -133,7 +133,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -144,7 +144,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -169,7 +169,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x359e, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -183,7 +183,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 07ce21f..47b98ba 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -112,7 +112,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -123,7 +123,7 @@ static void finalize_dev (device_t dev) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -168,7 +168,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -177,7 +177,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { /* * Assign memory resources for PCI devices @@ -187,13 +187,13 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -208,7 +208,7 @@ static void northbridge_init(struct device *dev) { } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device *dev) { } @@ -258,7 +258,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -271,7 +271,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index da27b25..01d60fb 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -68,7 +68,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -121,7 +121,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -261,7 +261,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -283,7 +283,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -297,7 +297,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -322,7 +322,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -375,7 +375,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -388,7 +388,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 716ee62..9f2d409 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -46,7 +46,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; @@ -73,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) return 0; } -static void mch_domain_read_resources(device_t dev) +static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0, usable_tomk; @@ -170,7 +170,7 @@ static void mch_domain_read_resources(device_t dev) } } -static void mch_domain_set_resources(device_t dev) +static void mch_domain_set_resources(struct device *dev) { struct resource *resource; int i; @@ -185,7 +185,7 @@ static void mch_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mch_domain_init(device_t dev) +static void mch_domain_init(struct device *dev) { u32 reg32; @@ -207,7 +207,7 @@ static struct device_operations pci_domain_ops = { }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -221,7 +221,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..35ceb68 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,7 +39,7 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -69,7 +69,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +106,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -126,7 +126,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -146,7 +146,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -203,7 +203,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -291,7 +291,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -383,7 +383,7 @@ static void mc_add_dram_resources(device_t dev) #endif } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -395,7 +395,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -433,7 +433,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; @@ -480,7 +480,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { bsp_init_and_start_aps(dev->link_list); } @@ -493,7 +493,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 2cf5ae1..ee448a7 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -39,9 +39,9 @@ static u32 max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; u32 pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 i3100_domain_scan_bus(device_t dev, u32 max) +static u32 i3100_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -159,7 +159,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -170,7 +170,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -180,7 +180,7 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u64 mmcfg; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = PCI_DEVICE_ID_INTEL_3100_MC, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -233,7 +233,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 12ff37b..bbda583 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -12,7 +12,7 @@ #include "northbridge.h" #include "i440bx.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -32,9 +32,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -static void i440bx_domain_set_resources(device_t dev) +static void i440bx_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -81,7 +81,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 60e62c1..5c96eca 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -38,7 +38,7 @@ * Maciej */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -58,9 +58,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -static void i440lx_domain_set_resources(device_t dev) +static void i440lx_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index a9b3560..49ceff8 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <cbmem.h> -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -40,15 +40,15 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0; - device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); - device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + struct device *dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + struct device *dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); pci_dev_read_resources(dev); @@ -139,7 +139,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = nb_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -151,7 +151,7 @@ static struct device_operations cpu_bus_ops = { .init = cpu_bus_init, .scan_bus = 0, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -165,7 +165,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index ce0dc20..fba09fc 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -32,7 +32,7 @@ #include "northbridge.h" #include "i82810.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -69,9 +69,9 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -136,7 +136,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4898aaf..5bb5ac3 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -30,7 +30,7 @@ #include <string.h> #include "i82830.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -50,9 +50,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -103,7 +103,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index fce7d57..4daacfe 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -32,7 +32,7 @@ #include <cpu/x86/cache.h> #include <cpu/cpu.h> -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -52,9 +52,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); @@ -119,7 +119,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 91c5c82..2baf935 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -81,7 +81,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { uint32_t pci_tolm; uint8_t tolud, reg8; @@ -185,7 +185,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -207,7 +207,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -221,7 +221,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,7 +274,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x27a0, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -287,7 +287,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..d9c6723 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -96,7 +96,7 @@ static void add_fixed_resources(struct device *dev, int index) #endif } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { uint32_t tseg_base; uint64_t TOUUD; @@ -165,13 +165,13 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { /* And call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -283,7 +283,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -324,7 +324,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -337,7 +337,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..4ed1db6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -66,7 +66,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -132,7 +132,7 @@ static void add_fixed_resources(struct device *dev, int index) bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -266,7 +266,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -288,7 +288,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -302,7 +302,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -412,7 +412,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -471,7 +471,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -484,7 +484,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..7ecdbc4 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { u32 pci_tolm; u8 reg8; @@ -200,7 +200,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -226,7 +226,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -239,7 +239,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -292,7 +292,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x8100, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -305,7 +305,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index d69c4f6..f85756c 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -33,7 +33,7 @@ static unsigned long get_memory_size(void) { - device_t nb_dev; + struct device *nb_dev; u8 size; nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, @@ -42,7 +42,7 @@ static unsigned long get_memory_size(void) return (2 * 1024) << size; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device *dev) { u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; @@ -92,7 +92,7 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current) return len; } -static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int rdc_get_smbios_data(struct device *dev, int *handle, unsigned long *current) { int len; len = rdc_get_smbios_data16(*handle, current); diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index b797179..1ecd2cf 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn400.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device *dev) { - device_t vlink_dev; + struct device *vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; int i, j; @@ -140,7 +140,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; -static void cn400_domain_read_resources(device_t dev) +static void cn400_domain_read_resources(struct device *dev) { struct resource *resource; @@ -162,7 +162,7 @@ static void cn400_domain_read_resources(device_t dev) } #ifdef UNUSED_CODE -static void ram_reservation(device_t dev, unsigned long index, +static void ram_reservation(struct device *dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +177,9 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif -static void cn400_domain_set_resources(device_t dev) +static void cn400_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +219,7 @@ static void cn400_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); } -static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device *dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__); @@ -236,7 +236,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 506bdd1..6c21b72 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn700.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device *dev) { - device_t vlink_dev; + struct device *vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg; @@ -97,11 +97,11 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device *mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -156,7 +156,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index cc9dabd..3dc5bc4 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -31,9 +31,9 @@ #include <cbmem.h> #include <arch/acpi.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; @@ -82,7 +82,7 @@ static void pci_domain_set_resources(device_t dev) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u64 mmcfg; dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 @@ -112,7 +112,7 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = acpi_write_hpet, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 1887491..6f2ad3d 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -17,7 +17,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -44,12 +44,12 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -102,7 +102,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 546db4c..01f4432 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -19,9 +19,9 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device *dev) { - device_t fb_dev; + struct device *fb_dev; unsigned long fb; unsigned char c; @@ -58,7 +58,7 @@ static void northbridge_init(device_t dev) } } -static void nullfunc(device_t dev) +static void nullfunc(struct device *dev) { /* Nothing to do */ } @@ -76,7 +76,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8623, }; -static void agp_init(device_t dev) +static void agp_init(struct device *dev) { printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n"); @@ -103,10 +103,10 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); @@ -162,7 +162,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index fad0c2f..52da40c 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -37,7 +37,7 @@ /* !!FIXME!! I declared this to fix the build. */ u8 acpi_sleep_type = 0; -static void memctrl_init(device_t dev) +static void memctrl_init(struct device *dev) { /* set VGA in uma_ram_setting.c, not in this function. @@ -71,13 +71,13 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device *mc_dev; u32 pci_tolm; u8 reg; @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index f9c225d..fe3e3ba 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -60,7 +60,7 @@ uint64_t get_uma_memory_base(void) return uma_memory_base; } -static u64 vx900_get_top_of_ram(device_t mcu) +static u64 vx900_get_top_of_ram(struct device *mcu) { u16 reg16; /* The last valid DRAM address is computed by the MCU @@ -97,7 +97,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) * * @return The new top of memory. */ -static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) +static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm) { size_t i; u8 reg8, start8, end8, start, end; @@ -216,7 +216,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) return newtor; } -static void vx900_set_resources(device_t dev) +static void vx900_set_resources(struct device *dev) { u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk; @@ -228,7 +228,7 @@ static void vx900_set_resources(device_t dev) "========================================\n"); int idx = 10; - const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); if (!mcu) { @@ -286,7 +286,7 @@ static void vx900_set_resources(device_t dev) assign_resources(dev->link_list); } -static void vx900_read_resources(device_t dev) +static void vx900_read_resources(struct device *dev) { /* Our fixed resources start at 0 */ int idx = 0; @@ -317,7 +317,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -330,7 +330,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 63295e5..4a7ae6d 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -74,7 +74,7 @@ static void vx900_print_sata_errors(u32 flags) print_debug("\tUNRECOGNIZED FIS type\n"); } -static void vx900_dbg_sata_errors(device_t dev) +static void vx900_dbg_sata_errors(struct device *dev) { /* Port 0 */ if (pci_read_config8(dev, 0xa0) & (1 << 0)) { @@ -103,7 +103,7 @@ static sata_phy_config reference_ephy = { 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static u32 sata_phy_read32(device_t dev, u8 index) +static u32 sata_phy_read32(struct device *dev, u8 index) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -115,7 +115,7 @@ static u32 sata_phy_read32(device_t dev, u8 index) return pci_read_config32(dev, 0x64); } -static void sata_phy_write32(device_t dev, u8 index, u32 val) +static void sata_phy_write32(struct device *dev, u8 index, u32 val) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -127,7 +127,7 @@ static void sata_phy_write32(device_t dev, u8 index, u32 val) pci_write_config32(dev, 0x64, val); } -static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -136,7 +136,7 @@ static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) } } -static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -181,7 +181,7 @@ static void vx900_sata_dump_phy_config(sata_phy_config cfg) * Our only option is to operate in IDE mode. We choose native IDE so that we * can freely assign an IRQ, and are not forced to use IRQ14 */ -static void vx900_native_ide_mode(device_t dev) +static void vx900_native_ide_mode(struct device *dev) { /* Disable subclass write protect */ pci_mod_config8(dev, 0x45, 1 << 7, 0); @@ -193,7 +193,7 @@ static void vx900_native_ide_mode(device_t dev) pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); } -static void vx900_sata_init(device_t dev) +static void vx900_sata_init(struct device *dev) { /* Enable SATA primary channel IO access */ pci_mod_config8(dev, 0x40, 0, 1 << 1); @@ -261,7 +261,7 @@ static void vx900_sata_init(device_t dev) vx900_dbg_sata_errors(dev); } -static void vx900_sata_read_resources(device_t dev) +static void vx900_sata_read_resources(struct device *dev) { pci_dev_read_resources(dev); }

1 0

Patch set updated for coreboot: c257a83 soc: Don't hide pointers behind typedefs
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7277 -gerrit commit c257a8387e47f0abdde4c97c89a55363a55557c8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 23:00:45 2014 +1100 soc: Don't hide pointers behind typedefs Change-Id: I05bb3b09cd1059cf43905a310f5c1ba04ed32336 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/baytrail/chip.c | 6 ++--- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 4 ++-- src/soc/intel/baytrail/emmc.c | 2 +- src/soc/intel/baytrail/gfx.c | 14 +++++------ src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/lpe.c | 12 +++++----- src/soc/intel/baytrail/lpss.c | 10 ++++---- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 14 +++++------ src/soc/intel/baytrail/pmutil.c | 8 +++---- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/sata.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/sd.c | 2 +- src/soc/intel/baytrail/smihandler.c | 2 +- src/soc/intel/baytrail/southcluster.c | 24 +++++++++---------- src/soc/intel/baytrail/spi.c | 6 ++--- src/soc/intel/baytrail/xhci.c | 6 ++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/broadwell/me.h | 2 +- src/soc/intel/broadwell/broadwell/pch.h | 2 +- src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++-- src/soc/intel/broadwell/broadwell/xhci.h | 2 +- src/soc/intel/broadwell/chip.c | 6 ++--- src/soc/intel/broadwell/cpu.c | 6 ++--- src/soc/intel/broadwell/ehci.c | 2 +- src/soc/intel/broadwell/lpc.c | 18 +++++++-------- src/soc/intel/broadwell/me.c | 24 +++++++++---------- src/soc/intel/broadwell/pch.c | 6 ++--- src/soc/intel/broadwell/pcie.c | 32 +++++++++++++------------- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/smbus.c | 8 +++---- src/soc/intel/broadwell/smihandler.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 6 ++--- src/soc/intel/broadwell/spi.c | 2 +- src/soc/intel/broadwell/systemagent.c | 22 +++++++++--------- src/soc/intel/broadwell/xhci.c | 8 +++---- src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/fsp_baytrail/chip.c | 8 +++---- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +++---- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 2 +- src/soc/intel/fsp_baytrail/smihandler.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++----------- src/soc/intel/fsp_baytrail/spi.c | 6 ++--- src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/soc.c | 6 ++--- src/soc/samsung/exynos5250/cpu.c | 8 +++---- src/soc/samsung/exynos5420/cpu.c | 8 +++---- 55 files changed, 191 insertions(+), 191 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index a8b5fdc..4a7b536 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -26,16 +26,16 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); +void southcluster_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 7a5b9c2..a29bef2 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -26,7 +26,7 @@ #include <baytrail/ramstage.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -49,7 +49,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -77,7 +77,7 @@ struct chip_operations soc_intel_baytrail_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e8f95ae..a5106dd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -78,7 +78,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -121,7 +121,7 @@ void baytrail_init_cpus(device_t dev) restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..accfed2 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = { REG_SCRIPT_END }; -static void usb2_phy_init(device_t dev) +static void usb2_phy_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev) reg_script_run(usb2_phy_script); } -static void ehci_init(device_t dev) +static void ehci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..74bdb4b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; -static void emmc_init(device_t dev) +static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 9d4768f..a47152d 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -38,7 +38,7 @@ * Lock Power Context Base Register to point to a 24KB block * of memory in GSM. Power context save data is stored here. */ -static void gfx_lock_pcbase(device_t dev) +static void gfx_lock_pcbase(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, @@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } -static void gfx_pre_vbios_init(device_t dev) +static void gfx_pre_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) +static void gfx_pm_init(struct device *dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); gfx_run_script(dev, gfx_init_script); @@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev) gfx_lock_pcbase(dev); } -static void gfx_post_vbios_init(device_t dev) +static void gfx_post_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void gfx_panel_setup(device_t dev) +static void gfx_panel_setup(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { @@ -340,7 +340,7 @@ static void gfx_panel_setup(device_t dev) } } -static void gfx_init(device_t dev) +static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..5733b95 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = { 0x20671f58, }; -static void hda_init(device_t dev) +static void hda_init(struct device *dev) { struct resource *res; int codec_mask; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..b6fb7c2 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -45,7 +45,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) { struct resource *res; @@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index) *field = res->base; } -static void lpe_enable_acpi_mode(device_t dev) +static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev) reg_script_run_on_dev(dev, ops); } -static void setup_codec_clock(device_t dev) +static void setup_codec_clock(struct device *dev) { uint32_t reg; int clk_reg; @@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } -static void lpe_stash_firmware_info(device_t dev) +static void lpe_stash_firmware_info(struct device *dev) { struct resource *res; struct resource *mmio; @@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev) } } -static void lpe_init(device_t dev) +static void lpe_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -161,7 +161,7 @@ static void lpe_init(device_t dev) lpe_enable_acpi_mode(dev); } -static void lpe_read_resources(device_t dev) +static void lpe_read_resources(struct device *dev) { pci_dev_read_resources(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..c548370 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -33,7 +33,7 @@ #include "chip.h" -static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, @@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; @@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(device_t dev) +static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { @@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev) } } -static void lpss_init(device_t dev) +static void lpss_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; int iosf_reg, nvs_index; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b119e24..2d4f20b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 4498f43..e530498 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -34,12 +34,12 @@ static int pll_en_off; static uint32_t strpfusecfg; -static inline int root_port_offset(device_t dev) +static inline int root_port_offset(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn); } -static inline int is_first_port(device_t dev) +static inline int is_first_port(struct device *dev) { return root_port_offset(dev) == PCIE_PORT1_FUNC; } @@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void byt_pcie_init(struct device *dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), @@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = { REG_SCRIPT_END, }; -static void check_port_enabled(device_t dev) +static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; @@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev) } } -static void check_device_present(device_t dev) +static void check_device_present(struct device *dev) { /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -172,7 +172,7 @@ static void check_device_present(device_t dev) } } -static void byt_pcie_enable(device_t dev) +static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did) { uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..935253c 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline pci_devfn_t get_pcu_dev(void) { return pcu_dev; } @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..10f7ff2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -78,7 +78,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8c..3c69985 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -159,7 +159,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { config_t *config = dev->chip_info; u8 reg8; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..e2bd1dd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -87,7 +87,7 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..6068e61 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -34,7 +34,7 @@ #define CAP_OVERRIDE_HIGH 0xa4 # define USE_CAP_OVERRIDES (1 << 31) -static void sd_init(device_t dev) +static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 22b60c4..94e6d81 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 500a13d..d3d284d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -43,12 +43,12 @@ #include "chip.h" static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; @@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -154,7 +154,7 @@ static void sc_rtc_init(void) * or configuration. This is definitely a hack, but it helps the kernel * along. */ -static void com1_configure_resume(device_t dev) +static void com1_configure_resume(struct device *dev) { const uint16_t port = 0x3f8; @@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev) outb(3, port + UART8250_LCR); } -static void sc_init(device_t dev) +static void sc_init(struct device *dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; @@ -224,7 +224,7 @@ static void sc_init(device_t dev) */ /* Set bit in function disble register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -362,7 +362,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8677b61..112b878 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -290,13 +290,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is stage dependent typed */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..3f3ed91 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = { }; /* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) +static void xhci_reset_port_usb3(struct device *dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ @@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port) } /* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) +static void xhci_route_all(struct device *dev) { static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ @@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev) } } -static void xhci_init(device_t dev) +static void xhci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f4cac7b..3259308 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package) static int generate_C_state_entries(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index ddecaf8..f3021ee 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -465,7 +465,7 @@ typedef struct { } __attribute__ ((packed)) mbp_plat_time; typedef struct { - u32 device_type : 2; + u32 struct device *ype : 2; u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data; diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index e677215..c58b695 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -47,6 +47,6 @@ int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h index 685de14..d66e8cc 100644 --- a/src/soc/intel/broadwell/broadwell/ramstage.h +++ b/src/soc/intel/broadwell/broadwell/ramstage.h @@ -24,8 +24,8 @@ #include <chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(device_t dev); -void broadwell_pch_enable_dev(device_t dev); +void broadwell_init_cpus(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h index 3f4fb4e..a5536fc 100644 --- a/src/soc/intel/broadwell/broadwell/xhci.h +++ b/src/soc/intel/broadwell/broadwell/xhci.h @@ -55,7 +55,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 2a12820..ef19e8e 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -24,7 +24,7 @@ #include <broadwell/ramstage.h> #include <chip.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -43,7 +43,7 @@ static struct device_operations cpu_bus_ops = { .init = &broadwell_init_cpus, }; -static void broadwell_enable(device_t dev) +static void broadwell_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -65,7 +65,7 @@ struct chip_operations soc_intel_broadwell_ops = { .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 58f81fc..416fe3c 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -444,7 +444,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; msr_t msr; @@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void cpu_core_init(device_t cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void broadwell_init_cpus(device_t dev) +void broadwell_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; int num_threads; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index a59d3c8..30f4acd 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -28,7 +28,7 @@ #include <broadwell/ehci.h> #include <broadwell/pch.h> -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { u8 access_cntl; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 4b21326..270316c 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u16 reg16; const char *state; @@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev) RCBA32_OR(0x3a6c, 0x00000001); } -static void pch_cg_init(device_t dev) +static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; @@ -420,7 +420,7 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 15bcc34..19bc754 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); /* MMIO base address for MEI interface */ static u32 mei_base_address; -void intel_me_mbp_clear(device_t dev); +void intel_me_mbp_clear(struct device *dev); #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +static void intel_me_mbp_give_up(struct device *dev) { struct mei_csr csr; @@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev) * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +void intel_me_mbp_clear(struct device *dev) { int count; struct me_hfs2 hfs2; @@ -568,7 +568,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(void) { - device_t dev = PCH_DEV_ME; + struct device *dev = PCH_DEV_ME; struct me_hfs hfs; u32 reg32; @@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev) } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { config_t *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -829,7 +829,7 @@ static void intel_me_init(device_t dev) */ } -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ @@ -882,7 +882,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 82390a4..e681620 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id) #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev) } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c..08e4863 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -32,8 +32,8 @@ #include <broadwell/rcba.h> #include <chip.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or); +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or); /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -52,23 +52,23 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[NUM_ROOT_PORTS]; + struct device *ports[NUM_ROOT_PORTS]; }; static struct root_port_config rpc; -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void) int enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -244,7 +244,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -297,7 +297,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; @@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 8214a8a..2517fef 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -52,7 +52,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + struct device *dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e8d1fbe..24a8ebe 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -221,7 +221,7 @@ static void sata_init(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index a1dbdfe..c214510 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -31,7 +31,7 @@ #include <broadwell/ramstage.h> #include <broadwell/smbus.h> -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_BASE_ADDRESS; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 6acd07c..49cf774 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index bd1fc26..9ba6a00 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; int num_cpus; msr_t msr; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 353323a..6095cf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -286,7 +286,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; + struct device *dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi; pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 2b3ce41..d940e33 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -37,7 +37,7 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -184,7 +184,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } -static void systemagent_read_resources(device_t dev) +static void systemagent_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) +static void systemagent_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 89e1139..9530422 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -27,7 +27,7 @@ #include <broadwell/xhci.h> #ifdef __SMM__ -static u32 usb_xhci_mem_base(device_t dev) +static u32 usb_xhci_mem_base(struct device *dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(struct device *dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(struct device *dev, int all) { u32 status, port_disabled; int timeout, port; @@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ) { u16 reg16; u32 reg32; diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a2377..d991d34 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -57,7 +57,7 @@ void rangeley_early_initialization(void); int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); +void soc_enable(struct device *dev); /* debugging functions */ void print_pci_devices(void); diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h index 095f09c..c1114df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -25,10 +25,10 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void southcluster_enable_dev(struct device *dev); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 732d1dc..5b54874 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -25,12 +25,12 @@ #include <drivers/intel/fsp/fsp_util.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -58,7 +58,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", dev_name(dev), dev->path.type); @@ -98,7 +98,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { .final = &finalize_chip, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 6f1e9c4..5c6375e 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev) } } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..010063e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 bmbound, bsmmrrl; int index = 0; @@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void nc_enable(device_t dev) +static void nc_enable(struct device *dev) { print_fsp_info(); } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..55abb4d 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -76,7 +76,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2225964..50b6ef4 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..307b006 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -51,12 +51,12 @@ typedef struct soc_intel_fsp_baytrail_config config_t; static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { #ifndef CONFIG_VIRTUAL_ROM_SIZE #error CONFIG_VIRTUAL_ROM_SIZE must be set. @@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -255,7 +255,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void sc_pirq_init(device_t dev) +static void sc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -409,7 +409,7 @@ static void sc_init(struct device *dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -534,7 +534,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4feb502..295e203 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -288,13 +288,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is type-dependent on stage */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 48ffbda..895fd89 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -567,7 +567,7 @@ struct disp_ctl_win { u32 out_h; /* Height of output window in pixels */ }; -void display_startup(device_t dev); +void display_startup(struct device *dev); void dp_bringup(u32 winb_addr); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 00dfbb6..9cc0cf0 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -234,7 +234,7 @@ uint32_t fb_base_mb(void) /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ -void display_startup(device_t dev) +void display_startup(struct device *dev) { u32 val; int i; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 8ad1aa9..5d95110 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -29,7 +29,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(device_t dev) +static void soc_enable(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -39,7 +39,7 @@ static void soc_enable(device_t dev) mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { display_startup(dev); printk(BIOS_INFO, "CPU: Tegra124\n"); @@ -53,7 +53,7 @@ static struct device_operations soc_ops = { .scan_bus = 0, }; -static void enable_tegra124_dev(device_t dev) +static void enable_tegra124_dev(struct device *dev) { dev->ops = &soc_ops; } diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 60fa55a..639a45a 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -59,7 +59,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5250_config *conf = dev->chip_info; @@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -123,7 +123,7 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); @@ -137,7 +137,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_exynos5250_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index c904636..1f4d739 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -73,7 +73,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5420_config *conf = dev->chip_info; @@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index) } } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -154,7 +154,7 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / 1000000); @@ -168,7 +168,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5420_dev(device_t dev) +static void enable_exynos5420_dev(struct device *dev) { dev->ops = &cpu_ops; }

1 0

Patch set updated for coreboot: 205ffbe northbridge: DEVICE_NOOP some stub function callbacks
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7344 -gerrit commit 205ffbec6aa0ab148b5c8a1c75c377f430c6b88e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Nov 6 08:57:40 2014 +1100 northbridge: DEVICE_NOOP some stub function callbacks Reduces loc and makes NOP's explicit. Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family14/northbridge.c | 14 +++----------- src/northbridge/amd/agesa/family15/northbridge.c | 12 ++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 12 ++---------- src/northbridge/amd/amdfam10/northbridge.c | 8 ++------ 4 files changed, 9 insertions(+), 37 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 57502e9..8384c98 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -779,15 +779,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ -} - -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus = dev->link_list; device_t cpu; @@ -846,8 +838,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = NULL, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index ce9785e..aab061e 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1092,17 +1092,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d77897d..2632321 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1054,17 +1054,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 76ffc5d..70d925b 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1411,11 +1411,7 @@ static void cpu_bus_init(device_t dev) #endif } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { @@ -1425,7 +1421,7 @@ static void cpu_bus_set_resources(device_t dev) } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, + .read_resources = DEVICE_NOOP, .set_resources = cpu_bus_set_resources, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init,

1 0

Patch set updated for coreboot: 4aac0e9 northbridge: style fix
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7343 -gerrit commit 4aac0e9a086162e1b386cfbd474c6be597b11f1b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Nov 6 08:51:13 2014 +1100 northbridge: style fix Change-Id: Ib3de17b3b1b8149f5d10ce203f128345394d11d1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/00730F01/northbridge.c | 70 +++++++++---------- src/northbridge/amd/agesa/family10/northbridge.c | 80 +++++++++++----------- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 50 +++++++------- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 54 +++++++-------- src/northbridge/amd/agesa/family15/northbridge.c | 72 +++++++++---------- src/northbridge/amd/agesa/family15tn/iommu.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 66 +++++++++--------- src/northbridge/amd/agesa/family16kb/northbridge.c | 70 +++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 72 +++++++++---------- src/northbridge/amd/amdk8/northbridge.c | 64 ++++++++--------- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 12 ++-- src/northbridge/amd/gx2/northbridge.c | 12 ++-- src/northbridge/amd/lx/northbridge.c | 12 ++-- src/northbridge/dmp/vortex86ex/northbridge.c | 6 +- src/northbridge/intel/e7501/northbridge.c | 6 +- src/northbridge/intel/e7505/northbridge.c | 8 +-- src/northbridge/intel/e7520/northbridge.c | 16 ++--- src/northbridge/intel/e7525/northbridge.c | 16 ++--- src/northbridge/intel/fsp_rangeley/northbridge.c | 20 +++--- .../intel/fsp_sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/gm45/northbridge.c | 12 ++-- src/northbridge/intel/haswell/northbridge.c | 30 ++++---- src/northbridge/intel/i3100/northbridge.c | 18 ++--- src/northbridge/intel/i440bx/northbridge.c | 8 +-- src/northbridge/intel/i440lx/northbridge.c | 8 +-- src/northbridge/intel/i5000/northbridge.c | 14 ++-- src/northbridge/intel/i82810/northbridge.c | 8 +-- src/northbridge/intel/i82830/northbridge.c | 8 +-- src/northbridge/intel/i855/northbridge.c | 8 +-- src/northbridge/intel/i945/northbridge.c | 14 ++-- src/northbridge/intel/nehalem/northbridge.c | 14 ++-- src/northbridge/intel/sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/sch/northbridge.c | 14 ++-- src/northbridge/rdc/r8610/northbridge.c | 6 +- src/northbridge/via/cn400/northbridge.c | 16 ++--- src/northbridge/via/cn700/northbridge.c | 10 +-- src/northbridge/via/cx700/northbridge.c | 8 +-- src/northbridge/via/vt8601/northbridge.c | 8 +-- src/northbridge/via/vt8623/northbridge.c | 14 ++-- src/northbridge/via/vx800/northbridge.c | 8 +-- src/northbridge/via/vx900/northbridge.c | 14 ++-- 44 files changed, 504 insertions(+), 504 deletions(-) diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c index 06fe3f6..7769b03 100644 --- a/src/northbridge/amd/agesa/00730F01/northbridge.c +++ b/src/northbridge/amd/agesa/00730F01/northbridge.c @@ -58,15 +58,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(struct device * dev) +static u32 amdfam16_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -287,7 +287,7 @@ static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -329,7 +329,7 @@ static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void read_resources(struct device * dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -342,7 +342,7 @@ static void read_resources(struct device * dev) } } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -393,7 +393,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -402,7 +402,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -422,7 +422,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(struct device * dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -449,11 +449,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(struct device * dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -499,7 +499,7 @@ struct chip_operations northbridge_amd_agesa_00730F01_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -512,7 +512,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -559,7 +559,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -663,7 +663,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -840,13 +840,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -882,12 +882,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -983,7 +983,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1068,7 +1068,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1076,12 +1076,12 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1092,7 +1092,7 @@ static void cpu_bus_read_resources(struct device * dev) #endif } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index bc4a25d..543966e 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -52,10 +52,10 @@ typedef struct dram_base_mask { struct amdfam10_sysconf_t sysconf; -static struct device * __f0_dev[NODE_NUMS]; -static struct device * __f1_dev[NODE_NUMS]; -static struct device * __f2_dev[NODE_NUMS]; -static struct device * __f4_dev[NODE_NUMS]; +static struct device *__f0_dev[NODE_NUMS]; +static struct device *__f1_dev[NODE_NUMS]; +static struct device *__f2_dev[NODE_NUMS]; +static struct device *__f4_dev[NODE_NUMS]; static unsigned fx_devs = 0; #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 @@ -64,7 +64,7 @@ static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; @@ -96,7 +96,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - struct device * dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -149,7 +149,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, #endif #if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(struct device * dev, u32 segbusn, u32 nodes, +static u32 check_segn(struct device *dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -249,7 +249,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, sysconf.mmio_addr_num = index+1; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -318,7 +318,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - struct device * dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first @@ -357,7 +357,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi #endif } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -407,7 +407,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -415,7 +415,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(struct device * dev) +static u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 unsigned busn; @@ -442,7 +442,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -450,7 +450,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -470,7 +470,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -505,7 +505,7 @@ static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -541,7 +541,7 @@ static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -600,7 +600,7 @@ static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(struct device * dev) +static void amdfam10_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -612,7 +612,7 @@ static void amdfam10_read_resources(struct device * dev) } } -static void amdfam10_set_resource(struct device * dev, struct resource *resource, +static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -667,7 +667,7 @@ static void amdfam10_set_resource(struct device * dev, struct resource *resource * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -676,7 +676,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -696,7 +696,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(struct device * dev) +static void amdfam10_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -723,12 +723,12 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0xff; nodeid = amdfam10_nodeid(dev); @@ -770,7 +770,7 @@ struct chip_operations northbridge_amd_agesa_family10_ops = { }; -static void amdfam10_domain_read_resources(struct device * dev) +static void amdfam10_domain_read_resources(struct device *dev) { unsigned reg; @@ -783,7 +783,7 @@ static void amdfam10_domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -829,7 +829,7 @@ static void amdfam10_domain_read_resources(struct device * dev) #endif } -static void amdfam10_domain_enable_resources(struct device * dev) +static void amdfam10_domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); @@ -904,7 +904,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void amdfam10_domain_set_resources(struct device * dev) +static void amdfam10_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1071,7 +1071,7 @@ static void amdfam10_domain_set_resources(struct device * dev) } } -static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1102,7 +1102,7 @@ static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) */ get_fx_devs(); for (i = 0; i < fx_devs; i++) { - struct device * f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1132,7 +1132,7 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1150,7 +1150,7 @@ static void sysconf_init(struct device * dev) // first node sysconf.bsp_apicid = lapicid(); } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1186,12 +1186,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int nodes; @@ -1282,7 +1282,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1363,7 +1363,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1371,12 +1371,12 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1387,7 +1387,7 @@ static void cpu_bus_read_resources(struct device * dev) #endif } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 116a466..aa7eb69 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - struct device * dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - struct device * dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 7d1b118..ca357ef 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,14 +41,14 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static struct device * __f0_dev[FX_DEVS]; -static struct device * __f1_dev[FX_DEVS]; -static struct device * __f2_dev[FX_DEVS]; -static struct device * __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs=0; -struct device * get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -89,7 +89,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -98,7 +98,7 @@ static void f1_write_config32(unsigned reg, u32 value) } -static u32 amdfam12_nodeid(struct device * dev) +static u32 amdfam12_nodeid(struct device *dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -108,7 +108,7 @@ static u32 amdfam12_nodeid(struct device * dev) #include "amdfam12_conf.c" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -137,7 +137,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -158,7 +158,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam12_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 result, reg; @@ -182,7 +182,7 @@ static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam12_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -218,7 +218,7 @@ static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u } -static void amdfam12_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam12_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -343,7 +343,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void read_resources(struct device * dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void read_resources(struct device * dev) } -static void set_resource(struct device * dev, struct resource *resource, +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -412,10 +412,10 @@ static void set_resource(struct device * dev, struct resource *resource, #if CONFIG_CONSOLE_VGA_MULTI -extern struct device * vga_pri; // the primary vga device, defined in device.c +extern struct device *vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -447,7 +447,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) } -static void set_resources(struct device * dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -503,7 +503,7 @@ static void setup_uma_memory(void) /* Domain/Root Complex related code */ -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -518,7 +518,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -581,7 +581,7 @@ static void domain_read_resources(struct device * dev) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -765,7 +765,7 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -783,7 +783,7 @@ static void domain_enable_resources(struct device * dev) /* Bus related code */ -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -797,7 +797,7 @@ static void cpu_bus_read_resources(struct device * dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -809,7 +809,7 @@ static void cpu_bus_set_resources(struct device * dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index b72b21b..b5fd94d 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - struct device * dev; + struct device *dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - struct device * dev; + struct device *dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - struct device * dev; + struct device *dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index de1465b..d7a352b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -44,13 +44,13 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static struct device * __f0_dev[FX_DEVS]; -static struct device * __f1_dev[FX_DEVS]; -static struct device * __f2_dev[FX_DEVS]; -static struct device * __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs = 0; -struct device * get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -88,7 +88,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -96,14 +96,14 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam14_nodeid(struct device * dev) +static u32 amdfam14_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #include "amdfam14_conf.c" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -119,7 +119,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -127,7 +127,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -146,7 +146,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodeid, +static struct resource *amdfam14_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -173,7 +173,7 @@ static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, +static struct resource *amdfam14_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -208,7 +208,7 @@ static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, return resource; } -static void amdfam14_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam14_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void nb_read_resources(struct device * dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(struct device * dev) #endif } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -409,10 +409,10 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod } #if CONFIG_CONSOLE_VGA_MULTI -extern struct device * vga_pri; // the primary vga device, defined in device.c +extern struct device *vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -444,7 +444,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void nb_set_resources(struct device * dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -477,7 +477,7 @@ static void nb_set_resources(struct device * dev) /* Domain/Root Complex related code */ -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -492,7 +492,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -566,7 +566,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -757,7 +757,7 @@ static void domain_set_resources(struct device * dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { #if CONFIG_AMD_SB_CIMX if (!acpi_is_wakeup_s3()) { @@ -779,18 +779,18 @@ static void domain_enable_resources(struct device * dev) /* Bus related code */ -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus = dev->link_list; - struct device * cpu; + struct device *cpu; int apic_id, cores_found; /* There is only one node for fam14, but there may be multiple cores. */ @@ -809,7 +809,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c7a141f..2d69939 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -57,16 +57,16 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(struct device * dev) +static u32 amdfam15_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -288,7 +288,7 @@ static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u } -static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void nb_read_resources(struct device * dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(struct device * dev) } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -412,7 +412,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -422,7 +422,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -443,7 +443,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) } -static void nb_set_resources(struct device * dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -476,11 +476,11 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(struct device * dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { @@ -526,7 +526,7 @@ struct chip_operations northbridge_amd_agesa_family15_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -540,7 +540,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -588,7 +588,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); @@ -681,7 +681,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -860,13 +860,13 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -902,12 +902,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -987,7 +987,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1079,7 +1079,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1087,16 +1087,16 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { } @@ -1136,7 +1136,7 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { }; /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(struct device *dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); return max; diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 5b3529b..396ba02 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <lib.h> -static void iommu_read_resources(struct device * dev) +static void iommu_read_resources(struct device *dev) { struct resource *res; @@ -39,7 +39,7 @@ static void iommu_read_resources(struct device * dev) res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(struct device * dev) +static void iommu_set_resources(struct device *dev) { struct resource *res; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 5f0cafc..1fccec1 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(struct device * dev) +static u32 amdfam15_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void nb_read_resources(struct device * dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -354,7 +354,7 @@ static void nb_read_resources(struct device * dev) #endif } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -405,7 +405,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -414,7 +414,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -434,7 +434,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void nb_set_resources(struct device * dev) +static void nb_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -494,7 +494,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -507,7 +507,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -554,7 +554,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -647,7 +647,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -824,13 +824,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -866,12 +866,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -951,7 +951,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1041,7 +1041,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1049,16 +1049,16 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cc79da3..f91bbbb 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static struct device * __f0_dev[MAX_NODE_NUMS]; -static struct device * __f1_dev[MAX_NODE_NUMS]; -static struct device * __f2_dev[MAX_NODE_NUMS]; -static struct device * __f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - struct device * dev; + struct device *dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static struct device * get_node_pci(u32 nodeid, u32 fn) +static struct device *get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(struct device * dev) +static u32 amdfam16_nodeid(struct device *dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u return resource; } -static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) } -static void read_resources(struct device * dev) +static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -341,7 +341,7 @@ static void read_resources(struct device * dev) } } -static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -392,7 +392,7 @@ static void set_resource(struct device * dev, struct resource *resource, u32 nod * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device * dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -401,7 +401,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -421,7 +421,7 @@ static void create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(struct device * dev) +static void set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -448,11 +448,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(struct device * dev, unsigned max) +static unsigned scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; - struct device * io_hub = NULL; + struct device *io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -498,7 +498,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = { .enable_dev = 0, }; -static void domain_read_resources(struct device * dev) +static void domain_read_resources(struct device *dev) { unsigned reg; @@ -511,7 +511,7 @@ static void domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -558,7 +558,7 @@ static void domain_read_resources(struct device * dev) #endif } -static void domain_enable_resources(struct device * dev) +static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -653,7 +653,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(struct device * dev) +static void domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -830,13 +830,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -872,12 +872,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int coreid_bits; @@ -957,7 +957,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1047,7 +1047,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1055,12 +1055,12 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1071,7 +1071,7 @@ static void cpu_bus_read_resources(struct device * dev) #endif } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8b87abc..779a0d6 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -53,13 +53,13 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS -static struct device * __f0_dev[FX_DEVS]; -static struct device * __f1_dev[FX_DEVS]; -static struct device * __f2_dev[FX_DEVS]; -static struct device * __f4_dev[FX_DEVS]; +static struct device *__f0_dev[FX_DEVS]; +static struct device *__f1_dev[FX_DEVS]; +static struct device *__f2_dev[FX_DEVS]; +static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs=0; -struct device * get_node_pci(u32 nodeid, u32 fn) +struct device *get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if((CONFIG_CDB + nodeid) < 32) { @@ -102,7 +102,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(struct device * dev) +static u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 unsigned busn; @@ -139,7 +139,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdfam10_scan_chain(struct device *dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -152,7 +152,7 @@ static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link u32 max_bus; u32 min_bus; u32 is_sublink1 = (link_num>3); - struct device * devx; + struct device *devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -284,7 +284,7 @@ static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link return max; } -static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -327,7 +327,7 @@ static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -335,7 +335,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -355,7 +355,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -389,7 +389,7 @@ static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodei return resource; } -static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -425,7 +425,7 @@ static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u } -static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) { struct resource *resource; @@ -484,7 +484,7 @@ static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(struct device * dev) +static void amdfam10_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -496,7 +496,7 @@ static void amdfam10_read_resources(struct device * dev) } } -static void amdfam10_set_resource(struct device * dev, struct resource *resource, +static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -551,7 +551,7 @@ static void amdfam10_set_resource(struct device * dev, struct resource *resource * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) { struct bus *link; @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -580,7 +580,7 @@ static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(struct device * dev) +static void amdfam10_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -629,7 +629,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { .enable_dev = 0, }; -static void amdfam10_domain_read_resources(struct device * dev) +static void amdfam10_domain_read_resources(struct device *dev) { unsigned reg; @@ -642,7 +642,7 @@ static void amdfam10_domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -767,7 +767,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - struct device * dev; + struct device *dev; struct dram_base_mask_t d; u32 sel_m; u32 sel_hi_en; @@ -871,7 +871,7 @@ static void setup_uma_memory(void) #endif } -static void amdfam10_domain_set_resources(struct device * dev) +static void amdfam10_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1087,7 +1087,7 @@ static void amdfam10_domain_set_resources(struct device * dev) } } -static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1118,7 +1118,7 @@ static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1146,7 +1146,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(struct device * dev) // first node +static void sysconf_init(struct device *dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1188,7 +1188,7 @@ static void sysconf_init(struct device * dev) // first node #endif } -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1224,12 +1224,12 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; #if CONFIG_CBB - struct device * pci_domain; + struct device *pci_domain; #endif int i,j; int nodes; @@ -1324,7 +1324,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < nodes; i++) { - struct device * cdb_dev; + struct device *cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1394,7 +1394,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) } } #endif - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1402,7 +1402,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX @@ -1412,11 +1412,11 @@ static void cpu_bus_init(struct device * dev) } -static void cpu_bus_read_resources(struct device * dev) +static void cpu_bus_read_resources(struct device *dev) { } -static void cpu_bus_set_resources(struct device * dev) +static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 816d9e4..e14f706 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -40,8 +40,8 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 -static struct device * __f0_dev[MAX_FX_DEVS]; -static struct device * __f1_dev[MAX_FX_DEVS]; +static struct device *__f0_dev[MAX_FX_DEVS]; +static struct device *__f1_dev[MAX_FX_DEVS]; static unsigned fx_devs=0; static void get_fx_devs(void) @@ -71,7 +71,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * dev; + struct device *dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -79,12 +79,12 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdk8_nodeid(struct device * dev) +static u32 amdk8_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdk8_scan_chain(struct device *dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u return max; } -static unsigned amdk8_scan_chains(struct device * dev, unsigned max) +static unsigned amdk8_scan_chains(struct device *dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -271,7 +271,7 @@ static unsigned amdk8_scan_chains(struct device * dev, unsigned max) } -static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -279,7 +279,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device * dev; + struct device *dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -299,7 +299,7 @@ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nod return result; } -static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned link, +static unsigned amdk8_find_reg(struct device *dev, unsigned nodeid, unsigned link, unsigned min, unsigned max) { unsigned resource; @@ -327,17 +327,17 @@ static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned li return resource; } -static unsigned amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_iopair(struct device *dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8); } -static unsigned amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_mempair(struct device *dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8); } -static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device *dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -376,9 +376,9 @@ static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned } } -static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid); +static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid); -static void amdk8_read_resources(struct device * dev) +static void amdk8_read_resources(struct device *dev) { unsigned nodeid; struct bus *link; @@ -391,7 +391,7 @@ static void amdk8_read_resources(struct device * dev) amdk8_create_vga_resource(dev, nodeid); } -static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device *dev, struct resource *resource, unsigned nodeid) { struct bus *link; resource_t rbase, rend; @@ -488,7 +488,7 @@ static void amdk8_set_resource(struct device * dev, struct resource *resource, u report_resource_stored(dev, resource, buf); } -static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid) { struct resource *resource; struct bus *link; @@ -498,7 +498,7 @@ static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern struct device * vga_pri; // the primary vga device, defined in device.c + extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -529,7 +529,7 @@ static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) IORESOURCE_ASSIGNED; } -static void amdk8_set_resources(struct device * dev) +static void amdk8_set_resources(struct device *dev) { unsigned nodeid; struct bus *bus; @@ -638,7 +638,7 @@ struct chip_operations northbridge_amd_amdk8_ops = { .enable_dev = 0, }; -static void amdk8_domain_read_resources(struct device * dev) +static void amdk8_domain_read_resources(struct device *dev) { unsigned reg; @@ -651,7 +651,7 @@ static void amdk8_domain_read_resources(struct device * dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - struct device * reg_dev; + struct device *reg_dev; nodeid = limit & 7; reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; @@ -765,7 +765,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - struct device * dev; + struct device *dev; u32 base, limit; u32 hoist; u32 hole_sizek; @@ -810,7 +810,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; u32 carry_over; - struct device * dev; + struct device *dev; u32 base, limit; u32 basek; u32 hoist; @@ -904,7 +904,7 @@ static void setup_uma_memory(void) #endif } -static void amdk8_domain_set_resources(struct device * dev) +static void amdk8_domain_set_resources(struct device *dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1121,7 +1121,7 @@ static void amdk8_domain_set_resources(struct device * dev) } -static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) +static u32 amdk8_domain_scan_bus(struct device *dev, u32 max) { u32 reg; int i; @@ -1136,7 +1136,7 @@ static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - struct device * f0_dev; + struct device *f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1164,7 +1164,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void add_more_links(struct device * dev, unsigned total_links) +static void add_more_links(struct device *dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1200,10 +1200,10 @@ static void add_more_links(struct device * dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(struct device * dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus; - struct device * dev_mc; + struct device *dev_mc; int bsp_apicid; int i,j; unsigned nb_cfg_54; @@ -1258,7 +1258,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < sysconf.nodes; i++) { - struct device * cpu_dev; + struct device *cpu_dev; /* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1267,7 +1267,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) * ensure all of the cpu's pci devices are found. */ int local_j; - struct device * dev_f0; + struct device *dev_f0; for(local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); @@ -1334,7 +1334,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) } } - struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1342,7 +1342,7 @@ static u32 cpu_bus_scan(struct device * dev, u32 max) return max; } -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { #if CONFIG_WAIT_BEFORE_CPUS_INIT cpus_ready_for_init(); diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 09cdce5..937095b 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -66,7 +66,7 @@ void nb_Late_Post_Init(void) LibSystemApiCall(AmdLatePostInit, &gConfig); } -static void rd890_enable(struct device * dev) +static void rd890_enable(struct device *dev) { u32 address = 0; u32 devfn; diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index d960406..25add9f 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -14,7 +14,7 @@ /* */ -static void optimize_xbus(struct device * dev) +static void optimize_xbus(struct device *dev) { /* Optimise X-Bus performance */ pci_write_config8(dev, 0x40, 0x1e); @@ -31,13 +31,13 @@ static void optimize_xbus(struct device * dev) * this region? **/ -static void enable_shadow(struct device * dev) +static void enable_shadow(struct device *dev) { write32(GX_BASE+BC_XMAP_2, 0x77777777); write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); @@ -65,9 +65,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -126,7 +126,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e7a37f1..50f72ce 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -213,12 +213,12 @@ int sizeram(void) return sizem; } -static void enable_shadow(struct device * dev) +static void enable_shadow(struct device *dev) { } -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); @@ -273,11 +273,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { int idx; u32 tomk; - struct device * mc_dev; + struct device *mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -296,7 +296,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void pci_domain_enable(struct device * dev) +static void pci_domain_enable(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -318,7 +318,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 9a75fc4..f7971c3 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -291,11 +291,11 @@ int sizeram(void) return sizem; } -static void enable_shadow(struct device * dev) +static void enable_shadow(struct device *dev) { } -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { //msr_t msr; @@ -372,11 +372,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { int idx; u32 tomk; - struct device * mc_dev; + struct device *mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -395,7 +395,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void pci_domain_enable(struct device * dev) +static void pci_domain_enable(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -422,7 +422,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index e193168..03c52cd 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -30,7 +30,7 @@ #define SPI_BASE 0xfc00 -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. @@ -75,9 +75,9 @@ static void set_cmos_memory_size(unsigned long sizek) * don't touch it. */ } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 407df57..e3bdb42 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -20,9 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -110,7 +110,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 0f6a1ce..417b5b7 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -16,9 +16,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -97,7 +97,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -117,7 +117,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 42c2f84..143fd7c 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static u32 e7520_domain_scan_bus(struct device * dev, u32 max) +static u32 e7520_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -122,7 +122,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -134,7 +134,7 @@ static void mc_read_resources(struct device * dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -145,7 +145,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -170,7 +170,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x3590, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -184,7 +184,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index b6cb7fc..b011fc9 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -106,7 +106,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static u32 e7525_domain_scan_bus(struct device * dev, u32 max) +static u32 e7525_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -121,7 +121,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -133,7 +133,7 @@ static void mc_read_resources(struct device * dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -144,7 +144,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -169,7 +169,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x359e, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -183,7 +183,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 04cb5d9..47b98ba 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -112,7 +112,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (struct device * dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -123,7 +123,7 @@ static void finalize_dev (struct device * dev) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); } -static void mc_add_dram_resources(struct device * dev) +static void mc_add_dram_resources(struct device *dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -168,7 +168,7 @@ static void mc_add_dram_resources(struct device * dev) index = add_fixed_resources(dev, index); } -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -177,7 +177,7 @@ static void mc_read_resources(struct device * dev) mc_add_dram_resources(dev); } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { /* * Assign memory resources for PCI devices @@ -187,13 +187,13 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -208,7 +208,7 @@ static void northbridge_init(struct device *dev) { } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { } @@ -258,7 +258,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -271,7 +271,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index e6f1fec..01d60fb 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -68,7 +68,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -121,7 +121,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -261,7 +261,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -283,7 +283,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -297,7 +297,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -322,7 +322,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -375,7 +375,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -388,7 +388,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index b7737aa..9f2d409 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -46,7 +46,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - struct device * dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; @@ -73,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) return 0; } -static void mch_domain_read_resources(struct device * dev) +static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0, usable_tomk; @@ -170,7 +170,7 @@ static void mch_domain_read_resources(struct device * dev) } } -static void mch_domain_set_resources(struct device * dev) +static void mch_domain_set_resources(struct device *dev) { struct resource *resource; int i; @@ -185,7 +185,7 @@ static void mch_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void mch_domain_init(struct device * dev) +static void mch_domain_init(struct device *dev) { u32 reg32; @@ -207,7 +207,7 @@ static struct device_operations pci_domain_ops = { }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -221,7 +221,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 1cd6ac0..35ceb68 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,7 +39,7 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -69,7 +69,7 @@ static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 return 0; } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +106,7 @@ static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -126,7 +126,7 @@ static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(struct device * dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -146,7 +146,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(struct device * dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -203,7 +203,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(struct device * dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(struct device * dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(struct device * dev, uint64_t *values) } } -static void mc_report_map_entries(struct device * dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -291,7 +291,7 @@ static void mc_report_map_entries(struct device * dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(struct device * dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -383,7 +383,7 @@ static void mc_add_dram_resources(struct device * dev) #endif } -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -395,7 +395,7 @@ static void mc_read_resources(struct device * dev) mc_add_dram_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -433,7 +433,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; @@ -480,7 +480,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { bsp_init_and_start_aps(dev->link_list); } @@ -493,7 +493,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 8f30486..ee448a7 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -39,9 +39,9 @@ static u32 max_bus; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -132,7 +132,7 @@ static void pci_domain_set_resources(struct device * dev) assign_resources(dev->link_list); } -static u32 i3100_domain_scan_bus(struct device * dev, u32 max) +static u32 i3100_domain_scan_bus(struct device *dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -159,7 +159,7 @@ static void mc_read_resources(struct device * dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -170,7 +170,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -180,7 +180,7 @@ static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned d unsigned long acpi_fill_mcfg(unsigned long current) { - struct device * dev; + struct device *dev; u64 mmcfg; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = PCI_DEVICE_ID_INTEL_3100_MC, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -233,7 +233,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 866a778..bbda583 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -12,7 +12,7 @@ #include "northbridge.h" #include "i440bx.h" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -32,9 +32,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -static void i440bx_domain_set_resources(struct device * dev) +static void i440bx_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -81,7 +81,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 4070c7a..5c96eca 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -38,7 +38,7 @@ * Maciej */ -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -58,9 +58,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -static void i440lx_domain_set_resources(struct device * dev) +static void i440lx_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 30517bb..49ceff8 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <cbmem.h> -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -40,15 +40,15 @@ static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned d } } -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0; - struct device * dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); - struct device * dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + struct device *dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + struct device *dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); pci_dev_read_resources(dev); @@ -139,7 +139,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = nb_ids, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -151,7 +151,7 @@ static struct device_operations cpu_bus_ops = { .init = cpu_bus_init, .scan_bus = 0, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -165,7 +165,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 5925e63..fba09fc 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -32,7 +32,7 @@ #include "northbridge.h" #include "i82810.h" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -69,9 +69,9 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -136,7 +136,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index a317613..5bb5ac3 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -30,7 +30,7 @@ #include <string.h> #include "i82830.h" -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -50,9 +50,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -103,7 +103,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index ff3ca5b..4daacfe 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -32,7 +32,7 @@ #include <cpu/x86/cache.h> #include <cpu/cpu.h> -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -52,9 +52,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); @@ -119,7 +119,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 494253f..2baf935 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -81,7 +81,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { uint32_t pci_tolm; uint8_t tolud, reg8; @@ -185,7 +185,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -207,7 +207,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -221,7 +221,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,7 +274,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x27a0, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -287,7 +287,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index ea14c12..d9c6723 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -96,7 +96,7 @@ static void add_fixed_resources(struct device *dev, int index) #endif } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { uint32_t tseg_base; uint64_t TOUUD; @@ -165,13 +165,13 @@ static void mc_read_resources(struct device * dev) add_fixed_resources(dev, 10); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { /* And call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -283,7 +283,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -324,7 +324,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -337,7 +337,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ab28093..4ed1db6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -66,7 +66,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -132,7 +132,7 @@ static void add_fixed_resources(struct device *dev, int index) bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -266,7 +266,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -288,7 +288,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -302,7 +302,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -412,7 +412,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(struct device * dev) +static void northbridge_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -471,7 +471,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -484,7 +484,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index e2cc496..7ecdbc4 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - struct device * dev; + struct device *dev; u32 pciexbar_reg; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { u32 pci_tolm; u8 reg8; @@ -200,7 +200,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(struct device * dev) +static void mc_read_resources(struct device *dev) { struct resource *resource; @@ -226,7 +226,7 @@ static void mc_read_resources(struct device * dev) (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(struct device * dev) +static void mc_set_resources(struct device *dev) { struct resource *resource; @@ -239,7 +239,7 @@ static void mc_set_resources(struct device * dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -292,7 +292,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x8100, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -305,7 +305,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 5ca0ab3..f85756c 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -33,7 +33,7 @@ static unsigned long get_memory_size(void) { - struct device * nb_dev; + struct device *nb_dev; u8 size; nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, @@ -42,7 +42,7 @@ static unsigned long get_memory_size(void) return (2 * 1024) << size; } -static void cpu_pci_domain_set_resources(struct device * dev) +static void cpu_pci_domain_set_resources(struct device *dev) { u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; @@ -92,7 +92,7 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current) return len; } -static int rdc_get_smbios_data(struct device * dev, int *handle, unsigned long *current) +static int rdc_get_smbios_data(struct device *dev, int *handle, unsigned long *current) { int len; len = rdc_get_smbios_data16(*handle, current); diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index dc64991..1ecd2cf 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn400.h" -static void memctrl_init(struct device * dev) +static void memctrl_init(struct device *dev) { - struct device * vlink_dev; + struct device *vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; int i, j; @@ -140,7 +140,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; -static void cn400_domain_read_resources(struct device * dev) +static void cn400_domain_read_resources(struct device *dev) { struct resource *resource; @@ -162,7 +162,7 @@ static void cn400_domain_read_resources(struct device * dev) } #ifdef UNUSED_CODE -static void ram_reservation(struct device * dev, unsigned long index, +static void ram_reservation(struct device *dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +177,9 @@ static void ram_reservation(struct device * dev, unsigned long index, } #endif -static void cn400_domain_set_resources(struct device * dev) +static void cn400_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +219,7 @@ static void cn400_domain_set_resources(struct device * dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); } -static unsigned int cn400_domain_scan_bus(struct device * dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device *dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__); @@ -236,7 +236,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index c1bd74c..6c21b72 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn700.h" -static void memctrl_init(struct device * dev) +static void memctrl_init(struct device *dev) { - struct device * vlink_dev; + struct device *vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg; @@ -97,11 +97,11 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -156,7 +156,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index bb8caf9..3dc5bc4 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -31,9 +31,9 @@ #include <cbmem.h> #include <arch/acpi.h> -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; @@ -82,7 +82,7 @@ static void pci_domain_set_resources(struct device * dev) unsigned long acpi_fill_mcfg(unsigned long current) { - struct device * dev; + struct device *dev; u64 mmcfg; dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 @@ -112,7 +112,7 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = acpi_write_hpet, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 2565b1d..6f2ad3d 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -17,7 +17,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -44,12 +44,12 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -102,7 +102,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 0b5030b..01f4432 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -19,9 +19,9 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(struct device * dev) +static void northbridge_init(struct device *dev) { - struct device * fb_dev; + struct device *fb_dev; unsigned long fb; unsigned char c; @@ -58,7 +58,7 @@ static void northbridge_init(struct device * dev) } } -static void nullfunc(struct device * dev) +static void nullfunc(struct device *dev) { /* Nothing to do */ } @@ -76,7 +76,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8623, }; -static void agp_init(struct device * dev) +static void agp_init(struct device *dev) { printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n"); @@ -103,10 +103,10 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; - struct device * mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); @@ -162,7 +162,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index e0fb06f..52da40c 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -37,7 +37,7 @@ /* !!FIXME!! I declared this to fix the build. */ u8 acpi_sleep_type = 0; -static void memctrl_init(struct device * dev) +static void memctrl_init(struct device *dev) { /* set VGA in uma_ram_setting.c, not in this function. @@ -71,13 +71,13 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - struct device * mc_dev; + struct device *mc_dev; u32 pci_tolm; u8 reg; @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 7047a04..fe3e3ba 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -60,7 +60,7 @@ uint64_t get_uma_memory_base(void) return uma_memory_base; } -static u64 vx900_get_top_of_ram(struct device * mcu) +static u64 vx900_get_top_of_ram(struct device *mcu) { u16 reg16; /* The last valid DRAM address is computed by the MCU @@ -97,7 +97,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) * * @return The new top of memory. */ -static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) +static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm) { size_t i; u8 reg8, start8, end8, start, end; @@ -216,7 +216,7 @@ static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) return newtor; } -static void vx900_set_resources(struct device * dev) +static void vx900_set_resources(struct device *dev) { u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk; @@ -228,7 +228,7 @@ static void vx900_set_resources(struct device * dev) "========================================\n"); int idx = 10; - struct device * mcu = dev_find_device(PCI_VENDOR_ID_VIA, + struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); if (!mcu) { @@ -286,7 +286,7 @@ static void vx900_set_resources(struct device * dev) assign_resources(dev->link_list); } -static void vx900_read_resources(struct device * dev) +static void vx900_read_resources(struct device *dev) { /* Our fixed resources start at 0 */ int idx = 0; @@ -317,7 +317,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(struct device * dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -330,7 +330,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(struct device * dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) {

1 0

Patch set updated for coreboot: 7bd463d southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 7bd463d9171701d562f00367dac6e11ceaa66d58 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/cx700/lpc.c | 8 ++++---- src/northbridge/via/vx800/lpc.c | 6 +++--- src/northbridge/via/vx900/lpc.c | 14 +++++++------- src/southbridge/amd/agesa/hudson/lpc.c | 12 ++++++------ src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb700/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb700/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/cimx/sb800/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb800/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/cimx/sb900/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb900/lpc.h | 6 +++--- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb600/lpc.c | 12 ++++++------ src/southbridge/amd/sb600/sata.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/amd/sb700/lpc.c | 12 ++++++------ src/southbridge/amd/sb700/sata.c | 2 +- src/southbridge/amd/sb800/lpc.c | 12 ++++++------ src/southbridge/amd/sb800/sata.c | 2 +- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/intel/bd82x6x/lpc.c | 18 +++++++++--------- src/southbridge/intel/bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/bd82x6x/sata.c | 4 ++-- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/esb6300/lpc.c | 22 +++++++++++----------- src/southbridge/intel/esb6300/sata.c | 2 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/fsp_bd82x6x/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_rangeley/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/intel/i3100/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i3100/sata.c | 2 +- src/southbridge/intel/i82801ax/lpc.c | 10 +++++----- src/southbridge/intel/i82801bx/lpc.c | 10 +++++----- src/southbridge/intel/i82801cx/lpc.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 10 +++++----- src/southbridge/intel/i82801ex/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i82801gx/lpc.c | 16 ++++++++-------- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 14 +++++++------- src/southbridge/intel/i82801ix/sata.c | 8 ++++---- src/southbridge/intel/ibexpeak/lpc.c | 18 +++++++++--------- src/southbridge/intel/ibexpeak/me.c | 14 +++++++------- src/southbridge/intel/ibexpeak/sata.c | 4 ++-- src/southbridge/intel/lynxpoint/lpc.c | 26 +++++++++++++------------- src/southbridge/intel/lynxpoint/sata.c | 4 ++-- src/southbridge/intel/sch/lpc.c | 8 ++++---- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/sis/sis966/lpc.c | 18 +++++++++--------- src/southbridge/sis/sis966/sata.c | 2 +- src/southbridge/via/vt8231/early_serial.c | 2 +- src/southbridge/via/vt8231/lpc.c | 2 +- src/southbridge/via/vt8235/lpc.c | 6 +++--- src/southbridge/via/vt8237r/lpc.c | 8 ++++---- src/southbridge/via/vt8237r/sata.c | 2 +- src/southbridge/via/vt82c686/early_serial.c | 4 ++-- 81 files changed, 329 insertions(+), 329 deletions(-) diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 1e6d2ce..db810d2 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -80,7 +80,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -232,7 +232,7 @@ static void cx700_set_lpc_registers(struct device *dev) } -static void cx700_read_resources(device_t dev) +static void cx700_read_resources(struct device *dev) { struct resource *res; @@ -254,7 +254,7 @@ static void cx700_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void cx700_set_resources(device_t dev) +static void cx700_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); @@ -262,7 +262,7 @@ static void cx700_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void cx700_enable_resources(device_t dev) +static void cx700_enable_resources(struct device *dev) { /* Enable SuperIO decoding */ pci_dev_enable_resources(dev); diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index c2a8a1d..ca9bfc2 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -103,7 +103,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); } -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ @@ -300,7 +300,7 @@ static void vx800_sb_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vx800_read_resources(device_t dev) +static void vx800_read_resources(struct device *dev) { struct resource *resource; @@ -313,7 +313,7 @@ static void vx800_read_resources(device_t dev) resource->base = 0x2e; } -static void vx800_set_resources(device_t dev) +static void vx800_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index ac5e4c8..f22cee5 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -50,7 +50,7 @@ * it will work, but perhaps this should be more configurable. */ -static void vx900_lpc_misc_stuff(device_t dev) +static void vx900_lpc_misc_stuff(struct device *dev) { char extint; u8 val; @@ -74,7 +74,7 @@ static void vx900_lpc_misc_stuff(device_t dev) } } -static void vx900_lpc_dma_setup(device_t dev) +static void vx900_lpc_dma_setup(struct device *dev) { /* These are the steps recommended by VIA in order to get DMA running */ @@ -107,12 +107,12 @@ static void vx900_lpc_dma_setup(device_t dev) * We are assuming this is called before the drivers/generic/ioapic code, * which should be the case if devicetree.cb is set up properly. */ -static void vx900_lpc_ioapic_setup(device_t dev) +static void vx900_lpc_ioapic_setup(struct device *dev) { /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb * If it's not, then the generic ioapic driver will not set it up * correctly, and the MP table will not be correctly generated */ - device_t ioapic; + struct device *ioapic; for (ioapic = dev->next; ioapic; ioapic = ioapic->next) { if (ioapic->path.type == DEVICE_PATH_IOAPIC) break; @@ -154,7 +154,7 @@ static void vx900_lpc_ioapic_setup(device_t dev) pci_mod_config8(dev, 0x58, 0, 1 << 6); } -static void vx900_lpc_interrupt_stuff(device_t dev) +static void vx900_lpc_interrupt_stuff(struct device *dev) { /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports * And enable I/O recovery time */ @@ -180,7 +180,7 @@ static void vx900_lpc_interrupt_stuff(device_t dev) vx900_lpc_ioapic_setup(dev); } -static void vx900_lpc_init(device_t dev) +static void vx900_lpc_init(struct device *dev) { vx900_lpc_interrupt_stuff(dev); vx900_lpc_misc_stuff(dev); @@ -204,7 +204,7 @@ static const struct pci_driver lpc_driver __pci_driver = { #if CONFIG_PIRQ_ROUTE void pirq_assign_irqs(const u8 * pirq) { - device_t lpc; + struct device *lpc; lpc = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_LPC, 0); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 1f60bc4..3b0c90d 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -31,11 +31,11 @@ #include <arch/ioapic.h> #include "hudson.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -80,7 +80,7 @@ static void lpc_init(device_t dev) cmos_init(0); } -static void hudson_lpc_read_resources(device_t dev) +static void hudson_lpc_read_resources(struct device *dev) { struct resource *res; @@ -128,7 +128,7 @@ static void hudson_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void hudson_lpc_enable_childrens_resources(device_t dev) +static void hudson_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -168,7 +168,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) reg_var[0] = pci_read_config16(dev, 0x64); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -307,7 +307,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void hudson_lpc_enable_resources(device_t dev) +static void hudson_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); hudson_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..ce22d34 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 718b40b..d8fb2e7 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -86,7 +86,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void amd8111_lpc_read_resources(device_t dev) +static void amd8111_lpc_read_resources(struct device *dev) { struct resource *res; @@ -112,7 +112,7 @@ static void amd8111_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 5d05762..3b4a40a 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -38,7 +38,7 @@ void backup_top_of_ram(uint64_t ramtop) } } -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -92,7 +92,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -104,7 +104,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h index b30f247..7d1874f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.h +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 519e3c1..4663c9f 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include <cbmem.h> -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -80,7 +80,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -92,7 +92,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 8a657d8..032db06 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..86e4f89 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index ce1be11..5a56b49 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -23,7 +23,7 @@ #include <arch/ioapic.h> -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -77,7 +77,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -89,7 +89,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h index 66f3ccd..fe2f84b 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ b/src/southbridge/amd/cimx/sb900/lpc.h @@ -24,8 +24,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index d8e63b5..1a1fab7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -33,11 +33,11 @@ #include <cpu/amd/powernow.h> #include "sb600.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -66,7 +66,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); } -static void sb600_lpc_read_resources(device_t dev) +static void sb600_lpc_read_resources(struct device *dev) { struct resource *res; @@ -102,7 +102,7 @@ static void sb600_lpc_read_resources(device_t dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb600_lpc_enable_childrens_resources(device_t dev) +static void sb600_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -114,7 +114,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -213,7 +213,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb600_lpc_enable_resources(device_t dev) +static void sb600_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb600_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index a17aab8..b965bb9 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -70,7 +70,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb600_config *conf; conf = dev->chip_info; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 173de83..c266402 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -40,11 +40,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -104,7 +104,7 @@ void backup_top_of_ram(uint64_t ramtop) } } -static void sb700_lpc_read_resources(device_t dev) +static void sb700_lpc_read_resources(struct device *dev) { struct resource *res; @@ -151,7 +151,7 @@ static void sb700_lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -static void sb700_lpc_enable_childrens_resources(device_t dev) +static void sb700_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -163,7 +163,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -262,7 +262,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb700_lpc_enable_resources(device_t dev) +static void sb700_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb700_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index c0e3c0f..1a7410b 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -86,7 +86,7 @@ static void sata_init(struct device *dev) u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 7a4dd83..143e717 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -28,11 +28,11 @@ #include <arch/io.h> #include "sb800.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); } -static void sb800_lpc_read_resources(device_t dev) +static void sb800_lpc_read_resources(struct device *dev) { struct resource *res; @@ -118,7 +118,7 @@ static void sb800_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb800_lpc_enable_childrens_resources(device_t dev) +static void sb800_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -130,7 +130,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -229,7 +229,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb800_lpc_enable_resources(device_t dev) +static void sb800_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb800_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 5ac6144..c592298 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -89,7 +89,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb800_config *conf; conf = dev->chip_info; - device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..35173d3 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device *dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..d2b908e 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0e3a4f6..04f38d1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -393,7 +393,7 @@ static void enable_hpet(void) RCBA32(HPTC) = reg32; } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -581,7 +581,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -645,13 +645,13 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -660,7 +660,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 44c7273..a316ea0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -548,7 +548,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -615,7 +615,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -645,7 +645,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -692,14 +692,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -741,7 +741,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index cb5699e..897470b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -211,7 +211,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -236,7 +236,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..e5783e7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + struct device * dev; ich9_spi_regs *ich9_spi; uint16_t hsfs; diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index b5b77ef..b2dcd06 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -24,7 +24,7 @@ #endif #define SERIRQ_CNTL 0x64 -static void esb6300_enable_serial_irqs(device_t dev) +static void esb6300_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -32,14 +32,14 @@ static void esb6300_enable_serial_irqs(device_t dev) } #define PCI_DMA_CFG 0x90 -static void esb6300_pci_dma_cfg(device_t dev) +static void esb6300_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } #define LPC_EN 0xe6 -static void esb6300_enable_lpc(device_t dev) +static void esb6300_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -48,7 +48,7 @@ static void esb6300_enable_lpc(device_t dev) typedef struct southbridge_intel_esb6300_config config_t; static void set_esb6300_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; @@ -81,7 +81,7 @@ static void set_esb6300_gpio_use_sel( } static void set_esb6300_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; @@ -114,7 +114,7 @@ static void set_esb6300_gpio_direction( } static void set_esb6300_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -154,7 +154,7 @@ static void set_esb6300_gpio_level( } static void set_esb6300_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv; @@ -176,7 +176,7 @@ static void set_esb6300_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void esb6300_pirq_init(device_t dev) +static void esb6300_pirq_init(struct device *dev) { config_t *config; @@ -192,7 +192,7 @@ static void esb6300_pirq_init(device_t dev) } -static void esb6300_gpio_init(device_t dev) +static void esb6300_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -303,7 +303,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); } -static void esb6300_lpc_read_resources(device_t dev) +static void esb6300_lpc_read_resources(struct device *dev) { struct resource *res; @@ -335,7 +335,7 @@ static void esb6300_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void esb6300_lpc_enable_resources(device_t dev) +static void esb6300_lpc_enable_resources(struct device *dev) { uint8_t acpi_cntl, gpio_cntl; diff --git a/src/southbridge/intel/esb6300/sata.c b/src/southbridge/intel/esb6300/sata.c index b08f0ed..cc11006 100644 --- a/src/southbridge/intel/esb6300/sata.c +++ b/src/southbridge/intel/esb6300/sata.c @@ -42,7 +42,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); } -static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void esb6300_sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* This value is also visible in usb1, usb2 and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..edd5dc7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -116,9 +116,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -158,7 +158,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -187,7 +187,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -547,7 +547,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -608,18 +608,18 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 2282378..ddec118 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -119,7 +119,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -547,7 +547,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -614,7 +614,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -644,7 +644,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -691,14 +691,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -740,7 +740,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 591bdbc..cbbb76b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -82,11 +82,11 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8576b61..9b1df7a 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -113,8 +113,8 @@ static void soc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -197,7 +197,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void soc_pirq_init(device_t dev) +static void soc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -242,7 +242,7 @@ static void soc_pirq_init(device_t dev) write_pci_config_irqs(); } -static void soc_power_options(device_t dev) +static void soc_power_options(struct device *dev) { u8 reg8; u16 pmbase; @@ -344,7 +344,7 @@ static void lpc_init(struct device *dev) soc_disable_smm_only_flashing(dev); } -static void soc_lpc_read_resources(device_t dev) +static void soc_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -405,17 +405,17 @@ static void soc_lpc_read_resources(device_t dev) } } -static void soc_lpc_enable_resources(device_t dev) +static void soc_lpc_enable_resources(struct device *dev) { return pci_dev_enable_resources(dev); } -static void soc_lpc_enable(device_t dev) +static void soc_lpc_enable(struct device *dev) { soc_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index f672e4c..dcaa230 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -95,11 +95,11 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..c4e8a1c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + struct device * dev; uint32_t ids; uint16_t vendor_id, device_id; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index ba74f30..6cfec63 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void i3100_enable_serial_irqs(device_t dev) +static void i3100_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -62,7 +62,7 @@ static void i3100_enable_serial_irqs(device_t dev) typedef struct southbridge_intel_i3100_config config_t; static void set_i3100_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_use_sel, gpio_use_sel2; int i; @@ -95,7 +95,7 @@ static void set_i3100_gpio_use_sel( } static void set_i3100_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_io_sel, gpio_io_sel2; int i; @@ -128,7 +128,7 @@ static void set_i3100_gpio_direction( } static void set_i3100_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_lvl, gpio_lvl2; u32 gpio_blink; @@ -172,7 +172,7 @@ static void set_i3100_gpio_level( } static void set_i3100_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_inv; int i; @@ -196,9 +196,9 @@ static void set_i3100_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void i3100_pirq_init(device_t dev) +static void i3100_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config; /* Get the chip configuration */ @@ -245,7 +245,7 @@ static void i3100_pirq_init(device_t dev) } -static void i3100_power_options(device_t dev) { +static void i3100_power_options(struct device *dev) { u8 reg8; u16 reg16; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; @@ -308,7 +308,7 @@ static void i3100_power_options(device_t dev) { // i82801gx_gpi_routing(dev); } -static void i3100_gpio_init(device_t dev) +static void i3100_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -384,7 +384,7 @@ static void lpc_init(struct device *dev) i8259_configure_irq_trigger(9, 1); } -static void i3100_lpc_read_resources(device_t dev) +static void i3100_lpc_read_resources(struct device *dev) { struct resource *res; @@ -424,7 +424,7 @@ static void i3100_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM; } -static void i3100_lpc_enable_resources(device_t dev) +static void i3100_lpc_enable_resources(struct device *dev) { u8 acpi_cntl, gpio_cntl; diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index 0740440..6f4ebf9 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -111,7 +111,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 11519c1..c96ac00 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -122,7 +122,7 @@ static void i82801ax_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801ax_pirq_init(device_t dev) +static void i82801ax_pirq_init(struct device *dev) { u8 reg8; config_t *config = dev->chip_info; @@ -140,7 +140,7 @@ static void i82801ax_pirq_init(device_t dev) pci_write_config8(dev, PIRQD_ROUT, reg8); } -static void i82801ax_power_options(device_t dev) +static void i82801ax_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -170,7 +170,7 @@ static void i82801ax_power_options(device_t dev) } } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); pci_write_config8(dev, GPIO_CNTL, GPIO_EN); @@ -211,7 +211,7 @@ static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801ax_lpc_decode_en(device_t dev) +static void i82801ax_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -255,7 +255,7 @@ static void lpc_init(struct device *dev) i82801ax_lpc_decode_en(dev); } -static void i82801ax_lpc_read_resources(device_t dev) +static void i82801ax_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 278d65c..3bd6570 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -123,7 +123,7 @@ static void i82801bx_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801bx_pirq_init(struct device *dev, uint16_t ich_model) { u8 reg8; config_t *config = dev->chip_info; @@ -154,7 +154,7 @@ static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) pci_write_config8(dev, PIRQH_ROUT, reg8); } -static void i82801bx_power_options(device_t dev) +static void i82801bx_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -184,7 +184,7 @@ static void i82801bx_power_options(device_t dev) } } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); @@ -226,7 +226,7 @@ static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801bx_lpc_decode_en(struct device *dev, uint16_t ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -273,7 +273,7 @@ static void lpc_init(struct device *dev) i82801bx_lpc_decode_en(dev, ich_model); } -static void i82801bx_lpc_read_resources(device_t dev) +static void i82801bx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f6c33b7..9978842 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -199,7 +199,7 @@ static void lpc_init(struct device *dev) i82801cx_1f0_misc(dev); } -static void i82801cx_lpc_read_resources(device_t dev) +static void i82801cx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1b23fad..c5821c6 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -85,7 +85,7 @@ static void i82801dx_enable_serial_irqs(struct device *dev) (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -static void i82801dx_pirq_init(device_t dev) +static void i82801dx_pirq_init(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -100,7 +100,7 @@ static void i82801dx_pirq_init(device_t dev) pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); } -static void i82801dx_power_options(device_t dev) +static void i82801dx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -179,7 +179,7 @@ static void i82801dx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* This should be done in romstage.c already */ pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); @@ -221,7 +221,7 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(device_t dev) +static void i82801dx_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -305,7 +305,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801dx_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 1823e65..7703d14 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -61,7 +61,7 @@ static void i82801ex_general_cntl(struct device *dev) } #define SERIRQ_CNTL 0x64 -static void i82801ex_enable_serial_irqs(device_t dev) +static void i82801ex_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -69,14 +69,14 @@ static void i82801ex_enable_serial_irqs(device_t dev) } #define PCI_DMA_CFG 0x90 -static void i82801ex_pci_dma_cfg(device_t dev) +static void i82801ex_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } #define LPC_EN 0xe6 -static void i82801ex_enable_lpc(device_t dev) +static void i82801ex_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -85,7 +85,7 @@ static void i82801ex_enable_lpc(device_t dev) typedef struct southbridge_intel_i82801ex_config config_t; static void set_i82801ex_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; int i; @@ -114,7 +114,7 @@ static void set_i82801ex_gpio_use_sel( } static void set_i82801ex_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; int i; @@ -143,7 +143,7 @@ static void set_i82801ex_gpio_direction( } static void set_i82801ex_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -178,7 +178,7 @@ static void set_i82801ex_gpio_level( } static void set_i82801ex_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv; int i; @@ -198,7 +198,7 @@ static void set_i82801ex_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void i82801ex_pirq_init(device_t dev) +static void i82801ex_pirq_init(struct device *dev) { config_t *config; @@ -214,7 +214,7 @@ static void i82801ex_pirq_init(device_t dev) } -static void i82801ex_gpio_init(device_t dev) +static void i82801ex_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -319,7 +319,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801ex_lpc_read_resources(device_t dev) +static void i82801ex_lpc_read_resources(struct device *dev) { struct resource *res; @@ -351,7 +351,7 @@ static void i82801ex_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void i82801ex_lpc_enable_resources(device_t dev) +static void i82801ex_lpc_enable_resources(struct device *dev) { /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3b6b71a..021884d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -90,9 +90,9 @@ static void i82801gx_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801gx_pirq_init(device_t dev) +static void i82801gx_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -132,7 +132,7 @@ static void i82801gx_pirq_init(device_t dev) } } -static void i82801gx_gpi_routing(device_t dev) +static void i82801gx_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -161,7 +161,7 @@ static void i82801gx_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void i82801gx_power_options(device_t dev) +static void i82801gx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -265,7 +265,7 @@ static void i82801gx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void i82801gx_configure_cstates(device_t dev) +static void i82801gx_configure_cstates(struct device *dev) { u8 reg8; @@ -457,7 +457,7 @@ static void lpc_init(struct device *dev) void acpi_fill_fadt(acpi_fadt_t * fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -575,7 +575,7 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) } } -static void i82801gx_lpc_read_resources(device_t dev) +static void i82801gx_lpc_read_resources(struct device *dev) { struct resource *res; @@ -601,7 +601,7 @@ static void i82801gx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index ea29986..e0794d6 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -188,7 +188,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, reg32); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 664088c..b4ded0f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -92,9 +92,9 @@ static void i82801ix_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801ix_pirq_init(device_t dev) +static void i82801ix_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -134,7 +134,7 @@ static void i82801ix_pirq_init(device_t dev) } } -static void i82801ix_gpi_routing(device_t dev) +static void i82801ix_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -163,7 +163,7 @@ static void i82801ix_gpi_routing(device_t dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } -static void i82801ix_power_options(device_t dev) +static void i82801ix_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -295,7 +295,7 @@ static void i82801ix_power_options(device_t dev) outl(reg32, pmbase + 0x10); } -static void i82801ix_configure_cstates(device_t dev) +static void i82801ix_configure_cstates(struct device *dev) { u8 reg8; @@ -471,7 +471,7 @@ static void lpc_init(struct device *dev) #endif } -static void i82801ix_lpc_read_resources(device_t dev) +static void i82801ix_lpc_read_resources(struct device *dev) { /* * I/O Resources @@ -527,7 +527,7 @@ static void i82801ix_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 10c8a2b..0fcf7bd 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -141,7 +141,7 @@ static void sata_program_indexed(struct device *const dev, const int is_mobile) pci_write_config32(dev, D31F2_SDAT, reg32); } -static void sata_init(struct device *const dev) +static void sata_init(struct device *dev) { u16 reg16; @@ -212,7 +212,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg); if (is_mobile && config->sata_traffic_monitor) { - const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct device *lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); @@ -228,7 +228,7 @@ static void sata_init(struct device *const dev) sata_program_indexed(dev, is_mobile); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ const config_t *const config = dev->chip_info; @@ -255,7 +255,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a833a3d..31b8389 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -400,7 +400,7 @@ static void enable_hpet(void) write32(0xfed00010, read32(0xfed00010) | 1); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -578,7 +578,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -639,13 +639,13 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -654,7 +654,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 99920f5..0a5b20f 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -430,7 +430,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -497,7 +497,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -527,7 +527,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -574,14 +574,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -616,7 +616,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 5f3c4d3..cee66c5 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -212,7 +212,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -237,7 +237,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a202424..6adc8a5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -107,9 +107,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -149,7 +149,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -178,7 +178,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16; @@ -416,7 +416,7 @@ static void enable_hpet(void) reg32 = RCBA32(HPTC); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ u32 reg32; @@ -441,7 +441,7 @@ static void enable_clock_gating(device_t dev) RCBA32_OR(0x38c0, 0x7); // SPI Dynamic } -static void enable_lp_clock_gating(device_t dev) +static void enable_lp_clock_gating(struct device *dev) { /* LynxPoint LP */ u32 reg32; @@ -591,7 +591,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -653,7 +653,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -666,7 +666,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -679,7 +679,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -704,7 +704,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; @@ -723,7 +723,7 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -732,7 +732,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 43a99c8..0812fe5 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -305,7 +305,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x300, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -326,7 +326,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index 7d209b1..beaf090 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -76,9 +76,9 @@ typedef struct southbridge_intel_sch_config config_t; #define PIRQG 0x0B #define PIRQH 0x0C -static void sch_pirq_init(device_t dev) +static void sch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -151,7 +151,7 @@ static void lpc_init(struct device *dev) sch_fixups(dev); } -static void sch_lpc_read_resources(device_t dev) +static void sch_lpc_read_resources(struct device *dev) { struct resource *res; @@ -177,7 +177,7 @@ static void sch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..d62075f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device *dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device *dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device *dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device *dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..a2a3b22 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device *dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device *dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device *dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0e11c6f..55a5e43 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -56,7 +56,7 @@ #undef SLAVE_INIT -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device *dev) { uint8_t byte; uint32_t ioapic_base; @@ -71,13 +71,13 @@ static void lpc_common_init(device_t dev) } #ifdef SLAVE_INIT -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); } #endif -static void lpc_usb_legacy_init(device_t dev) +static void lpc_usb_legacy_init(struct device *dev) { uint16_t acpi_base; @@ -87,7 +87,7 @@ static void lpc_usb_legacy_init(device_t dev) outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba); } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { uint8_t byte; uint8_t byte_old; @@ -156,7 +156,7 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "LPC_INIT <--------\n"); } -static void sis966_lpc_read_resources(device_t dev) +static void sis966_lpc_read_resources(struct device *dev) { struct resource *res; @@ -187,7 +187,7 @@ static void sis966_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void sis966_lpc_enable_childrens_resources(device_t dev) +static void sis966_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg, reg_var[4]; @@ -197,7 +197,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -238,13 +238,13 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) } -static void sis966_lpc_enable_resources(device_t dev) +static void sis966_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sis966_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 3f8c28f..1f942aa 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -171,7 +171,7 @@ for (i=0;i<10;i++){ } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c index a0aec65..8c500b9 100644 --- a/src/southbridge/via/vt8231/early_serial.c +++ b/src/southbridge/via/vt8231/early_serial.c @@ -33,7 +33,7 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) static void enable_vt8231_serial(void) { uint8_t c; - device_t dev; + pnp_devfn_t dev; post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c index c6b74fd..862b1ad 100644 --- a/src/southbridge/via/vt8231/lpc.c +++ b/src/southbridge/via/vt8231/lpc.c @@ -124,7 +124,7 @@ static void vt8231_init(struct device *dev) cmos_init(0); } -static void vt8231_read_resources(device_t dev) +static void vt8231_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c index 2c78481..396b647 100644 --- a/src/southbridge/via/vt8235/lpc.c +++ b/src/southbridge/via/vt8235/lpc.c @@ -104,7 +104,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { // Set gen config 0 pci_write_config8(dev, 0x80, 0x20); @@ -214,7 +214,7 @@ static void vt8235_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vt8235_read_resources(device_t dev) +static void vt8235_read_resources(struct device *dev) { struct resource *res; @@ -232,7 +232,7 @@ static void vt8235_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vt8235_set_resources(device_t dev) +static void vt8235_set_resources(struct device *dev) { //struct resource *resource; //resource = find_resource(dev,1); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 9e8f6f6..70b6120 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -66,7 +66,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT - device_t pdev; + struct device *pdev; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -148,7 +148,7 @@ static void pci_routing_fixup(struct device *dev) * This avoids having to handle any System Management Interrupts (SMIs). */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; struct southbridge_via_vt8237r_config *cfg; @@ -568,7 +568,7 @@ static void vt8237_common_init(struct device *dev) cmos_init(0); } -static void vt8237r_read_resources(device_t dev) +static void vt8237r_read_resources(struct device *dev) { struct resource *res; @@ -640,7 +640,7 @@ static void southbridge_init_common(struct device *dev) } -static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0x70, vendor); pci_write_config16(dev, 0x72, device); diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c index 606c33e..0246d54 100644 --- a/src/southbridge/via/vt8237r/sata.c +++ b/src/southbridge/via/vt8237r/sata.c @@ -96,7 +96,7 @@ static void sata_ii_init(struct device *dev) } -static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0xd4, vendor); pci_write_config16(dev, 0xd6, device); diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 55742a7..9cdf943 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -48,10 +48,10 @@ static void vt82c686_sio_write(uint8_t index, uint8_t value) * @param dev TODO * @param iobase TODO */ -static void vt82c686_enable_serial(device_t dev, unsigned iobase) +static void vt82c686_enable_serial(pnp_devfn_t dev, unsigned iobase) { uint8_t reg; - device_t sbdev; + pnp_devfn_t sbdev; /* TODO: Use info from 'dev' and 'iobase'. */ /* TODO: Only enable one serial port (depending on config) or both? */

1 0

Patch set updated for coreboot: a11d620 northbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7166 -gerrit commit a11d620158428b13298b2fbaf21c331b7b74845f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 22 22:03:49 2014 +1100 northbridge: Don't hide pointers behind typedefs Change-Id: Ib2c373695820e71a6e41e4f173d2615ee5838f28 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 10 +-- src/northbridge/amd/agesa/00730F01/northbridge.c | 70 +++++++++---------- src/northbridge/amd/agesa/family10/northbridge.c | 80 +++++++++++----------- src/northbridge/amd/agesa/family10/reset_test.h | 4 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 50 +++++++------- src/northbridge/amd/agesa/family12/northbridge.h | 2 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 54 +++++++-------- src/northbridge/amd/agesa/family14/northbridge.h | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 72 +++++++++---------- src/northbridge/amd/agesa/family15/northbridge.h | 2 +- src/northbridge/amd/agesa/family15tn/iommu.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 66 +++++++++--------- src/northbridge/amd/agesa/family16kb/northbridge.c | 70 +++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 73 ++++++++++---------- src/northbridge/amd/amdk8/northbridge.c | 64 ++++++++--------- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 12 ++-- src/northbridge/amd/gx2/northbridge.c | 12 ++-- src/northbridge/amd/lx/northbridge.c | 12 ++-- src/northbridge/dmp/vortex86ex/northbridge.c | 6 +- src/northbridge/intel/e7501/northbridge.c | 6 +- src/northbridge/intel/e7505/northbridge.c | 8 +-- src/northbridge/intel/e7520/northbridge.c | 16 ++--- src/northbridge/intel/e7525/northbridge.c | 16 ++--- src/northbridge/intel/fsp_rangeley/northbridge.c | 20 +++--- .../intel/fsp_sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/gm45/northbridge.c | 12 ++-- src/northbridge/intel/haswell/northbridge.c | 30 ++++---- src/northbridge/intel/i3100/northbridge.c | 18 ++--- src/northbridge/intel/i440bx/northbridge.c | 8 +-- src/northbridge/intel/i440lx/northbridge.c | 8 +-- src/northbridge/intel/i5000/northbridge.c | 14 ++-- src/northbridge/intel/i82810/northbridge.c | 8 +-- src/northbridge/intel/i82830/northbridge.c | 8 +-- src/northbridge/intel/i855/northbridge.c | 8 +-- src/northbridge/intel/i945/northbridge.c | 14 ++-- src/northbridge/intel/nehalem/northbridge.c | 14 ++-- src/northbridge/intel/sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/sch/northbridge.c | 14 ++-- src/northbridge/rdc/r8610/northbridge.c | 6 +- src/northbridge/via/cn400/northbridge.c | 16 ++--- src/northbridge/via/cn700/northbridge.c | 10 +-- src/northbridge/via/cx700/northbridge.c | 8 +-- src/northbridge/via/vt8601/northbridge.c | 8 +-- src/northbridge/via/vt8623/northbridge.c | 14 ++-- src/northbridge/via/vx800/northbridge.c | 8 +-- src/northbridge/via/vx900/northbridge.c | 14 ++-- src/northbridge/via/vx900/sata.c | 16 ++--- 50 files changed, 523 insertions(+), 522 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 2714052..b1967de 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -46,7 +46,7 @@ static void qemu_reserve_ports(struct device *dev, unsigned int idx, IORESOURCE_ASSIGNED; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -213,7 +213,7 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * return len; } -static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int qemu_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = qemu_get_smbios_data16(*handle, current); @@ -234,15 +234,15 @@ static struct device_operations pci_domain_ops = { #endif }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +static unsigned int cpu_bus_scan(struct device * bus, unsigned int max) { int max_cpus = fw_cfg_max_cpus(); - device_t cpu; + struct device * cpu; int i; if (max_cpus < 0) diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c index 03433af..06fe3f6 100644 --- a/src/northbridge/amd/agesa/00730F01/northbridge.c +++ b/src/northbridge/amd/agesa/00730F01/northbridge.c @@ -58,15 +58,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -287,7 +287,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -329,7 +329,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -342,7 +342,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -402,7 +402,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -449,11 +449,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -499,7 +499,7 @@ struct chip_operations northbridge_amd_agesa_00730F01_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -512,7 +512,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -559,7 +559,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -663,7 +663,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -840,13 +840,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -882,12 +882,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -983,7 +983,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1068,7 +1068,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1076,12 +1076,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1092,7 +1092,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b1f0890..bc4a25d 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -52,10 +52,10 @@ typedef struct dram_base_mask { struct amdfam10_sysconf_t sysconf; -static device_t __f0_dev[NODE_NUMS]; -static device_t __f1_dev[NODE_NUMS]; -static device_t __f2_dev[NODE_NUMS]; -static device_t __f4_dev[NODE_NUMS]; +static struct device * __f0_dev[NODE_NUMS]; +static struct device * __f1_dev[NODE_NUMS]; +static struct device * __f2_dev[NODE_NUMS]; +static struct device * __f4_dev[NODE_NUMS]; static unsigned fx_devs = 0; #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 @@ -64,7 +64,7 @@ static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; @@ -96,7 +96,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -149,7 +149,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, #endif #if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, +static u32 check_segn(struct device * dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -249,7 +249,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, sysconf.mmio_addr_num = index+1; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -318,7 +318,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first @@ -357,7 +357,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi #endif } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -407,7 +407,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -415,7 +415,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -442,7 +442,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -450,7 +450,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -470,7 +470,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -505,7 +505,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -541,7 +541,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -600,7 +600,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -612,7 +612,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -667,7 +667,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -676,7 +676,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -696,7 +696,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -723,12 +723,12 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0xff; nodeid = amdfam10_nodeid(dev); @@ -770,7 +770,7 @@ struct chip_operations northbridge_amd_agesa_family10_ops = { }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg; @@ -783,7 +783,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -829,7 +829,7 @@ static void amdfam10_domain_read_resources(device_t dev) #endif } -static void amdfam10_domain_enable_resources(device_t dev) +static void amdfam10_domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); @@ -904,7 +904,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1071,7 +1071,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1102,7 +1102,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1132,7 +1132,7 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1150,7 +1150,7 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1186,12 +1186,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1282,7 +1282,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1363,7 +1363,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1371,12 +1371,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1387,7 +1387,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 8c8d9a0..a38cde8 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -33,7 +33,7 @@ static inline u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -42,7 +42,7 @@ static inline u32 warm_reset_detect(u8 nodeid) static inline void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 00ff641..116a466 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 94de010..7d1b118 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,14 +41,14 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -89,7 +89,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -98,7 +98,7 @@ static void f1_write_config32(unsigned reg, u32 value) } -static u32 amdfam12_nodeid(device_t dev) +static u32 amdfam12_nodeid(struct device * dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -108,7 +108,7 @@ static u32 amdfam12_nodeid(device_t dev) #include "amdfam12_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -137,7 +137,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -158,7 +158,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 result, reg; @@ -182,7 +182,7 @@ static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -218,7 +218,7 @@ static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam12_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -343,7 +343,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -412,10 +412,10 @@ static void set_resource(device_t dev, struct resource *resource, #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -447,7 +447,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -503,7 +503,7 @@ static void setup_uma_memory(void) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -518,7 +518,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -581,7 +581,7 @@ static void domain_read_resources(device_t dev) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -765,7 +765,7 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -783,7 +783,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -797,7 +797,7 @@ static void cpu_bus_read_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -809,7 +809,7 @@ static void cpu_bus_set_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h index 4edb525..c3fc171 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.h +++ b/src/northbridge/amd/agesa/family12/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */ diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index c255213..b72b21b 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 57502e9..de1465b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -44,13 +44,13 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs = 0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -88,7 +88,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -96,14 +96,14 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam14_nodeid(device_t dev) +static u32 amdfam14_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #include "amdfam14_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -119,7 +119,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -127,7 +127,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -146,7 +146,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, +static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -173,7 +173,7 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, return resource; } -static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, +static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -208,7 +208,7 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, return resource; } -static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam14_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -409,10 +409,10 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) } #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -444,7 +444,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -477,7 +477,7 @@ static void nb_set_resources(device_t dev) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -492,7 +492,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -566,7 +566,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -757,7 +757,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { #if CONFIG_AMD_SB_CIMX if (!acpi_is_wakeup_s3()) { @@ -779,18 +779,18 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus = dev->link_list; - device_t cpu; + struct device * cpu; int apic_id, cores_found; /* There is only one node for fam14, but there may be multiple cores. */ @@ -809,7 +809,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h index 474e74c..6046137 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.h +++ b/src/northbridge/amd/agesa/family14/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */ diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index ce9785e..c7a141f 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -57,16 +57,16 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -288,7 +288,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -412,7 +412,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -443,7 +443,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -476,11 +476,11 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { @@ -526,7 +526,7 @@ struct chip_operations northbridge_amd_agesa_family15_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -588,7 +588,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); @@ -681,7 +681,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -860,13 +860,13 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -902,12 +902,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -987,7 +987,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1079,7 +1079,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1087,16 +1087,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } @@ -1136,7 +1136,7 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { }; /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); return max; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h index 99fdcae..3a90964 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.h +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -22,6 +22,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max); +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max); #endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 3765f20..5b3529b 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <lib.h> -static void iommu_read_resources(device_t dev) +static void iommu_read_resources(struct device * dev) { struct resource *res; @@ -39,7 +39,7 @@ static void iommu_read_resources(device_t dev) res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(device_t dev) +static void iommu_set_resources(struct device * dev) { struct resource *res; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d77897d..5f0cafc 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -354,7 +354,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -405,7 +405,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -414,7 +414,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -434,7 +434,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -494,7 +494,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -507,7 +507,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -554,7 +554,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -647,7 +647,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -824,13 +824,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -866,12 +866,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -951,7 +951,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1041,7 +1041,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1049,16 +1049,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d47a00d..cc79da3 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -341,7 +341,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -392,7 +392,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -401,7 +401,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -421,7 +421,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -448,11 +448,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -498,7 +498,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -511,7 +511,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -558,7 +558,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -653,7 +653,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -830,13 +830,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -872,12 +872,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -957,7 +957,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1047,7 +1047,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1055,12 +1055,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1071,7 +1071,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 76ffc5d..8b87abc 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -53,13 +53,13 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if((CONFIG_CDB + nodeid) < 32) { @@ -102,7 +102,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -139,7 +139,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -152,7 +152,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l u32 max_bus; u32 min_bus; u32 is_sublink1 = (link_num>3); - device_t devx; + struct device * devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -284,7 +284,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l return max; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -327,7 +327,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -335,7 +335,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -355,7 +355,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -389,7 +389,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -425,7 +425,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -484,7 +484,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -496,7 +496,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -551,7 +551,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -580,7 +580,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -629,7 +629,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { .enable_dev = 0, }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg; @@ -642,7 +642,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -767,7 +767,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; struct dram_base_mask_t d; u32 sel_m; u32 sel_hi_en; @@ -871,7 +871,7 @@ static void setup_uma_memory(void) #endif } -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1087,7 +1087,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1118,7 +1118,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1146,7 +1146,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1188,7 +1188,7 @@ static void sysconf_init(device_t dev) // first node #endif } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1224,12 +1224,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1324,7 +1324,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1394,7 +1394,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } #endif - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1402,7 +1402,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX @@ -1411,11 +1411,12 @@ static void cpu_bus_init(device_t dev) #endif } -static void cpu_bus_read_resources(device_t dev) + +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a91a499..816d9e4 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -40,8 +40,8 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 -static device_t __f0_dev[MAX_FX_DEVS]; -static device_t __f1_dev[MAX_FX_DEVS]; +static struct device * __f0_dev[MAX_FX_DEVS]; +static struct device * __f1_dev[MAX_FX_DEVS]; static unsigned fx_devs=0; static void get_fx_devs(void) @@ -71,7 +71,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -79,12 +79,12 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdk8_nodeid(device_t dev) +static u32 amdk8_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link return max; } -static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static unsigned amdk8_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -271,7 +271,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -279,7 +279,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -299,7 +299,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, +static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned link, unsigned min, unsigned max) { unsigned resource; @@ -327,17 +327,17 @@ static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, return resource; } -static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8); } -static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8); } -static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -376,9 +376,9 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) } } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid); +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid); -static void amdk8_read_resources(device_t dev) +static void amdk8_read_resources(struct device * dev) { unsigned nodeid; struct bus *link; @@ -391,7 +391,7 @@ static void amdk8_read_resources(device_t dev) amdk8_create_vga_resource(dev, nodeid); } -static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) { struct bus *link; resource_t rbase, rend; @@ -488,7 +488,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned report_resource_stored(dev, resource, buf); } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) { struct resource *resource; struct bus *link; @@ -498,7 +498,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -529,7 +529,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) IORESOURCE_ASSIGNED; } -static void amdk8_set_resources(device_t dev) +static void amdk8_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -638,7 +638,7 @@ struct chip_operations northbridge_amd_amdk8_ops = { .enable_dev = 0, }; -static void amdk8_domain_read_resources(device_t dev) +static void amdk8_domain_read_resources(struct device * dev) { unsigned reg; @@ -651,7 +651,7 @@ static void amdk8_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; nodeid = limit & 7; reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; @@ -765,7 +765,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; u32 base, limit; u32 hoist; u32 hole_sizek; @@ -810,7 +810,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; u32 carry_over; - device_t dev; + struct device * dev; u32 base, limit; u32 basek; u32 hoist; @@ -904,7 +904,7 @@ static void setup_uma_memory(void) #endif } -static void amdk8_domain_set_resources(device_t dev) +static void amdk8_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1121,7 +1121,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1136,7 +1136,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1164,7 +1164,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1200,10 +1200,10 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; int bsp_apicid; int i,j; unsigned nb_cfg_54; @@ -1258,7 +1258,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < sysconf.nodes; i++) { - device_t cpu_dev; + struct device * cpu_dev; /* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1267,7 +1267,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * ensure all of the cpu's pci devices are found. */ int local_j; - device_t dev_f0; + struct device * dev_f0; for(local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); @@ -1334,7 +1334,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1342,7 +1342,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { #if CONFIG_WAIT_BEFORE_CPUS_INIT cpus_ready_for_init(); diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index fa23344..09cdce5 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -66,7 +66,7 @@ void nb_Late_Post_Init(void) LibSystemApiCall(AmdLatePostInit, &gConfig); } -static void rd890_enable(device_t dev) +static void rd890_enable(struct device * dev) { u32 address = 0; u32 devfn; diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index bcb6e56..d960406 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -14,7 +14,7 @@ /* */ -static void optimize_xbus(device_t dev) +static void optimize_xbus(struct device * dev) { /* Optimise X-Bus performance */ pci_write_config8(dev, 0x40, 0x1e); @@ -31,13 +31,13 @@ static void optimize_xbus(device_t dev) * this region? **/ -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { write32(GX_BASE+BC_XMAP_2, 0x77777777); write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); @@ -65,9 +65,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -126,7 +126,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..e7a37f1 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -213,12 +213,12 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); @@ -273,11 +273,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -296,7 +296,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -318,7 +318,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..9a75fc4 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -291,11 +291,11 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { //msr_t msr; @@ -372,11 +372,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -395,7 +395,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -422,7 +422,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index fcebed8..e193168 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -30,7 +30,7 @@ #define SPI_BASE 0xfc00 -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. @@ -75,9 +75,9 @@ static void set_cmos_memory_size(unsigned long sizek) * don't touch it. */ } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 64bf840..407df57 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -20,9 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -110,7 +110,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023..0f6a1ce 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -16,9 +16,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -97,7 +97,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -117,7 +117,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 6e0379e..42c2f84 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7520_domain_scan_bus(device_t dev, u32 max) +static u32 e7520_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -122,7 +122,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -134,7 +134,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -145,7 +145,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -170,7 +170,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x3590, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -184,7 +184,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 68fdc74..b6cb7fc 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -106,7 +106,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7525_domain_scan_bus(device_t dev, u32 max) +static u32 e7525_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -121,7 +121,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -133,7 +133,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -144,7 +144,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -169,7 +169,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x359e, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -183,7 +183,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 07ce21f..04cb5d9 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -112,7 +112,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device * dev) { /* * Notify FSP for PostPciEnumeration. @@ -123,7 +123,7 @@ static void finalize_dev (device_t dev) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -168,7 +168,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -177,7 +177,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * Assign memory resources for PCI devices @@ -187,13 +187,13 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -208,7 +208,7 @@ static void northbridge_init(struct device *dev) { } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { } @@ -258,7 +258,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -271,7 +271,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index da27b25..e6f1fec 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -68,7 +68,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -121,7 +121,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -261,7 +261,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -283,7 +283,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -297,7 +297,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -322,7 +322,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -375,7 +375,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -388,7 +388,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 716ee62..b7737aa 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -46,7 +46,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; @@ -73,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) return 0; } -static void mch_domain_read_resources(device_t dev) +static void mch_domain_read_resources(struct device * dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0, usable_tomk; @@ -170,7 +170,7 @@ static void mch_domain_read_resources(device_t dev) } } -static void mch_domain_set_resources(device_t dev) +static void mch_domain_set_resources(struct device * dev) { struct resource *resource; int i; @@ -185,7 +185,7 @@ static void mch_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mch_domain_init(device_t dev) +static void mch_domain_init(struct device * dev) { u32 reg32; @@ -207,7 +207,7 @@ static struct device_operations pci_domain_ops = { }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -221,7 +221,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..1cd6ac0 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,7 +39,7 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -69,7 +69,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +106,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -126,7 +126,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device * dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -146,7 +146,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device * dev) { int i; @@ -203,7 +203,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device * dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -291,7 +291,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -383,7 +383,7 @@ static void mc_add_dram_resources(device_t dev) #endif } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -395,7 +395,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -433,7 +433,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; @@ -480,7 +480,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { bsp_init_and_start_aps(dev->link_list); } @@ -493,7 +493,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 2cf5ae1..8f30486 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -39,9 +39,9 @@ static u32 max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 i3100_domain_scan_bus(device_t dev, u32 max) +static u32 i3100_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -159,7 +159,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -170,7 +170,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -180,7 +180,7 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = PCI_DEVICE_ID_INTEL_3100_MC, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -233,7 +233,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 12ff37b..866a778 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -12,7 +12,7 @@ #include "northbridge.h" #include "i440bx.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -32,9 +32,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -static void i440bx_domain_set_resources(device_t dev) +static void i440bx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -81,7 +81,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 60e62c1..4070c7a 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -38,7 +38,7 @@ * Maciej */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -58,9 +58,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -static void i440lx_domain_set_resources(device_t dev) +static void i440lx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index a9b3560..30517bb 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <cbmem.h> -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -40,15 +40,15 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0; - device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); - device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + struct device * dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + struct device * dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); pci_dev_read_resources(dev); @@ -139,7 +139,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = nb_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -151,7 +151,7 @@ static struct device_operations cpu_bus_ops = { .init = cpu_bus_init, .scan_bus = 0, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -165,7 +165,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index ce0dc20..5925e63 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -32,7 +32,7 @@ #include "northbridge.h" #include "i82810.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -69,9 +69,9 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -136,7 +136,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4898aaf..a317613 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -30,7 +30,7 @@ #include <string.h> #include "i82830.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -50,9 +50,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -103,7 +103,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index fce7d57..ff3ca5b 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -32,7 +32,7 @@ #include <cpu/x86/cache.h> #include <cpu/cpu.h> -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -52,9 +52,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); @@ -119,7 +119,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 91c5c82..494253f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -81,7 +81,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint32_t pci_tolm; uint8_t tolud, reg8; @@ -185,7 +185,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -207,7 +207,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -221,7 +221,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,7 +274,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x27a0, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -287,7 +287,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..ea14c12 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -96,7 +96,7 @@ static void add_fixed_resources(struct device *dev, int index) #endif } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { uint32_t tseg_base; uint64_t TOUUD; @@ -165,13 +165,13 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* And call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -283,7 +283,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -324,7 +324,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -337,7 +337,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..ab28093 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -66,7 +66,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -132,7 +132,7 @@ static void add_fixed_resources(struct device *dev, int index) bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -266,7 +266,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -288,7 +288,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -302,7 +302,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -412,7 +412,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -471,7 +471,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -484,7 +484,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..e2cc496 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { u32 pci_tolm; u8 reg8; @@ -200,7 +200,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -226,7 +226,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -239,7 +239,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -292,7 +292,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x8100, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -305,7 +305,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index d69c4f6..5ca0ab3 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -33,7 +33,7 @@ static unsigned long get_memory_size(void) { - device_t nb_dev; + struct device * nb_dev; u8 size; nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, @@ -42,7 +42,7 @@ static unsigned long get_memory_size(void) return (2 * 1024) << size; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; @@ -92,7 +92,7 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current) return len; } -static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int rdc_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = rdc_get_smbios_data16(*handle, current); diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index b797179..dc64991 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn400.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; int i, j; @@ -140,7 +140,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; -static void cn400_domain_read_resources(device_t dev) +static void cn400_domain_read_resources(struct device * dev) { struct resource *resource; @@ -162,7 +162,7 @@ static void cn400_domain_read_resources(device_t dev) } #ifdef UNUSED_CODE -static void ram_reservation(device_t dev, unsigned long index, +static void ram_reservation(struct device * dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +177,9 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif -static void cn400_domain_set_resources(device_t dev) +static void cn400_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +219,7 @@ static void cn400_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); } -static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device * dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__); @@ -236,7 +236,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 506bdd1..c1bd74c 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn700.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg; @@ -97,11 +97,11 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -156,7 +156,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index cc9dabd..bb8caf9 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -31,9 +31,9 @@ #include <cbmem.h> #include <arch/acpi.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; @@ -82,7 +82,7 @@ static void pci_domain_set_resources(device_t dev) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg; dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 @@ -112,7 +112,7 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = acpi_write_hpet, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 1887491..2565b1d 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -17,7 +17,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -44,12 +44,12 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -102,7 +102,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 546db4c..0b5030b 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -19,9 +19,9 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { - device_t fb_dev; + struct device * fb_dev; unsigned long fb; unsigned char c; @@ -58,7 +58,7 @@ static void northbridge_init(device_t dev) } } -static void nullfunc(device_t dev) +static void nullfunc(struct device * dev) { /* Nothing to do */ } @@ -76,7 +76,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8623, }; -static void agp_init(device_t dev) +static void agp_init(struct device * dev) { printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n"); @@ -103,10 +103,10 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); @@ -162,7 +162,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index fad0c2f..e0fb06f 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -37,7 +37,7 @@ /* !!FIXME!! I declared this to fix the build. */ u8 acpi_sleep_type = 0; -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { /* set VGA in uma_ram_setting.c, not in this function. @@ -71,13 +71,13 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; u8 reg; @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index f9c225d..7047a04 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -60,7 +60,7 @@ uint64_t get_uma_memory_base(void) return uma_memory_base; } -static u64 vx900_get_top_of_ram(device_t mcu) +static u64 vx900_get_top_of_ram(struct device * mcu) { u16 reg16; /* The last valid DRAM address is computed by the MCU @@ -97,7 +97,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) * * @return The new top of memory. */ -static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) +static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) { size_t i; u8 reg8, start8, end8, start, end; @@ -216,7 +216,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) return newtor; } -static void vx900_set_resources(device_t dev) +static void vx900_set_resources(struct device * dev) { u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk; @@ -228,7 +228,7 @@ static void vx900_set_resources(device_t dev) "========================================\n"); int idx = 10; - const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + struct device * mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); if (!mcu) { @@ -286,7 +286,7 @@ static void vx900_set_resources(device_t dev) assign_resources(dev->link_list); } -static void vx900_read_resources(device_t dev) +static void vx900_read_resources(struct device * dev) { /* Our fixed resources start at 0 */ int idx = 0; @@ -317,7 +317,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -330,7 +330,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 63295e5..4a7ae6d 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -74,7 +74,7 @@ static void vx900_print_sata_errors(u32 flags) print_debug("\tUNRECOGNIZED FIS type\n"); } -static void vx900_dbg_sata_errors(device_t dev) +static void vx900_dbg_sata_errors(struct device *dev) { /* Port 0 */ if (pci_read_config8(dev, 0xa0) & (1 << 0)) { @@ -103,7 +103,7 @@ static sata_phy_config reference_ephy = { 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static u32 sata_phy_read32(device_t dev, u8 index) +static u32 sata_phy_read32(struct device *dev, u8 index) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -115,7 +115,7 @@ static u32 sata_phy_read32(device_t dev, u8 index) return pci_read_config32(dev, 0x64); } -static void sata_phy_write32(device_t dev, u8 index, u32 val) +static void sata_phy_write32(struct device *dev, u8 index, u32 val) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -127,7 +127,7 @@ static void sata_phy_write32(device_t dev, u8 index, u32 val) pci_write_config32(dev, 0x64, val); } -static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -136,7 +136,7 @@ static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) } } -static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -181,7 +181,7 @@ static void vx900_sata_dump_phy_config(sata_phy_config cfg) * Our only option is to operate in IDE mode. We choose native IDE so that we * can freely assign an IRQ, and are not forced to use IRQ14 */ -static void vx900_native_ide_mode(device_t dev) +static void vx900_native_ide_mode(struct device *dev) { /* Disable subclass write protect */ pci_mod_config8(dev, 0x45, 1 << 7, 0); @@ -193,7 +193,7 @@ static void vx900_native_ide_mode(device_t dev) pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); } -static void vx900_sata_init(device_t dev) +static void vx900_sata_init(struct device *dev) { /* Enable SATA primary channel IO access */ pci_mod_config8(dev, 0x40, 0, 1 << 1); @@ -261,7 +261,7 @@ static void vx900_sata_init(device_t dev) vx900_dbg_sata_errors(dev); } -static void vx900_sata_read_resources(device_t dev) +static void vx900_sata_read_resources(struct device *dev) { pci_dev_read_resources(dev); }

1 0

Patch set updated for coreboot: 9dd4635 northbridge: DEVICE_NOOP some stub function callbacks
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7344 -gerrit commit 9dd4635e991911fc15fab68fb68ff4dd55db10e8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Nov 6 08:57:40 2014 +1100 northbridge: DEVICE_NOOP some stub function callbacks Reduces loc and makes NOP's explicit. Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family14/northbridge.c | 12 ++---------- src/northbridge/amd/agesa/family15/northbridge.c | 12 ++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 12 ++---------- src/northbridge/amd/amdfam10/northbridge.c | 6 +----- 4 files changed, 7 insertions(+), 35 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index d7a352b..f8464c8 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -779,14 +779,6 @@ static void domain_enable_resources(struct device *dev) /* Bus related code */ -static void cpu_bus_read_resources(struct device *dev) -{ -} - -static void cpu_bus_set_resources(struct device *dev) -{ -} - static u32 cpu_bus_scan(struct device *dev, u32 max) { struct bus *cpu_bus = dev->link_list; @@ -846,8 +838,8 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = NULL, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 2d69939..2b0b8b8 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1092,17 +1092,9 @@ static void cpu_bus_init(struct device *dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device *dev) -{ -} - -static void cpu_bus_set_resources(struct device *dev) -{ -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 1fccec1..5c650f3 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1054,17 +1054,9 @@ static void cpu_bus_init(struct device *dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(struct device *dev) -{ -} - -static void cpu_bus_set_resources(struct device *dev) -{ -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 779a0d6..e49deec 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1412,10 +1412,6 @@ static void cpu_bus_init(struct device *dev) } -static void cpu_bus_read_resources(struct device *dev) -{ -} - static void cpu_bus_set_resources(struct device *dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -1426,7 +1422,7 @@ static void cpu_bus_set_resources(struct device *dev) } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, + .read_resources = DEVICE_NOOP, .set_resources = cpu_bus_set_resources, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init,

1 0

New patch to review for coreboot: 4ee7564 mainboard: Kill off some ancient-aliens non-CAR romcc boards
by Edward O'Callaghan 06 Nov '14

06 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7346 -gerrit commit 4ee756432c5c887caf128cf14b48e3672a3e38ca Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Nov 6 10:53:14 2014 +1100 mainboard: Kill off some ancient-aliens non-CAR romcc boards Change-Id: I506d99c6a63a24cc512c8379b225bc2a60d43335 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/Kconfig | 18 -- src/mainboard/advantech/Kconfig | 35 --- src/mainboard/advantech/pcm-5820/Kconfig | 45 ---- src/mainboard/advantech/pcm-5820/board_info.txt | 5 - src/mainboard/advantech/pcm-5820/devicetree.cb | 56 ----- src/mainboard/advantech/pcm-5820/irq_tables.c | 45 ---- src/mainboard/advantech/pcm-5820/romstage.c | 41 ---- src/mainboard/asi/Kconfig | 38 ---- src/mainboard/asi/mb_5blgp/Kconfig | 45 ---- src/mainboard/asi/mb_5blgp/board_info.txt | 2 - src/mainboard/asi/mb_5blgp/devicetree.cb | 55 ----- src/mainboard/asi/mb_5blgp/irq_tables.c | 46 ---- src/mainboard/asi/mb_5blgp/romstage.c | 41 ---- src/mainboard/asi/mb_5blmp/Kconfig | 45 ---- src/mainboard/asi/mb_5blmp/board_info.txt | 4 - src/mainboard/asi/mb_5blmp/devicetree.cb | 48 ----- src/mainboard/asi/mb_5blmp/irq_tables.c | 39 ---- src/mainboard/asi/mb_5blmp/romstage.c | 42 ---- src/mainboard/axus/Kconfig | 35 --- src/mainboard/axus/tc320/Kconfig | 46 ---- src/mainboard/axus/tc320/board_info.txt | 2 - src/mainboard/axus/tc320/devicetree.cb | 55 ----- src/mainboard/axus/tc320/irq_tables.c | 122 ----------- src/mainboard/axus/tc320/romstage.c | 42 ---- src/mainboard/bcom/Kconfig | 3 - src/mainboard/bcom/winnet100/Kconfig | 46 ---- src/mainboard/bcom/winnet100/board_info.txt | 4 - src/mainboard/bcom/winnet100/devicetree.cb | 56 ----- src/mainboard/bcom/winnet100/irq_tables.c | 121 ----------- src/mainboard/bcom/winnet100/romstage.c | 42 ---- src/mainboard/bifferos/Kconfig | 36 ---- src/mainboard/bifferos/bifferboard/Kconfig | 21 -- src/mainboard/bifferos/bifferboard/board_info.txt | 1 - src/mainboard/bifferos/bifferboard/devicetree.cb | 8 - src/mainboard/bifferos/bifferboard/romstage.c | 62 ------ src/mainboard/digitallogic/Kconfig | 3 - src/mainboard/digitallogic/msm586seg/Kconfig | 23 -- .../digitallogic/msm586seg/board_info.txt | 2 - src/mainboard/digitallogic/msm586seg/cmos.layout | 72 ------- src/mainboard/digitallogic/msm586seg/devicetree.cb | 7 - src/mainboard/digitallogic/msm586seg/irq_tables.c | 31 --- src/mainboard/digitallogic/msm586seg/mainboard.c | 133 ------------ src/mainboard/digitallogic/msm586seg/romstage.c | 240 --------------------- src/mainboard/technologic/Kconfig | 17 -- src/mainboard/technologic/ts5300/Kconfig | 23 -- src/mainboard/technologic/ts5300/board_info.txt | 2 - src/mainboard/technologic/ts5300/cmos.layout | 72 ------- src/mainboard/technologic/ts5300/devicetree.cb | 6 - src/mainboard/technologic/ts5300/irq_tables.c | 31 --- src/mainboard/technologic/ts5300/mainboard.c | 147 ------------- src/mainboard/technologic/ts5300/romstage.c | 169 --------------- src/mainboard/televideo/Kconfig | 35 --- src/mainboard/televideo/tc7020/Kconfig | 45 ---- src/mainboard/televideo/tc7020/board_info.txt | 2 - src/mainboard/televideo/tc7020/devicetree.cb | 57 ----- src/mainboard/televideo/tc7020/irq_tables.c | 148 ------------- src/mainboard/televideo/tc7020/romstage.c | 42 ---- 57 files changed, 2659 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 29b439c..5934d36 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -12,8 +12,6 @@ config VENDOR_ADLINK bool "ADLINK" config VENDOR_ADVANSUS bool "Advansus" -config VENDOR_ADVANTECH - bool "Advantech" config VENDOR_AMD bool "AMD" config VENDOR_AOPEN @@ -24,8 +22,6 @@ config VENDOR_ARIMA bool "Arima" config VENDOR_ARTECGROUP bool "Artec Group" -config VENDOR_ASI - bool "ASI" config VENDOR_ASROCK bool "ASROCK" config VENDOR_ASUS @@ -34,16 +30,12 @@ config VENDOR_A_TREND bool "A-Trend" config VENDOR_AVALUE bool "AVALUE" -config VENDOR_AXUS - bool "AXUS" config VENDOR_AZZA bool "AZZA" config VENDOR_BACHMANN bool "Bachmann electronic" config VENDOR_BCOM bool "BCOM" -config VENDOR_BIFFEROS - bool "Bifferos" config VENDOR_BIOSTAR bool "Biostar" config VENDOR_BROADCOM @@ -128,10 +120,6 @@ config VENDOR_SUPERMICRO bool "Supermicro" config VENDOR_TECHNEXION bool "Technexion" -config VENDOR_TECHNOLOGIC - bool "Technologic" -config VENDOR_TELEVIDEO - bool "TeleVideo" config VENDOR_TI bool "TI" config VENDOR_THOMSON @@ -154,21 +142,17 @@ source "src/mainboard/aaeon/Kconfig" source "src/mainboard/abit/Kconfig" source "src/mainboard/adlink/Kconfig" source "src/mainboard/advansus/Kconfig" -source "src/mainboard/advantech/Kconfig" source "src/mainboard/amd/Kconfig" source "src/mainboard/aopen/Kconfig" source "src/mainboard/apple/Kconfig" source "src/mainboard/arima/Kconfig" source "src/mainboard/artecgroup/Kconfig" -source "src/mainboard/asi/Kconfig" source "src/mainboard/asrock/Kconfig" source "src/mainboard/asus/Kconfig" source "src/mainboard/avalue/Kconfig" -source "src/mainboard/axus/Kconfig" source "src/mainboard/azza/Kconfig" source "src/mainboard/bachmann/Kconfig" source "src/mainboard/bcom/Kconfig" -source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" @@ -211,8 +195,6 @@ source "src/mainboard/soyo/Kconfig" source "src/mainboard/sunw/Kconfig" source "src/mainboard/supermicro/Kconfig" source "src/mainboard/technexion/Kconfig" -source "src/mainboard/technologic/Kconfig" -source "src/mainboard/televideo/Kconfig" source "src/mainboard/thomson/Kconfig" source "src/mainboard/ti/Kconfig" source "src/mainboard/traverse/Kconfig" diff --git a/src/mainboard/advantech/Kconfig b/src/mainboard/advantech/Kconfig deleted file mode 100644 index ab46f96..0000000 --- a/src/mainboard/advantech/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if VENDOR_ADVANTECH - -choice - prompt "Mainboard model" - -config BOARD_ADVANTECH_PCM_5820 - bool "PCM-5820" - -endchoice - -source "src/mainboard/advantech/pcm-5820/Kconfig" - -config MAINBOARD_VENDOR - string - default "Advantech" - -endif # VENDOR_ADVANTECH diff --git a/src/mainboard/advantech/pcm-5820/Kconfig b/src/mainboard/advantech/pcm-5820/Kconfig deleted file mode 100644 index 86bcd7a..0000000 --- a/src/mainboard/advantech/pcm-5820/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if BOARD_ADVANTECH_PCM_5820 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_GEODE_GX1 - select NORTHBRIDGE_AMD_GX1 - select SOUTHBRIDGE_AMD_CS5530 - select SUPERIO_WINBOND_W83977F - select ROMCC - select HAVE_PIRQ_TABLE - select PIRQ_ROUTE - select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default advantech/pcm-5820 - -config MAINBOARD_PART_NUMBER - string - default "PCM-5820" - -config IRQ_SLOT_COUNT - int - default 2 - -endif # BOARD_ADVANTECH_PCM_5820 diff --git a/src/mainboard/advantech/pcm-5820/board_info.txt b/src/mainboard/advantech/pcm-5820/board_info.txt deleted file mode 100644 index 84b3c8d..0000000 --- a/src/mainboard/advantech/pcm-5820/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: half -Board URL: http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8 -ROM package: PLCC32 -ROM socketed: y -Flashrom support: y diff --git a/src/mainboard/advantech/pcm-5820/devicetree.cb b/src/mainboard/advantech/pcm-5820/devicetree.cb deleted file mode 100644 index 8027ee2..0000000 --- a/src/mainboard/advantech/pcm-5820/devicetree.cb +++ /dev/null @@ -1,56 +0,0 @@ -chip northbridge/amd/gx1 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/winbond/w83977f # SUper I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.4 on # RTC / On-Now control - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # IR - # TODO? - end - device pnp 3f0.7 on # GPIO 1 - # TODO? - end - device pnp 3f0.8 on # GPIO 2 - # TODO? - end - end - end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio (onboard) - device pci 12.4 on end # VGA - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end - chip cpu/amd/geode_gx1 # CPU - end -end diff --git a/src/mainboard/advantech/pcm-5820/irq_tables.c b/src/mainboard/advantech/pcm-5820/irq_tables.c deleted file mode 100644 index ac25227..0000000 --- a/src/mainboard/advantech/pcm-5820/irq_tables.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x12 << 3) | 0x0, /* Interrupt router device */ - 0xc00, /* IRQs devoted exclusively to PCI usage */ - 0x1078, /* Vendor */ - 0x2, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xde, /* Checksum */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x0b << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c deleted file mode 100644 index a6b856e..0000000 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> -#include "northbridge/amd/gx1/raminit.c" -#include "cpu/x86/bist.h" -#include "superio/winbond/w83977f/early_serial.c" -#include "southbridge/amd/cs5530/enable_rom.c" - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - cs5530_enable_rom(); - sdram_init(); -} diff --git a/src/mainboard/asi/Kconfig b/src/mainboard/asi/Kconfig deleted file mode 100644 index 29f0895..0000000 --- a/src/mainboard/asi/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if VENDOR_ASI - -choice - prompt "Mainboard model" - -config BOARD_ASI_MB_5BLGP - bool "MB-5BLGP" -config BOARD_ASI_MB_5BLMP - bool "MB-5BLMP" - -endchoice - -source "src/mainboard/asi/mb_5blgp/Kconfig" -source "src/mainboard/asi/mb_5blmp/Kconfig" - -config MAINBOARD_VENDOR - string - default "ASI" - -endif # VENDOR_ASI diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig deleted file mode 100644 index f69f6ef..0000000 --- a/src/mainboard/asi/mb_5blgp/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if BOARD_ASI_MB_5BLGP - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_GEODE_GX1 - select NORTHBRIDGE_AMD_GX1 - select SOUTHBRIDGE_AMD_CS5530 - select SUPERIO_NSC_PC87351 - select ROMCC - select HAVE_PIRQ_TABLE - select PIRQ_ROUTE - select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default asi/mb_5blgp - -config MAINBOARD_PART_NUMBER - string - default "MB-5BLGP" - -config IRQ_SLOT_COUNT - int - default 3 - -endif # BOARD_ASI_MB_5BLGP diff --git a/src/mainboard/asi/mb_5blgp/board_info.txt b/src/mainboard/asi/mb_5blgp/board_info.txt deleted file mode 100644 index 0dcbbea..0000000 --- a/src/mainboard/asi/mb_5blgp/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Board name: MB-5BLGP (Neoware Eon 4000s) -Category: settop diff --git a/src/mainboard/asi/mb_5blgp/devicetree.cb b/src/mainboard/asi/mb_5blgp/devicetree.cb deleted file mode 100644 index d84bf0e..0000000 --- a/src/mainboard/asi/mb_5blgp/devicetree.cb +++ /dev/null @@ -1,55 +0,0 @@ -chip northbridge/amd/gx1 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 on end # Ethernet - device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.e on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # System wake-up control (SWC) - irq 0x60 = 0x500 - end - device pnp 2e.5 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 on # GPIO - irq 0x60 = 0x800 - end - device pnp 2e.8 on # Fan speed control - irq 0x60 = 0x900 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "0" # No connector on this board - end - end - chip cpu/amd/geode_gx1 # CPU - end -end diff --git a/src/mainboard/asi/mb_5blgp/irq_tables.c b/src/mainboard/asi/mb_5blgp/irq_tables.c deleted file mode 100644 index b37e8f9..0000000 --- a/src/mainboard/asi/mb_5blgp/irq_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x12 << 3) | 0x0, /* Interrupt router device */ - 0x8800, /* IRQs devoted exclusively to PCI usage */ - 0x1078, /* Vendor */ - 0x2, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x96, /* Checksum */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */ - {0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */ - {0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */ - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c deleted file mode 100644 index 43c5cf7..0000000 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> -#include "northbridge/amd/gx1/raminit.c" -#include "cpu/x86/bist.h" -#include "superio/nsc/pc87351/early_serial.c" -#include "southbridge/amd/cs5530/enable_rom.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - cs5530_enable_rom(); - sdram_init(); -} diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig deleted file mode 100644 index a40c86c..0000000 --- a/src/mainboard/asi/mb_5blmp/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if BOARD_ASI_MB_5BLMP - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_GEODE_GX1 - select NORTHBRIDGE_AMD_GX1 - select SOUTHBRIDGE_AMD_CS5530 - select SUPERIO_NSC_PC87351 - select ROMCC - select HAVE_PIRQ_TABLE - select PIRQ_ROUTE - select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default asi/mb_5blmp - -config MAINBOARD_PART_NUMBER - string - default "MB-5BLMP" - -config IRQ_SLOT_COUNT - int - default 5 - -endif # BOARD_ASI_MB_5BLMP diff --git a/src/mainboard/asi/mb_5blmp/board_info.txt b/src/mainboard/asi/mb_5blmp/board_info.txt deleted file mode 100644 index da529cb..0000000 --- a/src/mainboard/asi/mb_5blmp/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board name: MB-5BLMP (IGEL WinNET III) -Category: settop -Board URL: http://www.hojerteknik.com/winnet.htm -Flashrom support: y diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb deleted file mode 100644 index e8e6ac3..0000000 --- a/src/mainboard/asi/mb_5blmp/devicetree.cb +++ /dev/null @@ -1,48 +0,0 @@ -chip northbridge/amd/gx1 # Northbridge - device domain 0 on - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 off end # Ethernet (Realtek RTL8139B) - device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.4 on # PS/2 keyboard (+ mouse?) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - # irq 0x72 = 12 - end - device pnp 2e.a on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.e on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.f off # Floppy - io 0x60 = 0x3f2 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.10 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.12 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end - chip cpu/amd/geode_gx1 # CPU - end -end - diff --git a/src/mainboard/asi/mb_5blmp/irq_tables.c b/src/mainboard/asi/mb_5blmp/irq_tables.c deleted file mode 100644 index 01d364d..0000000 --- a/src/mainboard/asi/mb_5blmp/irq_tables.c +++ /dev/null @@ -1,39 +0,0 @@ -/* TODO: This is currently copied from the IEI NOVA-4899R target, but it's - * quite surely wrong for this board. It gets me further in the boot process - * than using no irq_tables.c file at all, though! - */ - -/* TODO: Add license header. */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0xe00, /* IRQs devoted exclusively to PCI usage */ - 0x1078, /* Vendor */ - 0x0002, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x2d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - // USB - {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - // eth0 - {0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x3, 0x0}, - // eth1 - {0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x2, 0x0}, - // eth2 - {0x00,(0x0c<<3)|0x0, {{0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x1, 0x0}, - // PCI slot - {0x00,(0x0f<<3)|0x0, {{0x04, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c deleted file mode 100644 index 1fb3378..0000000 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> -#include "northbridge/amd/gx1/raminit.c" -#include "superio/nsc/pc87351/early_serial.c" -#include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/enable_rom.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - cs5530_enable_rom(); - sdram_init(); -} diff --git a/src/mainboard/axus/Kconfig b/src/mainboard/axus/Kconfig deleted file mode 100644 index cdf807f..0000000 --- a/src/mainboard/axus/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if VENDOR_AXUS - -choice - prompt "Mainboard model" - -config BOARD_AXUS_TC320 - bool "TC320" - -endchoice - -source "src/mainboard/axus/tc320/Kconfig" - -config MAINBOARD_VENDOR - string - default "AXUS" - -endif # VENDOR_AXUS diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig deleted file mode 100644 index 97c33aa..0000000 --- a/src/mainboard/axus/tc320/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if BOARD_AXUS_TC320 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_GEODE_GX1 - select NORTHBRIDGE_AMD_GX1 - select SOUTHBRIDGE_AMD_CS5530 - select SUPERIO_NSC_PC97317 - select ROMCC - select HAVE_PIRQ_TABLE - select PIRQ_ROUTE - select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default axus/tc320 - -config MAINBOARD_PART_NUMBER - string - default "TC320" - -# Soldered NIC, internal USB, no real PCI slots. -config IRQ_SLOT_COUNT - int - default 2 - -endif # BOARD_AXUS_TC320 diff --git a/src/mainboard/axus/tc320/board_info.txt b/src/mainboard/axus/tc320/board_info.txt deleted file mode 100644 index 005c28d..0000000 --- a/src/mainboard/axus/tc320/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: settop -Board URL: http://www.keyton.co.jp/products/UAXT/TC-320.html diff --git a/src/mainboard/axus/tc320/devicetree.cb b/src/mainboard/axus/tc320/devicetree.cb deleted file mode 100644 index 970f71f..0000000 --- a/src/mainboard/axus/tc320/devicetree.cb +++ /dev/null @@ -1,55 +0,0 @@ -chip northbridge/amd/gx1 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe800 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 off end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - # register "ide0_enable" = "1" - # register "ide1_enable" = "1" - end - end - chip cpu/amd/geode_gx1 # CPU - end -end diff --git a/src/mainboard/axus/tc320/irq_tables.c b/src/mainboard/axus/tc320/irq_tables.c deleted file mode 100644 index 71cf2e1..0000000 --- a/src/mainboard/axus/tc320/irq_tables.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * Interrupt routing description for the AXUS TC320 board. - * It was not possible to read back the PIRQ table. There was no BIOS to ask - * for it, only a bootloader for an embedded OS. - * But with the method described here: - * http://coreboot.org/Creating_Valid_IRQ_Tables - * it was possible to detect the physical IRQ routing on this board. - * - * This is the physical routing on this board: - * - * IRQ 5530 USB Network - * controller northbridge device device - * 00.13.0 00.0e.00 - * -------------------------------------------- - * 11 INTA# INTA# n.c. - * 15 INTB# n.c. INTA# - * INTC# n.c. n.c. - * INTD# n.c. n.c. - */ - -#include <arch/pirq_routing.h> - -#define INT_A 0x01 -#define INT_B 0x02 -#define INT_C 0x03 -#define INT_D 0x04 - -/* - * The USB controller should be connected to IRQ11, - * the network controller should be connected to IRQ15. - */ - -#define IRQ_BITMAP_LINK0 0x0800 -#define IRQ_BITMAP_LINK1 0x8000 -#define IRQ_BITMAP_LINK2 0x0000 -#define IRQ_BITMAP_LINK3 0x0000 - -/** Reserved interrupt channels for exclusive PCI usage. */ -#define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK1) - -/** - * Routing description. - * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx - */ -static const struct irq_routing_table intel_irq_routing_table = { - .signature = PIRQ_SIGNATURE, /* PIRQ signature */ - .version = PIRQ_VERSION, /* PIRQ version */ - .size = 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */ - .rtr_bus = 0x00, /* Interrupt router bus */ - .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ - .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ - .rtr_vendor = 0x1078, /* Vendor */ - .rtr_device = 0x0100, /* Device */ - .miniport_data = 0, /* Miniport data */ - .checksum = 0xe3, /* Checksum */ - .slots = { - /* - * Definition for "slot#1". There is no real slot, - * the USB device is embedded... - */ - [0] = { - .bus = 0x00, - .devfn = (0x13 << 3) | 0x0, - .irq = { - /* Link Bitmap */ - [0] = { INT_A, IRQ_BITMAP_LINK0 }, - [1] = { INT_B, IRQ_BITMAP_LINK1 }, - [2] = { INT_C, IRQ_BITMAP_LINK2 }, - [3] = { INT_D, IRQ_BITMAP_LINK3 }, - }, - .slot = 0x0, - }, - /* - * Definition for "slot#2". There is no real slot, - * the network device is soldered... - */ - [1] = { - .bus = 0x00, - .devfn = (0x0e << 3) | 0x0, - .irq = { - /* Link Bitmap */ - [0] = { INT_B, IRQ_BITMAP_LINK1 }, - [1] = { INT_C, IRQ_BITMAP_LINK2 }, - [2] = { INT_D, IRQ_BITMAP_LINK3 }, - [3] = { INT_A, IRQ_BITMAP_LINK0 }, - }, - .slot = 0x0, - } - } -}; - -/** - * Copy the IRQ routing table to memory. - * - * @param[in] addr Destination address (between 0xF0000...0x100000). - * @return TODO. - */ -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c deleted file mode 100644 index 15362e3..0000000 --- a/src/mainboard/axus/tc320/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> -#include "northbridge/amd/gx1/raminit.c" -#include "superio/nsc/pc97317/early_serial.c" -#include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/enable_rom.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - cs5530_enable_rom(); - sdram_init(); -} diff --git a/src/mainboard/bcom/Kconfig b/src/mainboard/bcom/Kconfig index 60945d6..5c7e41b 100644 --- a/src/mainboard/bcom/Kconfig +++ b/src/mainboard/bcom/Kconfig @@ -21,14 +21,11 @@ if VENDOR_BCOM choice prompt "Mainboard model" -config BOARD_BCOM_WINNET100 - bool "WinNET100" config BOARD_BCOM_WINNETP680 bool "WinNET P680" endchoice -source "src/mainboard/bcom/winnet100/Kconfig" source "src/mainboard/bcom/winnetp680/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/bcom/winnet100/Kconfig b/src/mainboard/bcom/winnet100/Kconfig deleted file mode 100644 index 503c92b..0000000 --- a/src/mainboard/bcom/winnet100/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if BOARD_BCOM_WINNET100 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_GEODE_GX1 - select NORTHBRIDGE_AMD_GX1 - select SOUTHBRIDGE_AMD_CS5530 - select SUPERIO_NSC_PC97317 - select ROMCC - select HAVE_PIRQ_TABLE - select PIRQ_ROUTE - select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default bcom/winnet100 - -config MAINBOARD_PART_NUMBER - string - default "WinNET100" - -# Soldered NIC, internal USB, no real PCI slots. -config IRQ_SLOT_COUNT - int - default 2 - -endif # BOARD_BCOM_WINNET100 diff --git a/src/mainboard/bcom/winnet100/board_info.txt b/src/mainboard/bcom/winnet100/board_info.txt deleted file mode 100644 index 85e561a..0000000 --- a/src/mainboard/bcom/winnet100/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: settop -Board name: WinNET100 (IGEL-316) -Board URL: http://web.archive.org/web/20031207003521/http://www.igel.co.za/igel_316_co… -Flashrom support: y diff --git a/src/mainboard/bcom/winnet100/devicetree.cb b/src/mainboard/bcom/winnet100/devicetree.cb deleted file mode 100644 index 61a71e6..0000000 --- a/src/mainboard/bcom/winnet100/devicetree.cb +++ /dev/null @@ -1,56 +0,0 @@ -chip northbridge/amd/gx1 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 on end # Ethernet (onboard) - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, Advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 (used for smartcard reader) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe8 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "0" # Not available/needed on this board - end - end - chip cpu/amd/geode_gx1 # CPU - end -end diff --git a/src/mainboard/bcom/winnet100/irq_tables.c b/src/mainboard/bcom/winnet100/irq_tables.c deleted file mode 100644 index 8d9e157..0000000 --- a/src/mainboard/bcom/winnet100/irq_tables.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * Interrupt routing description for BCOM's Winnet100 board. - * It was not possible to read back the pirq-Table. In the 0xF segment was - * no string like $PIRQ... - * But the already running 2.4.21 kernel provides eth0 IRQ15 and USB IRQ 11. - * The Realtek was device 0.f.0, the USB 0.13.0. - * - * This is the physical routing on this board: - * - * 5530 USB Network - * northbridge device device - * 00.13.0 00.0f.00 - * ------------------------------------ - * INTA# INTA# n.c. - * INTB# n.c. n.c. - * INTC# n.c. INTA# - * INTD# n.c. n.c. - */ - -#include <arch/pirq_routing.h> - -#define INT_A 0x01 -#define INT_B 0x02 -#define INT_C 0x03 -#define INT_D 0x04 - -/* - * The USB controller should be connected to IRQ11, - * the network controller should be connected to IRQ15. - */ -#define IRQ_BITMAP_LINK0 0x0800 -#define IRQ_BITMAP_LINK1 0x0400 -#define IRQ_BITMAP_LINK2 0x8000 -#define IRQ_BITMAP_LINK3 0x0200 - -/** Reserved interrupt channels for exclusive PCI usage. */ -#define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK2) - -/** - * Routing description. - * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx - */ -static const struct irq_routing_table intel_irq_routing_table = { - .signature = PIRQ_SIGNATURE, /* PIRQ signature */ - .version = PIRQ_VERSION, /* PIRQ version */ - .size = 32 +16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */ - .rtr_bus = 0x00, /* Interrupt router bus */ - .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ - .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ - .rtr_vendor = 0x1078, /* Vendor */ - .rtr_device = 0x0100, /* Device */ - .miniport_data = 0, /* Miniport data */ - .checksum = 0xbf + 16, /* Checksum */ - .slots = { - /* - * Definition for "slot#1". There is no real slot, - * the USB device is embedded... - */ - [0] = { - .bus = 0x00, - .devfn = (0x13 << 3) | 0x0, - .irq = { - /* Link Bitmap */ - [0] = { INT_A, IRQ_BITMAP_LINK0 }, - [1] = { INT_B, IRQ_BITMAP_LINK1 }, - [2] = { INT_C, IRQ_BITMAP_LINK2 }, - [3] = { INT_D, IRQ_BITMAP_LINK3 }, - }, - .slot = 0x0, - }, - - /* - * Definition for "slot#3". There is no real slot, - * the network device is soldered... - */ - [1] = { - .bus = 0x00, - .devfn = (0x0f << 3) | 0x0, - .irq = { - /* Link Bitmap */ - [0] = { INT_C, IRQ_BITMAP_LINK2 }, - [1] = { INT_D, IRQ_BITMAP_LINK3 }, - [2] = { INT_A, IRQ_BITMAP_LINK0 }, - [3] = { INT_B, IRQ_BITMAP_LINK1 }, - }, - .slot = 0x0, - } - } -}; - -/** - * Copy the IRQ routing table to memory. - * - * @param[in] addr Destination address (between 0xF0000...0x100000). - * @return TODO. - */ -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c deleted file mode 100644 index 15362e3..0000000 --- a/src/mainboard/bcom/winnet100/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> -#include "northbridge/amd/gx1/raminit.c" -#include "superio/nsc/pc97317/early_serial.c" -#include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/enable_rom.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - cs5530_enable_rom(); - sdram_init(); -} diff --git a/src/mainboard/bifferos/Kconfig b/src/mainboard/bifferos/Kconfig deleted file mode 100644 index de6fb5c..0000000 --- a/src/mainboard/bifferos/Kconfig +++ /dev/null @@ -1,36 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -if VENDOR_BIFFEROS - -choice - prompt "Mainboard model" - -config BOARD_BIFFEROS_BIFFERBOARD - bool "Bifferboard" - -endchoice - -source "src/mainboard/bifferos/bifferboard/Kconfig" - -config MAINBOARD_VENDOR - string - default "Bifferos" - -endif # VENDOR_BIFFEROS diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig deleted file mode 100644 index 9d00f5e..0000000 --- a/src/mainboard/bifferos/bifferboard/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -if BOARD_BIFFEROS_BIFFERBOARD - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ROMCC - select BOARD_ROMSIZE_KB_128 - select NORTHBRIDGE_RDC_R8610 - select SOUTHBRIDGE_RDC_R8610 - -config MAINBOARD_DIR - string - default bifferos/bifferboard - -config MAINBOARD_PART_NUMBER - string - default "Bifferboard" - -endif # BOARD_BIFFEROS_BIFFERBOARD diff --git a/src/mainboard/bifferos/bifferboard/board_info.txt b/src/mainboard/bifferos/bifferboard/board_info.txt deleted file mode 100644 index 7680e6f..0000000 --- a/src/mainboard/bifferos/bifferboard/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: half diff --git a/src/mainboard/bifferos/bifferboard/devicetree.cb b/src/mainboard/bifferos/bifferboard/devicetree.cb deleted file mode 100644 index 09dde33..0000000 --- a/src/mainboard/bifferos/bifferboard/devicetree.cb +++ /dev/null @@ -1,8 +0,0 @@ -chip northbridge/rdc/r8610 - device domain 0 on - device pci 0.0 on end - chip southbridge/rdc/r8610 # Southbridge - device pci 7.0 on end # SB - end - end -end diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c deleted file mode 100644 index dd2553e..0000000 --- a/src/mainboard/bifferos/bifferboard/romstage.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/x86/cache.h> - -static void main(void) -{ - uint32_t tmp; - post_code(0x05); - - /* Set timer1 to pulse generator 15us for memory refresh */ - outb(0x54, 0x43); - outb(0x12, 0x41); - - /* CPU setup, romcc pukes on invd() */ - asm volatile ("invd"); - enable_cache(); - - /* Set serial base */ - pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8); - /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */ - pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012); - - console_init(); - - /* memory init */ - pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f); - pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451); - pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003); - - /* memory phase/buffer strength for read and writes */ - tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64); - tmp &= 0x0FF00FFFF; - tmp |= 0x790000; - pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp); - /* Route Cseg, Dseg, Eseg and Fseg to RAM */ - pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ffffff0); -} diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig index 9f490b0..8aff47c 100644 --- a/src/mainboard/digitallogic/Kconfig +++ b/src/mainboard/digitallogic/Kconfig @@ -5,15 +5,12 @@ choice config BOARD_DIGITALLOGIC_ADL855PC bool "smartModule855" -config BOARD_DIGITALLOGIC_MSM586SEG - bool "MSM586SEG" config BOARD_DIGITALLOGIC_MSM800SEV bool "MSM800SEV" endchoice source "src/mainboard/digitallogic/adl855pc/Kconfig" -source "src/mainboard/digitallogic/msm586seg/Kconfig" source "src/mainboard/digitallogic/msm800sev/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/digitallogic/msm586seg/Kconfig b/src/mainboard/digitallogic/msm586seg/Kconfig deleted file mode 100644 index 4cd6f11..0000000 --- a/src/mainboard/digitallogic/msm586seg/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if BOARD_DIGITALLOGIC_MSM586SEG - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SC520 - select HAVE_PIRQ_TABLE - select HAVE_OPTION_TABLE - select BOARD_ROMSIZE_KB_512 - select ROMCC - -config MAINBOARD_DIR - string - default digitallogic/msm586seg - -config MAINBOARD_PART_NUMBER - string - default "MSM586SEG" - -config IRQ_SLOT_COUNT - int - default 2 - -endif # BOARD_DIGITALLOGIC_MSM586SEG diff --git a/src/mainboard/digitallogic/msm586seg/board_info.txt b/src/mainboard/digitallogic/msm586seg/board_info.txt deleted file mode 100644 index 90fda6d..0000000 --- a/src/mainboard/digitallogic/msm586seg/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: half -Board URL: http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?… diff --git a/src/mainboard/digitallogic/msm586seg/cmos.layout b/src/mainboard/digitallogic/msm586seg/cmos.layout deleted file mode 100644 index 9050c3d..0000000 --- a/src/mainboard/digitallogic/msm586seg/cmos.layout +++ /dev/null @@ -1,72 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/digitallogic/msm586seg/devicetree.cb b/src/mainboard/digitallogic/msm586seg/devicetree.cb deleted file mode 100644 index e43ebff..0000000 --- a/src/mainboard/digitallogic/msm586seg/devicetree.cb +++ /dev/null @@ -1,7 +0,0 @@ -chip cpu/amd/sc520 - device domain 0 on - device pci 0.0 on end - device pci 12.0 on end # enet - device pci 14.0 on end # 69000 - end -end diff --git a/src/mainboard/digitallogic/msm586seg/irq_tables.c b/src/mainboard/digitallogic/msm586seg/irq_tables.c deleted file mode 100644 index 15dcddd..0000000 --- a/src/mainboard/digitallogic/msm586seg/irq_tables.c +++ /dev/null @@ -1,31 +0,0 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0}, - {0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0}, - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c deleted file mode 100644 index 0310176..0000000 --- a/src/mainboard/digitallogic/msm586seg/mainboard.c +++ /dev/null @@ -1,133 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/amd/sc520.h> - - -static void irqdump(void) -{ - volatile unsigned char *irq; - void *mmcr; - int i; - int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, - 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, - 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, - 0xd30, 0xd31, 0xd32, 0xd33, - 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, - 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, - -1}; - mmcr = (void *) 0xfffef000; - - printk(BIOS_ERR, "mmcr is %p\n", mmcr); - for(i = 0; irqlist[i] >= 0; i++) { - irq = mmcr + irqlist[i]; - printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq); - } - -} - -/* TODO: finish up mmcr struct in sc520.h, and; - - set ADDDECTL (now done in raminit.c in cpu/amd/sc520 -*/ -static void mainboard_enable(struct device *dev) -{ - //volatile struct mmcrpic *pic = MMCRPIC; - volatile struct mmcr *mmcr = MMCRDEFAULT; - - /* msm586seg has this register set to a weird value. - * follow the board, not the manual! - */ - - /* currently, nothing in the device to use, so ignore it. */ - printk(BIOS_ERR, "digital logic msm586 seg ENTER %s\n", __func__); - - - /* from fuctory bios */ - /* NOTE: the following interrupt settings made interrupts work - * for hard drive, and serial, but not for ethernet - */ - /* just do what they say and nobody gets hurt. */ - mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE; - /* all ints to level */ - mmcr->pic.mpicmode = 0; - mmcr->pic.sl1picmode = 0; - mmcr->pic.sl2picmode = 0x80; - - mmcr->pic.intpinpol = 0; - - mmcr->pic.pit0map = 1; - mmcr->pic.uart1map = 0xc; - mmcr->pic.uart2map = 0xb; - mmcr->pic.rtcmap = 3; - mmcr->pic.ferrmap = 8; - mmcr->pic.gp0imap = 6; - mmcr->pic.gp1imap = 2; - mmcr->pic.gp2imap = 7; - mmcr->pic.gp6imap = 0x15; - mmcr->pic.gp7imap = 0x16; - mmcr->pic.gp10imap = 0x9; - mmcr->pic.gp9imap = 0x4; - - irqdump(); - printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0); - - printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20); - printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22); - - /* The following block has NOT proven sufficient to get - * the VGA hardware to talk to us - */ - /* let's set some mmcr stuff per the BIOS settings */ - mmcr->dbctl.dbctl = 0x10; - mmcr->sysarb.ctl = 6; - mmcr->sysarb.menb = 0xf; - mmcr->sysarb.prictl = 0xc0000f0f; - /* this is bios setting, depends on sysarb above */ - mmcr->hostbridge.ctl = 0x108; - printk(BIOS_ERR, "digital logic msm586 seg EXIT %s\n", __func__); - - /* pio */ - mmcr->pio.data31_16 = 0xffbf; - - /* pci stuff */ - mmcr->pic.pciintamap = 0xa; - - /* END block where vga hardware still will not talk to us */ - /* all we get from VGA I/O addresses are ffff etc. - */ - mmcr->sysmap.adddecctl = 0x10; - - /* VGA now talks to us, so this adddecctl was the trick. - * still no interrupts from enet. - * Let's try fixing the piodata stuff, as there may be - * some wire there not documented. - */ - mmcr->pio.data31_16 = 0xffbf; - /* also, our sl?picmode needs to match fuctory bios */ - mmcr->pic.sl1picmode = 0x80; - mmcr->pic.sl2picmode = 0x0; - /* and, finally, they do set gp5imap and we don't. - */ - mmcr->pic.gp5imap = 0xd; - /* remaining problem: almost certainly, the irq table is bogus - * NO SHOCK as it came from fuctory bios. - * but let's try these 4 changes for now and see what shakes. - */ - /* still not interrupts. */ - /* their IRQ table is wrong. Just hardwire it */ - { - unsigned char pciints[4] = {15, 15, 15, 15}; - pci_assign_irqs(0, 12, pciints); - } - /* the assigned failed but we just noticed -- there is no - * dma mapping, and selftest on e100 requires that dma work - */ - /* follow fuctory here */ - mmcr->dmacontrol.extchanmapa = 0x3210; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c deleted file mode 100644 index ab944a4..0000000 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ /dev/null @@ -1,240 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include "cpu/x86/bist.h" - -void setup_pars(void) -{ - volatile unsigned long *par; - /* as per the book: */ - /* PAR register setup */ - /* set up the PAR registers as they are on the MSM586SEG */ - par = (unsigned long *) 0xfffef088; - - /* NOTE: move this to mainboard.c ASAP */ - *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/ - *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/ - *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/ - *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/ - *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/ - *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/ - *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/ - *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/ - *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/ - *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/ - *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/ - *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/ - *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/ - *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/ - *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/ - *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/ -} - -#include "cpu/amd/sc520/raminit.c" - -struct mem_controller { - int i; -}; - -static int spd_read_byte(unsigned device, unsigned address) { } - -static inline void dumpmem(void){ - int i, j; - unsigned char *l; - unsigned char c; - - for(i = 0x4000; i < 0x5000; i += 16) { - print_err_hex32(i); print_err(":"); - for(j = 0; j < 16; j++) { - l = (unsigned char *)i + j; - c = *l; - print_err_hex8(c); - print_err(" "); - } - print_err("\n"); - } -} - -static inline void irqinit(void){ - volatile unsigned char *cp; -#if 0 -/* these values taken from the msm board itself. - * and they cause the board to not even come out of calibrating_delay_loop - * if you can believe it. Our problem right now is no IDE or serial interrupts - * So we'll try to put interrupts in, one at a time. IDE first. - */ - cp = (volatile unsigned char *) 0xfffefd00; - *cp = 0x11; - cp = (volatile unsigned char *) 0xfffefd02; - *cp = 0x02; - cp = (volatile unsigned char *) 0xfffefd03; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd04; - *cp = 0xf7; - cp = (volatile unsigned char *) 0xfffefd08; - *cp = 0xf7; - cp = (volatile unsigned char *) 0xfffefd0a; - *cp = 0x8b; - cp = (volatile unsigned char *) 0xfffefd10; - *cp = 0x18; - cp = (volatile unsigned char *) 0xfffefd14; - *cp = 0x09; - cp = (volatile unsigned char *) 0xfffefd18; - *cp = 0x88; - cp = (volatile unsigned char *) 0xfffefd1a; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd1b; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd1c; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd20; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd21; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd22; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd28; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd29; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd30; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd31; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd32; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd33; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd40; - *cp = 0x10; - cp = (volatile unsigned char *) 0xfffefd41; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd42; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd43; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd44; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd45; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd46; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd50; - *cp = 0x37; - cp = (volatile unsigned char *) 0xfffefd51; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd52; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd53; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd54; - *cp = 0x37; - cp = (volatile unsigned char *) 0xfffefd55; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd56; - *cp = 0x37; - cp = (volatile unsigned char *) 0xfffefd57; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd58; - *cp = 0xff; - cp = (volatile unsigned char *) 0xfffefd59; - *cp = 0xff; - cp = (volatile unsigned char *) 0xfffefd5a; - *cp = 0xff; -#endif -#if 0 - /* this fails too */ - /* IDE only ... */ - cp = (volatile unsigned char *) 0xfffefd56; - *cp = 0xe; -#endif -} - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - volatile int i; - for(i = 0; i < 100; i++) - ; - - setupsc520(); - irqinit(); - console_init(); - for(i = 0; i < 100; i++) - print_err("fill usart\n"); - // while(1) - print_err("HI THERE!\n"); - // sizemem(); - staticmem(); - -/* Void warranty when label is removed. */ -dummy_romcc_workaround_label: - do { } while (0); - - print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); - print_err("\n"); - - // while(1) - print_err("STATIC MEM DONE\n"); - post_code(0xee); - print_err("loop forever ...\n"); - -#if 0 - - /* clear memory 1meg */ - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $4,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (1024*1024) - ); - - -#endif - -#if 0 - dump_pci_devices(); -#endif -#if 0 - dump_pci_device(PCI_DEV(0, 0, 0)); -#endif - -#if 1 - { - volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000; - volatile unsigned char *dst = (unsigned char *) 0x4000; - for(i = 0; i < 0x20000; i++) { - /* - print_err("Set dst "); print_err_hex32((unsigned long) dst); - print_err(" to "); print_err_hex32(*src); print_err("\n"); - */ - *dst = *src; - //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n"); - dst++, src++; - post_code(i & 0xff); - } - } - dumpmem(); - post_code(0x00); - - print_err("loop forever\n"); - post_code(0xdd); - __asm__ volatile( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - : - : "a" (0x4000) - ); - - print_err("Oh dear, I'm afraid it didn't work...\n"); - - while(1); -#endif -} diff --git a/src/mainboard/technologic/Kconfig b/src/mainboard/technologic/Kconfig deleted file mode 100644 index 792dc5e..0000000 --- a/src/mainboard/technologic/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if VENDOR_TECHNOLOGIC - -choice - prompt "Mainboard model" - -config BOARD_TECHNOLOGIC_TS5300 - bool "TS-5300" - -endchoice - -source "src/mainboard/technologic/ts5300/Kconfig" - -config MAINBOARD_VENDOR - string - default "Technologic" - -endif # VENDOR_TECHNOLOGIC diff --git a/src/mainboard/technologic/ts5300/Kconfig b/src/mainboard/technologic/ts5300/Kconfig deleted file mode 100644 index 0006fd7..0000000 --- a/src/mainboard/technologic/ts5300/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if BOARD_TECHNOLOGIC_TS5300 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SC520 - select ROMCC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_1024 - -config MAINBOARD_DIR - string - default technologic/ts5300 - -config MAINBOARD_PART_NUMBER - string - default "TS-5300" - -config IRQ_SLOT_COUNT - int - default 2 - -endif # BOARD_TECHNOLOGIC_TS5300 diff --git a/src/mainboard/technologic/ts5300/board_info.txt b/src/mainboard/technologic/ts5300/board_info.txt deleted file mode 100644 index ef8a731..0000000 --- a/src/mainboard/technologic/ts5300/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: half -Board URL: http://www.embeddedarm.com/epc/ts5300-spec-h.html diff --git a/src/mainboard/technologic/ts5300/cmos.layout b/src/mainboard/technologic/ts5300/cmos.layout deleted file mode 100644 index 9050c3d..0000000 --- a/src/mainboard/technologic/ts5300/cmos.layout +++ /dev/null @@ -1,72 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/technologic/ts5300/devicetree.cb b/src/mainboard/technologic/ts5300/devicetree.cb deleted file mode 100644 index 6c83e20..0000000 --- a/src/mainboard/technologic/ts5300/devicetree.cb +++ /dev/null @@ -1,6 +0,0 @@ -chip cpu/amd/sc520 - device domain 0 on - device pci 0.0 on end - end - -end diff --git a/src/mainboard/technologic/ts5300/irq_tables.c b/src/mainboard/technologic/ts5300/irq_tables.c deleted file mode 100644 index 15dcddd..0000000 --- a/src/mainboard/technologic/ts5300/irq_tables.c +++ /dev/null @@ -1,31 +0,0 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0}, - {0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0}, - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c deleted file mode 100644 index 20b893e..0000000 --- a/src/mainboard/technologic/ts5300/mainboard.c +++ /dev/null @@ -1,147 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/amd/sc520.h> - - -#if 0 -static void irqdump(void) -{ - volatile unsigned char *irq; - void *mmcr; - - - int i; - int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, - 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, - 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, - 0xd30, 0xd31, 0xd32, 0xd33, - 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, - 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, - -1}; - mmcr = (void *) 0xfffef000; - - printk(BIOS_ERR, "mmcr is %p\n", mmcr); - for(i = 0; irqlist[i] >= 0; i++) { - irq = mmcr + irqlist[i]; - printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq); - } - -} -#endif - -/* TODO: finish up mmcr struct in sc520.h, and; - - set ADDDECTL (now done in raminit.c in cpu/amd/sc520 -*/ -static void mainboard_enable(struct device *dev) -{ - volatile struct mmcr *mmcr = MMCRDEFAULT; - - /* currently, nothing in the device to use, so ignore it. */ - printk(BIOS_ERR, "Technologic Systems 5300 ENTER %s\n", __func__); - - /* from fuctory bios */ - /* NOTE: the following interrupt settings made interrupts work - * for hard drive, and serial, but not for ethernet - */ - - printk(BIOS_ERR, "Setting up PIC\n"); - /* just do what they say and nobody gets hurt. */ - mmcr->pic.pcicr = 0 ; - /* all ints to level */ - mmcr->pic.mpicmode = 0; - mmcr->pic.sl1picmode = 0; - mmcr->pic.sl2picmode = 0; - - mmcr->pic.intpinpol = 0x100; - - mmcr->pic.pit0map = 1; - mmcr->pic.uart1map = 0x0c; - mmcr->pic.uart2map = 0x0b; - mmcr->pic.rtcmap = 0x03; - mmcr->pic.ferrmap = 0x00; - mmcr->pic.intpinpol = 0x100; - - mmcr->pic.gp0imap = 0x00; - mmcr->pic.gp1imap = 0x02; - mmcr->pic.gp2imap = 0x07; - mmcr->pic.gp3imap = 0x05; - mmcr->pic.gp4imap = 0x06; - mmcr->pic.gp5imap = 0x0d; - mmcr->pic.gp6imap = 0x15; - mmcr->pic.gp7imap = 0x16; - mmcr->pic.gp8imap = 0x3; - mmcr->pic.gp9imap = 0x4; - mmcr->pic.gp10imap = 0x9; - - // irqdump(); - - printk(BIOS_ERR, "Setting up sysarb\n"); - mmcr->dbctl.dbctl = 0x01; - mmcr->sysarb.ctl = 0x00; - mmcr->sysarb.menb = 0x1f; - mmcr->sysarb.prictl = 0x40000f0f; - - /* this is bios setting, depends on sysarb above */ - mmcr->hostbridge.ctl = 0x0; - mmcr->hostbridge.tgtirqctl = 0x0; - mmcr->hostbridge.tgtirqsta = 0xf00; - mmcr->hostbridge.mstirqctl = 0x0; - mmcr->hostbridge.mstirqsta = 0x708; - - printk(BIOS_ERR, "Setting up pio\n"); - /* pio */ - mmcr->pio.pfs15_0 = 0xffff; - mmcr->pio.pfs31_16 = 0xffff; - mmcr->pio.cspfs = 0xfe; - mmcr->pio.clksel = 0x13; - mmcr->pio.dsctl = 0x200; - mmcr->pio.data15_0 = 0xde04; - mmcr->pio.data31_16 = 0xef9f; - - printk(BIOS_ERR, "Setting up sysmap\n"); - /* system memory map */ - mmcr->sysmap.adddecctl = 0x04; - mmcr->sysmap.wpvsta = 0x8006; - mmcr->sysmap.par[1] = 0x340f0070; - mmcr->sysmap.par[2] = 0x380701f0; - mmcr->sysmap.par[3] = 0x3c0103f6; - mmcr->sysmap.par[4] = 0x2c0f0300; - mmcr->sysmap.par[5] = 0x447c00a0; - mmcr->sysmap.par[6] = 0xe600000c; - mmcr->sysmap.par[7] = 0x300046e8; - mmcr->sysmap.par[8] = 0x500400d0; - mmcr->sysmap.par[9] = 0x281f0140; - mmcr->sysmap.par[13] = 0x8a07c940; - mmcr->sysmap.par[15] = 0xee00400e; - - printk(BIOS_ERR, "Setting up gpctl\n"); - mmcr->gpctl.gpcsrt = 0x01; - mmcr->gpctl.gpcspw = 0x09; - mmcr->gpctl.gpcsoff = 0x01; - mmcr->gpctl.gprdw = 0x07; - mmcr->gpctl.gprdoff = 0x02; - mmcr->gpctl.gpwrw = 0x07; - mmcr->gpctl.gpwroff = 0x02; - - //mmcr->reset.sysinfo = 0xdf; - //mmcr->reset.rescfg = 0x5; - /* their IRQ table is wrong. Just hardwire it */ - //{ - // char pciints[4] = {15, 15, 15, 15}; - // pci_assign_irqs(0, 12, pciints); - //} - /* the assigned failed but we just noticed -- there is no - * dma mapping, and selftest on e100 requires that dma work - */ - mmcr->dmacontrol.extchanmapa = 0xf210; - mmcr->dmacontrol.extchanmapb = 0xffff; - - printk(BIOS_ERR, "TS5300 EXIT %s\n", __func__); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c deleted file mode 100644 index 5d33bae..0000000 --- a/src/mainboard/technologic/ts5300/romstage.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * TS5300 specific initialization code. - * written by Stefan Reinauer <stepan(a)coresystems.de> - * (c) 2006 coresystems GmbH - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include "cpu/x86/bist.h" - -#define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77) -#define TS5300_LED_ON outb((inb(0x77)|1), 0x77) - -#define TS9500_LED_OFF outb((inb(0x19a)&0xfe), 0x19a) -#define TS9500_LED_ON outb((inb(0x19a)|1), 0x19a) - -/* PAR register setup */ -void setup_pars(void) -{ - volatile unsigned long *par; - par = (unsigned long *) 0xfffef088; - - /* NOTE: Ron says, move this to mainboard.c */ - *par++ = 0x00000000; - *par++ = 0x340f0070; - *par++ = 0x380701f0; - *par++ = 0x3c0103f6; - *par++ = 0x2c0f0300; - *par++ = 0x447c00a0; - *par++ = 0xe600000c; - *par++ = 0x300046e8; - *par++ = 0x500400d0; - *par++ = 0x281f0140; - *par++ = 0x00000000; - *par++ = 0x00000000; - *par++ = 0x00000000; - *par++ = 0x8a07c940; /* Flash setup */ - *par++ = 0x00000000; - *par++ = 0xee00400e; -} - -#include "cpu/amd/sc520/raminit.c" - -static void identify_ts9500(void) -{ - unsigned i, val; - - TS9500_LED_ON; - - print_err("TS-9500 add-on found:\n"); - val=inb(0x19b); - for (i=0; i<8; i++) { - print_err(" DIP"); - print_err_char(i+0x31); - print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); - else - print_err("off\n"); - } - print_err("\n"); - - val=inb(0x19a); - - for (i=6; i<8; i++) { - print_err(" JP"); - print_err_char(i+0x30-5); - print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); - else - print_err("off\n"); - } - print_err("\n"); - - TS9500_LED_OFF; -} - -static void identify_system(void) -{ - unsigned i,val; - - print_err("Mainboard: "); - val=inb(0x74); - switch(val) { - case 0x50: print_err("TS-5300\n"); break; - case 0x40: print_err("TS-5400\n"); break; - case 0x60: print_err("TS-5500\n"); break; - case 0x20: print_err("TS-5600\n"); break; - case 0x70: print_err("TS-5700\n"); break; - default: print_err("unknown\n"); break; - } - - val=inb(0x75); - print_err(" SRAM option: "); - if((val&1)==0) print_err("not "); - print_err("installed\n"); - - print_err(" RS-485 option: "); - if((val&2)==0) print_err("not "); - print_err("installed\n"); - - val=inb(0x76); - print_err(" Temp. range: "); - if((val&2)==0) print_err("commercial\n"); - else print_err("industrial\n"); - - print_err("\n"); - - val=inb(0x77); - for (i=1; i<8; i++) { - print_err(" JP"); - print_err_char(i+0x30); - print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); - else - print_err("off\n"); - } - print_err("\n"); - - /* Detect TS-9500 */ - val=inb(0x19d); - if(val==0x5f) - identify_ts9500(); -} - -static void hard_reset(void) -{ - print_err("Hard reset called.\n"); - while (1) ; -} - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - volatile int i; - unsigned val; - - TS5300_LED_ON; - - // Let the hardware settle a bit. - for(i = 0; i < 100; i++) - ; - - setupsc520(); - console_init(); - - - print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n"); - staticmem(); - -/* Void warranty when label is removed. */ -dummy_romcc_workaround_label: - do { } while (0); - - print_err("Memory initialized: 32MB\n"); - -#if 1 - identify_system(); -#endif - - TS5300_LED_OFF; -} diff --git a/src/mainboard/televideo/Kconfig b/src/mainboard/televideo/Kconfig deleted file mode 100644 index aa2f5a1..0000000 --- a/src/mainboard/televideo/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if VENDOR_TELEVIDEO - -choice - prompt "Mainboard model" - -config BOARD_TELEVIDEO_TC7020 - bool "TC7020" - -endchoice - -source "src/mainboard/televideo/tc7020/Kconfig" - -config MAINBOARD_VENDOR - string - default "TeleVideo" - -endif # VENDOR_TELEVIDEO diff --git a/src/mainboard/televideo/tc7020/Kconfig b/src/mainboard/televideo/tc7020/Kconfig deleted file mode 100644 index 6d77f59..0000000 --- a/src/mainboard/televideo/tc7020/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -if BOARD_TELEVIDEO_TC7020 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_GEODE_GX1 - select NORTHBRIDGE_AMD_GX1 - select SOUTHBRIDGE_AMD_CS5530 - select SUPERIO_NSC_PC97317 - select ROMCC - select HAVE_PIRQ_TABLE - select PIRQ_ROUTE - select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default televideo/tc7020 - -config MAINBOARD_PART_NUMBER - string - default "TC7020" - -config IRQ_SLOT_COUNT - int - default 3 - -endif # BOARD_TELEVIDEO_TC7020 diff --git a/src/mainboard/televideo/tc7020/board_info.txt b/src/mainboard/televideo/tc7020/board_info.txt deleted file mode 100644 index 93e6c5c..0000000 --- a/src/mainboard/televideo/tc7020/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: settop -Board URL: http://www.televideo.com/TeleVideo/TC7000_WinCE_Series.htm diff --git a/src/mainboard/televideo/tc7020/devicetree.cb b/src/mainboard/televideo/tc7020/devicetree.cb deleted file mode 100644 index d1fa6bd..0000000 --- a/src/mainboard/televideo/tc7020/devicetree.cb +++ /dev/null @@ -1,57 +0,0 @@ -chip northbridge/amd/gx1 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, Advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe8 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - device pci 14.0 on end # MiniPCI slot - device pci 15.0 on end # Ethernet (onboard) - register "ide0_enable" = "1" - register "ide1_enable" = "0" # Not available/needed on this board - end - end - chip cpu/amd/geode_gx1 # CPU - end -end diff --git a/src/mainboard/televideo/tc7020/irq_tables.c b/src/mainboard/televideo/tc7020/irq_tables.c deleted file mode 100644 index 5eef0c0..0000000 --- a/src/mainboard/televideo/tc7020/irq_tables.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> - * Copyright (C) 2007 Kenji Noguchi <tokyo246(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci.h> - -/* Platform IRQs */ -#define PIRQA 11 -#define PIRQB 10 -#define PIRQC 9 -#define PIRQD 12 - -/* Link */ -#define LINK_PIRQA 1 -#define LINK_PIRQB 2 -#define LINK_PIRQC 3 -#define LINK_PIRQD 4 -#define LINK_NONE 0 - -/* Map */ -#define IRQ_BITMAP_LINKA (1 << PIRQA) -#define IRQ_BITMAP_LINKB (1 << PIRQB) -#define IRQ_BITMAP_LINKC (1 << PIRQC) -#define IRQ_BITMAP_LINKD (1 << PIRQD) -#define IRQ_BITMAP_NOLINK 0x0 - -#define EXCLUSIVE_PCI_IRQS (IRQ_BITMAP_LINKA | IRQ_BITMAP_LINKB | IRQ_BITMAP_LINKC | IRQ_BITMAP_LINKD) - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be a total of CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ - EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */ - 0x1078, /* Vendor */ - 0x1, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x60, /* u8 checksum. This has to be set to some - value that would give 0 after the sum of all - bytes for this structure (including checksum) */ - - .slots = { - [0] = { - .slot = 0x0, /* means also "on board" */ - .bus = 0x00, - .devfn = (0x13<<3)|0x0, /* 0x13 is USB OHCI */ - .irq = { - [0] = { /* <-- 0 means this is INTA# output from the device or slot */ - .link = LINK_PIRQA, - .bitmap = IRQ_BITMAP_LINKA - }, - [1] = { /* <-- 1 means this is INTB# output from the device or slot */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - }, - [2] = { /* <-- 2 means this is INTC# output from the device or slot */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - }, - [3] = { /* <-- 3 means this is INTD# output from the device or slot */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - } - } - }, - - [1] = { - .slot = 0x0, /* means also "on board" */ - .bus = 0x00, - .devfn = (0x15<<3)|0x0, /* 0x15 is NSC Network device */ - .irq = { - [0] = { /* <-- 0 means this is INTA# output from the device or slot */ - .link = LINK_PIRQB, - .bitmap = IRQ_BITMAP_LINKB - }, - [1] = { /* <-- 1 means this is INTB# output from the device or slot */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - }, - [2] = { /* <-- 2 means this is INTC# output from the device or slot */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - }, - [3] = { /* <-- 3 means this is INTD# output from the device or slot */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - } - } - }, - - [2] = { - .slot = 0x1, /* This is a Mini PCI slot */ - .bus = 0x00, - .devfn = (0x14<<3)|0x0, - .irq = { - [0] = { /* <-- 0 means this is INTA# output from the device or slot */ - .link = LINK_PIRQC, - .bitmap = IRQ_BITMAP_LINKC - }, - [1] = { /* <-- 1 means this is INTB# output from the device or slot */ - /* NEEDSWORK: not confirmed. No device to test which uses both INTA and INTB */ - .link = LINK_PIRQD, - .bitmap = IRQ_BITMAP_LINKD - }, - [2] = { /* No INTC# for Mini PCI */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - }, - [3] = { /* No INTD# for Mini PCI */ - .link = LINK_NONE, - .bitmap = IRQ_BITMAP_NOLINK - } - } - }, - } -}; - -/** - * Copy the IRQ routing table to memory. - * - * @param addr Destination address (between 0xF0000...0x100000). - * @return The end address of the pirq routing table in memory. - */ -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c deleted file mode 100644 index 15362e3..0000000 --- a/src/mainboard/televideo/tc7020/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> -#include "northbridge/amd/gx1/raminit.c" -#include "superio/nsc/pc97317/early_serial.c" -#include "cpu/x86/bist.h" -#include "southbridge/amd/cs5530/enable_rom.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - cs5530_enable_rom(); - sdram_init(); -}

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New patch to review for coreboot: b855c6a lpc.c TEST
by Edward O'Callaghan 05 Nov '14

05 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7345 -gerrit commit b855c6afde4ef490e4f6ba10052a3258c2cc7cb0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Nov 6 09:11:02 2014 +1100 lpc.c TEST Change-Id: Id3d86112919a6076d34fd2ad6e2440f3827335ef Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/cx700/lpc.c | 8 ++++---- src/northbridge/via/vx800/lpc.c | 6 +++--- src/northbridge/via/vx900/lpc.c | 14 +++++++------- src/southbridge/amd/agesa/hudson/lpc.c | 12 ++++++------ src/southbridge/amd/amd8111/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb700/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb700/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb800/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb900/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb900/lpc.h | 6 +++--- src/southbridge/amd/sb600/lpc.c | 12 ++++++------ src/southbridge/amd/sb700/lpc.c | 12 ++++++------ src/southbridge/amd/sb800/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/intel/bd82x6x/lpc.c | 18 +++++++++--------- src/southbridge/intel/esb6300/lpc.c | 22 +++++++++++----------- src/southbridge/intel/fsp_bd82x6x/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_rangeley/lpc.c | 16 ++++++++-------- src/southbridge/intel/i3100/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i82801ax/lpc.c | 10 +++++----- src/southbridge/intel/i82801bx/lpc.c | 10 +++++----- src/southbridge/intel/i82801cx/lpc.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 10 +++++----- src/southbridge/intel/i82801ex/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i82801gx/lpc.c | 16 ++++++++-------- src/southbridge/intel/i82801ix/lpc.c | 14 +++++++------- src/southbridge/intel/ibexpeak/lpc.c | 18 +++++++++--------- src/southbridge/intel/lynxpoint/lpc.c | 26 +++++++++++++------------- src/southbridge/intel/sch/lpc.c | 8 ++++---- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/sis/sis966/lpc.c | 18 +++++++++--------- src/southbridge/via/vt8231/lpc.c | 2 +- src/southbridge/via/vt8235/lpc.c | 6 +++--- src/southbridge/via/vt8237r/lpc.c | 8 ++++---- 36 files changed, 212 insertions(+), 212 deletions(-) diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 1e6d2ce..db810d2 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -80,7 +80,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -232,7 +232,7 @@ static void cx700_set_lpc_registers(struct device *dev) } -static void cx700_read_resources(device_t dev) +static void cx700_read_resources(struct device *dev) { struct resource *res; @@ -254,7 +254,7 @@ static void cx700_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void cx700_set_resources(device_t dev) +static void cx700_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); @@ -262,7 +262,7 @@ static void cx700_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void cx700_enable_resources(device_t dev) +static void cx700_enable_resources(struct device *dev) { /* Enable SuperIO decoding */ pci_dev_enable_resources(dev); diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index c2a8a1d..ca9bfc2 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -103,7 +103,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); } -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ @@ -300,7 +300,7 @@ static void vx800_sb_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vx800_read_resources(device_t dev) +static void vx800_read_resources(struct device *dev) { struct resource *resource; @@ -313,7 +313,7 @@ static void vx800_read_resources(device_t dev) resource->base = 0x2e; } -static void vx800_set_resources(device_t dev) +static void vx800_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index ac5e4c8..f22cee5 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -50,7 +50,7 @@ * it will work, but perhaps this should be more configurable. */ -static void vx900_lpc_misc_stuff(device_t dev) +static void vx900_lpc_misc_stuff(struct device *dev) { char extint; u8 val; @@ -74,7 +74,7 @@ static void vx900_lpc_misc_stuff(device_t dev) } } -static void vx900_lpc_dma_setup(device_t dev) +static void vx900_lpc_dma_setup(struct device *dev) { /* These are the steps recommended by VIA in order to get DMA running */ @@ -107,12 +107,12 @@ static void vx900_lpc_dma_setup(device_t dev) * We are assuming this is called before the drivers/generic/ioapic code, * which should be the case if devicetree.cb is set up properly. */ -static void vx900_lpc_ioapic_setup(device_t dev) +static void vx900_lpc_ioapic_setup(struct device *dev) { /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb * If it's not, then the generic ioapic driver will not set it up * correctly, and the MP table will not be correctly generated */ - device_t ioapic; + struct device *ioapic; for (ioapic = dev->next; ioapic; ioapic = ioapic->next) { if (ioapic->path.type == DEVICE_PATH_IOAPIC) break; @@ -154,7 +154,7 @@ static void vx900_lpc_ioapic_setup(device_t dev) pci_mod_config8(dev, 0x58, 0, 1 << 6); } -static void vx900_lpc_interrupt_stuff(device_t dev) +static void vx900_lpc_interrupt_stuff(struct device *dev) { /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports * And enable I/O recovery time */ @@ -180,7 +180,7 @@ static void vx900_lpc_interrupt_stuff(device_t dev) vx900_lpc_ioapic_setup(dev); } -static void vx900_lpc_init(device_t dev) +static void vx900_lpc_init(struct device *dev) { vx900_lpc_interrupt_stuff(dev); vx900_lpc_misc_stuff(dev); @@ -204,7 +204,7 @@ static const struct pci_driver lpc_driver __pci_driver = { #if CONFIG_PIRQ_ROUTE void pirq_assign_irqs(const u8 * pirq) { - device_t lpc; + struct device *lpc; lpc = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_LPC, 0); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 1f60bc4..3b0c90d 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -31,11 +31,11 @@ #include <arch/ioapic.h> #include "hudson.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -80,7 +80,7 @@ static void lpc_init(device_t dev) cmos_init(0); } -static void hudson_lpc_read_resources(device_t dev) +static void hudson_lpc_read_resources(struct device *dev) { struct resource *res; @@ -128,7 +128,7 @@ static void hudson_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void hudson_lpc_enable_childrens_resources(device_t dev) +static void hudson_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -168,7 +168,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) reg_var[0] = pci_read_config16(dev, 0x64); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -307,7 +307,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void hudson_lpc_enable_resources(device_t dev) +static void hudson_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); hudson_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 718b40b..d8fb2e7 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -86,7 +86,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void amd8111_lpc_read_resources(device_t dev) +static void amd8111_lpc_read_resources(struct device *dev) { struct resource *res; @@ -112,7 +112,7 @@ static void amd8111_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 5d05762..3b4a40a 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -38,7 +38,7 @@ void backup_top_of_ram(uint64_t ramtop) } } -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -92,7 +92,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -104,7 +104,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h index b30f247..7d1874f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.h +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 519e3c1..4663c9f 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include <cbmem.h> -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -80,7 +80,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -92,7 +92,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 8a657d8..032db06 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index ce1be11..5a56b49 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -23,7 +23,7 @@ #include <arch/ioapic.h> -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -77,7 +77,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -89,7 +89,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h index 66f3ccd..fe2f84b 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ b/src/southbridge/amd/cimx/sb900/lpc.h @@ -24,8 +24,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index d8e63b5..1a1fab7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -33,11 +33,11 @@ #include <cpu/amd/powernow.h> #include "sb600.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -66,7 +66,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); } -static void sb600_lpc_read_resources(device_t dev) +static void sb600_lpc_read_resources(struct device *dev) { struct resource *res; @@ -102,7 +102,7 @@ static void sb600_lpc_read_resources(device_t dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb600_lpc_enable_childrens_resources(device_t dev) +static void sb600_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -114,7 +114,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -213,7 +213,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb600_lpc_enable_resources(device_t dev) +static void sb600_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb600_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 173de83..c266402 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -40,11 +40,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -104,7 +104,7 @@ void backup_top_of_ram(uint64_t ramtop) } } -static void sb700_lpc_read_resources(device_t dev) +static void sb700_lpc_read_resources(struct device *dev) { struct resource *res; @@ -151,7 +151,7 @@ static void sb700_lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -static void sb700_lpc_enable_childrens_resources(device_t dev) +static void sb700_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -163,7 +163,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -262,7 +262,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb700_lpc_enable_resources(device_t dev) +static void sb700_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb700_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 7a4dd83..143e717 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -28,11 +28,11 @@ #include <arch/io.h> #include "sb800.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); } -static void sb800_lpc_read_resources(device_t dev) +static void sb800_lpc_read_resources(struct device *dev) { struct resource *res; @@ -118,7 +118,7 @@ static void sb800_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb800_lpc_enable_childrens_resources(device_t dev) +static void sb800_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -130,7 +130,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -229,7 +229,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void sb800_lpc_enable_resources(device_t dev) +static void sb800_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb800_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 5cf1376..35173d3 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(struct device * dev) +static void lpc_init(struct device *dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(struct device * dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(struct device * dev) +static void bcm5785_lpc_read_resources(struct device *dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(struct device * dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(struct device * dev) +static void bcm5785_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(struct device * dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - struct device * child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(struct device * dev) } -static void bcm5785_lpc_enable_resources(struct device * dev) +static void bcm5785_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0e3a4f6..04f38d1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -393,7 +393,7 @@ static void enable_hpet(void) RCBA32(HPTC) = reg32; } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -581,7 +581,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -645,13 +645,13 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -660,7 +660,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index b5b77ef..b2dcd06 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -24,7 +24,7 @@ #endif #define SERIRQ_CNTL 0x64 -static void esb6300_enable_serial_irqs(device_t dev) +static void esb6300_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -32,14 +32,14 @@ static void esb6300_enable_serial_irqs(device_t dev) } #define PCI_DMA_CFG 0x90 -static void esb6300_pci_dma_cfg(device_t dev) +static void esb6300_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } #define LPC_EN 0xe6 -static void esb6300_enable_lpc(device_t dev) +static void esb6300_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -48,7 +48,7 @@ static void esb6300_enable_lpc(device_t dev) typedef struct southbridge_intel_esb6300_config config_t; static void set_esb6300_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; @@ -81,7 +81,7 @@ static void set_esb6300_gpio_use_sel( } static void set_esb6300_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; @@ -114,7 +114,7 @@ static void set_esb6300_gpio_direction( } static void set_esb6300_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -154,7 +154,7 @@ static void set_esb6300_gpio_level( } static void set_esb6300_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv; @@ -176,7 +176,7 @@ static void set_esb6300_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void esb6300_pirq_init(device_t dev) +static void esb6300_pirq_init(struct device *dev) { config_t *config; @@ -192,7 +192,7 @@ static void esb6300_pirq_init(device_t dev) } -static void esb6300_gpio_init(device_t dev) +static void esb6300_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -303,7 +303,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); } -static void esb6300_lpc_read_resources(device_t dev) +static void esb6300_lpc_read_resources(struct device *dev) { struct resource *res; @@ -335,7 +335,7 @@ static void esb6300_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void esb6300_lpc_enable_resources(device_t dev) +static void esb6300_lpc_enable_resources(struct device *dev) { uint8_t acpi_cntl, gpio_cntl; diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..edd5dc7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -116,9 +116,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -158,7 +158,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -187,7 +187,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -547,7 +547,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -608,18 +608,18 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8576b61..9b1df7a 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -113,8 +113,8 @@ static void soc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -197,7 +197,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void soc_pirq_init(device_t dev) +static void soc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -242,7 +242,7 @@ static void soc_pirq_init(device_t dev) write_pci_config_irqs(); } -static void soc_power_options(device_t dev) +static void soc_power_options(struct device *dev) { u8 reg8; u16 pmbase; @@ -344,7 +344,7 @@ static void lpc_init(struct device *dev) soc_disable_smm_only_flashing(dev); } -static void soc_lpc_read_resources(device_t dev) +static void soc_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -405,17 +405,17 @@ static void soc_lpc_read_resources(device_t dev) } } -static void soc_lpc_enable_resources(device_t dev) +static void soc_lpc_enable_resources(struct device *dev) { return pci_dev_enable_resources(dev); } -static void soc_lpc_enable(device_t dev) +static void soc_lpc_enable(struct device *dev) { soc_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index ba74f30..6cfec63 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void i3100_enable_serial_irqs(device_t dev) +static void i3100_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -62,7 +62,7 @@ static void i3100_enable_serial_irqs(device_t dev) typedef struct southbridge_intel_i3100_config config_t; static void set_i3100_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_use_sel, gpio_use_sel2; int i; @@ -95,7 +95,7 @@ static void set_i3100_gpio_use_sel( } static void set_i3100_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_io_sel, gpio_io_sel2; int i; @@ -128,7 +128,7 @@ static void set_i3100_gpio_direction( } static void set_i3100_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_lvl, gpio_lvl2; u32 gpio_blink; @@ -172,7 +172,7 @@ static void set_i3100_gpio_level( } static void set_i3100_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_inv; int i; @@ -196,9 +196,9 @@ static void set_i3100_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void i3100_pirq_init(device_t dev) +static void i3100_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config; /* Get the chip configuration */ @@ -245,7 +245,7 @@ static void i3100_pirq_init(device_t dev) } -static void i3100_power_options(device_t dev) { +static void i3100_power_options(struct device *dev) { u8 reg8; u16 reg16; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; @@ -308,7 +308,7 @@ static void i3100_power_options(device_t dev) { // i82801gx_gpi_routing(dev); } -static void i3100_gpio_init(device_t dev) +static void i3100_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -384,7 +384,7 @@ static void lpc_init(struct device *dev) i8259_configure_irq_trigger(9, 1); } -static void i3100_lpc_read_resources(device_t dev) +static void i3100_lpc_read_resources(struct device *dev) { struct resource *res; @@ -424,7 +424,7 @@ static void i3100_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM; } -static void i3100_lpc_enable_resources(device_t dev) +static void i3100_lpc_enable_resources(struct device *dev) { u8 acpi_cntl, gpio_cntl; diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 11519c1..c96ac00 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -122,7 +122,7 @@ static void i82801ax_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801ax_pirq_init(device_t dev) +static void i82801ax_pirq_init(struct device *dev) { u8 reg8; config_t *config = dev->chip_info; @@ -140,7 +140,7 @@ static void i82801ax_pirq_init(device_t dev) pci_write_config8(dev, PIRQD_ROUT, reg8); } -static void i82801ax_power_options(device_t dev) +static void i82801ax_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -170,7 +170,7 @@ static void i82801ax_power_options(device_t dev) } } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); pci_write_config8(dev, GPIO_CNTL, GPIO_EN); @@ -211,7 +211,7 @@ static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801ax_lpc_decode_en(device_t dev) +static void i82801ax_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -255,7 +255,7 @@ static void lpc_init(struct device *dev) i82801ax_lpc_decode_en(dev); } -static void i82801ax_lpc_read_resources(device_t dev) +static void i82801ax_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 278d65c..3bd6570 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -123,7 +123,7 @@ static void i82801bx_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801bx_pirq_init(struct device *dev, uint16_t ich_model) { u8 reg8; config_t *config = dev->chip_info; @@ -154,7 +154,7 @@ static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) pci_write_config8(dev, PIRQH_ROUT, reg8); } -static void i82801bx_power_options(device_t dev) +static void i82801bx_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -184,7 +184,7 @@ static void i82801bx_power_options(device_t dev) } } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); @@ -226,7 +226,7 @@ static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801bx_lpc_decode_en(struct device *dev, uint16_t ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -273,7 +273,7 @@ static void lpc_init(struct device *dev) i82801bx_lpc_decode_en(dev, ich_model); } -static void i82801bx_lpc_read_resources(device_t dev) +static void i82801bx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f6c33b7..9978842 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -199,7 +199,7 @@ static void lpc_init(struct device *dev) i82801cx_1f0_misc(dev); } -static void i82801cx_lpc_read_resources(device_t dev) +static void i82801cx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1b23fad..c5821c6 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -85,7 +85,7 @@ static void i82801dx_enable_serial_irqs(struct device *dev) (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -static void i82801dx_pirq_init(device_t dev) +static void i82801dx_pirq_init(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -100,7 +100,7 @@ static void i82801dx_pirq_init(device_t dev) pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); } -static void i82801dx_power_options(device_t dev) +static void i82801dx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -179,7 +179,7 @@ static void i82801dx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* This should be done in romstage.c already */ pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); @@ -221,7 +221,7 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(device_t dev) +static void i82801dx_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -305,7 +305,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801dx_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 1823e65..7703d14 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -61,7 +61,7 @@ static void i82801ex_general_cntl(struct device *dev) } #define SERIRQ_CNTL 0x64 -static void i82801ex_enable_serial_irqs(device_t dev) +static void i82801ex_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -69,14 +69,14 @@ static void i82801ex_enable_serial_irqs(device_t dev) } #define PCI_DMA_CFG 0x90 -static void i82801ex_pci_dma_cfg(device_t dev) +static void i82801ex_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } #define LPC_EN 0xe6 -static void i82801ex_enable_lpc(device_t dev) +static void i82801ex_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -85,7 +85,7 @@ static void i82801ex_enable_lpc(device_t dev) typedef struct southbridge_intel_i82801ex_config config_t; static void set_i82801ex_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; int i; @@ -114,7 +114,7 @@ static void set_i82801ex_gpio_use_sel( } static void set_i82801ex_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; int i; @@ -143,7 +143,7 @@ static void set_i82801ex_gpio_direction( } static void set_i82801ex_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -178,7 +178,7 @@ static void set_i82801ex_gpio_level( } static void set_i82801ex_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv; int i; @@ -198,7 +198,7 @@ static void set_i82801ex_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void i82801ex_pirq_init(device_t dev) +static void i82801ex_pirq_init(struct device *dev) { config_t *config; @@ -214,7 +214,7 @@ static void i82801ex_pirq_init(device_t dev) } -static void i82801ex_gpio_init(device_t dev) +static void i82801ex_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -319,7 +319,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801ex_lpc_read_resources(device_t dev) +static void i82801ex_lpc_read_resources(struct device *dev) { struct resource *res; @@ -351,7 +351,7 @@ static void i82801ex_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void i82801ex_lpc_enable_resources(device_t dev) +static void i82801ex_lpc_enable_resources(struct device *dev) { /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3b6b71a..021884d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -90,9 +90,9 @@ static void i82801gx_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801gx_pirq_init(device_t dev) +static void i82801gx_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -132,7 +132,7 @@ static void i82801gx_pirq_init(device_t dev) } } -static void i82801gx_gpi_routing(device_t dev) +static void i82801gx_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -161,7 +161,7 @@ static void i82801gx_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void i82801gx_power_options(device_t dev) +static void i82801gx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -265,7 +265,7 @@ static void i82801gx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void i82801gx_configure_cstates(device_t dev) +static void i82801gx_configure_cstates(struct device *dev) { u8 reg8; @@ -457,7 +457,7 @@ static void lpc_init(struct device *dev) void acpi_fill_fadt(acpi_fadt_t * fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -575,7 +575,7 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) } } -static void i82801gx_lpc_read_resources(device_t dev) +static void i82801gx_lpc_read_resources(struct device *dev) { struct resource *res; @@ -601,7 +601,7 @@ static void i82801gx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 664088c..b4ded0f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -92,9 +92,9 @@ static void i82801ix_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801ix_pirq_init(device_t dev) +static void i82801ix_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -134,7 +134,7 @@ static void i82801ix_pirq_init(device_t dev) } } -static void i82801ix_gpi_routing(device_t dev) +static void i82801ix_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -163,7 +163,7 @@ static void i82801ix_gpi_routing(device_t dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } -static void i82801ix_power_options(device_t dev) +static void i82801ix_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -295,7 +295,7 @@ static void i82801ix_power_options(device_t dev) outl(reg32, pmbase + 0x10); } -static void i82801ix_configure_cstates(device_t dev) +static void i82801ix_configure_cstates(struct device *dev) { u8 reg8; @@ -471,7 +471,7 @@ static void lpc_init(struct device *dev) #endif } -static void i82801ix_lpc_read_resources(device_t dev) +static void i82801ix_lpc_read_resources(struct device *dev) { /* * I/O Resources @@ -527,7 +527,7 @@ static void i82801ix_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a833a3d..31b8389 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -400,7 +400,7 @@ static void enable_hpet(void) write32(0xfed00010, read32(0xfed00010) | 1); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -578,7 +578,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -639,13 +639,13 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -654,7 +654,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a202424..6adc8a5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -107,9 +107,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -149,7 +149,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -178,7 +178,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16; @@ -416,7 +416,7 @@ static void enable_hpet(void) reg32 = RCBA32(HPTC); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ u32 reg32; @@ -441,7 +441,7 @@ static void enable_clock_gating(device_t dev) RCBA32_OR(0x38c0, 0x7); // SPI Dynamic } -static void enable_lp_clock_gating(device_t dev) +static void enable_lp_clock_gating(struct device *dev) { /* LynxPoint LP */ u32 reg32; @@ -591,7 +591,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -653,7 +653,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -666,7 +666,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -679,7 +679,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -704,7 +704,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; @@ -723,7 +723,7 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -732,7 +732,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index 7d209b1..beaf090 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -76,9 +76,9 @@ typedef struct southbridge_intel_sch_config config_t; #define PIRQG 0x0B #define PIRQH 0x0C -static void sch_pirq_init(device_t dev) +static void sch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -151,7 +151,7 @@ static void lpc_init(struct device *dev) sch_fixups(dev); } -static void sch_lpc_read_resources(device_t dev) +static void sch_lpc_read_resources(struct device *dev) { struct resource *res; @@ -177,7 +177,7 @@ static void sch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index a48401f..d62075f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(struct device * dev) +static void lpc_common_init(struct device *dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(struct device * dev) #endif } -static void lpc_slave_init(struct device * dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); } -static void rom_dummy_write(struct device * dev) +static void rom_dummy_write(struct device *dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(struct device * dev) unsigned pm_base = 0; -static void lpc_init(struct device * dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(struct device * dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(struct device * dev) +static void ck804_lpc_read_resources(struct device *dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(struct device * dev) } } -static void ck804_lpc_set_resources(struct device * dev) +static void ck804_lpc_set_resources(struct device *dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(struct device * dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(struct device * dev) +static void ck804_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(struct device * dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - struct device * child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(struct device * dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(struct device * dev) +static void ck804_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index ebf2a01..a2a3b22 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(struct device * dev, int master) +static void lpc_common_init(struct device *dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(struct device * dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(struct device * dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(struct device * dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(struct device * dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(struct device * dev) +static void mcp55_lpc_read_resources(struct device *dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(struct device * dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(struct device * dev) +static void mcp55_lpc_enable_childrens_resources(struct device *dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(struct device * dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - struct device * child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(struct device * dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(struct device * dev) +static void mcp55_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0e11c6f..55a5e43 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -56,7 +56,7 @@ #undef SLAVE_INIT -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device *dev) { uint8_t byte; uint32_t ioapic_base; @@ -71,13 +71,13 @@ static void lpc_common_init(device_t dev) } #ifdef SLAVE_INIT -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); } #endif -static void lpc_usb_legacy_init(device_t dev) +static void lpc_usb_legacy_init(struct device *dev) { uint16_t acpi_base; @@ -87,7 +87,7 @@ static void lpc_usb_legacy_init(device_t dev) outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba); } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { uint8_t byte; uint8_t byte_old; @@ -156,7 +156,7 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "LPC_INIT <--------\n"); } -static void sis966_lpc_read_resources(device_t dev) +static void sis966_lpc_read_resources(struct device *dev) { struct resource *res; @@ -187,7 +187,7 @@ static void sis966_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void sis966_lpc_enable_childrens_resources(device_t dev) +static void sis966_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg, reg_var[4]; @@ -197,7 +197,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -238,13 +238,13 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) } -static void sis966_lpc_enable_resources(device_t dev) +static void sis966_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sis966_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c index c6b74fd..862b1ad 100644 --- a/src/southbridge/via/vt8231/lpc.c +++ b/src/southbridge/via/vt8231/lpc.c @@ -124,7 +124,7 @@ static void vt8231_init(struct device *dev) cmos_init(0); } -static void vt8231_read_resources(device_t dev) +static void vt8231_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c index 2c78481..396b647 100644 --- a/src/southbridge/via/vt8235/lpc.c +++ b/src/southbridge/via/vt8235/lpc.c @@ -104,7 +104,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { // Set gen config 0 pci_write_config8(dev, 0x80, 0x20); @@ -214,7 +214,7 @@ static void vt8235_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vt8235_read_resources(device_t dev) +static void vt8235_read_resources(struct device *dev) { struct resource *res; @@ -232,7 +232,7 @@ static void vt8235_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vt8235_set_resources(device_t dev) +static void vt8235_set_resources(struct device *dev) { //struct resource *resource; //resource = find_resource(dev,1); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 9e8f6f6..70b6120 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -66,7 +66,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT - device_t pdev; + struct device *pdev; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -148,7 +148,7 @@ static void pci_routing_fixup(struct device *dev) * This avoids having to handle any System Management Interrupts (SMIs). */ -static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; struct southbridge_via_vt8237r_config *cfg; @@ -568,7 +568,7 @@ static void vt8237_common_init(struct device *dev) cmos_init(0); } -static void vt8237r_read_resources(device_t dev) +static void vt8237r_read_resources(struct device *dev) { struct resource *res; @@ -640,7 +640,7 @@ static void southbridge_init_common(struct device *dev) } -static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0x70, vendor); pci_write_config16(dev, 0x72, device);

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coreboot-gerrit November 2014