Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7028
-gerrit
commit 5585eb9ef0d5b4c136e32ad9fed2487dd1cfaccb
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Oct 8 00:26:42 2014 +0200
NOTFORMERGE: build-check to see which mobos are still monolithic ACPI
Change-Id: I37fab85eabac79b8596031fa4efb9ef630ae5664
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/Kconfig b/src/Kconfig
index 4deed2a..41ca70c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -472,7 +472,7 @@ config MAX_PIRQ_LINKS
config PER_DEVICE_ACPI_TABLES
bool
- default n
+ default y
config COMMON_FADT
bool
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7135
-gerrit
commit a66ddbb53bf4d69a8d910ed6fb2c7474946ca38a
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Mon Oct 20 19:38:27 2014 +0200
Kconfig: Remove ACPI_SSDTX_NUM.
Its scope is limited to a single mainboard and is only to go through ifdef.
Kill it and move the value to the code.
Change-Id: I76a87e2790d57dee8f37b51e33d0689fffd3a59d
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/Kconfig | 4 ----
src/mainboard/amd/olivehill/Kconfig | 4 ----
src/mainboard/amd/olivehillplus/Kconfig | 4 ----
src/mainboard/amd/serengeti_cheetah/Kconfig | 4 ----
src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 3 ---
src/mainboard/amd/serengeti_cheetah/readme_acpi.txt | 2 +-
src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 4 ----
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c | 5 -----
src/mainboard/asrock/imb-a180/Kconfig | 4 ----
src/mainboard/iwill/dk8_htx/Kconfig | 4 ----
src/northbridge/amd/amdfam10/get_pci1234.c | 3 +--
src/northbridge/amd/amdk8/get_sblk_pci1234.c | 3 ---
12 files changed, 2 insertions(+), 42 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 41ca70c..eb55a85 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -346,10 +346,6 @@ config HAVE_ACPI_SLIC
bool
default n
-config ACPI_SSDTX_NUM
- int
- default 0
-
config HAVE_HARD_RESET
bool
default n
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index a089d21..7cd50e6 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -64,10 +64,6 @@ config HEAP_SIZE
hex
default 0xc0000
-config ACPI_SSDTX_NUM
- int
- default 0
-
config RAMBASE
hex
default 0x200000
diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig
index a61859f..069bd84 100644
--- a/src/mainboard/amd/olivehillplus/Kconfig
+++ b/src/mainboard/amd/olivehillplus/Kconfig
@@ -64,10 +64,6 @@ config HEAP_SIZE
hex
default 0xc0000
-config ACPI_SSDTX_NUM
- int
- default 0
-
config RAMBASE
hex
default 0x200000
diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
index ae0e1f4..e1363eb 100644
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -71,8 +71,4 @@ config IRQ_SLOT_COUNT
int
default 11
-config ACPI_SSDTX_NUM
- int
- default 4
-
endif # BOARD_AMD_SERENGETI_CHEETAH
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
index 65b8fc5..802635c 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
@@ -136,8 +136,6 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp
start = ALIGN(start, 16);
current = start;
-#if CONFIG_ACPI_SSDTX_NUM >= 1
-
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
@@ -173,7 +171,6 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
acpi_add_table(rsdp, ssdtx);
}
-#endif
return current;
}
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index 685cd7a..5d27554 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -12,7 +12,7 @@ Change dsdt.asl, according to MB layout
Change acpi_tables.c
sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is coreboot run-time configurable now.
- if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
+ if there is HT-IO board, need to preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
Regarding pci bridge apic and pic
need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
index c542d8c..8954f26 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
@@ -70,10 +70,6 @@ config HEAP_SIZE
hex
default 0xc0000
-config ACPI_SSDTX_NUM
- int
- default 5
-
config RAMBASE
hex
default 0x200000
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
index ea3ec6c..cb91132 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
@@ -30,12 +30,10 @@
#include "mb_sysconf.h"
#include "mainboard.h"
-#if CONFIG_ACPI_SSDTX_NUM >= 1
extern const unsigned char AmlCode_ssdt2[];
extern const unsigned char AmlCode_ssdt3[];
extern const unsigned char AmlCode_ssdt4[];
extern const unsigned char AmlCode_ssdt5[];
-#endif
unsigned long acpi_fill_madt(unsigned long current)
{
@@ -143,8 +141,6 @@ unsigned long mainboard_write_acpi_tables(unsigned long current,
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
-#if CONFIG_ACPI_SSDTX_NUM >= 1
-
/* same htio, but different possition? We may have to copy,
change HCIN, and recalculate the checknum and add_table */
@@ -182,7 +178,6 @@ unsigned long mainboard_write_acpi_tables(unsigned long current,
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
acpi_add_table(rsdp, ssdtx);
}
-#endif
return current;
}
diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig
index aa075c8..e361e22 100644
--- a/src/mainboard/asrock/imb-a180/Kconfig
+++ b/src/mainboard/asrock/imb-a180/Kconfig
@@ -65,10 +65,6 @@ config HEAP_SIZE
hex
default 0xc0000
-config ACPI_SSDTX_NUM
- int
- default 0
-
config RAMBASE
hex
default 0x200000
diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig
index f4a137d..cdfd99a 100644
--- a/src/mainboard/iwill/dk8_htx/Kconfig
+++ b/src/mainboard/iwill/dk8_htx/Kconfig
@@ -54,8 +54,4 @@ config IRQ_SLOT_COUNT
int
default 11
-config ACPI_SSDTX_NUM
- int
- default 5
-
endif # BOARD_IWILL_DK8_HTX
diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c
index 6831013..c5642c7 100644
--- a/src/northbridge/amd/amdfam10/get_pci1234.c
+++ b/src/northbridge/amd/amdfam10/get_pci1234.c
@@ -49,8 +49,7 @@
* reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk)
*
* Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c
- * on MB dir. Also, don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc if you have
- * too much SSDT. How about co-processor on socket 1 on 2 way system.
+ * on MB dir. How about co-processor on socket 1 on 2 way system.
* or socket 2, and socket3 on 4 way system? treat that as one hc too!
*
*/
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index 6fdc3c4..2db726c 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -176,9 +176,6 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
* Just put all the possible HT Node/link to the list tp pci1234[] in
* src/mainboard/<vendor>/<mainboard>get_bus_conf.c
*
- * Also don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc (FIXME what else) if
- * you have too many SSDTs
- *
* What about co-processor in socket 1 on a 2 way system? Or socket 2 and
* socket 3 on a 4 way system? Treat that as an HC, too!
*
the following patch was just integrated into master:
commit 5ad6ec55f84076982c3342d4c7695aa918ac663b
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Wed Nov 5 21:27:01 2014 +0100
inteltool: Fix message in case of multiple LPC controllers
If we find multiple LPC controllers, we want to tell the user that we'll
ignore all but the first. However, we use 'dev' in the message (the
current device found) instead of 'sb' (the one we want to use).
Fix the message by using 'sb' and break the loop right away in this
case. It's sufficient to tell the user once which LPC controller we'll
use.
Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
Reviewed-on: http://review.coreboot.org/7342
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/7342 for details.
-gerrit
the following patch was just integrated into master:
commit 0cc8f29316f6930406d70f71fc9409e295516b1e
Author: Felix Held <felix-coreboot(a)felixheld.de>
Date: Wed Nov 5 03:18:44 2014 +0100
inteltool: Add support for Sandy Bridge desktop processors
Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-on: http://review.coreboot.org/7337
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Mathias Krause <minipli(a)googlemail.com>
See http://review.coreboot.org/7337 for details.
-gerrit