Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7325
-gerrit
commit d337638612f2023847fc617743fd912d7bc942b9
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Nov 2 21:51:22 2014 +0100
acpigen: Add new function acpigen_pop_len
acpigen_patch_len doesn't really need its argument: length always includes
everything from length bytes to current pointer and never bytes before it.
Hence just infer all the info implicitly.
Argument is wrong in several places through the codebase but ACPI parsing
is lax enough to swallow incorrect SSDT. After this function is used throughout
the codebase, these issues will be fixed.
Change-Id: I9fa536a614c5595146a7a1cd71f2676d8a8d9c2f
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/acpigen.c | 13 +++++++++++++
src/arch/x86/include/arch/acpigen.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index 222a2db..0689273 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -57,6 +57,19 @@ void acpigen_patch_len(int len)
}
+void acpigen_pop_len(void)
+{
+ int len;
+ ASSERT(ltop > 0)
+ char *p = len_stack[--ltop];
+ len = gencurrent - p;
+ ASSERT(len <= ACPIGEN_MAXLEN)
+ /* generate store length for 0xfff max */
+ p[0] = (0x40 | (len & 0xf));
+ p[1] = (len >> 4 & 0xff);
+
+}
+
void acpigen_set_current(char *curr)
{
gencurrent = curr;
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index 3217dbe..d9df5d0 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -27,6 +27,7 @@
int acpigen_write_len_f(void);
void acpigen_patch_len(int len);
+void acpigen_pop_len(void);
void acpigen_set_current(char *curr);
char *acpigen_get_current(void);
int acpigen_write_package(int nr_el);
the following patch was just integrated into master:
commit 2837ab2cdf267a65aacff01aaad738a4d1828606
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Thu Nov 6 08:57:40 2014 +1100
northbridge: DEVICE_NOOP some stub function callbacks
Reduces loc and makes NOP's explicit.
Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7344
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/7344 for details.
-gerrit
York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7335
-gerrit
commit af3faa4c3dec1d4d580a0fa0c41219b27e61c473
Author: York Yang <york.yang(a)intel.com>
Date: Tue Nov 4 17:20:46 2014 -0700
abandon: merge this #7334 - intel/fsp_baytrail: add Gold3 FSP support
Intel Baytrail Gold2 and earlier FSP Staying Supported
UPD_DATA_REGION structure has been updated to support Baytrail Gold3
FSP, but incompatible with previous FSP. Adjust the offset of those
changed fields if FSP version is early than Gold3.
Change-Id: Ia77431d31bed424ae25f297df893e45157a288a0
Signed-off-by: York Yang <york.yang(a)intel.com>
---
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 11 +++++++++++
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 4 ++++
2 files changed, 15 insertions(+)
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index c4b781a..297ccf9 100755
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -48,6 +48,17 @@ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase);
UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
+
+ /* adjust struct UPD_DATA_REGION content for Gold2 and earlier FSP */
+ /* Gold3 FSP changes the UPD_DATA_REGION fields, adjust the struct */
+ /* content in order to backward compatible with older FSP */
+ /* */
+ /* ISPEnable and PcdRegionTerminator are following PcdGttSize in */
+ /* Gold2 and older FSP */
+ if (FspInfo->ImageRevision < FSP_GOLD3_REV_ID) {
+ *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = UpdData->ISPEnable;
+ *(&(UpdData->PcdGttSize)+sizeof(UINT8)+sizeof(UINT8)) = UpdData->PcdRegionTerminator;
+ }
}
/* default to just enabling HDMI audio */
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
old mode 100644
new mode 100755
index 1b60398..3861ac1
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -46,4 +47,7 @@
#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */
#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */
+/* Revision of the FSP binary */
+#define FSP_GOLD3_REV_ID 0x00000303
+
#endif /* CHIPSET_FSP_UTIL_H */