coreboot-gerrit November 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d9591c7 Include IPQ8064 SBLs code in the coreboot bootblock
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7262 -gerrit commit d9591c76ec6361249db5d20341cc39db90709c5f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Apr 7 18:59:53 2014 -0700 Include IPQ8064 SBLs code in the coreboot bootblock We want the coreboot build produce an image which can be run on the target, even if the remaining parts of the bootprom (recovery path, read-write stages, gbb, etc.) are not available yet. This is achieved by including the Qualcomm SBLs blob in the bootblock. CQ-DEPEND=CL:193518 BRANCH=None BUG=chrome-os-partner:27784 TEST=manual . run the following commands inside chroot to confirm expected image layout (no actual code is executed on the target yet): $ emerge-storm coreboot $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1 000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000 220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193540 (cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200 --- src/soc/qualcomm/ipq806x/Kconfig | 8 ++++---- src/soc/qualcomm/ipq806x/Makefile.inc | 21 +++++++++++++++++---- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 0f65990..88dbd36 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -13,11 +13,11 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" - default 0x18000 + default 0x221000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" - default 0x18080 + default 0x221080 config MBN_ENCAPSULATION depends on USE_BLOBS @@ -34,7 +34,7 @@ config SBL_BLOB vendor. config BOOTBLOCK_BASE - hex "64K bytes left for TZBSP" - default 0x2a010000 + hex "256K bytes left for TZBSP" + default 0x2a040000 endif diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 2487f46..1da8489 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -7,12 +7,25 @@ romstage-y += timer.c ramstage-y += cbfs.c ramstage-y += timer.c -ifeq ($(CONFIG_MBN_ENCAPSULATION),y) +ifeq ($(CONFIG_USE_BLOBS),y) -$(objcbfs)/%.bin: $(objcbfs)/%.elf +# Generate the actual coreboot bootblock code +$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY_bootblock) -O binary $< $@.prembn + $(OBJCOPY_bootblock) -O binary $< $@.tmp + @mv $@.tmp $@ + +# Add MBN header to allow SBL3 to start coreboot bootblock +$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw @printf " ADD MBN $(subst $(obj)/,,$(@))\n" - ./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $@.prembn $@.tmp + ./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $< $@.tmp @mv $@.tmp $@ + +# Create a complete bootblock which will start up the system +$(objcbfs)/bootblock.bin: ./$(call strip_quotes,$(CONFIG_SBL_BLOB)) \ + $(objcbfs)/bootblock.mbn + @printf " CAT $(subst $(obj)/,,$(@))\n" + @cat $^ > $@.tmp + @mv $@.tmp $@ + endif

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Patch set updated for coreboot: 52b07f7 Provide ability to integrate with QComm SBLs
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7261 -gerrit commit 52b07f713674b6bee27b87b1d24a396f53979c52 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Apr 7 15:26:39 2014 -0700 Provide ability to integrate with QComm SBLs Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary user provided bootloader. The only bootloader requirements imposed by the SBLs are that it is concatenated with the SBL chunks in the bootprm AND it uses MBN encapsulation (mostly to specify the size and load address). This patch adds configuration options to specify the location of the SBL blobs and to require MBN encapsulation of the bootblock. BRANCH=none BUG=chrome-os-partner:27784 TEST=manual - the below demonstrates added encapsulation, no code run attempts have been made yet: $ FEATURES=noclean emerge-storm coreboot $ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999 $ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3 0000000 00000005 00000003 00000000 2a010000 0000020 00000be0 00000be0 2a010be0 00000000 0000040 2a010be0 00000000 e32bf0df e59f0030 Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193511 (cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b --- src/soc/qualcomm/ipq806x/Kconfig | 18 ++++++++++++++++++ src/soc/qualcomm/ipq806x/Makefile.inc | 10 ++++++++++ 2 files changed, 28 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index fcf8ccd..0f65990 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -19,4 +19,22 @@ config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x18080 +config MBN_ENCAPSULATION + depends on USE_BLOBS + bool "bootblock encapsulation for ipq8064" + default y + +config SBL_BLOB + depends on USE_BLOBS + string "file name of the Qualcomm SBL blob" + default "3rdparty/cpu/qualcomm/ipq8064/sbls.bin" + help + The path and filename of the binary blob containing + ipq806x early initialization code, as supplied by the + vendor. + +config BOOTBLOCK_BASE + hex "64K bytes left for TZBSP" + default 0x2a010000 + endif diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index be37581..2487f46 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -6,3 +6,13 @@ romstage-y += timer.c ramstage-y += cbfs.c ramstage-y += timer.c + +ifeq ($(CONFIG_MBN_ENCAPSULATION),y) + +$(objcbfs)/%.bin: $(objcbfs)/%.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_bootblock) -O binary $< $@.prembn + @printf " ADD MBN $(subst $(obj)/,,$(@))\n" + ./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $@.prembn $@.tmp + @mv $@.tmp $@ +endif

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Patch merged into coreboot/master: cfa06c7 blobs: Update to IPQ blob commit
by gerrit＠coreboot.org 08 Nov '14

08 Nov '14

the following patch was just integrated into master: commit cfa06c746023fbb79169260012539253811525aa Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Nov 7 16:41:06 2014 -0700 blobs: Update to IPQ blob commit Update the 3rdparty repo to the IPQ binary commit Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7354 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/7354 for details. -gerrit

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New patch to review for coreboot: 4daeed9 Hudson: Add support for hiding the USB1.1-only OHCI
by Tobias Diedrich 08 Nov '14

08 Nov '14

Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7355 -gerrit commit 4daeed9c113d11041f12300aeb6821318900d56d Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Sat Nov 8 00:38:33 2014 +0100 Hudson: Add support for hiding the USB1.1-only OHCI The hudson chipset has 4 USB controllers, the fourth is USB1.1-only and (presumably) not used very often, add support for hiding it. On the F2A85M the vendor BIOS is hiding both the USB4 OHCI and the SD controller, adjust devicetree.cb accordingly. Support for hiding the SD controller already exists, but was not yet used in the F2A85M devicetree.cb. Includes a small whitespace fix. Change-Id: I804e7852fd0a6f870dd118b429473cb06ebac9a4 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- src/mainboard/asus/f2a85-m/devicetree.cb | 7 +++---- src/southbridge/amd/agesa/hudson/hudson.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 9ac5574..40d9c88 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 2.0 on end # PCIE SLOT0 x16 blue device pci 3.0 off end # unused? device pci 4.0 on end # PCIE 4x black device pci 5.0 off end # unused? @@ -108,10 +108,9 @@ chip northbridge/amd/agesa/family15tn/root_complex end #superio/ite/it8728f end #device pci 14.3 # LPC device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 + device pci 14.5 off end # Hide USB4 (USB1.1-only OHCI) device pci 14.6 off end # Gec - # SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away) - device pci 14.7 on end + device pci 14.7 off end # Hide unused SD controller device pci 15.0 on end # PCIe 0 - onboard PCIe 1x device pci 15.1 on end # PCIe 1 onboard gigabit device pci 15.2 off end # unused diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 3b57221..c33dc9b 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -109,6 +109,20 @@ void hudson_enable(device_t dev) pm_write8(0xd3, reg8); } break; + case (0x14 << 3) | 5: /* 0:14.5 USB1.1 OHCI (USB4) */ + if (dev->enabled == 0) { + // read the VENDEV ID + device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 5)); + u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16; + u8 reg8; + if (sd_device_id == PCI_DEVICE_ID_ATI_SB900_USB_20_5) { + /* turn off and remove device 0:14.5 from PCI space */ + reg8 = pm_read8(0xef); + reg8 &= ~(1 << 6); + pm_write8(0xef, reg8); + } + } + break; default: break; }

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Patch set updated for coreboot: 0f43233 ipq806x: Typecast address to void * in read/write operations
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7265 -gerrit commit 0f4323318e598ea6112b2142fcc904d0e4a4a12d Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Apr 11 14:57:11 2014 -0700 ipq806x: Typecast address to void * in read/write operations Typecast address to void* to accomodate address being passed as integers BUG=None BRANCH=None TEST=Compiled successfully Original-Change-Id: Iceb51056c8a30a9a9dbd0594f75c23000faa6120 Original-Reviewed-on: https://chromium-review.googlesource.com/194365 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit abf9b1e77b8a078e6ed873cbf34246bd97c81e98) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1806e96e194e936975a43e95b9fd7d7458ef1653 --- src/soc/qualcomm/ipq806x/include/iomap.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index 514c6a7..a7066af 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -37,6 +37,15 @@ #define _PLATFORM_MSM8960_IOMAP_H_ #include <configs/ipq806x_cdp.h> + +/* Typecast to allow integers being passed as address + This needs to be included because vendor code is not compliant with our + macros for read/write. Hence, special macros for readl_i and writel_i are + included to do this in one place for all occurrences in vendor code + */ +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v,a) write32(v,(void *)a) + #define MSM_CLK_CTL_BASE 0x00900000 #define MSM_TMR_BASE 0x0200A000

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Patch set updated for coreboot: c3936c0 ipq806x: Add support for GPIO operations
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7266 -gerrit commit c3936c04216bf5a3f12b74f3e11b27fc5bf694ec Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Apr 10 20:35:05 2014 -0700 ipq806x: Add support for GPIO operations Basic support for ipq806x GPIO CFG and IO reg operations Reference: IPQ806x PRM, u-boot arch-ipq806x/gpio.* BUG=None BRANCH=None TEST=Compiled successfully Original-Change-Id: Ia0a9f288de3ac7bdb1cd4acbf44ba46af4dcc4e2 Original-Reviewed-on: https://chromium-review.googlesource.com/194217 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0b48e6655e63b467fe79d52149be01d23a2a3712) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I09e222f35b4b20c8eb901f33cf4451085c4c99cc --- src/soc/qualcomm/ipq806x/Makefile.inc | 3 + src/soc/qualcomm/ipq806x/gpio.c | 123 +++++++++++++++++++++++++++---- src/soc/qualcomm/ipq806x/include/gpio.h | 44 +++++++++-- src/soc/qualcomm/ipq806x/include/iomap.h | 8 +- 4 files changed, 154 insertions(+), 24 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 35ff932..33bd763 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -1,8 +1,11 @@ bootblock-y += cbfs.c +bootblock-y += gpio.c romstage-y += cbfs.c +romstage-y += gpio.c ramstage-y += cbfs.c +ramstage-y += gpio.c ifeq ($(CONFIG_USE_BLOBS),y) diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 6e4140e..ac41e1a 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -28,16 +28,29 @@ * SUCH DAMAGE. */ -#include <asm/arch-ipq806x/iomap.h> -#include <asm/arch-ipq806x/gpio.h> -#include <asm/io.h> +#include <iomap.h> +#include <gpio.h> +#include <arch/io.h> + +/******************************************************* +Function description: check for invalid GPIO # +Arguments : +gpio_t gpio - Gpio number + +Return : GPIO Valid(0)/Invalid(1) +*******************************************************/ + +static inline int gpio_not_valid(gpio_t gpio) +{ + return (gpio > GPIO_MAX_NUM); +} + /******************************************************* Function description: configure GPIO functinality Arguments : -unsigned int gpio - Gpio number +gpio_t gpio - Gpio number unsigned int func - Functionality number -unsigned int dir - direction 0- i/p, 1- o/p unsigned int pull - pull up/down, no pull range(0-3) unsigned int drvstr - range (0 - 7)-> (2- 16)MA steps of 2 unsigned int enable - 1 - Disable, 2- Enable. @@ -46,17 +59,101 @@ Return : None *******************************************************/ -void gpio_tlmm_config(unsigned int gpio, unsigned int func, - unsigned int dir, unsigned int pull, - unsigned int drvstr, unsigned int enable) +void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, + unsigned int pull, unsigned int drvstr, + unsigned int enable) { unsigned int val = 0; - val |= pull; - val |= func << 2; - val |= drvstr << 6; - val |= enable << 9; + + if (gpio_not_valid(gpio)) + return; + + val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT; + val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT; + val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT; + val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT; unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); writel(val, addr); - return; } +/******************************************************* +Function description: Get GPIO configuration +Arguments : +gpio_t gpio - Gpio number +unsigned int *func - Functionality number +unsigned int *pull - pull up/down, no pull range(0-3) +unsigned int *drvstr - range (0 - 7)-> (2- 16)MA steps of 2 +unsigned int *enable - 1 - Disable, 2- Enable. + +Return : None +*******************************************************/ + + +void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, + unsigned int *pull, unsigned int *drvstr, + unsigned int *enable) +{ + unsigned int val; + + if (gpio_not_valid(gpio)) + return; + + unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); + val = readl(addr); + + *pull = (val >> GPIO_CFG_PULL_SHIFT) & GPIO_CFG_PULL_MASK; + *func = (val >> GPIO_CFG_FUNC_SHIFT) & GPIO_CFG_FUNC_MASK; + *drvstr = (val >> GPIO_CFG_DRV_SHIFT) & GPIO_CFG_DRV_MASK; + *enable = (val >> GPIO_CFG_OE_SHIFT) & GPIO_CFG_OE_MASK; +} + +/******************************************************* +Function description: configure GPIO IO functinality +Arguments : +gpio_t gpio - Gpio number +unsigned int out - Controls value of GPIO output + +Return : None +*******************************************************/ + +void gpio_io_config_set(gpio_t gpio, unsigned int out) +{ + unsigned int val; + + if (gpio_not_valid(gpio)) + return; + + unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); + + val = readl(addr); + if (out) + val |= (1 << GPIO_IO_OUT_SHIFT); + else + val &= (~(1 << GPIO_IO_OUT_SHIFT)); + + writel(val,addr); +} + +/******************************************************* +Function description: get GPIO IO functinality details +Arguments : +gpio_t gpio - Gpio number +unsigned int *in - Value of GPIO input +unsigned int *out - Value of GPIO output + +Return : None +*******************************************************/ + +void gpio_io_config_get(gpio_t gpio, unsigned int *in, unsigned int *out) +{ + unsigned int val; + + if (gpio_not_valid(gpio)) + return; + + unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); + + val = readl(addr); + *in = (val >> GPIO_IO_IN_SHIFT) & GPIO_IO_IN_MASK; + *out = (val >> GPIO_IO_OUT_SHIFT) & GPIO_IO_OUT_MASK; +} diff --git a/src/soc/qualcomm/ipq806x/include/gpio.h b/src/soc/qualcomm/ipq806x/include/gpio.h index e2b281e..678da0d 100644 --- a/src/soc/qualcomm/ipq806x/include/gpio.h +++ b/src/soc/qualcomm/ipq806x/include/gpio.h @@ -30,8 +30,10 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __PLATFORM_AKRONITE_GPIO_H_ -#define __PLATFORM_AKRONITE_GPIO_H_ +#ifndef __SOC_QUALCOMM_IPQ806X_GPIO_H_ +#define __SOC_QUALCOMM_IPQ806X_GPIO_H_ + +typedef unsigned int gpio_t; /* GPIO TLMM: Direction */ #define GPIO_INPUT 0 @@ -57,7 +59,37 @@ #define GPIO_ENABLE 0 #define GPIO_DISABLE 1 -void gpio_tlmm_config(unsigned int gpio, unsigned int func, - unsigned int dir, unsigned int pull, - unsigned int drvstr, unsigned int enable); -#endif +/* GPIO MAX Valid # */ +#define GPIO_MAX_NUM 68 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_MASK 0x3 +#define GPIO_CFG_FUNC_MASK 0xF +#define GPIO_CFG_DRV_MASK 0x7 +#define GPIO_CFG_OE_MASK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHIFT 0 +#define GPIO_CFG_FUNC_SHIFT 2 +#define GPIO_CFG_DRV_SHIFT 6 +#define GPIO_CFG_OE_SHIFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_MASK 0x1 +#define GPIO_IO_OUT_MASK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHIFT 0 +#define GPIO_IO_OUT_SHIFT 1 + +void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, + unsigned int pull, unsigned int drvstr, + unsigned int enable); + +void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, + unsigned int *pull, unsigned int *drvstr, + unsigned int *enable); + +void gpio_io_config_set(gpio_t gpio, unsigned int out); +void gpio_io_config_get(gpio_t gpio, unsigned int *in, unsigned int *out); +#endif // __SOC_QUALCOMM_IPQ806X_GPIO_H_ diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index a7066af..5fcfde9 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -33,10 +33,8 @@ * SUCH DAMAGE. */ -#ifndef _PLATFORM_MSM8960_IOMAP_H_ -#define _PLATFORM_MSM8960_IOMAP_H_ - -#include <configs/ipq806x_cdp.h> +#ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_ +#define __SOC_QUALCOMM_IPQ806X_IOMAP_H_ /* Typecast to allow integers being passed as address This needs to be included because vendor code is not compliant with our @@ -96,4 +94,4 @@ #define UART2_DM_BASE 0x12490000 #define UART_GSBI2_BASE 0x12480000 -#endif +#endif // __SOC_QUALCOMM_IPQ806X_IOMAP_H_

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Patch set updated for coreboot: 6c8cf57 Use sbl blobs from a private location
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7267 -gerrit commit 6c8cf57b664a1dcd839970c91b4b4b562f06f83f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Apr 15 14:42:30 2014 -0700 Use sbl blobs from a private location The sbl blobs could not yet be published, they have been moved to a private location. Update coreboot to pick up the blobs at the correct place. BRANCH=None CQ-DEPEND=CL:195003 BUG=chrome-os-partner:28059 TEST=manual $ emerge-storm coreboot succeeds Original-Change-Id: I8c4163bc978307e41c156ef9f7f2a211d57db7a8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194997 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 1a1848b00acfc2f58990559e824ea9c13c3c239c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If597ebbfd348039d578c99cd7a8e3c4bcbf60c10 --- src/soc/qualcomm/ipq806x/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 33bd763..002e59c 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -22,7 +22,7 @@ $(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw @mv $@.tmp $@ # Create a complete bootblock which will start up the system -$(objcbfs)/bootblock.bin: ./$(call strip_quotes,$(CONFIG_SBL_BLOB)) \ +$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \ $(objcbfs)/bootblock.mbn @printf " CAT $(subst $(obj)/,,$(@))\n" @cat $^ > $@.tmp

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Patch set updated for coreboot: 170ede4 ipq8064: Configure proper bootblock stack and load address
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7268 -gerrit commit 170ede4a44af98c08d8e80af3cb451cf1cce7196 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Apr 21 18:53:47 2014 -0700 ipq8064: Configure proper bootblock stack and load address The SBL3 currently seems to be preventing the bootblock from being loaded into the IMEM. As a temporary measure, map bootblock into DRAM (as it is available after SBL2 finished running) and specify the correct stack space. BUG=chrome-os-partner:27784 TEST=not much testing yet, just verify 'emerge-storm coreboot' still succeeds. Original-Change-Id: Ibe9d4911ad22ada1bbd01af54a2ef80009df3a28 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196168 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 950323d6091c3b795034c24a08b6c176f56f0e0f) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib3ec21f2cb4058b3e3cc82864de89dadf3b6aa84 --- src/soc/qualcomm/ipq806x/Kconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 88dbd36..03be33a 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -35,6 +35,14 @@ config SBL_BLOB config BOOTBLOCK_BASE hex "256K bytes left for TZBSP" - default 0x2a040000 + default 0x40600000 + +config STACK_TOP + hex + default 0x40600000 + +config STACK_BOTTOM + hex + default 0x405fc000 endif

1 0

Patch set updated for coreboot: f1c02de ipq8064: Make timer code compile
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7269 -gerrit commit f1c02de09a8510504c3711bae7932f48ead1b5f2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 9 19:23:04 2014 -0700 ipq8064: Make timer code compile Commment out nonessential timer services and modify the source code to cleanly build in coeboot environment. Do not remove dead code just yet, these functions might be necessary later. Need to rename the soc timer.h to prevent collisions with timer.h in the top level include directory. Currently build timer code for ramstage only. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: Ib10133ccb42697840708845a8ea6d75ceeaeb3d5 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194067 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 987ce95220953c16216d1e1d70d5a941d05fc9bc) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia9cf175da11c70709354def5e51bf79df4fda2fe --- src/soc/qualcomm/ipq806x/Makefile.inc | 1 + src/soc/qualcomm/ipq806x/cbfs.c | 9 ------ src/soc/qualcomm/ipq806x/include/cdp.h | 40 +++++++++++++++++------- src/soc/qualcomm/ipq806x/include/iomap.h | 4 ++- src/soc/qualcomm/ipq806x/include/ipq_timer.h | 40 ++++++++++++++++++++++++ src/soc/qualcomm/ipq806x/include/timer.h | 40 ------------------------ src/soc/qualcomm/ipq806x/timer.c | 46 ++++++++++++---------------- 7 files changed, 93 insertions(+), 87 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 002e59c..41cde31 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -6,6 +6,7 @@ romstage-y += gpio.c ramstage-y += cbfs.c ramstage-y += gpio.c +ramstage-y += timer.c ifeq ($(CONFIG_USE_BLOBS),y) diff --git a/src/soc/qualcomm/ipq806x/cbfs.c b/src/soc/qualcomm/ipq806x/cbfs.c index eec9b73..97ae548 100644 --- a/src/soc/qualcomm/ipq806x/cbfs.c +++ b/src/soc/qualcomm/ipq806x/cbfs.c @@ -24,12 +24,3 @@ int init_default_cbfs_media(struct cbfs_media *media) { return 0; } - -/* - * Temporary change to make sure storm code still builds. Will be dropped - * shortly. - */ -#include <delay.h> /* This driver serves as a CBFS media source. */ -void init_timer(void) -{ -} diff --git a/src/soc/qualcomm/ipq806x/include/cdp.h b/src/soc/qualcomm/ipq806x/include/cdp.h index 4ae476a..22ba192 100644 --- a/src/soc/qualcomm/ipq806x/include/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/cdp.h @@ -4,9 +4,23 @@ #ifndef _IPQ806X_CDP_H_ #define _IPQ806X_CDP_H_ -#include <phy.h> +unsigned smem_get_board_machtype(void); -unsigned int smem_get_board_machtype(void); +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; typedef struct { unsigned int gpio; @@ -73,17 +87,17 @@ typedef struct { } spinorflash_params_t; typedef struct { - uint count; - u8 addr[7]; + unsigned count; + uint8_t addr[7]; } ipq_gmac_phy_addr_t; typedef struct { - uint base; + unsigned base; int unit; - uint is_macsec; - uint mac_pwr0; - uint mac_pwr1; - uint mac_conn_to_phy; + unsigned is_macsec; + unsigned mac_pwr0; + unsigned mac_pwr1; + unsigned mac_conn_to_phy; phy_interface_t phy; ipq_gmac_phy_addr_t phy_addr; } ipq_gmac_board_cfg_t; @@ -98,6 +112,7 @@ typedef struct { unsigned int uart_gsbi_base; unsigned int uart_dm_base; unsigned int clk_dummy; +#if 0 uart_clk_mnd_t mnd_value; unsigned int gmac_gpio_count; gpio_func_data_t *gmac_gpio; @@ -105,10 +120,12 @@ typedef struct { flash_desc flashdesc; spinorflash_params_t flash_param; gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; +#endif } __attribute__ ((__packed__)) board_ipq806x_params_t; extern board_ipq806x_params_t *gboard_param; +#if 0 static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) { /* @@ -121,7 +138,8 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); } +#endif -unsigned int get_board_index(unsigned int machid); -void ipq_configure_gpio(gpio_func_data_t *gpio, uint count); +unsigned int get_board_index(unsigned machid); +void ipq_configure_gpio(gpio_func_data_t *gpio, unsigned count); #endif diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index 5fcfde9..8642410 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -43,6 +43,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v,a) write32(v,(void *)a) +#include <arch/io.h> +#include <cdp.h> #define MSM_CLK_CTL_BASE 0x00900000 @@ -50,7 +52,7 @@ #define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) -#define GPT_REG(off) (MSM_GPT_BASE + (off)) +#define GPT_REG(off) (((uint8_t *)(MSM_GPT_BASE)) + (off)) #define DGT_REG(off) (MSM_DGT_BASE + (off)) #define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) diff --git a/src/soc/qualcomm/ipq806x/include/ipq_timer.h b/src/soc/qualcomm/ipq806x/include/ipq_timer.h new file mode 100644 index 0000000..4e1ef34 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/ipq_timer.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define TIMER_LOAD_VAL 0x21 + +#define GPT_ENABLE_CLR_ON_MATCH_EN 2 +#define GPT_ENABLE_EN 1 +#define DGT_ENABLE_CLR_ON_MATCH_EN 2 +#define DGT_ENABLE_EN 1 + +#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) + + diff --git a/src/soc/qualcomm/ipq806x/include/timer.h b/src/soc/qualcomm/ipq806x/include/timer.h deleted file mode 100644 index 4e1ef34..0000000 --- a/src/soc/qualcomm/ipq806x/include/timer.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#define TIMER_LOAD_VAL 0x21 - -#define GPT_ENABLE_CLR_ON_MATCH_EN 2 -#define GPT_ENABLE_EN 1 -#define DGT_ENABLE_CLR_ON_MATCH_EN 2 -#define DGT_ENABLE_EN 1 - -#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) - - diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 691ccbd..5c0dcb2 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -31,14 +31,10 @@ * SUCH DAMAGE. */ -#include <asm/arch-ipq806x/iomap.h> -#include <asm/io.h> -#include <common.h> -#include <asm/types.h> -#include <asm/arch-ipq806x/timer.h> - -static ulong timestamp; -static ulong lastinc; +#include <delay.h> +#include <iomap.h> +#include <ipq_timer.h> +#include <timer.h> #define GPT_FREQ_KHZ 32 #define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */ @@ -46,36 +42,24 @@ static ulong lastinc; /** * timer_init - initialize timer */ -int timer_init(void) +void init_timer(void) { writel(0, GPT_ENABLE); writel(GPT_ENABLE_EN, GPT_ENABLE); - return 0; -} - -/** - * get_timer - returns time lapsed - * @base: base/start time - * - * Returns time lapsed, since the specified base time value. - */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; } /** - * __udelay - generates micro second delay. + * udelay - generates micro second delay. * @usec: delay duration in microseconds * * With 32KHz clock, minimum possible delay is 31.25 Micro seconds and * its multiples. In Rumi GPT clock is 32 KHz */ -void __udelay(unsigned long usec) +void udelay(unsigned usec) { - unsigned int val; - ulong now, last; - ulong runcount; + unsigned val; + unsigned now, last; + unsigned runcount; usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ; last = readl(GPT_COUNT_VAL); @@ -92,6 +76,15 @@ void __udelay(unsigned long usec) } while (runcount < val); } +#if 0 + +/* + * TODO(vbendeb) clean it up later. + * Compile out the below code but leave it for now in case it will become + * necessary later in order to make the platform fully functional. + */ +static unsigned long timestamp; +static unsigned long lastinc; inline ulong gpt_to_sys_freq(unsigned int gpt) { @@ -137,3 +130,4 @@ ulong get_tbclk(void) { return GPT_FREQ; } +#endif

1 0

Patch set updated for coreboot: 67e5227 ipq8064: prepare UART driver for use in coreboot
by Marc Jones 08 Nov '14

08 Nov '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7270 -gerrit commit 67e522792f93013d5f572acf0112d178c31208a5 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Apr 22 15:25:10 2014 -0700 ipq8064: prepare UART driver for use in coreboot These driver needs to be in src/lib, and the include file needs to be renamed to avoid collision with the top level uart.h. BUG=chrome-os-partner:27784 TEST=emerge-storm coreboot still works Original-Change-Id: Ie12f44e055bbef0eb8b1a3ffc8d6742e7a446942 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196393 (cherry picked from commit c5618fd418642f5b009582f5f6bc51f7c9d54bec) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5e25ae350ac5e71b47a0daef078b03cc5ac35401 --- src/console/ipq806x_console.c | 440 ---------------------------- src/lib/uart_ipq806.c | 440 ++++++++++++++++++++++++++++ src/soc/qualcomm/ipq806x/include/ipq_uart.h | 281 ++++++++++++++++++ src/soc/qualcomm/ipq806x/include/uart.h | 281 ------------------ 4 files changed, 721 insertions(+), 721 deletions(-) diff --git a/src/console/ipq806x_console.c b/src/console/ipq806x_console.c deleted file mode 100644 index c65f876..0000000 --- a/src/console/ipq806x_console.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK boot - * - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - - -#include <common.h> -#include <asm/arch-ipq806x/gsbi.h> -#include <asm/arch-ipq806x/clock.h> -#include <asm/arch-ipq806x/uart.h> -#include <serial.h> - -#define FIFO_DATA_SIZE 4 - -extern board_ipq806x_params_t *gboard_param; - -static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base); - -/* Received data is valid or not */ -static int valid_data = 0; - -/* Received data */ -static unsigned int word = 0; - -/** - * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer - * @uart_dm_base: UART controller base address - */ -static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base) -{ - /* Reset receiver */ - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - /* Enable receiver */ - writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, - MSM_BOOT_UART_DM_DMRX(uart_dm_base)); - - /* Clear stale event */ - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - /* Enable stale event */ - writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_dm_read - reads a word from the RX FIFO. - * @data: location where the read data is stored - * @count: no of valid data in the FIFO - * @wait: indicates blocking call or not blocking call - * - * Reads a word from the RX FIFO. If no data is available blocks if - * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. - */ -static unsigned int -msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) -{ - static int total_rx_data = 0; - static int rx_data_read = 0; - unsigned int base = 0; - uint32_t status_reg; - - base = gboard_param->uart_dm_base; - - if (data == NULL) - return MSM_BOOT_UART_DM_E_INVAL; - - status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); - - /* Check for DM_RXSTALE for RX transfer to finish */ - while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { - status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); - if (!wait) - return MSM_BOOT_UART_DM_E_RX_NOT_READY; - } - - /* Check for Overrun error. We'll just reset Error Status */ - if (readl(MSM_BOOT_UART_DM_SR(base)) & - MSM_BOOT_UART_DM_SR_UART_OVERRUN) { - writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, - MSM_BOOT_UART_DM_CR(base)); - total_rx_data = rx_data_read = 0; - msm_boot_uart_dm_init(base); - return MSM_BOOT_UART_DM_E_RX_NOT_READY; - } - - /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ - if (total_rx_data == 0) - total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); - - /* Data available in FIFO; read a word. */ - *data = readl(MSM_BOOT_UART_DM_RF(base, 0)); - - /* WAR for http://prism/CR/548280 */ - if (*data == 0) { - return MSM_BOOT_UART_DM_E_RX_NOT_READY; - } - - /* increment the total count of chars we've read so far */ - rx_data_read += FIFO_DATA_SIZE; - - /* actual count of valid data in word */ - *count = ((total_rx_data < rx_data_read) ? - (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : - FIFO_DATA_SIZE); - - /* If there are still data left in FIFO we'll read them before - * initializing RX Transfer again - */ - if (rx_data_read < total_rx_data) - return MSM_BOOT_UART_DM_E_SUCCESS; - - msm_boot_uart_dm_init_rx_transfer(base); - total_rx_data = rx_data_read = 0; - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n" - * @data_in: characters to be converted - * @num_of_chars: no. of characters - * @data_out: location where converted chars are stored - * - * Replace linefeed char "\n" with carriage return + linefeed - * "\r\n". Currently keeping it simple than efficient. - */ -static unsigned int -msm_boot_uart_replace_lr_with_cr(char *data_in, - int num_of_chars, - char *data_out, int *num_of_chars_out) -{ - int i = 0, j = 0; - - if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - for (i = 0, j = 0; i < num_of_chars; i++, j++) { - if (data_in[i] == '\n') - data_out[j++] = '\r'; - - data_out[j] = data_in[i]; - } - - *num_of_chars_out = j; - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_dm_write - transmit data - * @data: data to transmit - * @num_of_chars: no. of bytes to transmit - * - * Writes the data to the TX FIFO. If no space is available blocks - * till space becomes available. - */ -static unsigned int -msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) -{ - unsigned int tx_word_count = 0; - unsigned int tx_char_left = 0, tx_char = 0; - unsigned int tx_word = 0; - int i = 0; - char *tx_data = NULL; - char new_data[1024]; - unsigned int base = gboard_param->uart_dm_base; - - if ((data == NULL) || (num_of_chars <= 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */ - msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i); - - tx_data = new_data; - num_of_chars = i; - - /* Write to NO_CHARS_FOR_TX register number of characters - * to be transmitted. However, before writing TX_FIFO must - * be empty as indicated by TX_READY interrupt in IMR register - */ - /* Check if transmit FIFO is empty. - * If not we'll wait for TX_READY interrupt. */ - - if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { - while (!(readl(MSM_BOOT_UART_DM_ISR(base)) & MSM_BOOT_UART_DM_TX_READY)) - __udelay(1); - } - - /* We are here. FIFO is ready to be written. */ - /* Write number of characters to be written */ - writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); - - /* Clear TX_READY interrupt */ - writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base)); - - /* We use four-character word FIFO. So we need to divide data into - * four characters and write in UART_DM_TF register */ - tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) : - (num_of_chars / 4); - tx_char_left = num_of_chars; - - for (i = 0; i < (int)tx_word_count; i++) { - tx_char = (tx_char_left < 4) ? tx_char_left : 4; - PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word); - - /* Wait till TX FIFO has space */ - while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY)) - __udelay(1); - - /* TX FIFO has space. Write the chars */ - writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); - tx_char_left = num_of_chars - (i + 1) * 4; - tx_data = tx_data + 4; - } - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/* - * msm_boot_uart_dm_reset - resets UART controller - * @base: UART controller base address - */ -static unsigned int msm_boot_uart_dm_reset(unsigned int base) -{ - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/* - * msm_boot_uart_dm_init - initilaizes UART controller - * @uart_dm_base: UART controller base address - */ -static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) -{ - /* Configure UART mode registers MR1 and MR2 */ - /* Hardware flow control isn't supported */ - writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); - - /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ - writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base)); - - /* Configure Interrupt Mask register IMR */ - writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base)); - - /* - * Configure Tx and Rx watermarks configuration registers - * TX watermark value is set to 0 - interrupt is generated when - * FIFO level is less than or equal to 0 - */ - writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base)); - - /* RX watermark value */ - writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base)); - - /* Configure Interrupt Programming Register */ - /* Set initial Stale timeout value */ - writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, - MSM_BOOT_UART_DM_IPR(uart_dm_base)); - - /* Configure IRDA if required */ - /* Disabling IRDA mode */ - writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); - - /* Configure hunt character value in HCR register */ - /* Keep it in reset state */ - writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); - - /* - * Configure Rx FIFO base address - * Both TX/RX shares same SRAM and default is half-n-half. - * Sticking with default value now. - * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). - * We have found RAM_ADDR_WIDTH = 0x7f - */ - - /* Issue soft reset command */ - msm_boot_uart_dm_reset(uart_dm_base); - - /* Enable/Disable Rx/Tx DM interfaces */ - /* Data Mover not currently utilized. */ - writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); - - /* Enable transmitter */ - writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - - /* Initialize Receive Path */ - msm_boot_uart_dm_init_rx_transfer(uart_dm_base); - - return 0; -} - -/** - * uart_dm_init - initializes UART - * - * Initializes clocks, GPIO and UART controller. - */ -static int uart_dm_init(void) -{ - unsigned int dm_base, gsbi_base; - - dm_base = gboard_param->uart_dm_base; - gsbi_base = gboard_param->uart_gsbi_base; - ipq_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS); - - /* Configure the uart clock */ - uart_clock_config(gboard_param->uart_gsbi, - gboard_param->mnd_value.m_value, - gboard_param->mnd_value.n_value, - gboard_param->mnd_value.d_value, - gboard_param->clk_dummy); - - writel(GSBI_PROTOCOL_CODE_I2C_UART << - GSBI_CTRL_REG_PROTOCOL_CODE_S, - GSBI_CTRL_REG(gsbi_base)); - writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); - /* Intialize UART_DM */ - msm_boot_uart_dm_init(dm_base); - - return 0; -} - -/** - * ipq806x_serial_putc - transmits a character - * @c: character to transmit - */ -static void ipq806x_serial_putc(char c) -{ - msm_boot_uart_dm_write(&c, 1); -} - -/** - * ipq806x_serial_puts - transmits a string of data - * @s: string to transmit - */ -static void ipq806x_serial_puts(const char *s) -{ - while (*s != '\0') - serial_putc(*s++); -} - -/** - * ipq806x_serial_tstc - checks if data available for reading - * - * Returns 1 if data available, 0 otherwise - */ -static int ipq806x_serial_tstc(void) -{ - /* Return if data is already read */ - if (valid_data) - return 1; - - /* Read data from the FIFO */ - if (msm_boot_uart_dm_read(&word, &valid_data, 0) != MSM_BOOT_UART_DM_E_SUCCESS) - return 0; - - return 1; -} - -/** - * ipq806x_serial_getc - reads a character - * - * Returns the character read from serial port. - */ -static int ipq806x_serial_getc(void) -{ - int byte; - - while (!serial_tstc()) { - /* wait for incoming data */ - } - - byte = (int)word & 0xff; - word = word >> 8; - valid_data--; - - return byte; -} - -static struct serial_device ipq_serial_device = { - .name = "ipq_serial", - .start = uart_dm_init, - .getc = ipq806x_serial_getc, - .tstc = ipq806x_serial_tstc, - .putc = ipq806x_serial_putc, - .puts = ipq806x_serial_puts, -}; - -__weak struct serial_device *default_serial_console(void) -{ - return &ipq_serial_device; -} - -/** - * ipq806x_serial_init - initializes serial controller - */ -void ipq806x_serial_initialize(void) -{ - serial_register(&ipq_serial_device); -} diff --git a/src/lib/uart_ipq806.c b/src/lib/uart_ipq806.c new file mode 100644 index 0000000..c65f876 --- /dev/null +++ b/src/lib/uart_ipq806.c @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK boot + * + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <common.h> +#include <asm/arch-ipq806x/gsbi.h> +#include <asm/arch-ipq806x/clock.h> +#include <asm/arch-ipq806x/uart.h> +#include <serial.h> + +#define FIFO_DATA_SIZE 4 + +extern board_ipq806x_params_t *gboard_param; + +static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base); + +/* Received data is valid or not */ +static int valid_data = 0; + +/* Received data */ +static unsigned int word = 0; + +/** + * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base) +{ + /* Reset receiver */ + writel(MSM_BOOT_UART_DM_CMD_RESET_RX, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + /* Enable receiver */ + writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, + MSM_BOOT_UART_DM_DMRX(uart_dm_base)); + + /* Clear stale event */ + writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + /* Enable stale event */ + writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * msm_boot_uart_dm_read - reads a word from the RX FIFO. + * @data: location where the read data is stored + * @count: no of valid data in the FIFO + * @wait: indicates blocking call or not blocking call + * + * Reads a word from the RX FIFO. If no data is available blocks if + * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. + */ +static unsigned int +msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) +{ + static int total_rx_data = 0; + static int rx_data_read = 0; + unsigned int base = 0; + uint32_t status_reg; + + base = gboard_param->uart_dm_base; + + if (data == NULL) + return MSM_BOOT_UART_DM_E_INVAL; + + status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); + + /* Check for DM_RXSTALE for RX transfer to finish */ + while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { + status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); + if (!wait) + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Check for Overrun error. We'll just reset Error Status */ + if (readl(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_UART_OVERRUN) { + writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, + MSM_BOOT_UART_DM_CR(base)); + total_rx_data = rx_data_read = 0; + msm_boot_uart_dm_init(base); + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ + if (total_rx_data == 0) + total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); + + /* Data available in FIFO; read a word. */ + *data = readl(MSM_BOOT_UART_DM_RF(base, 0)); + + /* WAR for http://prism/CR/548280 */ + if (*data == 0) { + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* increment the total count of chars we've read so far */ + rx_data_read += FIFO_DATA_SIZE; + + /* actual count of valid data in word */ + *count = ((total_rx_data < rx_data_read) ? + (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : + FIFO_DATA_SIZE); + + /* If there are still data left in FIFO we'll read them before + * initializing RX Transfer again + */ + if (rx_data_read < total_rx_data) + return MSM_BOOT_UART_DM_E_SUCCESS; + + msm_boot_uart_dm_init_rx_transfer(base); + total_rx_data = rx_data_read = 0; + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n" + * @data_in: characters to be converted + * @num_of_chars: no. of characters + * @data_out: location where converted chars are stored + * + * Replace linefeed char "\n" with carriage return + linefeed + * "\r\n". Currently keeping it simple than efficient. + */ +static unsigned int +msm_boot_uart_replace_lr_with_cr(char *data_in, + int num_of_chars, + char *data_out, int *num_of_chars_out) +{ + int i = 0, j = 0; + + if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0)) + return MSM_BOOT_UART_DM_E_INVAL; + + for (i = 0, j = 0; i < num_of_chars; i++, j++) { + if (data_in[i] == '\n') + data_out[j++] = '\r'; + + data_out[j] = data_in[i]; + } + + *num_of_chars_out = j; + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * msm_boot_uart_dm_write - transmit data + * @data: data to transmit + * @num_of_chars: no. of bytes to transmit + * + * Writes the data to the TX FIFO. If no space is available blocks + * till space becomes available. + */ +static unsigned int +msm_boot_uart_dm_write(char *data, unsigned int num_of_chars) +{ + unsigned int tx_word_count = 0; + unsigned int tx_char_left = 0, tx_char = 0; + unsigned int tx_word = 0; + int i = 0; + char *tx_data = NULL; + char new_data[1024]; + unsigned int base = gboard_param->uart_dm_base; + + if ((data == NULL) || (num_of_chars <= 0)) + return MSM_BOOT_UART_DM_E_INVAL; + + /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */ + msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i); + + tx_data = new_data; + num_of_chars = i; + + /* Write to NO_CHARS_FOR_TX register number of characters + * to be transmitted. However, before writing TX_FIFO must + * be empty as indicated by TX_READY interrupt in IMR register + */ + /* Check if transmit FIFO is empty. + * If not we'll wait for TX_READY interrupt. */ + + if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { + while (!(readl(MSM_BOOT_UART_DM_ISR(base)) & MSM_BOOT_UART_DM_TX_READY)) + __udelay(1); + } + + /* We are here. FIFO is ready to be written. */ + /* Write number of characters to be written */ + writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); + + /* Clear TX_READY interrupt */ + writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base)); + + /* We use four-character word FIFO. So we need to divide data into + * four characters and write in UART_DM_TF register */ + tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) : + (num_of_chars / 4); + tx_char_left = num_of_chars; + + for (i = 0; i < (int)tx_word_count; i++) { + tx_char = (tx_char_left < 4) ? tx_char_left : 4; + PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word); + + /* Wait till TX FIFO has space */ + while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY)) + __udelay(1); + + /* TX FIFO has space. Write the chars */ + writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); + tx_char_left = num_of_chars - (i + 1) * 4; + tx_data = tx_data + 4; + } + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/* + * msm_boot_uart_dm_reset - resets UART controller + * @base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(unsigned int base) +{ + writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); + writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/* + * msm_boot_uart_dm_init - initilaizes UART controller + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base)); + + /* Configure Interrupt Mask register IMR */ + writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base)); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base)); + + /* RX watermark value */ + writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base)); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, + MSM_BOOT_UART_DM_IPR(uart_dm_base)); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); + + /* Enable transmitter */ + writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, + MSM_BOOT_UART_DM_CR(uart_dm_base)); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * uart_dm_init - initializes UART + * + * Initializes clocks, GPIO and UART controller. + */ +static int uart_dm_init(void) +{ + unsigned int dm_base, gsbi_base; + + dm_base = gboard_param->uart_dm_base; + gsbi_base = gboard_param->uart_gsbi_base; + ipq_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS); + + /* Configure the uart clock */ + uart_clock_config(gboard_param->uart_gsbi, + gboard_param->mnd_value.m_value, + gboard_param->mnd_value.n_value, + gboard_param->mnd_value.d_value, + gboard_param->clk_dummy); + + writel(GSBI_PROTOCOL_CODE_I2C_UART << + GSBI_CTRL_REG_PROTOCOL_CODE_S, + GSBI_CTRL_REG(gsbi_base)); + writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); + /* Intialize UART_DM */ + msm_boot_uart_dm_init(dm_base); + + return 0; +} + +/** + * ipq806x_serial_putc - transmits a character + * @c: character to transmit + */ +static void ipq806x_serial_putc(char c) +{ + msm_boot_uart_dm_write(&c, 1); +} + +/** + * ipq806x_serial_puts - transmits a string of data + * @s: string to transmit + */ +static void ipq806x_serial_puts(const char *s) +{ + while (*s != '\0') + serial_putc(*s++); +} + +/** + * ipq806x_serial_tstc - checks if data available for reading + * + * Returns 1 if data available, 0 otherwise + */ +static int ipq806x_serial_tstc(void) +{ + /* Return if data is already read */ + if (valid_data) + return 1; + + /* Read data from the FIFO */ + if (msm_boot_uart_dm_read(&word, &valid_data, 0) != MSM_BOOT_UART_DM_E_SUCCESS) + return 0; + + return 1; +} + +/** + * ipq806x_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +static int ipq806x_serial_getc(void) +{ + int byte; + + while (!serial_tstc()) { + /* wait for incoming data */ + } + + byte = (int)word & 0xff; + word = word >> 8; + valid_data--; + + return byte; +} + +static struct serial_device ipq_serial_device = { + .name = "ipq_serial", + .start = uart_dm_init, + .getc = ipq806x_serial_getc, + .tstc = ipq806x_serial_tstc, + .putc = ipq806x_serial_putc, + .puts = ipq806x_serial_puts, +}; + +__weak struct serial_device *default_serial_console(void) +{ + return &ipq_serial_device; +} + +/** + * ipq806x_serial_init - initializes serial controller + */ +void ipq806x_serial_initialize(void) +{ + serial_register(&ipq_serial_device); +} diff --git a/src/soc/qualcomm/ipq806x/include/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/ipq_uart.h new file mode 100644 index 0000000..6fff046 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/ipq_uart.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + * + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#include <asm/io.h> +#include "common.h" +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos))\ + >> (32 - (end_pos - start_pos))) + + +extern void dsb(void); +#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \ + word = 0; \ + int j; \ + for(j=0; j < (int)cnt; j++) { \ + word |= (a[j] & 0xff)<< (j * 8);\ + } \ + } + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ + | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +#endif /* __UART_DM_H__ */ + diff --git a/src/soc/qualcomm/ipq806x/include/uart.h b/src/soc/qualcomm/ipq806x/include/uart.h deleted file mode 100644 index 6fff046..0000000 --- a/src/soc/qualcomm/ipq806x/include/uart.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* - * - * Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __UART_DM_H__ -#define __UART_DM_H__ - -#include <asm/io.h> -#include "common.h" -#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ - ((value << (32 - end_pos))\ - >> (32 - (end_pos - start_pos))) - - -extern void dsb(void); -#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \ - word = 0; \ - int j; \ - for(j=0; j < (int)cnt; j++) { \ - word |= (a[j] & 0xff)<< (j * 8);\ - } \ - } - -extern void __udelay(unsigned long usec); - - -enum MSM_BOOT_UART_DM_PARITY_MODE { - MSM_BOOT_UART_DM_NO_PARITY, - MSM_BOOT_UART_DM_ODD_PARITY, - MSM_BOOT_UART_DM_EVEN_PARITY, - MSM_BOOT_UART_DM_SPACE_PARITY -}; - -/* UART Stop Bit Length */ -enum MSM_BOOT_UART_DM_STOP_BIT_LEN { - MSM_BOOT_UART_DM_SBL_9_16, - MSM_BOOT_UART_DM_SBL_1, - MSM_BOOT_UART_DM_SBL_1_9_16, - MSM_BOOT_UART_DM_SBL_2 -}; - -/* UART Bits per Char */ -enum MSM_BOOT_UART_DM_BITS_PER_CHAR { - MSM_BOOT_UART_DM_5_BPS, - MSM_BOOT_UART_DM_6_BPS, - MSM_BOOT_UART_DM_7_BPS, - MSM_BOOT_UART_DM_8_BPS -}; - -/* 8-N-1 Configuration */ -#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ - (MSM_BOOT_UART_DM_SBL_1 << 2) | \ - (MSM_BOOT_UART_DM_8_BPS << 4)) - -/* UART_DM Registers */ - -/* UART Operational Mode Register */ -#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) -#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) -#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) -#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) - -/* UART Clock Selection Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) -#else -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) -#endif - -/* UART DM TX FIFO Registers - 4 */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) -#else -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) -#endif - -/* UART Command Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) -#else -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) -#endif -#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) -#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) -#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) -#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) - -/* UART Channel Command */ -#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) -#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) -#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ - | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) -#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) -#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) -#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) -#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) -#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) -#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) -#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) -#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) -#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) -#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) -#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) -#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) -#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) -#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) -#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) -#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) -#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) -#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) - -/*UART General Command */ -#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) - -#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) -#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) -#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) -#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) -#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) - -/* UART Interrupt Mask Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) -#else -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) -#endif - -#define MSM_BOOT_UART_DM_TXLEV (1 << 0) -#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) -#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) -#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) -#define MSM_BOOT_UART_DM_RXLEV (1 << 4) -#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) -#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) -#define MSM_BOOT_UART_DM_TX_READY (1 << 7) -#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) -#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) -#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) -#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) -#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) - -#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ - MSM_BOOT_UART_DM_TXLEV | \ - MSM_BOOT_UART_DM_RXSTALE) - -/* UART Interrupt Programming Register */ -#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ - -/* UART Transmit/Receive FIFO Watermark Register */ -#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) -/* Interrupt is generated when FIFO level is less than or equal to this value */ -#define MSM_BOOT_UART_DM_TFW_VALUE 0 - -#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) -/*Interrupt generated when no of words in RX FIFO is greater than this value */ -#define MSM_BOOT_UART_DM_RFW_VALUE 0 - -/* UART Hunt Character Register */ -#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) - -/* Used for RX transfer initialization */ -#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) - -/* Default DMRX value - any value bigger than FIFO size would be fine */ -#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 - -/* Register to enable IRDA function */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) -#else -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) -#endif - -/* UART Data Mover Enable Register */ -#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) - -/* Number of characters for Transmission */ -#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) - -/* UART RX FIFO Base Address */ -#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) - -/* UART Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) -#else -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) -#endif -#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) -#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) -#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) -#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) -#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) -#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) -#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) -#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) -#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) - -/* UART Receive FIFO Registers - 4 in numbers */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) -#else -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) -#endif - -/* UART Masked Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) -#else -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) -#endif - -/* UART Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) -#else -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) -#endif - -/* Number of characters received since the end of last RX transfer */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) -#else -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) -#endif - -/* UART TX FIFO Status Register */ -#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) -#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* UART RX FIFO Status Register */ -#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) -#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* Macros for Common Errors */ -#define MSM_BOOT_UART_DM_E_SUCCESS 0 -#define MSM_BOOT_UART_DM_E_FAILURE 1 -#define MSM_BOOT_UART_DM_E_TIMEOUT 2 -#define MSM_BOOT_UART_DM_E_INVAL 3 -#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 -#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 - -#endif /* __UART_DM_H__ */ -

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coreboot-gerrit November 2014