Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7325
-gerrit
commit 5512177efef69baacdf77f7a409b6fd9f014876c
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Nov 2 21:51:22 2014 +0100
acpigen: Add new function acpigen_pop_len
acpigen_patch_len doesn't really need its argument: length always includes
everything from length bytes to current pointer and never bytes before it.
Hence just infer all the info implicitly.
Argument is wrong in several places through the codebase but ACPI parsing
is lax enough to swallow incorrect SSDT. After this function is used throughout
the codebase, these issues will be fixed.
Change-Id: I9fa536a614c5595146a7a1cd71f2676d8a8d9c2f
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/acpigen.c | 13 +++++++++++++
src/arch/x86/include/arch/acpigen.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index 222a2db..0689273 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -57,6 +57,19 @@ void acpigen_patch_len(int len)
}
+void acpigen_pop_len(void)
+{
+ int len;
+ ASSERT(ltop > 0)
+ char *p = len_stack[--ltop];
+ len = gencurrent - p;
+ ASSERT(len <= ACPIGEN_MAXLEN)
+ /* generate store length for 0xfff max */
+ p[0] = (0x40 | (len & 0xf));
+ p[1] = (len >> 4 & 0xff);
+
+}
+
void acpigen_set_current(char *curr)
{
gencurrent = curr;
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index 3217dbe..d9df5d0 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -27,6 +27,7 @@
int acpigen_write_len_f(void);
void acpigen_patch_len(int len);
+void acpigen_pop_len(void);
void acpigen_set_current(char *curr);
char *acpigen_get_current(void);
int acpigen_write_package(int nr_el);
Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7355
-gerrit
commit da45e8a9892caaa6defbafb8eb0949b8bb3b622c
Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
Date: Sat Nov 8 00:38:33 2014 +0100
Hudson: Add support for hiding the USB1.1-only OHCI
The hudson chipset has 4 USB controllers, the fourth is USB1.1-only and
(presumably) not used very often, add support for hiding it:
00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03) USB1 (3.0, XHCI)
00:10.1 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03)
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB2 (2.0, OHCI+EHCI)
00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB3 (2.0, OHCI+EHCI)
00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB4 (1.1, OHCI only)
On the F2A85M the vendor BIOS is hiding both the USB4 OHCI and the SD
controller, adjust devicetree.cb accordingly.
Support for hiding the SD controller already exists, but was not yet
used in the F2A85M devicetree.cb.
Includes a small whitespace fix.
Change-Id: I804e7852fd0a6f870dd118b429473cb06ebac9a4
Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
---
src/mainboard/asus/f2a85-m/devicetree.cb | 7 +++----
src/southbridge/amd/agesa/hudson/hudson.c | 14 ++++++++++++++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 9ac5574..40d9c88 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -32,7 +32,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
- device pci 2.0 on end # PCIE SLOT0 x16 blue
+ device pci 2.0 on end # PCIE SLOT0 x16 blue
device pci 3.0 off end # unused?
device pci 4.0 on end # PCIE 4x black
device pci 5.0 off end # unused?
@@ -108,10 +108,9 @@ chip northbridge/amd/agesa/family15tn/root_complex
end #superio/ite/it8728f
end #device pci 14.3 # LPC
device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # USB 2
+ device pci 14.5 off end # Hide USB4 (USB1.1-only OHCI)
device pci 14.6 off end # Gec
- # SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away)
- device pci 14.7 on end
+ device pci 14.7 off end # Hide unused SD controller
device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
device pci 15.1 on end # PCIe 1 onboard gigabit
device pci 15.2 off end # unused
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index 3b57221..c33dc9b 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -109,6 +109,20 @@ void hudson_enable(device_t dev)
pm_write8(0xd3, reg8);
}
break;
+ case (0x14 << 3) | 5: /* 0:14.5 USB1.1 OHCI (USB4) */
+ if (dev->enabled == 0) {
+ // read the VENDEV ID
+ device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 5));
+ u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16;
+ u8 reg8;
+ if (sd_device_id == PCI_DEVICE_ID_ATI_SB900_USB_20_5) {
+ /* turn off and remove device 0:14.5 from PCI space */
+ reg8 = pm_read8(0xef);
+ reg8 &= ~(1 << 6);
+ pm_write8(0xef, reg8);
+ }
+ }
+ break;
default:
break;
}
the following patch was just integrated into master:
commit 67bfbfdfebb280fae5d2aac5e68bb8f014a7de71
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Oct 25 15:49:23 2014 +0200
ibexpeak: Move to common FADT
Change-Id: Ibb4dcc4356876f6385e79c10d8296fb680937827
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/7201
Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/7201 for details.
-gerrit
the following patch was just integrated into master:
commit 5b044ae6077bfd6bbc162741cc5b3086dbf56d34
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Oct 25 15:20:55 2014 +0200
bd82x6x: Move to common FADT.
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/7200
Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/7200 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7357
-gerrit
commit 43646692b0f18cd45206e16f6c316bec01a6bf9f
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Nov 8 13:16:46 2014 +0100
car globals: add "used" attribute
Otherwise clang feels free to optimize away that variable
(somewhat) and revive it in a different form inside .bss.
They probably have the language lawyery excuse for why
that's perfectly legal, so let's play it safe.
(relevant URL, sorry ron: http://llvm.org/bugs/show_bug.cgi?id=9520)
Change-Id: I603312ceea7207088dd29453cc8fb8f48c31af21
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/arch/x86/include/arch/early_variables.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
index ea57d89..c850a84 100644
--- a/src/arch/x86/include/arch/early_variables.h
+++ b/src/arch/x86/include/arch/early_variables.h
@@ -23,7 +23,7 @@
#ifdef __PRE_RAM__
asm(".section .car.global_data,\"w\",@nobits");
asm(".previous");
-#define CAR_GLOBAL __attribute__((section(".car.global_data")))
+#define CAR_GLOBAL __attribute__((used,section(".car.global_data")))
#else
#define CAR_GLOBAL
#endif