coreboot-gerrit June 2013

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New patch to review for coreboot: 0f1965a AMD southbridges: Move HAVE_HARD_RESET
by Kyösti Mälkki 16 Jun '13

16 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3486 -gerrit commit 0f1965abf6df4061e9afa9dfae58f7aabe84a4a1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 16 17:12:37 2013 +0300 AMD southbridges: Move HAVE_HARD_RESET All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Kconfig | 1 - src/mainboard/advansus/a785e-i/Makefile.inc | 2 - src/mainboard/advansus/a785e-i/reset.c | 65 ---------------------- src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/amd/dinar/Makefile.inc | 1 - src/mainboard/amd/dinar/reset.c | 67 ----------------------- src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/inagua/Makefile.inc | 1 - src/mainboard/amd/inagua/reset.c | 67 ----------------------- src/mainboard/amd/parmer/Kconfig | 1 - src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/persimmon/Makefile.inc | 1 - src/mainboard/amd/persimmon/reset.c | 67 ----------------------- src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/south_station/Makefile.inc | 1 - src/mainboard/amd/south_station/reset.c | 67 ----------------------- src/mainboard/amd/thatcher/Kconfig | 1 - src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/amd/torpedo/Makefile.inc | 1 - src/mainboard/amd/torpedo/reset.c | 67 ----------------------- src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/amd/union_station/Makefile.inc | 1 - src/mainboard/amd/union_station/reset.c | 67 ----------------------- src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asrock/e350m1/Makefile.inc | 1 - src/mainboard/asrock/e350m1/reset.c | 67 ----------------------- src/mainboard/asus/f2a85-m/Kconfig | 1 - src/mainboard/asus/m5a88-v/Kconfig | 1 - src/mainboard/asus/m5a88-v/Makefile.inc | 1 - src/mainboard/asus/m5a88-v/reset.c | 65 ---------------------- src/mainboard/avalue/eax-785e/Kconfig | 1 - src/mainboard/avalue/eax-785e/Makefile.inc | 2 - src/mainboard/avalue/eax-785e/reset.c | 65 ---------------------- src/mainboard/lippert/frontrunner-af/Kconfig | 1 - src/mainboard/lippert/frontrunner-af/Makefile.inc | 1 - src/mainboard/lippert/frontrunner-af/reset.c | 67 ----------------------- src/mainboard/lippert/toucan-af/Kconfig | 1 - src/mainboard/lippert/toucan-af/Makefile.inc | 1 - src/mainboard/lippert/toucan-af/reset.c | 67 ----------------------- src/mainboard/supermicro/h8qgi/Kconfig | 1 - src/mainboard/supermicro/h8qgi/Makefile.inc | 2 - src/mainboard/supermicro/h8qgi/reset.c | 67 ----------------------- src/mainboard/supermicro/h8scm/Kconfig | 1 - src/mainboard/supermicro/h8scm/Makefile.inc | 2 - src/mainboard/supermicro/h8scm/reset.c | 67 ----------------------- src/mainboard/tyan/s8226/Kconfig | 1 - src/mainboard/tyan/s8226/Makefile.inc | 2 - src/mainboard/tyan/s8226/reset.c | 67 ----------------------- src/southbridge/amd/agesa/hudson/Kconfig | 1 + src/southbridge/amd/cimx/sb700/Kconfig | 1 + src/southbridge/amd/cimx/sb700/Makefile.inc | 2 + src/southbridge/amd/cimx/sb700/reset.c | 67 +++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/Kconfig | 1 + src/southbridge/amd/cimx/sb800/Makefile.inc | 2 + src/southbridge/amd/cimx/sb800/reset.c | 67 +++++++++++++++++++++++ src/southbridge/amd/cimx/sb900/Kconfig | 1 + src/southbridge/amd/cimx/sb900/Makefile.inc | 2 + src/southbridge/amd/cimx/sb900/reset.c | 67 +++++++++++++++++++++++ 58 files changed, 211 insertions(+), 1037 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 3753df8..fdf08aa 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index d69a9bf..65a62ed 100644 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -1,6 +1,4 @@ -#romstage-y += reset.c #FIXME romstage have include test_rest.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/advansus/a785e-i/reset.c b/src/mainboard/advansus/a785e-i/reset.c deleted file mode 100644 index 678bc3d..0000000 --- a/src/mainboard/advansus/a785e-i/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index 48c1e74..3bb2257 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select HAVE_ACPI_TABLES #TODO select HAVE_ACPI_RESUME select ENABLE_APIC_EXT_ID diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc index 42f458b..8dfe21d 100644 --- a/src/mainboard/amd/dinar/Makefile.inc +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -29,7 +29,6 @@ ramstage-y += BiosCallOuts.c ramstage-y += sb700_cfg.c ramstage-y += rd890_cfg.c -ramstage-y += reset.c AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\ diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c deleted file mode 100644 index f2a2bcd..0000000 --- a/src/mainboard/amd/dinar/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 3c1431e..1d8128e 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc index b84a03a..f5c52f0 100644 --- a/src/mainboard/amd/inagua/Makefile.inc +++ b/src/mainboard/amd/inagua/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c ramstage-y += broadcom.c diff --git a/src/mainboard/amd/inagua/reset.c b/src/mainboard/amd/inagua/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/inagua/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 678432b..8dd457b 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 2e7442c..5758ecf 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index 17443bc..e1f18a9 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/persimmon/reset.c b/src/mainboard/amd/persimmon/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/persimmon/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 1c5e401..ec16e6c 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index 59c6cd0..2105082 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/south_station/reset.c b/src/mainboard/amd/south_station/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/south_station/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index f619478..a9227e5 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 2c70143..37255f2 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc index 26beb37..1102ea2 100644 --- a/src/mainboard/amd/torpedo/Makefile.inc +++ b/src/mainboard/amd/torpedo/Makefile.inc @@ -44,4 +44,3 @@ ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/torpedo/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index e3e4bfe..a096d66 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index 59c6cd0..2105082 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/union_station/reset.c b/src/mainboard/amd/union_station/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/union_station/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 4c05037..bf44af3 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc index 59c6cd0..2105082 100644 --- a/src/mainboard/asrock/e350m1/Makefile.inc +++ b/src/mainboard/asrock/e350m1/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/asrock/e350m1/reset.c b/src/mainboard/asrock/e350m1/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/asrock/e350m1/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index ad2c8b7..f26b8d5 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 5318977..942a81d 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_ITE_IT8721F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index 35b2043..924f9d6 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -1,4 +1,3 @@ -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/asus/m5a88-v/reset.c b/src/mainboard/asus/m5a88-v/reset.c deleted file mode 100644 index 678bc3d..0000000 --- a/src/mainboard/asus/m5a88-v/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 11fc657..99b9c67 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index d69a9bf..65a62ed 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -1,6 +1,4 @@ -#romstage-y += reset.c #FIXME romstage have include test_rest.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/avalue/eax-785e/reset.c b/src/mainboard/avalue/eax-785e/reset.c deleted file mode 100644 index 678bc3d..0000000 --- a/src/mainboard/avalue/eax-785e/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index d326746..9ddf970 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -35,7 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 17443bc..e1f18a9 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/lippert/frontrunner-af/reset.c b/src/mainboard/lippert/frontrunner-af/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/lippert/frontrunner-af/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index e8f5896..07fbbea 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -37,7 +37,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index 17443bc..e1f18a9 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/lippert/toucan-af/reset.c b/src/mainboard/lippert/toucan-af/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/lippert/toucan-af/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 1184a93..f13593e 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index 451e013..77e8719 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c deleted file mode 100644 index 7a96aa4..0000000 --- a/src/mainboard/supermicro/h8qgi/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 95e6f81..1eadc36 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc index 451e013..77e8719 100644 --- a/src/mainboard/supermicro/h8scm/Makefile.inc +++ b/src/mainboard/supermicro/h8scm/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/supermicro/h8scm/reset.c b/src/mainboard/supermicro/h8scm/reset.c deleted file mode 100644 index 7a96aa4..0000000 --- a/src/mainboard/supermicro/h8scm/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 1db75b3..0d832fe 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc index 451e013..77e8719 100644 --- a/src/mainboard/tyan/s8226/Makefile.inc +++ b/src/mainboard/tyan/s8226/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/tyan/s8226/reset.c b/src/mainboard/tyan/s8226/reset.c deleted file mode 100644 index 7a96aa4..0000000 --- a/src/mainboard/tyan/s8226/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 7aa3405..f67b663 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index e98d3ed..97cdf1c 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB700 bool select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB700 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc index 94a0dea..268629f 100644 --- a/src/southbridge/amd/cimx/sb700/Makefile.inc +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -22,8 +22,10 @@ romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += late.c +ramstage-y += reset.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c new file mode 100644 index 0000000..7a96aa4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 554d8c7..b82409d 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 default n select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 524c2d3..831cc2e 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -23,9 +23,11 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += cfg.c ramstage-y += late.c +ramstage-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c new file mode 100644 index 0000000..7a96aa4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index aa30e56..5d3b0a1 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB900 default n select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB900 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index ebb3e3f..cc4c553 100755 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -23,10 +23,12 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += cfg.c ramstage-y += early.c ramstage-y += late.c +ramstage-y += reset.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c new file mode 100644 index 0000000..7a96aa4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} +

1 0

New patch to review for coreboot: 109783c AMD boards: Clean use of Kconfig options
by Kyösti Mälkki 16 Jun '13

16 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3485 -gerrit commit 109783ceb0060da0f54825fba498c80fdf56b7cc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 16 17:30:29 2013 +0300 AMD boards: Clean use of Kconfig options The chip component is unconditionally selected for the mainboard so these uses are superfluous. Change-Id: I84b053ab47f7b1f68e88d968cf305e24bc95f4da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/supermicro/h8qgi/Makefile.inc | 12 ++++++------ src/mainboard/supermicro/h8scm/Makefile.inc | 12 ++++++------ src/mainboard/tyan/s8226/Makefile.inc | 12 ++++++------ 5 files changed, 18 insertions(+), 20 deletions(-) diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index 9edbe7a..48c1e74 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -146,7 +146,6 @@ config CONSOLE_POST config SATA_CONTROLLER_MODE hex default 0x0 - depends on SOUTHBRIDGE_AMD_CIMX_SB700 config ONBOARD_LAN bool diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index ac42a4f..2c70143 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -168,7 +168,6 @@ config CONSOLE_POST config SATA_CONTROLLER_MODE hex default 0x0 - depends on SOUTHBRIDGE_AMD_CIMX_SB900 config ONBOARD_LAN bool diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index cd56c47..451e013 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -17,17 +17,17 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +romstage-y += rd890_cfg.c +romstage-y += sb700_cfg.c +romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c -ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +ramstage-y += rd890_cfg.c +ramstage-y += sb700_cfg.c +ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc index cd56c47..451e013 100644 --- a/src/mainboard/supermicro/h8scm/Makefile.inc +++ b/src/mainboard/supermicro/h8scm/Makefile.inc @@ -17,17 +17,17 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +romstage-y += rd890_cfg.c +romstage-y += sb700_cfg.c +romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c -ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +ramstage-y += rd890_cfg.c +ramstage-y += sb700_cfg.c +ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc index cd56c47..451e013 100644 --- a/src/mainboard/tyan/s8226/Makefile.inc +++ b/src/mainboard/tyan/s8226/Makefile.inc @@ -17,17 +17,17 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +romstage-y += rd890_cfg.c +romstage-y += sb700_cfg.c +romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c -ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +ramstage-y += rd890_cfg.c +ramstage-y += sb700_cfg.c +ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c

1 0

Patch set updated for coreboot: 6014532 usbdebug: Support second EHCI controller with Debug Port
by Kyösti Mälkki 16 Jun '13

16 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3438 -gerrit commit 60145324d3b14a74797c8a2d5b64bf3c898dc826 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 11 23:43:08 2013 +0300 usbdebug: Support second EHCI controller with Debug Port Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 29 +++++++++++++++++----- src/console/console.c | 2 +- src/console/usbdebug_console.c | 7 ++++-- src/include/usbdebug.h | 6 ++++- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 15 +++++++---- src/southbridge/amd/sb600/enable_usbdebug.c | 9 +++++-- src/southbridge/amd/sb700/enable_usbdebug.c | 19 ++++++++------ src/southbridge/amd/sb800/enable_usbdebug.c | 15 +++++++---- src/southbridge/intel/common/usb_debug.c | 9 +++++-- src/southbridge/nvidia/ck804/enable_usbdebug.c | 11 +++++--- src/southbridge/nvidia/mcp55/enable_usbdebug.c | 11 +++++--- src/southbridge/sis/sis966/enable_usbdebug.c | 11 +++++--- 12 files changed, 104 insertions(+), 40 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index dc41fd3..c943c99 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -127,9 +127,13 @@ config SPKMODEM # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG - def_bool n + bool + default y if HAVE_USBDEBUG_OPTIONS + default n -config USBDEBUG +# Use "select HAVE_USBDEBUG_OPTIONS" on southbridges with multiple +# EHCI controllers having Debug Port capability +config HAVE_USBDEBUG_OPTIONS def_bool n config USBDEBUG @@ -153,13 +157,24 @@ config USBDEBUG If unsure, say N. -# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges -# as those hardcode the physical USB port to be used as Debug Port to 1. -# It cannot be changed by coreboot. +config USBDEBUG_HCD_INDEX + int "Index for EHCI controller to use with usbdebug" + default 0 + depends on USBDEBUG && HAVE_USBDEBUG_OPTIONS + help + Some boards have multiple EHCI controllers with possibly only + one having the Debug Port capability on an external USB port. + + Mapping of this index to PCI device functions is southbridge + specific and mainboard level Kconfig should already provide + a working default value here. + + If unsure, do not change. + config USBDEBUG_DEFAULT_PORT int "Default USB port to use as Debug Port" default 1 - depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600 + depends on USBDEBUG && HAVE_USBDEBUG_OPTIONS help This option selects which physical USB port coreboot will try to use as EHCI Debug Port first (valid values are: 1-15). @@ -174,6 +189,8 @@ config USBDEBUG_DEFAULT_PORT on your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error. + If unsure, do not change. + # TODO: Deps? # TODO: Improve description. config ONBOARD_VGA_IS_PRIMARY diff --git a/src/console/console.c b/src/console/console.c index 2f7de02..1391cb7 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -104,7 +104,7 @@ void console_init(void) #if CONFIG_EARLY_CONSOLE #if CONFIG_USBDEBUG - enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + enable_usbdebug(CONFIG_USBDEBUG_HCD_INDEX, CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif #if CONFIG_CONSOLE_SERIAL diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index 9cfb454..2f61c6b 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <usbdebug.h> #include <device/pci.h> +#include <device/pci_def.h> #include <pc80/mc146818rtc.h> static struct ehci_debug_info dbg_info; @@ -75,7 +76,9 @@ static void pci_ehci_set_resources(struct device *dev) void pci_ehci_read_resources(struct device *dev) { - if (!ehci_drv_ops) { + simple_device_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + + if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) { memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops)); ehci_drv_ops = dev->ops; ehci_dbg_ops.set_resources = pci_ehci_set_resources; @@ -91,7 +94,7 @@ void pci_ehci_read_resources(struct device *dev) static void dbgp_init(void) { #if !CONFIG_EARLY_CONSOLE - enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + enable_usbdebug(CONFIG_USBDEBUG_HCD_INDEX, CONFIG_USBDEBUG_DEFAULT_PORT); #endif usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info); } diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index bece8c6..9c549de 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -22,6 +22,10 @@ #define USBDEBUG_H #define EHCI_BAR_INDEX 0x10 +#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ + +typedef unsigned int simple_device_t; +simple_device_t pci_ehci_dbg_dev(unsigned hcd_idx); #ifndef __PRE_RAM__ #if !CONFIG_USBDEBUG @@ -51,7 +55,7 @@ struct ehci_debug_info { u8 bufidx; }; -void enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int hcd_idx, unsigned int port); int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); void set_ehci_base(unsigned ehci_base); diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 128885a..c6e7a08 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -29,6 +29,11 @@ #define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2); +} + void set_debug_port(unsigned int port) { u32 reg32; @@ -42,15 +47,15 @@ void set_debug_port(unsigned int port) } -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); + /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), - EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), - PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); set_debug_port(port); } diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 305362f..76ad481 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -23,15 +23,20 @@ #include <device/pci_def.h> #include "sb600.h" +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ +} + /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) { /* TODO: Allow changing the physical USB port used as Debug Port. */ } -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { - device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Select the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 2a7fc38..49e117a 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -27,6 +27,16 @@ #define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +/* + * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. + * This code currently only supports the first one, i.e., USB Debug devices + * attached to physical USB ports belonging to the first EHCI device. + */ +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x12, 2); +} + void set_debug_port(unsigned int port) { u32 reg32; @@ -39,14 +49,9 @@ void set_debug_port(unsigned int port) write32(DEBUGPORT_MISC_CONTROL, reg32); } -/* - * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. - * This code currently only supports the first one, i.e., USB Debug devices - * attached to physical USB ports belonging to the first EHCI device. - */ -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { - device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 28a1665..227c0c7 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -29,6 +29,11 @@ #define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2); +} + void set_debug_port(unsigned int port) { u32 reg32; @@ -42,15 +47,15 @@ void set_debug_port(unsigned int port) } -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); + /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); set_debug_port(port); } diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 397c686..af785d3 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -26,16 +26,21 @@ #include <usbdebug.h> #include <device/pci_def.h> +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x1d, 7); +} + /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { u32 dbgctl; - device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 659fdc6..3fe40af 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -33,10 +33,15 @@ #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ +} + void set_debug_port(unsigned int port) { u32 dword; - device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -45,9 +50,9 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { - device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index f753c78..1f63ecb 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -27,10 +27,15 @@ #include <device/pci_def.h> #include "mcp55.h" +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ +} + void set_debug_port(unsigned int port) { u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -39,9 +44,9 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index 78a3838..c408d28 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -29,10 +29,15 @@ #include <device/pci_def.h> #include "sis966.h" +simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ +} + void set_debug_port(unsigned int port) { u32 dword; - device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -41,9 +46,9 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int hcd_idx, unsigned int port) { - device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ + simple_device_t dev = pci_ehci_dbg_dev(hcd_idx); /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port);

1 0

Patch set updated for coreboot: 50806b2 Match device_t between romstage and ramstage
by Kyösti Mälkki 16 Jun '13

16 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3474 -gerrit commit 50806b2797f6beaeddcc376a93682bd37ec4c145 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 17:16:56 2013 +0300 Match device_t between romstage and ramstage The aliased typedef of device_t causes problems when a function declaration is included for a source compilied without __PRE_RAM__ but the function definition is compiled with __PRE_RAM__. For such cases use simple_device_t. Add a function to test if simple_device_t (from romstage) matches with a device_t (from ramstage) for PCI devices by comparing bus:dev.fn. Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 1 + src/device/pci_device.c | 13 +++++++++++++ src/include/device/device.h | 1 + src/include/device/pci.h | 1 + src/include/device/pci_def.h | 4 ++++ 5 files changed, 20 insertions(+) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 29c8339..3450cb2 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -207,6 +207,7 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ +typedef device_t simple_device_t; /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4c5a814..8a7d080 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1054,6 +1054,19 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) } /** + * Test for match between romstage and ramstage device instance. + * + * @param dev Pointer to the device structure. + * @param sdev Simple device model identifier, created with PCI_DEV(). + * @return Non-zero if bus:dev.fn of device matches. + */ +unsigned int pci_match_simple_dev(device_t dev, simple_device_t sdev) +{ + return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); +} + +/** * Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are diff --git a/src/include/device/device.h b/src/include/device/device.h index 44a9742..ac75b21 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -10,6 +10,7 @@ struct device; #ifndef __PRE_RAM__ typedef struct device * device_t; +typedef unsigned int simple_device_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..249c242 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -77,6 +77,7 @@ unsigned pci_find_capability(device_t dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); +unsigned int pci_match_simple_dev(device_t dev, simple_device_t sdev); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 58a7321..c24c445 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -474,4 +474,8 @@ #define PCI_FUNC(devfn) ((devfn) & 0x07) #define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8) +/* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ +#define PCI_DEV2DEVFN(sdev) ((sdev>>12)&0xff) +#define PCI_DEV2SEGBUS(sdev) ((sdev>>20)&0xfff) + #endif /* PCI_DEF_H */

1 0

New patch to review for coreboot: 5a8dbc5 pnp: Add some default functions to enter/exit config state
by Nico Huber 16 Jun '13

16 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3484 -gerrit commit 5a8dbc55036dfb34ce3253ea01e17747e41e717c Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 20:33:44 2013 +0200 pnp: Add some default functions to enter/exit config state Implement some common default functions to enter and exit the configuration state. Also provide default pnp_mode_ops for common enter()/exit() function pairs. The following cocci ensures their use: @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; @ enter_match_8787 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } @ depends on enter_match_8787 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_8787, }; @ enter_match_55 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x55, dev->path.pnp.port); } @ depends on enter_match_55 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_55, }; @ depends on enter_match_8787 || enter_match_55 @ identifier mode_match.enter; @@ -enter(...) {...} @ exit_match_aa @ identifier mode_match.exit, dev; @@ exit(...) { outb(0xaa, dev->path.pnp.port); } @ depends on exit_match_aa @ identifier mode_match.exit, mode_match.ops; @@ struct pnp_mode_ops ops = { - .exit_conf_mode = exit, + .exit_conf_mode = pnp_exit_conf_mode_aa, }; @ depends on exit_match_aa @ identifier mode_match.exit; @@ -exit(...) {...} @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @ @@ #include <device/pnp.h> +#include <superio/conf_mode.h> @ mode_match_55_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_55_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_55_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; @ mode_match_8787_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_8787_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_8787_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/include/superio/conf_mode.h | 15 ++++++++++ src/superio/Makefile.inc | 1 + src/superio/common/conf_mode.c | 50 +++++++++++++++++++++++++++++++++ src/superio/fintek/f71805f/superio.c | 19 ++----------- src/superio/fintek/f71859/superio.c | 19 ++----------- src/superio/fintek/f71863fg/superio.c | 19 ++----------- src/superio/fintek/f71872/superio.c | 19 ++----------- src/superio/fintek/f71889/superio.c | 19 ++----------- src/superio/fintek/f81865f/superio.c | 19 ++----------- src/superio/nuvoton/nct5104d/superio.c | 19 ++----------- src/superio/smsc/kbc1100/superio.c | 21 ++------------ src/superio/smsc/lpc47b272/superio.c | 21 ++------------ src/superio/smsc/lpc47b397/superio.c | 20 ++----------- src/superio/smsc/lpc47m10x/superio.c | 21 ++------------ src/superio/smsc/lpc47m15x/superio.c | 21 ++------------ src/superio/smsc/mec1308/superio.c | 18 ++---------- src/superio/smsc/sch4037/superio.c | 21 ++------------ src/superio/smsc/sio1036/superio.c | 21 ++------------ src/superio/smsc/smscsuperio/superio.c | 34 ++-------------------- src/superio/via/vt1211/vt1211.c | 19 ++----------- src/superio/winbond/w83627dhg/superio.c | 19 ++----------- src/superio/winbond/w83627ehg/superio.c | 19 ++----------- src/superio/winbond/w83627hf/superio.c | 19 ++----------- src/superio/winbond/w83627thg/superio.c | 19 ++----------- src/superio/winbond/w83627uhg/superio.c | 19 ++----------- src/superio/winbond/w83697hf/superio.c | 19 ++----------- src/superio/winbond/w83977f/superio.c | 19 ++----------- src/superio/winbond/w83977tf/superio.c | 19 ++----------- 28 files changed, 117 insertions(+), 451 deletions(-) diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h new file mode 100644 index 0000000..db341ba --- /dev/null +++ b/src/include/superio/conf_mode.h @@ -0,0 +1,15 @@ +#ifndef DEVICE_PNP_CONF_MODE_H +#define DEVICE_PNP_CONF_MODE_H + +#include <device/device.h> +#include <device/pnp.h> + +/* Common enter/exit implementations */ +void pnp_enter_conf_mode_55(device_t dev); +void pnp_enter_conf_mode_8787(device_t dev); +void pnp_exit_conf_mode_aa(device_t dev); + +extern const struct pnp_mode_ops pnp_conf_mode_55_aa; +extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; + +#endif diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index ff4d48f..e34fa89 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -28,3 +28,4 @@ subdirs-y += smsc subdirs-y += via subdirs-y += winbond +ramstage-$(CONFIG_ARCH_X86) += common/conf_mode.c diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c new file mode 100644 index 0000000..c4bd608 --- /dev/null +++ b/src/superio/common/conf_mode.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <superio/conf_mode.h> + +/* Common enter/exit implementations */ + +void pnp_enter_conf_mode_55(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +void pnp_enter_conf_mode_8787(device_t dev) +{ + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); +} + +void pnp_exit_conf_mode_aa(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +const struct pnp_mode_ops pnp_conf_mode_55_aa = { + .enter_conf_mode = pnp_enter_conf_mode_55, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + +const struct pnp_mode_ops pnp_conf_mode_8787_aa = { + .enter_conf_mode = pnp_enter_conf_mode_8787, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 50c3355..4a31606 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "f71805f.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71805f_init(device_t dev) { if (!dev->enabled) @@ -45,18 +35,13 @@ static void f71805f_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71805f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 1e5b6ec..2736c0b 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -22,22 +22,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "f71859.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71859_init(device_t dev) { if (!dev->enabled) @@ -46,18 +36,13 @@ static void f71859_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71859_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 84a7ec1..4159e6d 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -21,23 +21,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "chip.h" #include "f71863fg.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71863fg_init(device_t dev) { struct superio_fintek_f71863fg_config *conf = dev->chip_info; @@ -55,18 +45,13 @@ static void f71863fg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71863fg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 8db22a9..55a11b1 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include "chip.h" #include "f71872.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71872_init(device_t dev) { struct superio_fintek_f71872_config *conf = dev->chip_info; @@ -52,18 +42,13 @@ static void f71872_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71872_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 8de8ae8..450f938 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -21,23 +21,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "chip.h" #include "f71889.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71889_init(device_t dev) { struct superio_fintek_f71889_config *conf = dev->chip_info; @@ -53,18 +43,13 @@ static void f71889_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71889_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 050602c..85ac7ba 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include "chip.h" #include "f81865f.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f81865f_init(device_t dev) { struct superio_fintek_f81865f_config *conf = dev->chip_info; @@ -52,18 +42,13 @@ static void f81865f_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f81865f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index c8b696d..5eb8991 100755 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -20,36 +20,21 @@ #include <arch/io.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <stdlib.h> #include "nct5104d.h" -static void pnp_enter_exteded_mode(device_t dev) -{ - outb(0x87,dev->path.pnp.port); - outb(0x87,dev->path.pnp.port); -} - -static void pnp_exit_extended_mode(device_t dev) -{ - outb(0xaa,dev->path.pnp.port); -} - static void nct5104d_init(device_t dev) { } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_exteded_mode, - .exit_conf_mode = pnp_exit_extended_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = nct5104d_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index a6d0ef0..c56694c 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void kbc1100_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_kbc1100_ops = { CHIP_NAME("SMSC KBC1100 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = kbc1100_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -86,13 +79,3 @@ static void kbc1100_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index d06f094..8901ec4 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -26,6 +26,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -38,9 +39,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); static void lpc47b272_init(device_t dev); - -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); // static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47b272_ops = { @@ -48,18 +46,13 @@ struct chip_operations superio_smsc_lpc47b272_ops = { .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b272_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -105,16 +98,6 @@ static void lpc47b272_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - #if 0 /** * Print the values of all of the LPC47B272's configuration registers. diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 850b7bb..ff6e405 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -32,16 +33,6 @@ #include "chip.h" #include "lpc47b397.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -94,18 +85,13 @@ static void lpc47b397_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b397_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; #define HWM_INDEX 0 @@ -165,7 +151,7 @@ static struct device_operations ops_hwm = { .init = lpc47b397_init, .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 925defa..c1f3c2c 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -25,6 +25,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -37,9 +38,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); static void lpc47m10x_init(device_t dev); - -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); // static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47m10x_ops = { @@ -47,18 +45,13 @@ struct chip_operations superio_smsc_lpc47m10x_ops = { .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47m10x_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -104,16 +97,6 @@ static void lpc47m10x_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - #if 0 /** * Print the values of all of the LPC47M10X2's configuration registers. diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index a3b8fc5..7e400fc 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void lpc47m15x_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_lpc47m15x_ops = { CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47m15x_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -84,13 +77,3 @@ static void lpc47m15x_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 0385b26..448800e 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -33,16 +34,6 @@ #include <arch/acpi.h> #endif -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void mec1308_init(device_t dev) { struct superio_smsc_mec1308_config *conf = dev->chip_info; @@ -61,18 +52,13 @@ static void mec1308_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = mec1308_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 254b838..96d35fe 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void sch4037_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_sch4037_ops = { CHIP_NAME("SMSC SCH4037 Super I/O") .enable_dev = enable_dev, }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = sch4037_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -85,13 +78,3 @@ static void sch4037_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index 2ce2af2..ff7b5d1 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void sio1036_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_sio1036_ops = { CHIP_NAME("SMSC SIO1036 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = sio1036_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -84,13 +77,3 @@ static void sio1036_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index d45a967..42a9c09 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -37,6 +37,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <uart8250.h> #include <pc80/keyboard.h> @@ -144,32 +145,6 @@ static const struct logical_devices { }; /** - * Enter the configuration state by writing 0x55 to the config port. - * - * The Super I/O configuration registers can only be modified when the chip - * is in the configuration state. Thus, to program the registers you have - * to a) enter config mode, b) program the registers, c) exit config mode. - * - * @param dev The device to use. - */ -static void smsc_pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -/** - * Exit the configuration state by writing 0xaa to the config port. - * - * This puts the chip into the 'run' state again. - * - * @param dev The device to use. - */ -static void smsc_pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - -/** * Initialize those logical devices which need a special init. * * @param dev The device to use. @@ -199,11 +174,6 @@ static void smsc_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = smsc_pnp_enter_conf_state, - .exit_conf_mode = smsc_pnp_exit_conf_state, -}; - /** Standard device operations. */ static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -211,7 +181,7 @@ static struct device_operations ops = { .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = smsc_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; /** diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 8e09e4a..68fd999 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <uart8250.h> #include <stdlib.h> #include "vt1211.h" @@ -44,17 +45,6 @@ static u8 hwm_io_regs[] = { 0x5c,0x00, 0x5f,0x33, 0x40,0x01, }; -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase) { switch (dev->path.pnp.device) { @@ -172,18 +162,13 @@ static void vt1211_pnp_set_resources(struct device *dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = vt1211_pnp_set_resources, .enable_resources = vt1211_pnp_enable_resources, .enable = pnp_alt_enable, .init = vt1211_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 1a83b3d..59020a3 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -20,23 +20,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> #include "chip.h" #include "w83627dhg.h" -void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83627dhg_enable_UR2(device_t dev) { u8 reg8; @@ -65,18 +55,13 @@ static void w83627dhg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627dhg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 631105b..6f2c9de 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -33,17 +34,6 @@ #include "chip.h" #include "w83627ehg.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -141,18 +131,13 @@ static void w83627ehg_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = w83627ehg_pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627ehg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 4d68c35..5a4e964 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -33,17 +34,6 @@ #include "chip.h" #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -148,18 +138,13 @@ static void w83627hf_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = w83627hf_pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627hf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index f1c5603..257cd0a 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83627thg.h" -static void w83627thg_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83627thg_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83627thg_init(device_t dev) { struct superio_winbond_w83627thg_config *conf = dev->chip_info; @@ -55,18 +45,13 @@ static void w83627thg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83627thg_enter_ext_func_mode, - .exit_conf_mode = w83627thg_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83627thg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index d2cbdc9..3f1ca38 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <stdint.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83627uhg.h" -static void w83627uhg_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83627uhg_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - /* * Set the UART clock source. * @@ -101,18 +91,13 @@ static void w83627uhg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83627uhg_enter_ext_func_mode, - .exit_conf_mode = w83627uhg_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83627uhg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 9431b34..79ebcc9 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <lib.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83697hf.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { unsigned char enc, buf; @@ -81,18 +71,13 @@ static void w83697hf_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = w83697hf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index 8368839..6756830 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -29,17 +30,6 @@ #include "chip.h" #include "w83977f.h" -static void w83977f_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83977f_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83977f_init(device_t dev) { struct superio_winbond_w83977f_config *conf = dev->chip_info; @@ -54,18 +44,13 @@ static void w83977f_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83977f_enter_ext_func_mode, - .exit_conf_mode = w83977f_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83977f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index ff55f5d..0200d26 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -31,17 +32,6 @@ #include "chip.h" #include "w83977tf.h" -static void w83977tf_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83977tf_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83977tf_init(device_t dev) { struct superio_winbond_w83977tf_config *conf = dev->chip_info; @@ -56,18 +46,13 @@ static void w83977tf_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83977tf_enter_ext_func_mode, - .exit_conf_mode = w83977tf_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83977tf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = {

1 0

New patch to review for coreboot: 01548ee pnp: Remove now plain wrappers for default PnP functions
by Nico Huber 16 Jun '13

16 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3483 -gerrit commit 01548ee4f6c4e423d1147a090eca3a991cab2fb8 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 19:58:35 2013 +0200 pnp: Remove now plain wrappers for default PnP functions After removing the enter()/exit() functions for configuration mode, most wrappers for our standard PnP functions just call the underlying default implementation. Remove those with a little cocci: @ op_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; type device_t; identifier dev; @@ static void op(device_t dev) { pnp_op(dev); } @@ identifier op_match.op; @@ -op(...) {...} /* Three rules to match the alignment, hmmp... */ @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .set_resources = op, + .set_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable_resources = op, + .enable_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable = op, + .enable = pnp_op, }; Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/superio/fintek/f71805f/superio.c | 21 +++------------------ src/superio/fintek/f71859/superio.c | 21 +++------------------ src/superio/fintek/f71863fg/superio.c | 21 +++------------------ src/superio/fintek/f71872/superio.c | 21 +++------------------ src/superio/fintek/f71889/superio.c | 21 +++------------------ src/superio/fintek/f81865f/superio.c | 21 +++------------------ src/superio/intel/i3100/superio.c | 21 +++------------------ src/superio/ite/it8712f/superio.c | 21 +++------------------ src/superio/ite/it8716f/superio.c | 21 +++------------------ src/superio/ite/it8772f/superio.c | 21 +++------------------ src/superio/nuvoton/nct5104d/superio.c | 21 +++------------------ src/superio/smsc/kbc1100/superio.c | 24 +++--------------------- src/superio/smsc/lpc47b272/superio.c | 30 +++--------------------------- src/superio/smsc/lpc47b397/superio.c | 18 ++++-------------- src/superio/smsc/lpc47m10x/superio.c | 30 +++--------------------------- src/superio/smsc/lpc47m15x/superio.c | 24 +++--------------------- src/superio/smsc/mec1308/superio.c | 21 +++------------------ src/superio/smsc/sch4037/superio.c | 24 +++--------------------- src/superio/smsc/sio1036/superio.c | 24 +++--------------------- src/superio/smsc/smscsuperio/superio.c | 29 +++-------------------------- src/superio/via/vt1211/vt1211.c | 7 +------ src/superio/winbond/w83627dhg/superio.c | 21 +++------------------ src/superio/winbond/w83627ehg/superio.c | 14 ++------------ src/superio/winbond/w83627hf/superio.c | 14 ++------------ src/superio/winbond/w83627thg/superio.c | 21 +++------------------ src/superio/winbond/w83627uhg/superio.c | 21 +++------------------ src/superio/winbond/w83697hf/superio.c | 21 +++------------------ src/superio/winbond/w83977f/superio.c | 21 +++------------------ src/superio/winbond/w83977tf/superio.c | 21 +++------------------ 29 files changed, 84 insertions(+), 532 deletions(-) diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 3fb0c76..50c3355 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -45,21 +45,6 @@ static void f71805f_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static void f71805f_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void f71805f_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void f71805f_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_conf_state, .exit_conf_mode = pnp_exit_conf_state, @@ -67,9 +52,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = f71805f_pnp_set_resources, - .enable_resources = f71805f_pnp_enable_resources, - .enable = f71805f_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = f71805f_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 1f52ad7..1e5b6ec 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -46,21 +46,6 @@ static void f71859_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static void f71859_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void f71859_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void f71859_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_conf_state, .exit_conf_mode = pnp_exit_conf_state, @@ -68,9 +53,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = f71859_pnp_set_resources, - .enable_resources = f71859_pnp_enable_resources, - .enable = f71859_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = f71859_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 4aab676..84a7ec1 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -55,21 +55,6 @@ static void f71863fg_init(device_t dev) } } -static void f71863fg_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void f71863fg_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void f71863fg_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_conf_state, .exit_conf_mode = pnp_exit_conf_state, @@ -77,9 +62,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = f71863fg_pnp_set_resources, - .enable_resources = f71863fg_pnp_enable_resources, - .enable = f71863fg_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = f71863fg_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 8bc2b94..8db22a9 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -52,21 +52,6 @@ static void f71872_init(device_t dev) } } -static void f71872_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void f71872_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void f71872_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_conf_state, .exit_conf_mode = pnp_exit_conf_state, @@ -74,9 +59,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = f71872_pnp_set_resources, - .enable_resources = f71872_pnp_enable_resources, - .enable = f71872_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = f71872_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 5017505..8de8ae8 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -53,21 +53,6 @@ static void f71889_init(device_t dev) } } -static void f71889_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void f71889_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void f71889_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_conf_state, .exit_conf_mode = pnp_exit_conf_state, @@ -75,9 +60,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = f71889_pnp_set_resources, - .enable_resources = f71889_pnp_enable_resources, - .enable = f71889_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = f71889_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index ea322ea..050602c 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -52,21 +52,6 @@ static void f81865f_init(device_t dev) } } -static void f81865f_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void f81865f_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void f81865f_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_conf_state, .exit_conf_mode = pnp_exit_conf_state, @@ -74,9 +59,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = f81865f_pnp_set_resources, - .enable_resources = f81865f_pnp_enable_resources, - .enable = f81865f_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = f81865f_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index 503a233..f791d9d 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -43,21 +43,6 @@ static void i3100_init(device_t dev) return; } -static void i3100_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void i3100_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void i3100_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -65,9 +50,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = i3100_pnp_set_resources, - .enable_resources = i3100_pnp_enable_resources, - .enable = i3100_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = i3100_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index c713a68..619b260 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -72,21 +72,6 @@ static void it8712f_init(device_t dev) } } -static void it8712f_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void it8712f_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void it8712f_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -94,9 +79,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = it8712f_pnp_set_resources, - .enable_resources = it8712f_pnp_enable_resources, - .enable = it8712f_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = it8712f_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index af0db2d..4b58bb4 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -96,21 +96,6 @@ static void it8716f_init(device_t dev) } } -static void it8716f_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void it8716f_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void it8716f_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -118,9 +103,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = it8716f_pnp_set_resources, - .enable_resources = it8716f_pnp_enable_resources, - .enable = it8716f_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = it8716f_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 5985db5..5004c10 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -188,21 +188,6 @@ static void it8772f_init(device_t dev) } } -static void it8772f_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void it8772f_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void it8772f_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -210,9 +195,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = it8772f_pnp_set_resources, - .enable_resources = it8772f_pnp_enable_resources, - .enable = it8772f_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = it8772f_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 4615444..c8b696d 100755 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -38,21 +38,6 @@ static void nct5104d_init(device_t dev) { } -static void nct5104d_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void nct5104d_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void nct5104d_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_exteded_mode, .exit_conf_mode = pnp_exit_extended_mode, @@ -60,9 +45,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = nct5104d_pnp_set_resources, - .enable_resources = nct5104d_pnp_enable_resources, - .enable = nct5104d_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = nct5104d_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 2188899..a6d0ef0 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -33,9 +33,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); -static void kbc1100_pnp_set_resources(device_t dev); -static void kbc1100_pnp_enable_resources(device_t dev); -static void kbc1100_pnp_enable(device_t dev); static void kbc1100_init(device_t dev); static void pnp_enter_conf_state(device_t dev); @@ -53,9 +50,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = kbc1100_pnp_set_resources, - .enable_resources = kbc1100_pnp_enable_resources, - .enable = kbc1100_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = kbc1100_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; @@ -69,21 +66,6 @@ static void enable_dev(device_t dev) pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void kbc1100_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void kbc1100_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void kbc1100_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static void kbc1100_init(device_t dev) { struct superio_smsc_kbc1100_config *conf = dev->chip_info; diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 051b339..d06f094 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -37,9 +37,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); -static void lpc47b272_pnp_set_resources(device_t dev); -static void lpc47b272_pnp_enable_resources(device_t dev); -static void lpc47b272_pnp_enable(device_t dev); static void lpc47b272_init(device_t dev); static void pnp_enter_conf_state(device_t dev); @@ -58,9 +55,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = lpc47b272_pnp_set_resources, - .enable_resources = lpc47b272_pnp_enable_resources, - .enable = lpc47b272_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = lpc47b272_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; @@ -87,27 +84,6 @@ static void enable_dev(device_t dev) } /** - * Configure the specified Super I/O device with the resources (I/O space, - * etc.) that have been allocated for it. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void lpc47b272_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void lpc47b272_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void lpc47b272_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - -/** * Initialize the specified Super I/O device. * * Devices other than COM ports and the keyboard controller are ignored. diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index e8c62cd..850b7bb 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -78,11 +78,6 @@ static void lpc47b397_init(device_t dev) } } -static void lpc47b397_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - static void lpc47b397_pnp_enable_resources(device_t dev) { pnp_enable_resources(dev); @@ -99,11 +94,6 @@ static void lpc47b397_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static void lpc47b397_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_conf_state, .exit_conf_mode = pnp_exit_conf_state, @@ -111,9 +101,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = lpc47b397_pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, - .enable = lpc47b397_pnp_enable, + .enable = pnp_alt_enable, .init = lpc47b397_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; @@ -169,9 +159,9 @@ static struct smbus_bus_operations lops_smbus_bus = { static struct device_operations ops_hwm = { .read_resources = pnp_read_resources, - .set_resources = lpc47b397_pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, - .enable = lpc47b397_pnp_enable, + .enable = pnp_alt_enable, .init = lpc47b397_init, .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 0b55110..925defa 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -36,9 +36,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); -static void lpc47m10x_pnp_set_resources(device_t dev); -static void lpc47m10x_pnp_enable_resources(device_t dev); -static void lpc47m10x_pnp_enable(device_t dev); static void lpc47m10x_init(device_t dev); static void pnp_enter_conf_state(device_t dev); @@ -57,9 +54,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = lpc47m10x_pnp_set_resources, - .enable_resources = lpc47m10x_pnp_enable_resources, - .enable = lpc47m10x_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = lpc47m10x_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; @@ -86,27 +83,6 @@ static void enable_dev(device_t dev) } /** - * Configure the specified Super I/O device with the resources (I/O space, - * etc.) that have been allocated for it. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void lpc47m10x_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void lpc47m10x_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void lpc47m10x_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - -/** * Initialize the specified Super I/O device. * * Devices other than COM ports and the keyboard controller are ignored. diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index bcccb7a..a3b8fc5 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -33,9 +33,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); -static void lpc47m15x_pnp_set_resources(device_t dev); -static void lpc47m15x_pnp_enable_resources(device_t dev); -static void lpc47m15x_pnp_enable(device_t dev); static void lpc47m15x_init(device_t dev); static void pnp_enter_conf_state(device_t dev); @@ -53,9 +50,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = lpc47m15x_pnp_set_resources, - .enable_resources = lpc47m15x_pnp_enable_resources, - .enable = lpc47m15x_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = lpc47m15x_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; @@ -74,21 +71,6 @@ static void enable_dev(device_t dev) ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void lpc47m15x_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void lpc47m15x_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void lpc47m15x_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static void lpc47m15x_init(device_t dev) { struct superio_smsc_lpc47m15x_config *conf = dev->chip_info; diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index d08de2f..0385b26 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -43,21 +43,6 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, dev->path.pnp.port); } -static void mec1308_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void mec1308_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void mec1308_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static void mec1308_init(device_t dev) { struct superio_smsc_mec1308_config *conf = dev->chip_info; @@ -83,9 +68,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = mec1308_pnp_set_resources, - .enable_resources = mec1308_pnp_enable_resources, - .enable = mec1308_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = mec1308_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index c6daa18..254b838 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -33,9 +33,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); -static void sch4037_pnp_set_resources(device_t dev); -static void sch4037_pnp_enable_resources(device_t dev); -static void sch4037_pnp_enable(device_t dev); static void sch4037_init(device_t dev); static void pnp_enter_conf_state(device_t dev); @@ -53,9 +50,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = sch4037_pnp_set_resources, - .enable_resources = sch4037_pnp_enable_resources, - .enable = sch4037_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = sch4037_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; @@ -70,21 +67,6 @@ static void enable_dev(device_t dev) pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void sch4037_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void sch4037_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void sch4037_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static void sch4037_init(device_t dev) { struct superio_smsc_sch4037_config *conf = dev->chip_info; diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index 834fd49..2ce2af2 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -33,9 +33,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); -static void sio1036_pnp_set_resources(device_t dev); -static void sio1036_pnp_enable_resources(device_t dev); -static void sio1036_pnp_enable(device_t dev); static void sio1036_init(device_t dev); static void pnp_enter_conf_state(device_t dev); @@ -53,9 +50,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = sio1036_pnp_set_resources, - .enable_resources = sio1036_pnp_enable_resources, - .enable = sio1036_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = sio1036_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; @@ -69,21 +66,6 @@ static void enable_dev(device_t dev) pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void sio1036_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void sio1036_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void sio1036_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static void sio1036_init(device_t dev) { struct superio_smsc_sio1036_config *conf = dev->chip_info; diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 9af67a1..d45a967 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -169,29 +169,6 @@ static void smsc_pnp_exit_conf_state(device_t dev) outb(0xaa, dev->path.pnp.port); } -/** Wrapper for pnp_set_resources(). */ -static void smsc_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -/** Wrapper for pnp_enable_resources(). */ -static void smsc_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -/** - * If so configured, enable the specified device, otherwise - * explicitly disable it. - * - * @param dev The device to use. - */ -static void smsc_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - /** * Initialize those logical devices which need a special init. * @@ -230,9 +207,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { /** Standard device operations. */ static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = smsc_pnp_set_resources, - .enable_resources = smsc_pnp_enable_resources, - .enable = smsc_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = smsc_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index b66d530..8e09e4a 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -172,11 +172,6 @@ static void vt1211_pnp_set_resources(struct device *dev) pnp_exit_conf_mode(dev); } -static void vt1211_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -186,7 +181,7 @@ struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = vt1211_pnp_set_resources, .enable_resources = vt1211_pnp_enable_resources, - .enable = vt1211_pnp_enable, + .enable = pnp_alt_enable, .init = vt1211_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index d742112..1a83b3d 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -65,21 +65,6 @@ static void w83627dhg_init(device_t dev) } } -static void w83627dhg_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void w83627dhg_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void w83627dhg_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -87,9 +72,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83627dhg_pnp_set_resources, - .enable_resources = w83627dhg_pnp_enable_resources, - .enable = w83627dhg_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = w83627dhg_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index a94c4c0..631105b 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -127,11 +127,6 @@ static void w83627ehg_init(device_t dev) } } -static void w83627ehg_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - static void w83627ehg_pnp_enable_resources(device_t dev) { pnp_enable_resources(dev); @@ -146,11 +141,6 @@ static void w83627ehg_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static void w83627ehg_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -158,9 +148,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83627ehg_pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = w83627ehg_pnp_enable_resources, - .enable = w83627ehg_pnp_enable, + .enable = pnp_alt_enable, .init = w83627ehg_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 625f149..4d68c35 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -134,11 +134,6 @@ static void w83627hf_init(device_t dev) } } -static void w83627hf_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - static void w83627hf_pnp_enable_resources(device_t dev) { pnp_enable_resources(dev); @@ -153,11 +148,6 @@ static void w83627hf_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static void w83627hf_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -165,9 +155,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83627hf_pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = w83627hf_pnp_enable_resources, - .enable = w83627hf_pnp_enable, + .enable = pnp_alt_enable, .init = w83627hf_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 70d0c3d..f1c5603 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -55,21 +55,6 @@ static void w83627thg_init(device_t dev) } } -static void w83627thg_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void w83627thg_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void w83627thg_enable(device_t dev) -{ - pnp_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = w83627thg_enter_ext_func_mode, .exit_conf_mode = w83627thg_exit_ext_func_mode, @@ -77,9 +62,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83627thg_set_resources, - .enable_resources = w83627thg_enable_resources, - .enable = w83627thg_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, .init = w83627thg_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index adae491..d2cbdc9 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -101,21 +101,6 @@ static void w83627uhg_init(device_t dev) } } -static void w83627uhg_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void w83627uhg_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void w83627uhg_enable(device_t dev) -{ - pnp_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = w83627uhg_enter_ext_func_mode, .exit_conf_mode = w83627uhg_exit_ext_func_mode, @@ -123,9 +108,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83627uhg_set_resources, - .enable_resources = w83627uhg_enable_resources, - .enable = w83627uhg_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, .init = w83627uhg_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 2dd4f4f..9431b34 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -81,21 +81,6 @@ static void w83697hf_init(device_t dev) } } -static void w83697hf_pnp_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void w83697hf_pnp_enable(device_t dev) -{ - pnp_alt_enable(dev); -} - -static void w83697hf_pnp_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = pnp_enter_ext_func_mode, .exit_conf_mode = pnp_exit_ext_func_mode, @@ -103,9 +88,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83697hf_pnp_set_resources, - .enable_resources = w83697hf_pnp_enable_resources, - .enable = w83697hf_pnp_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, .init = w83697hf_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index a88cbe5..8368839 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -54,21 +54,6 @@ static void w83977f_init(device_t dev) } } -static void w83977f_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void w83977f_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void w83977f_enable(device_t dev) -{ - pnp_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = w83977f_enter_ext_func_mode, .exit_conf_mode = w83977f_exit_ext_func_mode, @@ -76,9 +61,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83977f_set_resources, - .enable_resources = w83977f_enable_resources, - .enable = w83977f_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, .init = w83977f_init, .ops_pnp_mode = &pnp_conf_mode_ops, }; diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index 30c2917..ff55f5d 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -56,21 +56,6 @@ static void w83977tf_init(device_t dev) } } -static void w83977tf_set_resources(device_t dev) -{ - pnp_set_resources(dev); -} - -static void w83977tf_enable_resources(device_t dev) -{ - pnp_enable_resources(dev); -} - -static void w83977tf_enable(device_t dev) -{ - pnp_enable(dev); -} - static const struct pnp_mode_ops pnp_conf_mode_ops = { .enter_conf_mode = w83977tf_enter_ext_func_mode, .exit_conf_mode = w83977tf_exit_ext_func_mode, @@ -78,9 +63,9 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = { static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = w83977tf_set_resources, - .enable_resources = w83977tf_enable_resources, - .enable = w83977tf_enable, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, .init = w83977tf_init, .ops_pnp_mode = &pnp_conf_mode_ops, };

1 0

New patch to review for coreboot: a625eea pnp: Register implementations of enter/exit config state
by Nico Huber 16 Jun '13

16 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3482 -gerrit commit a625eea4677f182d9cdbdb214f14028d7edaca8f Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 19:33:15 2013 +0200 pnp: Register implementations of enter/exit config state Find all the (ramstage) implementations of enter()/exit() functions for the configuration state, register and call them through the new struct pnp_mode_ops. As our standard PnP functions are aware of the pnp_mode_ops, it's not necessary to call enter()/exit() around them anymore. Patch generated with the cocci below. It's not perfect. The movement of the enter()/exit() calls is somehow fragile. So I checked the remaining calls for sense, and changed some empty lines. Also a duplicate insertion of pnp_conf_mode_ops had to be removed. /* Try to find enter and exit functions by their outb() structure and their usage around calls to our standard pnp functions: */ @ enter_match @ identifier enter; identifier dev; type device_t; @@ void enter(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ exit_match @ identifier exit; identifier dev; type device_t; @@ void exit(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ pnp_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; identifier enter_match.enter, exit_match.exit; type device_t; identifier dev; @@ void op(device_t dev) { ... enter(dev); ... pnp_op(dev); ... exit(dev); ... } /* Now add enter/exit to a pnp_mode_ops structure: */ @ depends on pnp_match @ identifier enter_match.enter; identifier exit_match.exit; identifier ops; @@ +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = enter, + .exit_conf_mode = exit, +}; + struct device_operations ops = { ..., + .ops_pnp_mode = &pnp_conf_mode_ops, }; /* Match against the new structure as we change the code and the above matches might not work anymore: */ @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; /* Replace enter()/enter() calls with new standard calls (e.g. pnp_enter_conf_mode()): */ @@ identifier mode_match.enter; expression e; @@ -enter(e) +pnp_enter_conf_mode(e) @@ identifier mode_match.exit; expression e; @@ -exit(e) +pnp_exit_conf_mode(e) /* If there are calls to standard PnP functions, (re)move the enter()/exit() calls around them: */ @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ -pnp_enter_conf_mode(e); pnp_op(e); +pnp_enter_conf_mode(e); ... pnp_exit_conf_mode(e); @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ pnp_enter_conf_mode(e); ... +pnp_exit_conf_mode(e); pnp_op(e); -pnp_exit_conf_mode(e); @@ expression e; @@ -pnp_enter_conf_mode(e); -pnp_exit_conf_mode(e); Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/superio/fintek/f71805f/superio.c | 12 ++++++------ src/superio/fintek/f71859/superio.c | 12 ++++++------ src/superio/fintek/f71863fg/superio.c | 12 ++++++------ src/superio/fintek/f71872/superio.c | 12 ++++++------ src/superio/fintek/f71889/superio.c | 12 ++++++------ src/superio/fintek/f81865f/superio.c | 12 ++++++------ src/superio/intel/i3100/superio.c | 12 ++++++------ src/superio/ite/it8712f/superio.c | 12 ++++++------ src/superio/ite/it8716f/superio.c | 12 ++++++------ src/superio/ite/it8772f/superio.c | 12 ++++++------ src/superio/nuvoton/nct5104d/superio.c | 12 ++++++------ src/superio/smsc/kbc1100/superio.c | 12 ++++++------ src/superio/smsc/lpc47b272/superio.c | 12 ++++++------ src/superio/smsc/lpc47b397/superio.c | 16 +++++++++------- src/superio/smsc/lpc47m10x/superio.c | 12 ++++++------ src/superio/smsc/lpc47m15x/superio.c | 12 ++++++------ src/superio/smsc/mec1308/superio.c | 12 ++++++------ src/superio/smsc/sch4037/superio.c | 12 ++++++------ src/superio/smsc/sio1036/superio.c | 12 ++++++------ src/superio/smsc/smscsuperio/superio.c | 16 ++++++++-------- src/superio/via/vt1211/vt1211.c | 14 ++++++++------ src/superio/winbond/w83627dhg/superio.c | 16 ++++++++-------- src/superio/winbond/w83627ehg/superio.c | 19 ++++++++++--------- src/superio/winbond/w83627hf/superio.c | 19 +++++++++++-------- src/superio/winbond/w83627thg/superio.c | 12 ++++++------ src/superio/winbond/w83627uhg/superio.c | 16 ++++++++-------- src/superio/winbond/w83697hf/superio.c | 12 ++++++------ src/superio/winbond/w83977f/superio.c | 12 ++++++------ src/superio/winbond/w83977tf/superio.c | 12 ++++++------ 29 files changed, 194 insertions(+), 186 deletions(-) diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index f46bd67..3fb0c76 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -47,31 +47,31 @@ static void f71805f_init(device_t dev) static void f71805f_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void f71805f_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void f71805f_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = f71805f_pnp_set_resources, .enable_resources = f71805f_pnp_enable_resources, .enable = f71805f_pnp_enable, .init = f71805f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index ed5da6e..1f52ad7 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -48,31 +48,31 @@ static void f71859_init(device_t dev) static void f71859_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void f71859_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void f71859_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = f71859_pnp_set_resources, .enable_resources = f71859_pnp_enable_resources, .enable = f71859_pnp_enable, .init = f71859_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index d133745..4aab676 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -57,31 +57,31 @@ static void f71863fg_init(device_t dev) static void f71863fg_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void f71863fg_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void f71863fg_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = f71863fg_pnp_set_resources, .enable_resources = f71863fg_pnp_enable_resources, .enable = f71863fg_pnp_enable, .init = f71863fg_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 5a2719b..8bc2b94 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -54,31 +54,31 @@ static void f71872_init(device_t dev) static void f71872_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void f71872_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void f71872_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = f71872_pnp_set_resources, .enable_resources = f71872_pnp_enable_resources, .enable = f71872_pnp_enable, .init = f71872_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 8daf766..5017505 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -55,31 +55,31 @@ static void f71889_init(device_t dev) static void f71889_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void f71889_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void f71889_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = f71889_pnp_set_resources, .enable_resources = f71889_pnp_enable_resources, .enable = f71889_pnp_enable, .init = f71889_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index eaae09c..ea322ea 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -54,31 +54,31 @@ static void f81865f_init(device_t dev) static void f81865f_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void f81865f_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void f81865f_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = f81865f_pnp_set_resources, .enable_resources = f81865f_pnp_enable_resources, .enable = f81865f_pnp_enable, .init = f81865f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index 152e419..503a233 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -45,31 +45,31 @@ static void i3100_init(device_t dev) static void i3100_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void i3100_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); } static void i3100_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = i3100_pnp_set_resources, .enable_resources = i3100_pnp_enable_resources, .enable = i3100_pnp_enable, .init = i3100_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 66b0aec..c713a68 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -74,31 +74,31 @@ static void it8712f_init(device_t dev) static void it8712f_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void it8712f_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); } static void it8712f_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = it8712f_pnp_set_resources, .enable_resources = it8712f_pnp_enable_resources, .enable = it8712f_pnp_enable, .init = it8712f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index f021a0b..af0db2d 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -98,31 +98,31 @@ static void it8716f_init(device_t dev) static void it8716f_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void it8716f_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); } static void it8716f_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = it8716f_pnp_set_resources, .enable_resources = it8716f_pnp_enable_resources, .enable = it8716f_pnp_enable, .init = it8716f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index de1c179..5985db5 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -190,31 +190,31 @@ static void it8772f_init(device_t dev) static void it8772f_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void it8772f_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); } static void it8772f_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = it8772f_pnp_set_resources, .enable_resources = it8772f_pnp_enable_resources, .enable = it8772f_pnp_enable, .init = it8772f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index ea6a342..4615444 100755 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -40,31 +40,31 @@ static void nct5104d_init(device_t dev) static void nct5104d_pnp_set_resources(device_t dev) { - pnp_enter_exteded_mode(dev); pnp_set_resources(dev); - pnp_exit_extended_mode(dev); } static void nct5104d_pnp_enable_resources(device_t dev) { - pnp_enter_exteded_mode(dev); pnp_enable_resources(dev); - pnp_exit_extended_mode(dev); } static void nct5104d_pnp_enable(device_t dev) { - pnp_enter_exteded_mode(dev); pnp_alt_enable(dev); - pnp_exit_extended_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_exteded_mode, + .exit_conf_mode = pnp_exit_extended_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = nct5104d_pnp_set_resources, .enable_resources = nct5104d_pnp_enable_resources, .enable = nct5104d_pnp_enable, .init = nct5104d_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index a8dad5e..2188899 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -46,12 +46,18 @@ struct chip_operations superio_smsc_kbc1100_ops = { .enable_dev = enable_dev }; +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = kbc1100_pnp_set_resources, .enable_resources = kbc1100_pnp_enable_resources, .enable = kbc1100_pnp_enable, .init = kbc1100_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { @@ -65,23 +71,17 @@ static void enable_dev(device_t dev) static void kbc1100_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void kbc1100_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void kbc1100_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } static void kbc1100_init(device_t dev) diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 8217769..051b339 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -51,12 +51,18 @@ struct chip_operations superio_smsc_lpc47b272_ops = { .enable_dev = enable_dev }; +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = lpc47b272_pnp_set_resources, .enable_resources = lpc47b272_pnp_enable_resources, .enable = lpc47b272_pnp_enable, .init = lpc47b272_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { @@ -88,23 +94,17 @@ static void enable_dev(device_t dev) */ static void lpc47b272_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void lpc47b272_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void lpc47b272_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } /** diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index cc78c36..e8c62cd 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -80,17 +80,14 @@ static void lpc47b397_init(device_t dev) static void lpc47b397_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - /* dump_pnp_device(dev); */ - pnp_exit_conf_state(dev); } static void lpc47b397_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); + pnp_enter_conf_mode(dev); switch(dev->path.pnp.device) { case LPC47B397_HWM: printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n"); @@ -99,22 +96,26 @@ static void lpc47b397_pnp_enable_resources(device_t dev) break; } /* dump_pnp_device(dev); */ - pnp_exit_conf_state(dev); + pnp_exit_conf_mode(dev); } static void lpc47b397_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = lpc47b397_pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, .enable = lpc47b397_pnp_enable, .init = lpc47b397_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; #define HWM_INDEX 0 @@ -174,6 +175,7 @@ static struct device_operations ops_hwm = { .init = lpc47b397_init, .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index d133c47..0b55110 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -50,12 +50,18 @@ struct chip_operations superio_smsc_lpc47m10x_ops = { .enable_dev = enable_dev }; +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = lpc47m10x_pnp_set_resources, .enable_resources = lpc47m10x_pnp_enable_resources, .enable = lpc47m10x_pnp_enable, .init = lpc47m10x_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { @@ -87,23 +93,17 @@ static void enable_dev(device_t dev) */ static void lpc47m10x_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void lpc47m10x_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void lpc47m10x_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } /** diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 253bfdc..bcccb7a 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -46,12 +46,18 @@ struct chip_operations superio_smsc_lpc47m15x_ops = { .enable_dev = enable_dev }; +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = lpc47m15x_pnp_set_resources, .enable_resources = lpc47m15x_pnp_enable_resources, .enable = lpc47m15x_pnp_enable, .init = lpc47m15x_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { @@ -70,23 +76,17 @@ static void enable_dev(device_t dev) static void lpc47m15x_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void lpc47m15x_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void lpc47m15x_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } static void lpc47m15x_init(device_t dev) diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 0fe473c..d08de2f 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -45,23 +45,17 @@ static void pnp_exit_conf_state(device_t dev) static void mec1308_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void mec1308_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void mec1308_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } static void mec1308_init(device_t dev) @@ -82,12 +76,18 @@ static void mec1308_init(device_t dev) } } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = mec1308_pnp_set_resources, .enable_resources = mec1308_pnp_enable_resources, .enable = mec1308_pnp_enable, .init = mec1308_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 9a19033..c6daa18 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -46,12 +46,18 @@ struct chip_operations superio_smsc_sch4037_ops = { .enable_dev = enable_dev, }; +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = sch4037_pnp_set_resources, .enable_resources = sch4037_pnp_enable_resources, .enable = sch4037_pnp_enable, .init = sch4037_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { @@ -66,23 +72,17 @@ static void enable_dev(device_t dev) static void sch4037_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void sch4037_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void sch4037_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } static void sch4037_init(device_t dev) diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index c25a674..834fd49 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -46,12 +46,18 @@ struct chip_operations superio_smsc_sio1036_ops = { .enable_dev = enable_dev }; +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_conf_state, + .exit_conf_mode = pnp_exit_conf_state, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = sio1036_pnp_set_resources, .enable_resources = sio1036_pnp_enable_resources, .enable = sio1036_pnp_enable, .init = sio1036_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { @@ -65,23 +71,17 @@ static void enable_dev(device_t dev) static void sio1036_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); } static void sio1036_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); pnp_enable_resources(dev); - pnp_exit_conf_state(dev); } static void sio1036_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); pnp_alt_enable(dev); - pnp_exit_conf_state(dev); } static void sio1036_init(device_t dev) diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index cdd223b..9af67a1 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -172,17 +172,13 @@ static void smsc_pnp_exit_conf_state(device_t dev) /** Wrapper for pnp_set_resources(). */ static void smsc_pnp_set_resources(device_t dev) { - smsc_pnp_enter_conf_state(dev); pnp_set_resources(dev); - smsc_pnp_exit_conf_state(dev); } /** Wrapper for pnp_enable_resources(). */ static void smsc_pnp_enable_resources(device_t dev) { - smsc_pnp_enter_conf_state(dev); pnp_enable_resources(dev); - smsc_pnp_exit_conf_state(dev); } /** @@ -193,9 +189,7 @@ static void smsc_pnp_enable_resources(device_t dev) */ static void smsc_pnp_enable(device_t dev) { - smsc_pnp_enter_conf_state(dev); pnp_alt_enable(dev); - smsc_pnp_exit_conf_state(dev); } /** @@ -228,6 +222,11 @@ static void smsc_init(device_t dev) } } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = smsc_pnp_enter_conf_state, + .exit_conf_mode = smsc_pnp_exit_conf_state, +}; + /** Standard device operations. */ static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -235,6 +234,7 @@ static struct device_operations ops = { .enable_resources = smsc_pnp_enable_resources, .enable = smsc_pnp_enable, .init = smsc_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; /** @@ -288,10 +288,10 @@ static void enable_dev(device_t dev) if (first_time) { /* Read the device ID and revision of the Super I/O chip. */ - smsc_pnp_enter_conf_state(dev); + pnp_enter_conf_mode(dev); superio_id = pnp_read_config(dev, DEVICE_ID_REG); superio_rev = pnp_read_config(dev, DEVICE_REV_REG); - smsc_pnp_exit_conf_state(dev); + pnp_exit_conf_mode(dev); /* TODO: Error handling? */ diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 0f56ee2..b66d530 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -121,9 +121,7 @@ static void vt1211_init(struct device *dev) static void vt1211_pnp_enable_resources(device_t dev) { printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev)); - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); } static void vt1211_pnp_set_resources(struct device *dev) @@ -141,7 +139,7 @@ static void vt1211_pnp_set_resources(struct device *dev) } #endif - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); @@ -171,22 +169,26 @@ static void vt1211_pnp_set_resources(struct device *dev) report_resource_stored(dev, res, ""); } - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_mode(dev); } static void vt1211_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = vt1211_pnp_set_resources, .enable_resources = vt1211_pnp_enable_resources, .enable = vt1211_pnp_enable, .init = vt1211_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 5310426..d742112 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -41,11 +41,11 @@ static void w83627dhg_enable_UR2(device_t dev) { u8 reg8; - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_mode(dev); reg8 = pnp_read_config(dev, 0x2c); reg8 |= (0x3); pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_mode(dev); } static void w83627dhg_init(device_t dev) @@ -67,31 +67,31 @@ static void w83627dhg_init(device_t dev) static void w83627dhg_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void w83627dhg_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); } static void w83627dhg_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83627dhg_pnp_set_resources, .enable_resources = w83627dhg_pnp_enable_resources, .enable = w83627dhg_pnp_enable, .init = w83627dhg_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index e0eea1b..a94c4c0 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -72,14 +72,14 @@ static void init_acpi(device_t dev) int power_on = 1; get_option(&power_on, "power_on_after_fail"); - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); value = pnp_read_config(dev, 0xe4); value &= ~(3 << 5); if (power_on) value |= (1 << 5); pnp_write_config(dev, 0xe4, value); - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_mode(dev); } static void init_hwm(u16 base) @@ -129,39 +129,40 @@ static void w83627ehg_init(device_t dev) static void w83627ehg_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void w83627ehg_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); + pnp_enter_conf_mode(dev); switch (dev->path.pnp.device) { case W83627EHG_HWM: printk(BIOS_DEBUG, "W83627EHG HWM SMBus enabled\n"); enable_hwm_smbus(dev); break; } - - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_mode(dev); } static void w83627ehg_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83627ehg_pnp_set_resources, .enable_resources = w83627ehg_pnp_enable_resources, .enable = w83627ehg_pnp_enable, .init = w83627ehg_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index a117e05..625f149 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -73,14 +73,14 @@ static void init_acpi(device_t dev) get_option(&power_on, "power_on_after_fail"); - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); value = pnp_read_config(dev, 0xE4); value &= ~(3 << 5); if (power_on) value |= (1 << 5); pnp_write_config(dev, 0xE4, value); - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_mode(dev); } static void init_hwm(u16 base) @@ -136,37 +136,40 @@ static void w83627hf_init(device_t dev) static void w83627hf_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void w83627hf_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); + + pnp_enter_conf_mode(dev); switch(dev->path.pnp.device) { case W83627HF_HWM: printk(BIOS_DEBUG, "W83627HF HWM SMBus enabled\n"); enable_hwm_smbus(dev); break; } - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_mode(dev); } static void w83627hf_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83627hf_pnp_set_resources, .enable_resources = w83627hf_pnp_enable_resources, .enable = w83627hf_pnp_enable, .init = w83627hf_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 1989fe2..70d0c3d 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -57,31 +57,31 @@ static void w83627thg_init(device_t dev) static void w83627thg_set_resources(device_t dev) { - w83627thg_enter_ext_func_mode(dev); pnp_set_resources(dev); - w83627thg_exit_ext_func_mode(dev); } static void w83627thg_enable_resources(device_t dev) { - w83627thg_enter_ext_func_mode(dev); pnp_enable_resources(dev); - w83627thg_exit_ext_func_mode(dev); } static void w83627thg_enable(device_t dev) { - w83627thg_enter_ext_func_mode(dev); pnp_enable(dev); - w83627thg_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = w83627thg_enter_ext_func_mode, + .exit_conf_mode = w83627thg_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83627thg_set_resources, .enable_resources = w83627thg_enable_resources, .enable = w83627thg_enable, .init = w83627thg_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index b4a4efe..adae491 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -60,13 +60,13 @@ static void set_uart_clock_source(device_t dev, u8 uart_clock) { u8 value; - w83627uhg_enter_ext_func_mode(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); value = pnp_read_config(dev, 0xf0); value &= ~0x03; value |= (uart_clock & 0x03); pnp_write_config(dev, 0xf0, value); - w83627uhg_exit_ext_func_mode(dev); + pnp_exit_conf_mode(dev); } static void w83627uhg_init(device_t dev) @@ -103,31 +103,31 @@ static void w83627uhg_init(device_t dev) static void w83627uhg_set_resources(device_t dev) { - w83627uhg_enter_ext_func_mode(dev); pnp_set_resources(dev); - w83627uhg_exit_ext_func_mode(dev); } static void w83627uhg_enable_resources(device_t dev) { - w83627uhg_enter_ext_func_mode(dev); pnp_enable_resources(dev); - w83627uhg_exit_ext_func_mode(dev); } static void w83627uhg_enable(device_t dev) { - w83627uhg_enter_ext_func_mode(dev); pnp_enable(dev); - w83627uhg_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = w83627uhg_enter_ext_func_mode, + .exit_conf_mode = w83627uhg_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83627uhg_set_resources, .enable_resources = w83627uhg_enable_resources, .enable = w83627uhg_enable, .init = w83627uhg_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index e3ce7e2..2dd4f4f 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -83,31 +83,31 @@ static void w83697hf_init(device_t dev) static void w83697hf_pnp_set_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); } static void w83697hf_pnp_enable(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_alt_enable(dev); - pnp_exit_ext_func_mode(dev); } static void w83697hf_pnp_enable_resources(device_t dev) { - pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83697hf_pnp_set_resources, .enable_resources = w83697hf_pnp_enable_resources, .enable = w83697hf_pnp_enable, .init = w83697hf_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index b084b11..a88cbe5 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -56,31 +56,31 @@ static void w83977f_init(device_t dev) static void w83977f_set_resources(device_t dev) { - w83977f_enter_ext_func_mode(dev); pnp_set_resources(dev); - w83977f_exit_ext_func_mode(dev); } static void w83977f_enable_resources(device_t dev) { - w83977f_enter_ext_func_mode(dev); pnp_enable_resources(dev); - w83977f_exit_ext_func_mode(dev); } static void w83977f_enable(device_t dev) { - w83977f_enter_ext_func_mode(dev); pnp_enable(dev); - w83977f_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = w83977f_enter_ext_func_mode, + .exit_conf_mode = w83977f_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83977f_set_resources, .enable_resources = w83977f_enable_resources, .enable = w83977f_enable, .init = w83977f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index 6ae9a6a..30c2917 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -58,31 +58,31 @@ static void w83977tf_init(device_t dev) static void w83977tf_set_resources(device_t dev) { - w83977tf_enter_ext_func_mode(dev); pnp_set_resources(dev); - w83977tf_exit_ext_func_mode(dev); } static void w83977tf_enable_resources(device_t dev) { - w83977tf_enter_ext_func_mode(dev); pnp_enable_resources(dev); - w83977tf_exit_ext_func_mode(dev); } static void w83977tf_enable(device_t dev) { - w83977tf_enter_ext_func_mode(dev); pnp_enable(dev); - w83977tf_exit_ext_func_mode(dev); } +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = w83977tf_enter_ext_func_mode, + .exit_conf_mode = w83977tf_exit_ext_func_mode, +}; + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83977tf_set_resources, .enable_resources = w83977tf_enable_resources, .enable = w83977tf_enable, .init = w83977tf_init, + .ops_pnp_mode = &pnp_conf_mode_ops, }; static struct pnp_info pnp_dev_info[] = {

1 0

New patch to review for coreboot: 84b5f77 pnp: Implement common handling for PnP config modes
by Nico Huber 16 Jun '13

16 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3481 -gerrit commit 84b5f7705dfeab0a6a0d472f95b2152b1acbbf97 Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Jun 10 22:08:35 2013 +0200 pnp: Implement common handling for PnP config modes Many super i/o chips only answer to PnP requests if they are in a configuration state (sometimes also called ext func mode). To cope with that, the code of many chips implements its own version of our default PnP functions like pnp_set_resource(), pnp_enable_resource() etc. To avoid this code duplication, this patch extends our PnP device interface with optional functions to enter and exit configuration mode. Change-Id: I9b7662a0db70ede93276764fa15020f251eb46bd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/device/pnp_device.c | 25 +++++++++++++++++++++++++ src/include/device/device.h | 2 ++ src/include/device/pnp.h | 7 +++++++ 3 files changed, 34 insertions(+) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index f39f8f9..987a253 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -6,6 +6,7 @@ * Copyright (C) 2004 Li-Ta Lo <ollie(a)lanl.gov> * Copyright (C) 2005 Tyan * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +30,20 @@ #include <device/device.h> #include <device/pnp.h> +/* PNP config mode wrappers */ + +void pnp_enter_conf_mode(device_t dev) +{ + if (dev->ops->ops_pnp_mode) + dev->ops->ops_pnp_mode->enter_conf_mode(dev); +} + +void pnp_exit_conf_mode(device_t dev) +{ + if (dev->ops->ops_pnp_mode) + dev->ops->ops_pnp_mode->exit_conf_mode(dev); +} + /* PNP fundamental operations */ void pnp_write_config(device_t dev, u8 reg, u8 value) @@ -133,32 +148,42 @@ void pnp_set_resources(device_t dev) { struct resource *res; + pnp_enter_conf_mode(dev); + /* Select the logical device (LDN). */ pnp_set_logical_device(dev); /* Paranoia says I should disable the device here... */ for (res = dev->resource_list; res; res = res->next) pnp_set_resource(dev, res); + + pnp_exit_conf_mode(dev); } void pnp_enable_resources(device_t dev) { + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); + pnp_exit_conf_mode(dev); } void pnp_enable(device_t dev) { if (!dev->enabled) { + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); + pnp_exit_conf_mode(dev); } } void pnp_alt_enable(device_t dev) { + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, !!dev->enabled); + pnp_exit_conf_mode(dev); } struct device_operations pnp_ops = { diff --git a/src/include/device/device.h b/src/include/device/device.h index 44a9742..9defb19 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -13,6 +13,7 @@ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations; +struct pnp_mode_ops; /* Chip operations */ struct chip_operations { @@ -42,6 +43,7 @@ struct device_operations { const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; + const struct pnp_mode_ops *ops_pnp_mode; }; #endif diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 5667223..434f0a4 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -52,5 +52,12 @@ struct resource *pnp_get_resource(device_t dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); +struct pnp_mode_ops { + void (*enter_conf_mode)(device_t dev); + void (*exit_conf_mode)(device_t dev); +}; +void pnp_enter_conf_mode(device_t dev); +void pnp_exit_conf_mode(device_t dev); + #endif #endif /* DEVICE_PNP_H */

1 0

New patch to review for coreboot: 393dedc pnp: Provide alternative pnp_enable() implementation
by Nico Huber 16 Jun '13

16 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3480 -gerrit commit 393dedc8bdd4956a904db0f0e8b420eaa58e4151 Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Jun 10 22:57:12 2013 +0200 pnp: Provide alternative pnp_enable() implementation The current default implementation of pnp_enable() only disables devices - if set so in the devicetree - but does not enable them. Enablement takes place in pnp_enable_resources(). Yet, many PnP chips implement their own version of pnp_enable() which also enables devices if set in the devicetree. It's arguable, if enabling those devices makes sense, before they get resources assigned. Maybe we can't write the resource registers if not, who knows? The least we can do is providing a common implementation for this behavior, and get rid of some code duplication. Used the following cocci: @@ expression e; @@ +pnp_alt_enable(e); -pnp_set_logical_device(e); ( -pnp_set_enable(e, !!e->enabled); | -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0); | -if (e->enabled) { pnp_set_enable(e, 1); } -else { pnp_set_enable(e, 0); } ) Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/device/pnp_device.c | 6 ++++++ src/include/device/pnp.h | 1 + src/superio/fintek/f71805f/superio.c | 3 +-- src/superio/fintek/f71859/superio.c | 3 +-- src/superio/fintek/f71863fg/superio.c | 3 +-- src/superio/fintek/f71872/superio.c | 3 +-- src/superio/fintek/f71889/superio.c | 3 +-- src/superio/fintek/f81865f/superio.c | 3 +-- src/superio/intel/i3100/superio.c | 3 +-- src/superio/ite/it8712f/superio.c | 3 +-- src/superio/ite/it8716f/superio.c | 3 +-- src/superio/ite/it8772f/superio.c | 3 +-- src/superio/nuvoton/nct5104d/superio.c | 3 +-- src/superio/smsc/kbc1100/superio.c | 9 +-------- src/superio/smsc/lpc47b272/superio.c | 3 +-- src/superio/smsc/lpc47b397/superio.c | 3 +-- src/superio/smsc/lpc47m10x/superio.c | 3 +-- src/superio/smsc/lpc47m15x/superio.c | 3 +-- src/superio/smsc/mec1308/superio.c | 9 +-------- src/superio/smsc/sch4037/superio.c | 9 +-------- src/superio/smsc/sio1036/superio.c | 9 +-------- src/superio/smsc/smscsuperio/superio.c | 3 +-- src/superio/via/vt1211/vt1211.c | 3 +-- src/superio/winbond/w83627dhg/superio.c | 3 +-- src/superio/winbond/w83627ehg/superio.c | 3 +-- src/superio/winbond/w83627hf/superio.c | 3 +-- src/superio/winbond/w83697hf/superio.c | 3 +-- 27 files changed, 32 insertions(+), 74 deletions(-) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index da691f8..f39f8f9 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -155,6 +155,12 @@ void pnp_enable(device_t dev) } } +void pnp_alt_enable(device_t dev) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, !!dev->enabled); +} + struct device_operations pnp_ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index f97b05d..5667223 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -21,6 +21,7 @@ void pnp_read_resources(device_t dev); void pnp_set_resources(device_t dev); void pnp_enable_resources(device_t dev); void pnp_enable(device_t dev); +void pnp_alt_enable(device_t dev); extern struct device_operations pnp_ops; diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 964f105..f46bd67 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -62,8 +62,7 @@ static void f71805f_pnp_enable_resources(device_t dev) static void f71805f_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index db7834d..ed5da6e 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -63,8 +63,7 @@ static void f71859_pnp_enable_resources(device_t dev) static void f71859_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index ab86922..d133745 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -72,8 +72,7 @@ static void f71863fg_pnp_enable_resources(device_t dev) static void f71863fg_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index ae53608..5a2719b 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -69,8 +69,7 @@ static void f71872_pnp_enable_resources(device_t dev) static void f71872_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 98306f9..8daf766 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -70,8 +70,7 @@ static void f71889_pnp_enable_resources(device_t dev) static void f71889_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index e09adbb..eaae09c 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -69,8 +69,7 @@ static void f81865f_pnp_enable_resources(device_t dev) static void f81865f_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index 3d4f28a..152e419 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -60,8 +60,7 @@ static void i3100_pnp_enable_resources(device_t dev) static void i3100_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index bf649da..66b0aec 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -89,8 +89,7 @@ static void it8712f_pnp_enable_resources(device_t dev) static void it8712f_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 98b6732..f021a0b 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -113,8 +113,7 @@ static void it8716f_pnp_enable_resources(device_t dev) static void it8716f_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index b6c4405..de1c179 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -205,8 +205,7 @@ static void it8772f_pnp_enable_resources(device_t dev) static void it8772f_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 3c78cbc..ea6a342 100755 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -55,8 +55,7 @@ static void nct5104d_pnp_enable_resources(device_t dev) static void nct5104d_pnp_enable(device_t dev) { pnp_enter_exteded_mode(dev); - pnp_set_logical_device(dev); - (dev->enabled) ? pnp_set_enable(dev,1) : pnp_set_enable(dev,0); + pnp_alt_enable(dev); pnp_exit_extended_mode(dev); } diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index b3d3d49..a8dad5e 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -80,14 +80,7 @@ static void kbc1100_pnp_enable_resources(device_t dev) static void kbc1100_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 79d07bb..8217769 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -103,8 +103,7 @@ static void lpc47b272_pnp_enable_resources(device_t dev) static void lpc47b272_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index fd13b03..cc78c36 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -105,8 +105,7 @@ static void lpc47b397_pnp_enable_resources(device_t dev) static void lpc47b397_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 53356d2..d133c47 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -102,8 +102,7 @@ static void lpc47m10x_pnp_enable_resources(device_t dev) static void lpc47m10x_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index e70c6e1..253bfdc 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -85,8 +85,7 @@ static void lpc47m15x_pnp_enable_resources(device_t dev) static void lpc47m15x_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index b4a1adf..0fe473c 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -60,14 +60,7 @@ static void mec1308_pnp_enable_resources(device_t dev) static void mec1308_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 386eafd..9a19033 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -81,14 +81,7 @@ static void sch4037_pnp_enable_resources(device_t dev) static void sch4037_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index 46f3f46..c25a674 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -80,14 +80,7 @@ static void sio1036_pnp_enable_resources(device_t dev) static void sio1036_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_alt_enable(dev); pnp_exit_conf_state(dev); } diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index d687bd1..cdd223b 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -194,8 +194,7 @@ static void smsc_pnp_enable_resources(device_t dev) static void smsc_pnp_enable(device_t dev) { smsc_pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); smsc_pnp_exit_conf_state(dev); } diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index abcae77..0f56ee2 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -177,8 +177,7 @@ static void vt1211_pnp_set_resources(struct device *dev) static void vt1211_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index bbde26a..5310426 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -82,8 +82,7 @@ static void w83627dhg_pnp_enable_resources(device_t dev) static void w83627dhg_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index b5234f1..e0eea1b 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -152,8 +152,7 @@ static void w83627ehg_pnp_enable_resources(device_t dev) static void w83627ehg_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 82408d4..a117e05 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -157,8 +157,7 @@ static void w83627hf_pnp_enable_resources(device_t dev) static void w83627hf_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 56d1358..e3ce7e2 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -91,8 +91,7 @@ static void w83697hf_pnp_set_resources(device_t dev) static void w83697hf_pnp_enable(device_t dev) { pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); + pnp_alt_enable(dev); pnp_exit_ext_func_mode(dev); }

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New patch to review for coreboot: b90b7bf pnp: Unify some alignment to ease autogenerating patches
by Nico Huber 16 Jun '13

16 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3479 -gerrit commit b90b7bfff946d5f80a5655256fa1c3ab8c8c3d96 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 15:30:19 2013 +0200 pnp: Unify some alignment to ease autogenerating patches Most PnP drivers align the initialization of their `device_operations` with spaces. Unify this, so next autogenerated patches always match the alignment. Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/ec/kontron/it8516e/ec.c | 10 +++++----- src/superio/ite/it8712f/superio.c | 10 +++++----- src/superio/ite/it8772f/superio.c | 10 +++++----- src/superio/smsc/smscsuperio/superio.c | 10 +++++----- src/superio/winbond/w83977f/superio.c | 10 +++++----- 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index f4df9c7..fa7bbc8 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -143,11 +143,11 @@ static void it8516e_pm2_init(const device_t dev) } static struct device_operations it8516e_pm2_ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = it8516e_pm2_init + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = it8516e_pm2_init }; static struct pnp_info it8516e_dev_infos[] = { diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index ae77ece..bf649da 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -95,11 +95,11 @@ static void it8712f_pnp_enable(device_t dev) } static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = it8712f_pnp_set_resources, - .enable_resources = it8712f_pnp_enable_resources, - .enable = it8712f_pnp_enable, - .init = it8712f_init, + .read_resources = pnp_read_resources, + .set_resources = it8712f_pnp_set_resources, + .enable_resources = it8712f_pnp_enable_resources, + .enable = it8712f_pnp_enable, + .init = it8712f_init, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index b4b54e9..b6c4405 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -211,11 +211,11 @@ static void it8772f_pnp_enable(device_t dev) } static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = it8772f_pnp_set_resources, - .enable_resources = it8772f_pnp_enable_resources, - .enable = it8772f_pnp_enable, - .init = it8772f_init, + .read_resources = pnp_read_resources, + .set_resources = it8772f_pnp_set_resources, + .enable_resources = it8772f_pnp_enable_resources, + .enable = it8772f_pnp_enable, + .init = it8772f_init, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 1d32b9f..d687bd1 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -231,11 +231,11 @@ static void smsc_init(device_t dev) /** Standard device operations. */ static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = smsc_pnp_set_resources, - .enable_resources = smsc_pnp_enable_resources, - .enable = smsc_pnp_enable, - .init = smsc_init, + .read_resources = pnp_read_resources, + .set_resources = smsc_pnp_set_resources, + .enable_resources = smsc_pnp_enable_resources, + .enable = smsc_pnp_enable, + .init = smsc_init, }; /** diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index f990b46..b084b11 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -76,11 +76,11 @@ static void w83977f_enable(device_t dev) } static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = w83977f_set_resources, - .enable_resources = w83977f_enable_resources, - .enable = w83977f_enable, - .init = w83977f_init, + .read_resources = pnp_read_resources, + .set_resources = w83977f_set_resources, + .enable_resources = w83977f_enable_resources, + .enable = w83977f_enable, + .init = w83977f_init, }; static struct pnp_info pnp_dev_info[] = {

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coreboot-gerrit June 2013