coreboot-gerrit June 2013

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Patch set updated for coreboot: 834daf3 pnp: Add some default functions to enter/exit config state
by Nico Huber 17 Jun '13

17 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3484 -gerrit commit 834daf34c9c12bc921cb4155a4833cb2d721c4ac Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 20:33:44 2013 +0200 pnp: Add some default functions to enter/exit config state Implement some common default functions to enter and exit the configuration state. Also provide default pnp_mode_ops for common enter()/exit() function pairs. The following cocci ensures their use: @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; @ enter_match_8787 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } @ depends on enter_match_8787 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_8787, }; @ enter_match_55 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x55, dev->path.pnp.port); } @ depends on enter_match_55 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_55, }; @ depends on enter_match_8787 || enter_match_55 @ identifier mode_match.enter; @@ -enter(...) {...} @ exit_match_aa @ identifier mode_match.exit, dev; @@ exit(...) { outb(0xaa, dev->path.pnp.port); } @ depends on exit_match_aa @ identifier mode_match.exit, mode_match.ops; @@ struct pnp_mode_ops ops = { - .exit_conf_mode = exit, + .exit_conf_mode = pnp_exit_conf_mode_aa, }; @ depends on exit_match_aa @ identifier mode_match.exit; @@ -exit(...) {...} @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @ @@ #include <device/pnp.h> +#include <superio/conf_mode.h> @ mode_match_55_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_55_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_55_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; @ mode_match_8787_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_8787_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_8787_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/include/superio/conf_mode.h | 15 ++++++++++ src/superio/Makefile.inc | 1 + src/superio/common/conf_mode.c | 50 +++++++++++++++++++++++++++++++++ src/superio/fintek/f71805f/superio.c | 19 ++----------- src/superio/fintek/f71859/superio.c | 19 ++----------- src/superio/fintek/f71863fg/superio.c | 19 ++----------- src/superio/fintek/f71872/superio.c | 19 ++----------- src/superio/fintek/f71889/superio.c | 19 ++----------- src/superio/fintek/f81865f/superio.c | 19 ++----------- src/superio/nuvoton/nct5104d/superio.c | 19 ++----------- src/superio/smsc/kbc1100/superio.c | 21 ++------------ src/superio/smsc/lpc47b272/superio.c | 21 ++------------ src/superio/smsc/lpc47b397/superio.c | 20 ++----------- src/superio/smsc/lpc47m10x/superio.c | 21 ++------------ src/superio/smsc/lpc47m15x/superio.c | 21 ++------------ src/superio/smsc/mec1308/superio.c | 18 ++---------- src/superio/smsc/sch4037/superio.c | 21 ++------------ src/superio/smsc/sio1036/superio.c | 21 ++------------ src/superio/smsc/smscsuperio/superio.c | 34 ++-------------------- src/superio/via/vt1211/vt1211.c | 19 ++----------- src/superio/winbond/w83627dhg/superio.c | 19 ++----------- src/superio/winbond/w83627ehg/superio.c | 19 ++----------- src/superio/winbond/w83627hf/superio.c | 19 ++----------- src/superio/winbond/w83627thg/superio.c | 19 ++----------- src/superio/winbond/w83627uhg/superio.c | 19 ++----------- src/superio/winbond/w83697hf/superio.c | 19 ++----------- src/superio/winbond/w83977f/superio.c | 19 ++----------- src/superio/winbond/w83977tf/superio.c | 19 ++----------- 28 files changed, 117 insertions(+), 451 deletions(-) diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h new file mode 100644 index 0000000..db341ba --- /dev/null +++ b/src/include/superio/conf_mode.h @@ -0,0 +1,15 @@ +#ifndef DEVICE_PNP_CONF_MODE_H +#define DEVICE_PNP_CONF_MODE_H + +#include <device/device.h> +#include <device/pnp.h> + +/* Common enter/exit implementations */ +void pnp_enter_conf_mode_55(device_t dev); +void pnp_enter_conf_mode_8787(device_t dev); +void pnp_exit_conf_mode_aa(device_t dev); + +extern const struct pnp_mode_ops pnp_conf_mode_55_aa; +extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; + +#endif diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index ff4d48f..e34fa89 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -28,3 +28,4 @@ subdirs-y += smsc subdirs-y += via subdirs-y += winbond +ramstage-$(CONFIG_ARCH_X86) += common/conf_mode.c diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c new file mode 100644 index 0000000..40583ff --- /dev/null +++ b/src/superio/common/conf_mode.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <superio/conf_mode.h> + +/* Common enter/exit implementations */ + +void pnp_enter_conf_mode_55(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +void pnp_enter_conf_mode_8787(device_t dev) +{ + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); +} + +void pnp_exit_conf_mode_aa(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +const struct pnp_mode_ops pnp_conf_mode_55_aa = { + .enter_conf_mode = pnp_enter_conf_mode_55, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + +const struct pnp_mode_ops pnp_conf_mode_8787_aa = { + .enter_conf_mode = pnp_enter_conf_mode_8787, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 50c3355..4a31606 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "f71805f.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71805f_init(device_t dev) { if (!dev->enabled) @@ -45,18 +35,13 @@ static void f71805f_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71805f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 1e5b6ec..2736c0b 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -22,22 +22,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "f71859.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71859_init(device_t dev) { if (!dev->enabled) @@ -46,18 +36,13 @@ static void f71859_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71859_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 84a7ec1..4159e6d 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -21,23 +21,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "chip.h" #include "f71863fg.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71863fg_init(device_t dev) { struct superio_fintek_f71863fg_config *conf = dev->chip_info; @@ -55,18 +45,13 @@ static void f71863fg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71863fg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 8db22a9..55a11b1 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include "chip.h" #include "f71872.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71872_init(device_t dev) { struct superio_fintek_f71872_config *conf = dev->chip_info; @@ -52,18 +42,13 @@ static void f71872_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71872_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 8de8ae8..450f938 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -21,23 +21,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "chip.h" #include "f71889.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71889_init(device_t dev) { struct superio_fintek_f71889_config *conf = dev->chip_info; @@ -53,18 +43,13 @@ static void f71889_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71889_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 050602c..85ac7ba 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include "chip.h" #include "f81865f.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f81865f_init(device_t dev) { struct superio_fintek_f81865f_config *conf = dev->chip_info; @@ -52,18 +42,13 @@ static void f81865f_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f81865f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index c8b696d..5eb8991 100755 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -20,36 +20,21 @@ #include <arch/io.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <stdlib.h> #include "nct5104d.h" -static void pnp_enter_exteded_mode(device_t dev) -{ - outb(0x87,dev->path.pnp.port); - outb(0x87,dev->path.pnp.port); -} - -static void pnp_exit_extended_mode(device_t dev) -{ - outb(0xaa,dev->path.pnp.port); -} - static void nct5104d_init(device_t dev) { } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_exteded_mode, - .exit_conf_mode = pnp_exit_extended_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = nct5104d_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index a6d0ef0..c56694c 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void kbc1100_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_kbc1100_ops = { CHIP_NAME("SMSC KBC1100 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = kbc1100_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -86,13 +79,3 @@ static void kbc1100_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index d06f094..8901ec4 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -26,6 +26,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -38,9 +39,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); static void lpc47b272_init(device_t dev); - -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); // static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47b272_ops = { @@ -48,18 +46,13 @@ struct chip_operations superio_smsc_lpc47b272_ops = { .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b272_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -105,16 +98,6 @@ static void lpc47b272_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - #if 0 /** * Print the values of all of the LPC47B272's configuration registers. diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 850b7bb..ff6e405 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -32,16 +33,6 @@ #include "chip.h" #include "lpc47b397.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -94,18 +85,13 @@ static void lpc47b397_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b397_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; #define HWM_INDEX 0 @@ -165,7 +151,7 @@ static struct device_operations ops_hwm = { .init = lpc47b397_init, .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 925defa..c1f3c2c 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -25,6 +25,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -37,9 +38,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); static void lpc47m10x_init(device_t dev); - -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); // static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47m10x_ops = { @@ -47,18 +45,13 @@ struct chip_operations superio_smsc_lpc47m10x_ops = { .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47m10x_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -104,16 +97,6 @@ static void lpc47m10x_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - #if 0 /** * Print the values of all of the LPC47M10X2's configuration registers. diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index a3b8fc5..7e400fc 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void lpc47m15x_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_lpc47m15x_ops = { CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47m15x_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -84,13 +77,3 @@ static void lpc47m15x_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 0385b26..448800e 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -33,16 +34,6 @@ #include <arch/acpi.h> #endif -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void mec1308_init(device_t dev) { struct superio_smsc_mec1308_config *conf = dev->chip_info; @@ -61,18 +52,13 @@ static void mec1308_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = mec1308_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 254b838..96d35fe 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void sch4037_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_sch4037_ops = { CHIP_NAME("SMSC SCH4037 Super I/O") .enable_dev = enable_dev, }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = sch4037_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -85,13 +78,3 @@ static void sch4037_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index 2ce2af2..ff7b5d1 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void sio1036_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_sio1036_ops = { CHIP_NAME("SMSC SIO1036 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = sio1036_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -84,13 +77,3 @@ static void sio1036_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index d45a967..42a9c09 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -37,6 +37,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <uart8250.h> #include <pc80/keyboard.h> @@ -144,32 +145,6 @@ static const struct logical_devices { }; /** - * Enter the configuration state by writing 0x55 to the config port. - * - * The Super I/O configuration registers can only be modified when the chip - * is in the configuration state. Thus, to program the registers you have - * to a) enter config mode, b) program the registers, c) exit config mode. - * - * @param dev The device to use. - */ -static void smsc_pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -/** - * Exit the configuration state by writing 0xaa to the config port. - * - * This puts the chip into the 'run' state again. - * - * @param dev The device to use. - */ -static void smsc_pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - -/** * Initialize those logical devices which need a special init. * * @param dev The device to use. @@ -199,11 +174,6 @@ static void smsc_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = smsc_pnp_enter_conf_state, - .exit_conf_mode = smsc_pnp_exit_conf_state, -}; - /** Standard device operations. */ static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -211,7 +181,7 @@ static struct device_operations ops = { .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = smsc_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; /** diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 8e09e4a..68fd999 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <uart8250.h> #include <stdlib.h> #include "vt1211.h" @@ -44,17 +45,6 @@ static u8 hwm_io_regs[] = { 0x5c,0x00, 0x5f,0x33, 0x40,0x01, }; -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase) { switch (dev->path.pnp.device) { @@ -172,18 +162,13 @@ static void vt1211_pnp_set_resources(struct device *dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = vt1211_pnp_set_resources, .enable_resources = vt1211_pnp_enable_resources, .enable = pnp_alt_enable, .init = vt1211_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 1a83b3d..59020a3 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -20,23 +20,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> #include "chip.h" #include "w83627dhg.h" -void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83627dhg_enable_UR2(device_t dev) { u8 reg8; @@ -65,18 +55,13 @@ static void w83627dhg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627dhg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 631105b..6f2c9de 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -33,17 +34,6 @@ #include "chip.h" #include "w83627ehg.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -141,18 +131,13 @@ static void w83627ehg_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = w83627ehg_pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627ehg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 4d68c35..5a4e964 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -33,17 +34,6 @@ #include "chip.h" #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -148,18 +138,13 @@ static void w83627hf_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = w83627hf_pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627hf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index f1c5603..257cd0a 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83627thg.h" -static void w83627thg_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83627thg_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83627thg_init(device_t dev) { struct superio_winbond_w83627thg_config *conf = dev->chip_info; @@ -55,18 +45,13 @@ static void w83627thg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83627thg_enter_ext_func_mode, - .exit_conf_mode = w83627thg_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83627thg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index d2cbdc9..3f1ca38 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <stdint.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83627uhg.h" -static void w83627uhg_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83627uhg_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - /* * Set the UART clock source. * @@ -101,18 +91,13 @@ static void w83627uhg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83627uhg_enter_ext_func_mode, - .exit_conf_mode = w83627uhg_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83627uhg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 9431b34..79ebcc9 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <lib.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83697hf.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { unsigned char enc, buf; @@ -81,18 +71,13 @@ static void w83697hf_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = w83697hf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index 8368839..6756830 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -29,17 +30,6 @@ #include "chip.h" #include "w83977f.h" -static void w83977f_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83977f_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83977f_init(device_t dev) { struct superio_winbond_w83977f_config *conf = dev->chip_info; @@ -54,18 +44,13 @@ static void w83977f_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83977f_enter_ext_func_mode, - .exit_conf_mode = w83977f_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83977f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index ff55f5d..0200d26 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -31,17 +32,6 @@ #include "chip.h" #include "w83977tf.h" -static void w83977tf_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83977tf_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83977tf_init(device_t dev) { struct superio_winbond_w83977tf_config *conf = dev->chip_info; @@ -56,18 +46,13 @@ static void w83977tf_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83977tf_enter_ext_func_mode, - .exit_conf_mode = w83977tf_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83977tf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = {

1 0

Patch set updated for coreboot: 160be2c qemu: add q35 support
by Gerd Hoffmann 17 Jun '13

17 Jun '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3430 -gerrit commit 160be2cc691a6c36caad971779b4c966bd8cda96 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Jun 7 16:03:44 2013 +0200 qemu: add q35 support Add support for the new q35 chipset emulation added in qemu 1.4. Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/cpu/qemu-x86/Makefile.inc | 1 + src/mainboard/emulation/Kconfig | 6 +- src/mainboard/emulation/qemu-i440fx/northbridge.c | 5 + src/mainboard/emulation/qemu-q35/Kconfig | 39 ++ src/mainboard/emulation/qemu-q35/Makefile.inc | 3 + src/mainboard/emulation/qemu-q35/acpi_tables.c | 339 ++++++++++++++++ src/mainboard/emulation/qemu-q35/devicetree.cb | 41 ++ src/mainboard/emulation/qemu-q35/dsdt.asl | 454 ++++++++++++++++++++++ src/mainboard/emulation/qemu-q35/mainboard.c | 89 +++++ src/mainboard/emulation/qemu-q35/romstage.c | 63 +++ 10 files changed, 1039 insertions(+), 1 deletion(-) diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index e206b4d..c65fcd0 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -19,3 +19,4 @@ ramstage-y += qemu.c subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic +subdirs-y += ../x86/smm diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 72b70af..3fbc415 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -6,6 +6,9 @@ choice config BOARD_EMULATION_QEMU_X86_I440FX bool "QEMU x86 i440fx/piix4 (aka qemu -M pc)" +config BOARD_EMULATION_QEMU_X86_Q35 + bool "QEMU x86 q35/ich9 (aka qemu -M q35, since v1.4)" + config BOARD_EMULATION_QEMU_ARMV7 bool "QEMU armv7 (vexpress-a9)" @@ -14,9 +17,10 @@ endchoice config BOARD_EMULATION_QEMU_X86 bool default y - depends on BOARD_EMULATION_QEMU_X86_I440FX + depends on BOARD_EMULATION_QEMU_X86_I440FX || BOARD_EMULATION_QEMU_X86_Q35 source "src/mainboard/emulation/qemu-i440fx/Kconfig" +source "src/mainboard/emulation/qemu-q35/Kconfig" source "src/mainboard/emulation/qemu-armv7/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index c2e4ba2..0e540d7 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -189,3 +189,8 @@ struct chip_operations mainboard_emulation_qemu_i440fx_ops = { CHIP_NAME("QEMU Northbridge i440fx") .enable_dev = northbridge_enable, }; + +struct chip_operations mainboard_emulation_qemu_q35_ops = { + CHIP_NAME("QEMU Northbridge q35") + .enable_dev = northbridge_enable, +}; diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig new file mode 100644 index 0000000..95209cb --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -0,0 +1,39 @@ +if BOARD_EMULATION_QEMU_X86_Q35 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_QEMU_X86 + select SOUTHBRIDGE_INTEL_I82801IX + select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS + select MMCONF_SUPPORT + select CACHE_AS_RAM +# select HAVE_OPTION_TABLE +# select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES +# select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_256 + select EARLY_CBMEM_INIT + +config MAINBOARD_DIR + string + default emulation/qemu-q35 + +config MAINBOARD_PART_NUMBER + string + default "QEMU x86 q35/ich9" + +#config IRQ_SLOT_COUNT +# int +# default 6 + +#config DCACHE_RAM_BASE +# hex +# default 0xd0000 + +#config DCACHE_RAM_SIZE +# hex +# default 0x10000 + + +endif # BOARD_EMULATION_QEMU_X86 diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc new file mode 100644 index 0000000..0a0f869 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -0,0 +1,3 @@ +cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +ramstage-y += ../qemu-i440fx/northbridge.c +ramstage-y += ../qemu-i440fx/fw_cfg.c diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c new file mode 100644 index 0000000..d894dc1 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; + + fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ + fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ + /* then FIRMWARE_CTRL must be zero. */ + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 reg; + + dev = dev_find_device(0x8086, 0x29c0, 0); + if (!dev) + return current; + + reg = pci_read_config32(dev, 0x60); + if ((reg & 0x07) != 0x01) // require enabled + 256MB size + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + reg & 0xf0000000, 0x0, 0x0, 255); + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb new file mode 100644 index 0000000..1ac55a0 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -0,0 +1,41 @@ +chip mainboard/emulation/qemu-q35 + device cpu_cluster 0 on + chip cpu/qemu-x86 + device lapic 0 on end + end + end + device domain 0 on + device pci 0.0 on end # northbridge (q35) + chip southbridge/intel/i82801ix + register "sata_ahci" = "1" + + # present unconditionally + device pci 1f.0 on end # LPC + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + + # presence depends in qemu config + # (see docs/q35-chipset.cfg in qemu src tree) + device pci 1a.0 on end # UHCI #4 + device pci 1a.1 on end # UHCI #5 + device pci 1a.2 on end # UHCI #6 + device pci 1a.7 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 on end # UHCI #1 + device pci 1d.1 on end # UHCI #2 + device pci 1d.2 on end # UHCI #3 + device pci 1d.7 on end # EHCI #1 + + # not present (not emulated by qemu) + device pci 19.0 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl new file mode 100644 index 0000000..3ae2154 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -0,0 +1,454 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* + * Copyright (c) 2010 Isaku Yamahata + * yamahata at valinux co jp + * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset. + */ + +DefinitionBlock ( + "dsdt.aml", // Output Filename + "DSDT", // Signature + 0x01, // DSDT Compliance Revision + "CORE", // OEMID + "COREBOOT", // TABLE ID + 0x2 // OEM Revision + ) +{ + +#include "../qemu-i440fx/acpi/dbug.asl" + + Scope(\_SB) { + OperationRegion(PCST, SystemIO, 0xae00, 0x0c) + OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) + Field(PCSB, AnyAcc, NoLock, WriteAsZeros) { + PCIB, 8, + } + } + + +/**************************************************************** + * PCI Bus definition + ****************************************************************/ + + Scope(\_SB) { + Device(PCI0) { + Name(_HID, EisaId("PNP0A08")) + Name(_CID, EisaId("PNP0A03")) + Name(_ADR, 0x00) + Name(_UID, 1) + + // _OSC: based on sample of ACPI3.0b spec + Name(SUPP, 0) // PCI _OSC Support Field value + Name(CTRL, 0) // PCI _OSC Control Field value + Method(_OSC, 4) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 0, CDW1) + + // Check for proper UUID + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 4, CDW2) + CreateDWordField(Arg3, 8, CDW3) + + // Save Capabilities DWORD2 & 3 + Store(CDW2, SUPP) + Store(CDW3, CTRL) + + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL, 0x1D, CTRL) + +#if 0 // For now, nothing to do + If (Not(And(CDW1, 1))) { // Query flag clear? + // Disable GPEs for features granted native control. + If (And(CTRL, 0x01)) { // Hot plug control granted? + Store(0, HPCE) // clear the hot plug SCI enable bit + Store(1, HPCS) // clear the hot plug SCI status bit + } + If (And(CTRL, 0x04)) { // PME control granted? + Store(0, PMCE) // clear the PME SCI enable bit + Store(1, PMCS) // clear the PME SCI status bit + } + If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? + // Set status to not restore PCI Express cap structure + // upon resume from S3 + Store(1, S3CR) + } + } +#endif + If (LNotEqual(Arg1, One)) { + // Unknown revision + Or(CDW1, 0x08, CDW1) + } + If (LNotEqual(CDW3, CTRL)) { + // Capabilities bits were masked + Or(CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL, CDW3) + } Else { + Or(CDW1, 4, CDW1) // Unrecognized UUID + } + Return (Arg3) + } + } + } + +#include "../qemu-i440fx/acpi/pci-crs.asl" +#include "../qemu-i440fx/acpi/hpet.asl" + + +/**************************************************************** + * VGA + ****************************************************************/ + + Scope(\_SB.PCI0) { + Device(VGA) { + Name(_ADR, 0x00010000) + Method(_S1D, 0, NotSerialized) { + Return (0x00) + } + Method(_S2D, 0, NotSerialized) { + Return (0x00) + } + Method(_S3D, 0, NotSerialized) { + Return (0x00) + } + } + } + + +/**************************************************************** + * LPC ISA bridge + ****************************************************************/ + + Scope(\_SB.PCI0) { + /* PCI D31:f0 LPC ISA bridge */ + Device(ISA) { + /* PCI D31:f0 */ + Name(_ADR, 0x001f0000) + + /* ICH9 PCI to ISA irq remapping */ + OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) + + OperationRegion(LPCD, PCI_Config, 0x80, 0x2) + Field(LPCD, AnyAcc, NoLock, Preserve) { + COMA, 3, + , 1, + COMB, 3, + + Offset(0x01), + LPTD, 2, + , 2, + FDCD, 2 + } + OperationRegion(LPCE, PCI_Config, 0x82, 0x2) + Field(LPCE, AnyAcc, NoLock, Preserve) { + CAEN, 1, + CBEN, 1, + LPEN, 1, + FDEN, 1 + } + } + } + +#include "../qemu-i440fx/acpi/isa.asl" + + +/**************************************************************** + * PCI IRQs + ****************************************************************/ + + /* Zero => PIC mode, One => APIC Mode */ + Name(\PICF, Zero) + Method(\_PIC, 1, NotSerialized) { + Store(Arg0, \PICF) + } + + Scope(\_SB) { + Scope(PCI0) { +#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \ + Package() { nr##ffff, 0, lnk0, 0 }, \ + Package() { nr##ffff, 1, lnk1, 0 }, \ + Package() { nr##ffff, 2, lnk2, 0 }, \ + Package() { nr##ffff, 3, lnk3, 0 } + +#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD) +#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA) +#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB) +#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC) + +#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH) +#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE) +#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF) +#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG) + + Name(PRTP, package() { + prt_slot_lnkE(0x0000), + prt_slot_lnkF(0x0001), + prt_slot_lnkG(0x0002), + prt_slot_lnkH(0x0003), + prt_slot_lnkE(0x0004), + prt_slot_lnkF(0x0005), + prt_slot_lnkG(0x0006), + prt_slot_lnkH(0x0007), + prt_slot_lnkE(0x0008), + prt_slot_lnkF(0x0009), + prt_slot_lnkG(0x000a), + prt_slot_lnkH(0x000b), + prt_slot_lnkE(0x000c), + prt_slot_lnkF(0x000d), + prt_slot_lnkG(0x000e), + prt_slot_lnkH(0x000f), + prt_slot_lnkE(0x0010), + prt_slot_lnkF(0x0011), + prt_slot_lnkG(0x0012), + prt_slot_lnkH(0x0013), + prt_slot_lnkE(0x0014), + prt_slot_lnkF(0x0015), + prt_slot_lnkG(0x0016), + prt_slot_lnkH(0x0017), + prt_slot_lnkE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31 + see the default value of D<N>IR */ + prt_slot_lnkA(0x0019), + prt_slot_lnkA(0x001a), + prt_slot_lnkA(0x001b), + prt_slot_lnkA(0x001c), + prt_slot_lnkA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_lnkE(0x001e), + + prt_slot_lnkA(0x001f) + }) + +#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ + Package() { nr##ffff, 0, gsi0, 0 }, \ + Package() { nr##ffff, 1, gsi1, 0 }, \ + Package() { nr##ffff, 2, gsi2, 0 }, \ + Package() { nr##ffff, 3, gsi3, 0 } + +#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) +#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA) +#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB) +#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC) + +#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH) +#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE) +#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF) +#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG) + + Name(PRTA, package() { + prt_slot_gsiE(0x0000), + prt_slot_gsiF(0x0001), + prt_slot_gsiG(0x0002), + prt_slot_gsiH(0x0003), + prt_slot_gsiE(0x0004), + prt_slot_gsiF(0x0005), + prt_slot_gsiG(0x0006), + prt_slot_gsiH(0x0007), + prt_slot_gsiE(0x0008), + prt_slot_gsiF(0x0009), + prt_slot_gsiG(0x000a), + prt_slot_gsiH(0x000b), + prt_slot_gsiE(0x000c), + prt_slot_gsiF(0x000d), + prt_slot_gsiG(0x000e), + prt_slot_gsiH(0x000f), + prt_slot_gsiE(0x0010), + prt_slot_gsiF(0x0011), + prt_slot_gsiG(0x0012), + prt_slot_gsiH(0x0013), + prt_slot_gsiE(0x0014), + prt_slot_gsiF(0x0015), + prt_slot_gsiG(0x0016), + prt_slot_gsiH(0x0017), + prt_slot_gsiE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31, but 30 + see the default value of D<N>IR */ + prt_slot_gsiA(0x0019), + prt_slot_gsiA(0x001a), + prt_slot_gsiA(0x001b), + prt_slot_gsiA(0x001c), + prt_slot_gsiA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_gsiE(0x001e), + + prt_slot_gsiA(0x001f) + }) + + Method(_PRT, 0, NotSerialized) { + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */ + If (LEqual(\PICF, Zero)) { + Return (PRTP) + } Else { + Return (PRTA) + } + } + } + + Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + + Offset(0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method(IQST, 1, NotSerialized) { + // _STA method - get status + If (And(0x80, Arg0)) { + Return (0x09) + } + Return (0x0B) + } + Method(IQCR, 1, NotSerialized) { + // _CRS method - get current settings + Name(PRR0, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 0 } + }) + CreateDWordField(PRR0, 0x05, PRRI) + Store(And(Arg0, 0x0F), PRRI) + Return (PRR0) + } + +#define define_link(link, uid, reg) \ + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + 5, 10, 11 \ + } \ + }) \ + Method(_STA, 0, NotSerialized) { \ + Return (IQST(reg)) \ + } \ + Method(_DIS, 0, NotSerialized) { \ + Or(reg, 0x80, reg) \ + } \ + Method(_CRS, 0, NotSerialized) { \ + Return (IQCR(reg)) \ + } \ + Method(_SRS, 1, NotSerialized) { \ + CreateDWordField(Arg0, 0x05, PRRI) \ + Store(PRRI, reg) \ + } \ + } + + define_link(LNKA, 0, PRQA) + define_link(LNKB, 1, PRQB) + define_link(LNKC, 2, PRQC) + define_link(LNKD, 3, PRQD) + define_link(LNKE, 4, PRQE) + define_link(LNKF, 5, PRQF) + define_link(LNKG, 6, PRQG) + define_link(LNKH, 7, PRQH) + +#define define_gsi_link(link, uid, gsi) \ + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Name(_CRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Method(_SRS, 1, NotSerialized) { \ + } \ + } + + define_gsi_link(GSIA, 0, 0x10) + define_gsi_link(GSIB, 0, 0x11) + define_gsi_link(GSIC, 0, 0x12) + define_gsi_link(GSID, 0, 0x13) + define_gsi_link(GSIE, 0, 0x14) + define_gsi_link(GSIF, 0, 0x15) + define_gsi_link(GSIG, 0, 0x16) + define_gsi_link(GSIH, 0, 0x17) + } + +#if 0 +#include "../qemu-i440fx/acpi/cpu-hotplug.asl" +#endif + + +/**************************************************************** + * General purpose events + ****************************************************************/ + + Scope(\_GPE) { + Name(_HID, "ACPI0006") + + Method(_L00) { + } + Method(_L01) { +#if 0 + // CPU hotplug event + \_SB.PRSC() +#endif + } + Method(_L02) { + } + Method(_L03) { + } + Method(_L04) { + } + Method(_L05) { + } + Method(_L06) { + } + Method(_L07) { + } + Method(_L08) { + } + Method(_L09) { + } + Method(_L0A) { + } + Method(_L0B) { + } + Method(_L0C) { + } + Method(_L0D) { + } + Method(_L0E) { + } + Method(_L0F) { + } + } +} diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c new file mode 100644 index 0000000..3740064 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer <stefan.reinauer(a)coreboot.org> + * Copyright (C) 2010 Kevin O'Connor <kevin(a)koconnor.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <console/console.h> + +#define Q35_PAM0 0x90 +#define Q35_PCIEXBAR_ADDR 0xb0000000 + +static const unsigned char qemu_q35_irqs[] = { + 10, 10, 11, 11, + 10, 10, 11, 11, +}; + +static void qemu_nb_init(device_t dev) +{ + /* Map memory at 0xc0000 - 0xfffff */ + int i; + uint8_t v = pci_read_config8(dev, Q35_PAM0); + v |= 0x30; + pci_write_config8(dev, Q35_PAM0, v); + pci_write_config8(dev, Q35_PAM0 + 1, 0x33); + pci_write_config8(dev, Q35_PAM0 + 2, 0x33); + pci_write_config8(dev, Q35_PAM0 + 3, 0x33); + pci_write_config8(dev, Q35_PAM0 + 4, 0x33); + pci_write_config8(dev, Q35_PAM0 + 5, 0x33); + pci_write_config8(dev, Q35_PAM0 + 6, 0x33); + + /* This sneaked in here, because Qemu does not + * emulate a SuperIO chip + */ + pc_keyboard_init(0); + + /* setup IRQ routing for pci slots */ + for (i = 0; i < 25; i++) + pci_assign_irqs(0, i, qemu_q35_irqs + (i % 4)); + /* setup IRQ routing southbridge devices */ + for (i = 25; i < 32; i++) + pci_assign_irqs(0, i, qemu_q35_irqs); + + /* setup mmconfig */ + pci_write_config32(dev, 0x60, Q35_PCIEXBAR_ADDR | 1); +} + +static void qemu_nb_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* reserve mmconfig */ + fixed_mem_resource(dev, 2, Q35_PCIEXBAR_ADDR >> 10, 0x10000000 >> 10, + IORESOURCE_RESERVE); +} + + +static struct device_operations nb_operations = { + .read_resources = qemu_nb_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = qemu_nb_init, + .ops_pci = 0, +}; + +static const struct pci_driver nb_driver __pci_driver = { + .ops = &nb_operations, + .vendor = 0x8086, + .device = 0x29c0, +}; diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c new file mode 100644 index 0000000..2606099 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <cpu/x86/bist.h> +#include <timestamp.h> +#include "drivers/pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" + +#include "../qemu-i440fx/memory.c" + +void main(unsigned long bist) +{ + int cbmem_was_initted; + + /* init_timer(); */ + post_code(0x05); + + i82801ix_early_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + //print_pci_devices(); + //dump_pci_devices(); + + cbmem_was_initted = !cbmem_initialize(); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(rdtsc()); + timestamp_add_now(TS_START_ROMSTAGE); +#endif +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif + +}

1 0

Patch set updated for coreboot: 14aaad9 qemu: i440fx whitespace fixup
by Gerd Hoffmann 17 Jun '13

17 Jun '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3488 -gerrit commit 14aaad9440b1edb8d76df458a65dd8638168335f Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Mon Jun 17 10:03:17 2013 +0200 qemu: i440fx whitespace fixup Change-Id: I0d499027ffb175638cba0a9830d6ec2041a139db Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-i440fx/mainboard.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index f651b99..90ad2db 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -51,10 +51,10 @@ static void qemu_nb_init(device_t dev) } static struct device_operations nb_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = qemu_nb_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = qemu_nb_init, .ops_pci = 0, };

1 0

New patch to review for coreboot: 7f8216f AM335x UART WIP
by Gabe Black 17 Jun '13

17 Jun '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3490 -gerrit commit 7f8216f2344c3b8f87a1284bb6c7c7baee540df2 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Jun 11 21:58:18 2013 -0400 AM335x UART WIP Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/uart.c | 187 ++++++++++++++++++++++++-------- src/mainboard/ti/beaglebone/bootblock.c | 31 ++++++ 2 files changed, 173 insertions(+), 45 deletions(-) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index fdf5c05..51254048 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,9 +1,5 @@ /* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> - * - * based on drivers/serial/s3c64xx.c + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,9 +14,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ +#include <config.h> #include <types.h> #include <uart.h> #include <arch/io.h> @@ -29,9 +25,36 @@ #include <cpu/ti/am335x/uart.h> -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) +#define EFR_ENHANCED_EN (1 << 4) +#define FCR_FIFO_EN (1 << 0) +#define MCR_TCR_TLR (1 << 6) +#define SYSC_SOFTRESET (1 << 1) +#define SYSS_RESETDONE (1 << 0) + +#define LSR_RXFIFOE (1 << 0) +#define LSR_TXFIFOE (1 << 5) + +#if 0 +enum register_mode { + CONFIG_A, /* config mode A, LCR[7] = 1, LCR[7:0] != 0xBF */ + CONFIG_B, /* config mode B, LCR[7] = 1, LCR[7:0] = 0xBF */ + OP, /* operational mode LCR[7] = 0 */ +}; + +static void set_register_mode(enum register_mode mode) +{ + switch (mode) { + case CONFIG_A: + break; + case CONFIG_B: + break; + case OP: + break; + default: + break; + }; +} +#endif /* * Initialise the serial port with the given baudrate. The settings @@ -39,28 +62,116 @@ */ static void am335x_uart_init_dev(void) { + struct am335x_uart *uart = (struct am335x_uart *) + CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + uint16_t lcr_orig, efr_orig, mcr_orig; + /* FIXME: implement this * ref: section 19.4.1.1.1 for reset * ref: section 19.4.1.1.2 for FIFO, skip DMA * ref: section 19.4.1.1.3 for baud rate, skip * interrupts and protocol stuff. - * */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; + */ + + /* reset the UART */ + write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); + while (!(read16(&uart->syss) & SYSS_RESETDONE)) + ; + + /* 1. switch to register config mode B */ + lcr_orig = read16(&uart->lcr); + write16(0xbf, &uart->lcr); + + /* + * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must + * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1. + */ + efr_orig = read16(&uart->efr); + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 3. Switch to register config mode A */ + write16(0x80, &uart->lcr); + + /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */ + mcr_orig = read16(&uart->mcr); + write16(mcr_orig | MCR_TCR_TLR, &uart->mcr); + + /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */ + write16(FCR_FIFO_EN, &uart->fcr); + + /* 6. Switch to configuration mode B */ + write16(0xbf, &uart->lcr); + /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */ + + /* 9. Restore original EFR value */ + write16(efr_orig, &uart->efr); + + /* 10. Switch to config mode A */ + write16(0x80, &uart->lcr); + + /* 11. Restore original MCR value */ + write16(mcr_orig, &uart->mcr); + + /* 12. Restore original LCR value */ + write16(lcr_orig, &uart->lcr); + + /* Protocol, baud rate and interrupt settings */ + + /* 1. Disable UART access to DLL and DLH registers */ + write16(read16(&uart->mdr1) | 0x7, &uart->mdr1); + + /* 2. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 3. Enable access to IER[7:4] */ + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 4. Switch to operational mode */ + write16(0x0, &uart->lcr); + + /* 5. Clear IER */ + write16(0x0, &uart->ier); + + /* 6. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 7. Set dll and dlh to the desired values (table 19-25) */ + if (CONFIG_CONSOLE_SERIAL_9600) { + write16(0x01, &uart->dlh); + write16(0x38, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_19200) { + write16(0x00, &uart->dlh); + write16(0x9c, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_38400) { + write16(0x00, &uart->dlh); + write16(0x4e, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_57600) { + write16(0x00, &uart->dlh); + write16(0x34, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_115200) { + write16(0x00, &uart->dlh); + write16(0x1a, &uart->dll); + } else { + /* Unrecognized baud rate? */ + } - // TODO initialize with correct peripheral id by base_port. - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + /* 8. Switch to operational mode to access ier */ + write16(0x0, &uart->lcr); - /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); + /* 9. Clear ier to disable all interrupts */ + write16(0x0, &uart->ier); - serial_setbrg_dev(); -#endif + /* 10. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 11. Restore efr */ + write16(efr_orig, &uart->efr); + + /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */ + write16(0x3, &uart->lcr); + + /* 13. Load the new UART mode */ + write16(0x0, &uart->mdr1); } /* @@ -70,20 +181,12 @@ static void am335x_uart_init_dev(void) */ static unsigned char am335x_uart_rx_byte(void) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | - RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) - return 0; - } + while (!(read16(&uart->lsr) & LSR_RXFIFOE)); - return readb(&uart->urxh) & 0xff; -#endif - return 0xaa; + return read8(&uart->rhr); } /* @@ -91,18 +194,12 @@ static unsigned char am335x_uart_rx_byte(void) */ static void am335x_uart_tx_byte(unsigned char data) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) - return; - } + while (!(read16(&uart->lsr) & LSR_TXFIFOE)); - writeb(data, &uart->utxh); -#endif + return write8(data, &uart->thr); } uint32_t uartmem_getbaseaddr(void) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index fbe73ea..18b5738 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -21,10 +21,13 @@ #include <types.h> #include <uart.h> #include <console/console.h> +#include <cpu/ti/am335x/pinmux.h> void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + void *uart_clock_ctrl = NULL; + /* Enable the GPIO module */ writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); @@ -38,8 +41,36 @@ void bootblock_mainboard_init(void) clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + writel(0x2, ((uint32_t *)(0x44e00000 + 0x0))); + + /* Set up the UART we're going to use */ + if (CONFIG_CONSOLE_SERIAL_UART0) { + am335x_pinmux_uart0(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); + } else if (CONFIG_CONSOLE_SERIAL_UART1) { + am335x_pinmux_uart1(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); + } else if (CONFIG_CONSOLE_SERIAL_UART2) { + am335x_pinmux_uart2(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); + } else if (CONFIG_CONSOLE_SERIAL_UART3) { + am335x_pinmux_uart3(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); + } else if (CONFIG_CONSOLE_SERIAL_UART4) { + am335x_pinmux_uart4(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); + } else if (CONFIG_CONSOLE_SERIAL_UART5) { + am335x_pinmux_uart5(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); + } + if (uart_clock_ctrl) + writel(0x2, uart_clock_ctrl); + /* Start monotonic timer */ //rtc_start(); console_init(); + + clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); + setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x3 << 21); }

1 0

New patch to review for coreboot: 24adbfc am335x: Add pinmux support based on the functions in U-Boot.
by Gabe Black 17 Jun '13

17 Jun '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3489 -gerrit commit 24adbfcf98c804a85b9e6c6750f3cd2b65349383 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jun 17 01:17:55 2013 -0700 am335x: Add pinmux support based on the functions in U-Boot. I was unable to find documentaiton that said what mode numbers correspond to what functionality, so I translated over what U-Boot does. Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 1 + src/cpu/ti/am335x/pinmux.c | 190 +++++++++++++++++++++++++++++ src/cpu/ti/am335x/pinmux.h | 268 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 459 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 9279c69..e1220fa 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += dmtimer.c bootblock-y += nand.c +bootblock-y += pinmux.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += nand.c diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c new file mode 100644 index 0000000..292865a --- /dev/null +++ b/src/cpu/ti/am335x/pinmux.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "pinmux.h" + +#include <arch/io.h> +#include <config.h> + +static struct am335x_pinmux_regs *regs = + (struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR; + +void am335x_pinmux_uart0(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart0_rxd); + writel(MODE(0) | PULLUDEN, &regs->uart0_txd); +} + +void am335x_pinmux_uart1(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart1_rxd); + writel(MODE(0) | PULLUDEN, &regs->uart1_txd); +} + +void am335x_pinmux_uart2(void) +{ + // UART2_RXD + writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_sclk); + // UART2_TXD + writel(MODE(1) | PULLUDEN, &regs->spi0_d0); +} + +void am335x_pinmux_uart3(void) +{ + // UART3_RXD + writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_cs1); + // UART3_TXD + writel(MODE(1) | PULLUDEN, &regs->ecap0_in_pwm0_out); +} + +void am335x_pinmux_uart4(void) +{ + // UART4_RXD + writel(MODE(6) | PULLUP_EN | RXACTIVE, &regs->gpmc_wait0); + // UART4_TXD + writel(MODE(6) | PULLUDEN, &regs->gpmc_wpn); +} + +void am335x_pinmux_uart5(void) +{ + // UART5_RXD + writel(MODE(4) | PULLUP_EN | RXACTIVE, &regs->lcd_data9); + // UART5_TXD + writel(MODE(4) | PULLUDEN, &regs->lcd_data8); +} + +void am335x_pinmux_mmc0(int cd, int sk_evm) +{ + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat0); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat1); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat2); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat3); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_clk); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_cmd); + if (!sk_evm) { + // MMC0_WP + writel(MODE(4) | RXACTIVE, &regs->mcasp0_aclkr); + } + if (cd) { + // MMC0_CD + writel(MODE(5) | RXACTIVE | PULLUP_EN, &regs->spi0_cs1); + } +} + +void am335x_pinmux_mmc1(void) +{ + // MMC1_DAT0 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad0); + // MMC1_DAT1 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad1); + // MMC1_DAT2 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad2); + // MMC1_DAT3 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad3); + // MMC1_CLK + writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn1); + // MMC1_CMD + writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn2); + // MMC1_WP + writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn0); + // MMC1_CD + writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_advn_ale); +} + +void am335x_pinmux_i2c0(void) +{ + writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_sda); + writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_scl); +} + +void am335x_pinmux_i2c1(void) +{ + // I2C_DATA + writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_d1); + // I2C_SCLK + writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_cs0); +} + +void am335x_pinmux_spi0(void) +{ + writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_sclk); + writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_d0); + writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_d1); + writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_cs0); +} + +void am335x_pinmux_gpio0_7(void) +{ + writel(MODE(7) | PULLUDEN, &regs->ecap0_in_pwm0_out); +} + +void am335x_pinmux_rgmii1(void) +{ + writel(MODE(2), &regs->mii1_txen); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxdv); + writel(MODE(2), &regs->mii1_txd0); + writel(MODE(2), &regs->mii1_txd1); + writel(MODE(2), &regs->mii1_txd2); + writel(MODE(2), &regs->mii1_txd3); + writel(MODE(2), &regs->mii1_txclk); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxclk); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd0); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd1); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd2); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd3); +} + +void am335x_pinmux_mii1(void) +{ + writel(MODE(0) | RXACTIVE, &regs->mii1_rxerr); + writel(MODE(0), &regs->mii1_txen); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxdv); + writel(MODE(0), &regs->mii1_txd0); + writel(MODE(0), &regs->mii1_txd1); + writel(MODE(0), &regs->mii1_txd2); + writel(MODE(0), &regs->mii1_txd3); + writel(MODE(0) | RXACTIVE, &regs->mii1_txclk); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxclk); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd0); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd1); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd2); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd3); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mdio_data); + writel(MODE(0) | PULLUP_EN, &regs->mdio_clk); +} + +void am335x_pinmux_nand(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad0); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad1); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad2); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad3); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad4); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad5); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad6); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad7); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->gpmc_wait0); + writel(MODE(7) | PULLUP_EN | RXACTIVE, &regs->gpmc_wpn); + writel(MODE(0) | PULLUDEN, &regs->gpmc_csn0); + writel(MODE(0) | PULLUDEN, &regs->gpmc_advn_ale); + writel(MODE(0) | PULLUDEN, &regs->gpmc_oen_ren); + writel(MODE(0) | PULLUDEN, &regs->gpmc_wen); + writel(MODE(0) | PULLUDEN, &regs->gpmc_be0n_cle); +} diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h new file mode 100644 index 0000000..69c1459 --- /dev/null +++ b/src/cpu/ti/am335x/pinmux.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_TI_AM335X_PINMUX_H +#define __CPU_TI_AM335X_PINMUX_H + +#include <stdint.h> + +// PAD Control Fields +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLDOWN_EN (0x0 << 4) // Pull down +#define PULLUP_EN (0x1 << 4) // Pull up +#define PULLUDEN (0x0 << 3) // Pull up enabled +#define PULLUDDIS (0x1 << 3) // Pull up disabled +#define MODE(val) val + +void am335x_pinmux_uart0(void); +void am335x_pinmux_uart1(void); +void am335x_pinmux_uart2(void); +void am335x_pinmux_uart3(void); +void am335x_pinmux_uart4(void); +void am335x_pinmux_uart5(void); + +void am335x_pinmux_mmc0(int cd, int sk_evm); +void am335x_pinmux_mmc1(void); + +void am335x_pinmux_i2c0(void); +void am335x_pinmux_i2c1(void); + +void am335x_pinmux_spi0(void); + +void am335x_pinmux_gpio0_7(void); + +void am335x_pinmux_rgmii1(void); +void am335x_pinmux_mii1(void); + +void am335x_pinmux_nand(void); + +#define AM335X_PINMUX_REG_ADDR 0x44e10000 + +struct am335x_pinmux_regs { + uint32_t gpmc_ad0; + uint32_t gpmc_ad1; + uint32_t gpmc_ad2; + uint32_t gpmc_ad3; + uint32_t gpmc_ad4; + uint32_t gpmc_ad5; + uint32_t gpmc_ad6; + uint32_t gpmc_ad7; + uint32_t gpmc_ad8; + uint32_t gpmc_ad9; + uint32_t gpmc_ad10; + uint32_t gpmc_ad11; + uint32_t gpmc_ad12; + uint32_t gpmc_ad13; + uint32_t gpmc_ad14; + uint32_t gpmc_ad15; + uint32_t gpmc_a0; + uint32_t gpmc_a1; + uint32_t gpmc_a2; + uint32_t gpmc_a3; + uint32_t gpmc_a4; + uint32_t gpmc_a5; + uint32_t gpmc_a6; + uint32_t gpmc_a7; + uint32_t gpmc_a8; + uint32_t gpmc_a9; + uint32_t gpmc_a10; + uint32_t gpmc_a11; + uint32_t gpmc_wait0; + uint32_t gpmc_wpn; + uint32_t gpmc_be1n; + uint32_t gpmc_csn0; + uint32_t gpmc_csn1; + uint32_t gpmc_csn2; + uint32_t gpmc_csn3; + uint32_t gpmc_clk; + uint32_t gpmc_advn_ale; + uint32_t gpmc_oen_ren; + uint32_t gpmc_wen; + uint32_t gpmc_be0n_cle; + uint32_t lcd_data0; + uint32_t lcd_data1; + uint32_t lcd_data2; + uint32_t lcd_data3; + uint32_t lcd_data4; + uint32_t lcd_data5; + uint32_t lcd_data6; + uint32_t lcd_data7; + uint32_t lcd_data8; + uint32_t lcd_data9; + uint32_t lcd_data10; + uint32_t lcd_data11; + uint32_t lcd_data12; + uint32_t lcd_data13; + uint32_t lcd_data14; + uint32_t lcd_data15; + uint32_t lcd_vsync; + uint32_t lcd_hsync; + uint32_t lcd_pclk; + uint32_t lcd_ac_bias_en; + uint32_t mmc0_dat3; + uint32_t mmc0_dat2; + uint32_t mmc0_dat1; + uint32_t mmc0_dat0; + uint32_t mmc0_clk; + uint32_t mmc0_cmd; + uint32_t mii1_col; + uint32_t mii1_crs; + uint32_t mii1_rxerr; + uint32_t mii1_txen; + uint32_t mii1_rxdv; + uint32_t mii1_txd3; + uint32_t mii1_txd2; + uint32_t mii1_txd1; + uint32_t mii1_txd0; + uint32_t mii1_txclk; + uint32_t mii1_rxclk; + uint32_t mii1_rxd3; + uint32_t mii1_rxd2; + uint32_t mii1_rxd1; + uint32_t mii1_rxd0; + uint32_t rmii1_refclk; + uint32_t mdio_data; + uint32_t mdio_clk; + uint32_t spi0_sclk; + uint32_t spi0_d0; + uint32_t spi0_d1; + uint32_t spi0_cs0; + uint32_t spi0_cs1; + uint32_t ecap0_in_pwm0_out; + uint32_t uart0_ctsn; + uint32_t uart0_rtsn; + uint32_t uart0_rxd; + uint32_t uart0_txd; + uint32_t uart1_ctsn; + uint32_t uart1_rtsn; + uint32_t uart1_rxd; + uint32_t uart1_txd; + uint32_t i2c0_sda; + uint32_t i2c0_scl; + uint32_t mcasp0_aclkx; + uint32_t mcasp0_fsx; + uint32_t mcasp0_axr0; + uint32_t mcasp0_ahclkr; + uint32_t mcasp0_aclkr; + uint32_t mcasp0_fsr; + uint32_t mcasp0_axr1; + uint32_t mcasp0_ahclkx; + uint32_t xdma_event_intr0; + uint32_t xdma_event_intr1; + uint32_t nresetin_out; + uint32_t porz; + uint32_t nnmi; + uint32_t osc0_in; + uint32_t osc0_out; + uint32_t rsvd1; + uint32_t tms; + uint32_t tdi; + uint32_t tdo; + uint32_t tck; + uint32_t ntrst; + uint32_t emu0; + uint32_t emu1; + uint32_t osc1_in; + uint32_t osc1_out; + uint32_t pmic_power_en; + uint32_t rtc_porz; + uint32_t rsvd2; + uint32_t ext_wakeup; + uint32_t enz_kaldo_1p8v; + uint32_t usb0_dm; + uint32_t usb0_dp; + uint32_t usb0_ce; + uint32_t usb0_id; + uint32_t usb0_vbus; + uint32_t usb0_drvvbus; + uint32_t usb1_dm; + uint32_t usb1_dp; + uint32_t usb1_ce; + uint32_t usb1_id; + uint32_t usb1_vbus; + uint32_t usb1_drvvbus; + uint32_t ddr_resetn; + uint32_t ddr_csn0; + uint32_t ddr_cke; + uint32_t ddr_ck; + uint32_t ddr_nck; + uint32_t ddr_casn; + uint32_t ddr_rasn; + uint32_t ddr_wen; + uint32_t ddr_ba0; + uint32_t ddr_ba1; + uint32_t ddr_ba2; + uint32_t ddr_a0; + uint32_t ddr_a1; + uint32_t ddr_a2; + uint32_t ddr_a3; + uint32_t ddr_a4; + uint32_t ddr_a5; + uint32_t ddr_a6; + uint32_t ddr_a7; + uint32_t ddr_a8; + uint32_t ddr_a9; + uint32_t ddr_a10; + uint32_t ddr_a11; + uint32_t ddr_a12; + uint32_t ddr_a13; + uint32_t ddr_a14; + uint32_t ddr_a15; + uint32_t ddr_odt; + uint32_t ddr_d0; + uint32_t ddr_d1; + uint32_t ddr_d2; + uint32_t ddr_d3; + uint32_t ddr_d4; + uint32_t ddr_d5; + uint32_t ddr_d6; + uint32_t ddr_d7; + uint32_t ddr_d8; + uint32_t ddr_d9; + uint32_t ddr_d10; + uint32_t ddr_d11; + uint32_t ddr_d12; + uint32_t ddr_d13; + uint32_t ddr_d14; + uint32_t ddr_d15; + uint32_t ddr_dqm0; + uint32_t ddr_dqm1; + uint32_t ddr_dqs0; + uint32_t ddr_dqsn0; + uint32_t ddr_dqs1; + uint32_t ddr_dqsn1; + uint32_t ddr_vref; + uint32_t ddr_vtp; + uint32_t ddr_strben0; + uint32_t ddr_strben1; + uint32_t ain7; + uint32_t ain6; + uint32_t ain5; + uint32_t ain4; + uint32_t ain3; + uint32_t ain2; + uint32_t ain1; + uint32_t ain0; + uint32_t vrefp; + uint32_t vrefn; +}; + +#endif

1 0

New patch to review for coreboot: f880875 qemu: i440fx whitespace fixup
by Gerd Hoffmann 17 Jun '13

17 Jun '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3488 -gerrit commit f880875458733e0483c8f39a446b8e375e36bed0 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Mon Jun 17 10:03:17 2013 +0200 qemu: i440fx whitespace fixup Change-Id: I0d499027ffb175638cba0a9830d6ec2041a139db Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-i440fx/mainboard.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index f651b99..90ad2db 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -51,10 +51,10 @@ static void qemu_nb_init(device_t dev) } static struct device_operations nb_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = qemu_nb_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = qemu_nb_init, .ops_pci = 0, };

1 0

Patch set updated for coreboot: 5508796 qemu: add q35 support
by Gerd Hoffmann 17 Jun '13

17 Jun '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3430 -gerrit commit 55087963ddce65caf3a281ef7c3caaa769798a7c Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Jun 7 16:03:44 2013 +0200 qemu: add q35 support Add support for the new q35 chipset emulation added in qemu 1.4. Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/cpu/qemu-x86/Makefile.inc | 1 + src/mainboard/emulation/Kconfig | 6 +- src/mainboard/emulation/qemu-i440fx/northbridge.c | 5 + src/mainboard/emulation/qemu-q35/Kconfig | 39 ++ src/mainboard/emulation/qemu-q35/Makefile.inc | 3 + src/mainboard/emulation/qemu-q35/acpi_tables.c | 339 ++++++++++++++++ src/mainboard/emulation/qemu-q35/devicetree.cb | 41 ++ src/mainboard/emulation/qemu-q35/dsdt.asl | 454 ++++++++++++++++++++++ src/mainboard/emulation/qemu-q35/mainboard.c | 89 +++++ src/mainboard/emulation/qemu-q35/romstage.c | 63 +++ 10 files changed, 1039 insertions(+), 1 deletion(-) diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index e206b4d..c65fcd0 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -19,3 +19,4 @@ ramstage-y += qemu.c subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic +subdirs-y += ../x86/smm diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 72b70af..a4ecec6 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -6,6 +6,9 @@ choice config BOARD_EMULATION_QEMU_X86_I440FX bool "QEMU x86 i440fx/piix4 (aka qemu -M pc)" +config BOARD_EMULATION_QEMU_X86_Q35 + bool "QEMU x86 i440fx/piix4 (aka qemu -M q35, since v1.4)" + config BOARD_EMULATION_QEMU_ARMV7 bool "QEMU armv7 (vexpress-a9)" @@ -14,9 +17,10 @@ endchoice config BOARD_EMULATION_QEMU_X86 bool default y - depends on BOARD_EMULATION_QEMU_X86_I440FX + depends on BOARD_EMULATION_QEMU_X86_I440FX || BOARD_EMULATION_QEMU_X86_Q35 source "src/mainboard/emulation/qemu-i440fx/Kconfig" +source "src/mainboard/emulation/qemu-q35/Kconfig" source "src/mainboard/emulation/qemu-armv7/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index c2e4ba2..0e540d7 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -189,3 +189,8 @@ struct chip_operations mainboard_emulation_qemu_i440fx_ops = { CHIP_NAME("QEMU Northbridge i440fx") .enable_dev = northbridge_enable, }; + +struct chip_operations mainboard_emulation_qemu_q35_ops = { + CHIP_NAME("QEMU Northbridge q35") + .enable_dev = northbridge_enable, +}; diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig new file mode 100644 index 0000000..95209cb --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -0,0 +1,39 @@ +if BOARD_EMULATION_QEMU_X86_Q35 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_QEMU_X86 + select SOUTHBRIDGE_INTEL_I82801IX + select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS + select MMCONF_SUPPORT + select CACHE_AS_RAM +# select HAVE_OPTION_TABLE +# select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES +# select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_256 + select EARLY_CBMEM_INIT + +config MAINBOARD_DIR + string + default emulation/qemu-q35 + +config MAINBOARD_PART_NUMBER + string + default "QEMU x86 q35/ich9" + +#config IRQ_SLOT_COUNT +# int +# default 6 + +#config DCACHE_RAM_BASE +# hex +# default 0xd0000 + +#config DCACHE_RAM_SIZE +# hex +# default 0x10000 + + +endif # BOARD_EMULATION_QEMU_X86 diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc new file mode 100644 index 0000000..0a0f869 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -0,0 +1,3 @@ +cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +ramstage-y += ../qemu-i440fx/northbridge.c +ramstage-y += ../qemu-i440fx/fw_cfg.c diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c new file mode 100644 index 0000000..d894dc1 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; + + fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ + fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ + /* then FIRMWARE_CTRL must be zero. */ + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 reg; + + dev = dev_find_device(0x8086, 0x29c0, 0); + if (!dev) + return current; + + reg = pci_read_config32(dev, 0x60); + if ((reg & 0x07) != 0x01) // require enabled + 256MB size + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + reg & 0xf0000000, 0x0, 0x0, 255); + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb new file mode 100644 index 0000000..1ac55a0 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -0,0 +1,41 @@ +chip mainboard/emulation/qemu-q35 + device cpu_cluster 0 on + chip cpu/qemu-x86 + device lapic 0 on end + end + end + device domain 0 on + device pci 0.0 on end # northbridge (q35) + chip southbridge/intel/i82801ix + register "sata_ahci" = "1" + + # present unconditionally + device pci 1f.0 on end # LPC + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + + # presence depends in qemu config + # (see docs/q35-chipset.cfg in qemu src tree) + device pci 1a.0 on end # UHCI #4 + device pci 1a.1 on end # UHCI #5 + device pci 1a.2 on end # UHCI #6 + device pci 1a.7 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 on end # UHCI #1 + device pci 1d.1 on end # UHCI #2 + device pci 1d.2 on end # UHCI #3 + device pci 1d.7 on end # EHCI #1 + + # not present (not emulated by qemu) + device pci 19.0 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl new file mode 100644 index 0000000..3ae2154 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -0,0 +1,454 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* + * Copyright (c) 2010 Isaku Yamahata + * yamahata at valinux co jp + * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset. + */ + +DefinitionBlock ( + "dsdt.aml", // Output Filename + "DSDT", // Signature + 0x01, // DSDT Compliance Revision + "CORE", // OEMID + "COREBOOT", // TABLE ID + 0x2 // OEM Revision + ) +{ + +#include "../qemu-i440fx/acpi/dbug.asl" + + Scope(\_SB) { + OperationRegion(PCST, SystemIO, 0xae00, 0x0c) + OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) + Field(PCSB, AnyAcc, NoLock, WriteAsZeros) { + PCIB, 8, + } + } + + +/**************************************************************** + * PCI Bus definition + ****************************************************************/ + + Scope(\_SB) { + Device(PCI0) { + Name(_HID, EisaId("PNP0A08")) + Name(_CID, EisaId("PNP0A03")) + Name(_ADR, 0x00) + Name(_UID, 1) + + // _OSC: based on sample of ACPI3.0b spec + Name(SUPP, 0) // PCI _OSC Support Field value + Name(CTRL, 0) // PCI _OSC Control Field value + Method(_OSC, 4) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 0, CDW1) + + // Check for proper UUID + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 4, CDW2) + CreateDWordField(Arg3, 8, CDW3) + + // Save Capabilities DWORD2 & 3 + Store(CDW2, SUPP) + Store(CDW3, CTRL) + + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL, 0x1D, CTRL) + +#if 0 // For now, nothing to do + If (Not(And(CDW1, 1))) { // Query flag clear? + // Disable GPEs for features granted native control. + If (And(CTRL, 0x01)) { // Hot plug control granted? + Store(0, HPCE) // clear the hot plug SCI enable bit + Store(1, HPCS) // clear the hot plug SCI status bit + } + If (And(CTRL, 0x04)) { // PME control granted? + Store(0, PMCE) // clear the PME SCI enable bit + Store(1, PMCS) // clear the PME SCI status bit + } + If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? + // Set status to not restore PCI Express cap structure + // upon resume from S3 + Store(1, S3CR) + } + } +#endif + If (LNotEqual(Arg1, One)) { + // Unknown revision + Or(CDW1, 0x08, CDW1) + } + If (LNotEqual(CDW3, CTRL)) { + // Capabilities bits were masked + Or(CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL, CDW3) + } Else { + Or(CDW1, 4, CDW1) // Unrecognized UUID + } + Return (Arg3) + } + } + } + +#include "../qemu-i440fx/acpi/pci-crs.asl" +#include "../qemu-i440fx/acpi/hpet.asl" + + +/**************************************************************** + * VGA + ****************************************************************/ + + Scope(\_SB.PCI0) { + Device(VGA) { + Name(_ADR, 0x00010000) + Method(_S1D, 0, NotSerialized) { + Return (0x00) + } + Method(_S2D, 0, NotSerialized) { + Return (0x00) + } + Method(_S3D, 0, NotSerialized) { + Return (0x00) + } + } + } + + +/**************************************************************** + * LPC ISA bridge + ****************************************************************/ + + Scope(\_SB.PCI0) { + /* PCI D31:f0 LPC ISA bridge */ + Device(ISA) { + /* PCI D31:f0 */ + Name(_ADR, 0x001f0000) + + /* ICH9 PCI to ISA irq remapping */ + OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) + + OperationRegion(LPCD, PCI_Config, 0x80, 0x2) + Field(LPCD, AnyAcc, NoLock, Preserve) { + COMA, 3, + , 1, + COMB, 3, + + Offset(0x01), + LPTD, 2, + , 2, + FDCD, 2 + } + OperationRegion(LPCE, PCI_Config, 0x82, 0x2) + Field(LPCE, AnyAcc, NoLock, Preserve) { + CAEN, 1, + CBEN, 1, + LPEN, 1, + FDEN, 1 + } + } + } + +#include "../qemu-i440fx/acpi/isa.asl" + + +/**************************************************************** + * PCI IRQs + ****************************************************************/ + + /* Zero => PIC mode, One => APIC Mode */ + Name(\PICF, Zero) + Method(\_PIC, 1, NotSerialized) { + Store(Arg0, \PICF) + } + + Scope(\_SB) { + Scope(PCI0) { +#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \ + Package() { nr##ffff, 0, lnk0, 0 }, \ + Package() { nr##ffff, 1, lnk1, 0 }, \ + Package() { nr##ffff, 2, lnk2, 0 }, \ + Package() { nr##ffff, 3, lnk3, 0 } + +#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD) +#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA) +#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB) +#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC) + +#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH) +#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE) +#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF) +#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG) + + Name(PRTP, package() { + prt_slot_lnkE(0x0000), + prt_slot_lnkF(0x0001), + prt_slot_lnkG(0x0002), + prt_slot_lnkH(0x0003), + prt_slot_lnkE(0x0004), + prt_slot_lnkF(0x0005), + prt_slot_lnkG(0x0006), + prt_slot_lnkH(0x0007), + prt_slot_lnkE(0x0008), + prt_slot_lnkF(0x0009), + prt_slot_lnkG(0x000a), + prt_slot_lnkH(0x000b), + prt_slot_lnkE(0x000c), + prt_slot_lnkF(0x000d), + prt_slot_lnkG(0x000e), + prt_slot_lnkH(0x000f), + prt_slot_lnkE(0x0010), + prt_slot_lnkF(0x0011), + prt_slot_lnkG(0x0012), + prt_slot_lnkH(0x0013), + prt_slot_lnkE(0x0014), + prt_slot_lnkF(0x0015), + prt_slot_lnkG(0x0016), + prt_slot_lnkH(0x0017), + prt_slot_lnkE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31 + see the default value of D<N>IR */ + prt_slot_lnkA(0x0019), + prt_slot_lnkA(0x001a), + prt_slot_lnkA(0x001b), + prt_slot_lnkA(0x001c), + prt_slot_lnkA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_lnkE(0x001e), + + prt_slot_lnkA(0x001f) + }) + +#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ + Package() { nr##ffff, 0, gsi0, 0 }, \ + Package() { nr##ffff, 1, gsi1, 0 }, \ + Package() { nr##ffff, 2, gsi2, 0 }, \ + Package() { nr##ffff, 3, gsi3, 0 } + +#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) +#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA) +#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB) +#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC) + +#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH) +#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE) +#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF) +#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG) + + Name(PRTA, package() { + prt_slot_gsiE(0x0000), + prt_slot_gsiF(0x0001), + prt_slot_gsiG(0x0002), + prt_slot_gsiH(0x0003), + prt_slot_gsiE(0x0004), + prt_slot_gsiF(0x0005), + prt_slot_gsiG(0x0006), + prt_slot_gsiH(0x0007), + prt_slot_gsiE(0x0008), + prt_slot_gsiF(0x0009), + prt_slot_gsiG(0x000a), + prt_slot_gsiH(0x000b), + prt_slot_gsiE(0x000c), + prt_slot_gsiF(0x000d), + prt_slot_gsiG(0x000e), + prt_slot_gsiH(0x000f), + prt_slot_gsiE(0x0010), + prt_slot_gsiF(0x0011), + prt_slot_gsiG(0x0012), + prt_slot_gsiH(0x0013), + prt_slot_gsiE(0x0014), + prt_slot_gsiF(0x0015), + prt_slot_gsiG(0x0016), + prt_slot_gsiH(0x0017), + prt_slot_gsiE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31, but 30 + see the default value of D<N>IR */ + prt_slot_gsiA(0x0019), + prt_slot_gsiA(0x001a), + prt_slot_gsiA(0x001b), + prt_slot_gsiA(0x001c), + prt_slot_gsiA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_gsiE(0x001e), + + prt_slot_gsiA(0x001f) + }) + + Method(_PRT, 0, NotSerialized) { + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */ + If (LEqual(\PICF, Zero)) { + Return (PRTP) + } Else { + Return (PRTA) + } + } + } + + Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + + Offset(0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method(IQST, 1, NotSerialized) { + // _STA method - get status + If (And(0x80, Arg0)) { + Return (0x09) + } + Return (0x0B) + } + Method(IQCR, 1, NotSerialized) { + // _CRS method - get current settings + Name(PRR0, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 0 } + }) + CreateDWordField(PRR0, 0x05, PRRI) + Store(And(Arg0, 0x0F), PRRI) + Return (PRR0) + } + +#define define_link(link, uid, reg) \ + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + 5, 10, 11 \ + } \ + }) \ + Method(_STA, 0, NotSerialized) { \ + Return (IQST(reg)) \ + } \ + Method(_DIS, 0, NotSerialized) { \ + Or(reg, 0x80, reg) \ + } \ + Method(_CRS, 0, NotSerialized) { \ + Return (IQCR(reg)) \ + } \ + Method(_SRS, 1, NotSerialized) { \ + CreateDWordField(Arg0, 0x05, PRRI) \ + Store(PRRI, reg) \ + } \ + } + + define_link(LNKA, 0, PRQA) + define_link(LNKB, 1, PRQB) + define_link(LNKC, 2, PRQC) + define_link(LNKD, 3, PRQD) + define_link(LNKE, 4, PRQE) + define_link(LNKF, 5, PRQF) + define_link(LNKG, 6, PRQG) + define_link(LNKH, 7, PRQH) + +#define define_gsi_link(link, uid, gsi) \ + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Name(_CRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Method(_SRS, 1, NotSerialized) { \ + } \ + } + + define_gsi_link(GSIA, 0, 0x10) + define_gsi_link(GSIB, 0, 0x11) + define_gsi_link(GSIC, 0, 0x12) + define_gsi_link(GSID, 0, 0x13) + define_gsi_link(GSIE, 0, 0x14) + define_gsi_link(GSIF, 0, 0x15) + define_gsi_link(GSIG, 0, 0x16) + define_gsi_link(GSIH, 0, 0x17) + } + +#if 0 +#include "../qemu-i440fx/acpi/cpu-hotplug.asl" +#endif + + +/**************************************************************** + * General purpose events + ****************************************************************/ + + Scope(\_GPE) { + Name(_HID, "ACPI0006") + + Method(_L00) { + } + Method(_L01) { +#if 0 + // CPU hotplug event + \_SB.PRSC() +#endif + } + Method(_L02) { + } + Method(_L03) { + } + Method(_L04) { + } + Method(_L05) { + } + Method(_L06) { + } + Method(_L07) { + } + Method(_L08) { + } + Method(_L09) { + } + Method(_L0A) { + } + Method(_L0B) { + } + Method(_L0C) { + } + Method(_L0D) { + } + Method(_L0E) { + } + Method(_L0F) { + } + } +} diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c new file mode 100644 index 0000000..3740064 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer <stefan.reinauer(a)coreboot.org> + * Copyright (C) 2010 Kevin O'Connor <kevin(a)koconnor.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <console/console.h> + +#define Q35_PAM0 0x90 +#define Q35_PCIEXBAR_ADDR 0xb0000000 + +static const unsigned char qemu_q35_irqs[] = { + 10, 10, 11, 11, + 10, 10, 11, 11, +}; + +static void qemu_nb_init(device_t dev) +{ + /* Map memory at 0xc0000 - 0xfffff */ + int i; + uint8_t v = pci_read_config8(dev, Q35_PAM0); + v |= 0x30; + pci_write_config8(dev, Q35_PAM0, v); + pci_write_config8(dev, Q35_PAM0 + 1, 0x33); + pci_write_config8(dev, Q35_PAM0 + 2, 0x33); + pci_write_config8(dev, Q35_PAM0 + 3, 0x33); + pci_write_config8(dev, Q35_PAM0 + 4, 0x33); + pci_write_config8(dev, Q35_PAM0 + 5, 0x33); + pci_write_config8(dev, Q35_PAM0 + 6, 0x33); + + /* This sneaked in here, because Qemu does not + * emulate a SuperIO chip + */ + pc_keyboard_init(0); + + /* setup IRQ routing for pci slots */ + for (i = 0; i < 25; i++) + pci_assign_irqs(0, i, qemu_q35_irqs + (i % 4)); + /* setup IRQ routing southbridge devices */ + for (i = 25; i < 32; i++) + pci_assign_irqs(0, i, qemu_q35_irqs); + + /* setup mmconfig */ + pci_write_config32(dev, 0x60, Q35_PCIEXBAR_ADDR | 1); +} + +static void qemu_nb_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* reserve mmconfig */ + fixed_mem_resource(dev, 2, Q35_PCIEXBAR_ADDR >> 10, 0x10000000 >> 10, + IORESOURCE_RESERVE); +} + + +static struct device_operations nb_operations = { + .read_resources = qemu_nb_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = qemu_nb_init, + .ops_pci = 0, +}; + +static const struct pci_driver nb_driver __pci_driver = { + .ops = &nb_operations, + .vendor = 0x8086, + .device = 0x29c0, +}; diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c new file mode 100644 index 0000000..2606099 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <cpu/x86/bist.h> +#include <timestamp.h> +#include "drivers/pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" + +#include "../qemu-i440fx/memory.c" + +void main(unsigned long bist) +{ + int cbmem_was_initted; + + /* init_timer(); */ + post_code(0x05); + + i82801ix_early_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + //print_pci_devices(); + //dump_pci_devices(); + + cbmem_was_initted = !cbmem_initialize(); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(rdtsc()); + timestamp_add_now(TS_START_ROMSTAGE); +#endif +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif + +}

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New patch to review for coreboot: 0e11ce1 AMD: Use same sourcecode for reset in romstage as ramstage
by Kyösti Mälkki 17 Jun '13

17 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3487 -gerrit commit 0e11ce1312788ef6f202bfff115d94290689429a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 17 01:09:07 2013 +0300 AMD: Use same sourcecode for reset in romstage as ramstage Confusingly, romstage compiled in different copy of soft_reset() than ramstage. Use source in reset.c for both. Change-Id: I2e4b6d1b89c859c7cf5d9e9c8f7748b43d369775 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Makefile.inc | 3 +-- src/mainboard/advansus/a785e-i/romstage.c | 7 ------- src/mainboard/asus/m5a88-v/Makefile.inc | 1 + src/mainboard/asus/m5a88-v/romstage.c | 7 ------- src/mainboard/avalue/eax-785e/Makefile.inc | 3 +-- src/mainboard/avalue/eax-785e/romstage.c | 8 -------- 6 files changed, 3 insertions(+), 26 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index d69a9bf..d7290af 100644 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -1,5 +1,4 @@ -#romstage-y += reset.c #FIXME romstage have include test_rest.c - +romstage-y += reset.c ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index ae283a4..1a4a276 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -72,14 +72,7 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" - #include <reset.h> -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index 35b2043..d7290af 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += reset.c ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index dbae2d3..ddb0e6f 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -72,14 +72,7 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" - #include <reset.h> -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index d69a9bf..d7290af 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -1,5 +1,4 @@ -#romstage-y += reset.c #FIXME romstage have include test_rest.c - +romstage-y += reset.c ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index d4704e8..5af67f7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -72,15 +72,7 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" - #include <reset.h> -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) {

1 0

Patch set updated for coreboot: 626e0db AMD southbridges: Move HAVE_HARD_RESET
by Kyösti Mälkki 17 Jun '13

17 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3486 -gerrit commit 626e0dbf7f4976c376b7e84ae0d64bada3085272 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 16 17:12:37 2013 +0300 AMD southbridges: Move HAVE_HARD_RESET All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Kconfig | 1 - src/mainboard/advansus/a785e-i/Makefile.inc | 2 - src/mainboard/advansus/a785e-i/reset.c | 65 ---------------------- src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/amd/dinar/Makefile.inc | 1 - src/mainboard/amd/dinar/reset.c | 67 ----------------------- src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/inagua/Makefile.inc | 1 - src/mainboard/amd/inagua/reset.c | 67 ----------------------- src/mainboard/amd/parmer/Kconfig | 1 - src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/persimmon/Makefile.inc | 1 - src/mainboard/amd/persimmon/reset.c | 67 ----------------------- src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/south_station/Makefile.inc | 1 - src/mainboard/amd/south_station/reset.c | 67 ----------------------- src/mainboard/amd/thatcher/Kconfig | 1 - src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/amd/torpedo/Makefile.inc | 1 - src/mainboard/amd/torpedo/reset.c | 67 ----------------------- src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/amd/union_station/Makefile.inc | 1 - src/mainboard/amd/union_station/reset.c | 67 ----------------------- src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asrock/e350m1/Makefile.inc | 1 - src/mainboard/asrock/e350m1/reset.c | 67 ----------------------- src/mainboard/asus/f2a85-m/Kconfig | 1 - src/mainboard/asus/m5a88-v/Kconfig | 1 - src/mainboard/asus/m5a88-v/Makefile.inc | 2 - src/mainboard/asus/m5a88-v/reset.c | 65 ---------------------- src/mainboard/avalue/eax-785e/Kconfig | 1 - src/mainboard/avalue/eax-785e/Makefile.inc | 2 - src/mainboard/avalue/eax-785e/reset.c | 65 ---------------------- src/mainboard/lippert/frontrunner-af/Kconfig | 1 - src/mainboard/lippert/frontrunner-af/Makefile.inc | 1 - src/mainboard/lippert/frontrunner-af/reset.c | 67 ----------------------- src/mainboard/lippert/toucan-af/Kconfig | 1 - src/mainboard/lippert/toucan-af/Makefile.inc | 1 - src/mainboard/lippert/toucan-af/reset.c | 67 ----------------------- src/mainboard/supermicro/h8qgi/Kconfig | 1 - src/mainboard/supermicro/h8qgi/Makefile.inc | 2 - src/mainboard/supermicro/h8qgi/reset.c | 67 ----------------------- src/mainboard/supermicro/h8scm/Kconfig | 1 - src/mainboard/supermicro/h8scm/Makefile.inc | 2 - src/mainboard/supermicro/h8scm/reset.c | 67 ----------------------- src/mainboard/tyan/s8226/Kconfig | 1 - src/mainboard/tyan/s8226/Makefile.inc | 2 - src/mainboard/tyan/s8226/reset.c | 67 ----------------------- src/southbridge/amd/agesa/hudson/Kconfig | 1 + src/southbridge/amd/cimx/sb700/Kconfig | 1 + src/southbridge/amd/cimx/sb700/Makefile.inc | 2 + src/southbridge/amd/cimx/sb700/reset.c | 67 +++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/Kconfig | 1 + src/southbridge/amd/cimx/sb800/Makefile.inc | 2 + src/southbridge/amd/cimx/sb800/reset.c | 67 +++++++++++++++++++++++ src/southbridge/amd/cimx/sb900/Kconfig | 1 + src/southbridge/amd/cimx/sb900/Makefile.inc | 2 + src/southbridge/amd/cimx/sb900/reset.c | 67 +++++++++++++++++++++++ 58 files changed, 211 insertions(+), 1038 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 3753df8..fdf08aa 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index d7290af..924f9d6 100644 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += reset.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/advansus/a785e-i/reset.c b/src/mainboard/advansus/a785e-i/reset.c deleted file mode 100644 index 678bc3d..0000000 --- a/src/mainboard/advansus/a785e-i/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index 48c1e74..3bb2257 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select HAVE_ACPI_TABLES #TODO select HAVE_ACPI_RESUME select ENABLE_APIC_EXT_ID diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc index 42f458b..8dfe21d 100644 --- a/src/mainboard/amd/dinar/Makefile.inc +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -29,7 +29,6 @@ ramstage-y += BiosCallOuts.c ramstage-y += sb700_cfg.c ramstage-y += rd890_cfg.c -ramstage-y += reset.c AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\ diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c deleted file mode 100644 index f2a2bcd..0000000 --- a/src/mainboard/amd/dinar/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 3c1431e..1d8128e 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc index b84a03a..f5c52f0 100644 --- a/src/mainboard/amd/inagua/Makefile.inc +++ b/src/mainboard/amd/inagua/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c ramstage-y += broadcom.c diff --git a/src/mainboard/amd/inagua/reset.c b/src/mainboard/amd/inagua/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/inagua/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 678432b..8dd457b 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 2e7442c..5758ecf 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index 17443bc..e1f18a9 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/persimmon/reset.c b/src/mainboard/amd/persimmon/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/persimmon/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 1c5e401..ec16e6c 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index 59c6cd0..2105082 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/south_station/reset.c b/src/mainboard/amd/south_station/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/south_station/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index f619478..a9227e5 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 2c70143..37255f2 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc index 26beb37..1102ea2 100644 --- a/src/mainboard/amd/torpedo/Makefile.inc +++ b/src/mainboard/amd/torpedo/Makefile.inc @@ -44,4 +44,3 @@ ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/torpedo/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index e3e4bfe..a096d66 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index 59c6cd0..2105082 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/union_station/reset.c b/src/mainboard/amd/union_station/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/amd/union_station/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 4c05037..bf44af3 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc index 59c6cd0..2105082 100644 --- a/src/mainboard/asrock/e350m1/Makefile.inc +++ b/src/mainboard/asrock/e350m1/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/asrock/e350m1/reset.c b/src/mainboard/asrock/e350m1/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/asrock/e350m1/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index ad2c8b7..f26b8d5 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 5318977..942a81d 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_ITE_IT8721F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index d7290af..924f9d6 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += reset.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/asus/m5a88-v/reset.c b/src/mainboard/asus/m5a88-v/reset.c deleted file mode 100644 index 678bc3d..0000000 --- a/src/mainboard/asus/m5a88-v/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 11fc657..99b9c67 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index d7290af..924f9d6 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += reset.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/avalue/eax-785e/reset.c b/src/mainboard/avalue/eax-785e/reset.c deleted file mode 100644 index 678bc3d..0000000 --- a/src/mainboard/avalue/eax-785e/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index d326746..9ddf970 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -35,7 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 17443bc..e1f18a9 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/lippert/frontrunner-af/reset.c b/src/mainboard/lippert/frontrunner-af/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/lippert/frontrunner-af/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index e8f5896..07fbbea 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -37,7 +37,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index 17443bc..e1f18a9 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/lippert/toucan-af/reset.c b/src/mainboard/lippert/toucan-af/reset.c deleted file mode 100644 index bb2482b..0000000 --- a/src/mainboard/lippert/toucan-af/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 1184a93..f13593e 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index 451e013..77e8719 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c deleted file mode 100644 index 7a96aa4..0000000 --- a/src/mainboard/supermicro/h8qgi/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 95e6f81..1eadc36 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc index 451e013..77e8719 100644 --- a/src/mainboard/supermicro/h8scm/Makefile.inc +++ b/src/mainboard/supermicro/h8scm/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/supermicro/h8scm/reset.c b/src/mainboard/supermicro/h8scm/reset.c deleted file mode 100644 index 7a96aa4..0000000 --- a/src/mainboard/supermicro/h8scm/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 1db75b3..0d832fe 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc index 451e013..77e8719 100644 --- a/src/mainboard/tyan/s8226/Makefile.inc +++ b/src/mainboard/tyan/s8226/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/tyan/s8226/reset.c b/src/mainboard/tyan/s8226/reset.c deleted file mode 100644 index 7a96aa4..0000000 --- a/src/mainboard/tyan/s8226/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 7aa3405..f67b663 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index e98d3ed..97cdf1c 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB700 bool select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB700 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc index 94a0dea..268629f 100644 --- a/src/southbridge/amd/cimx/sb700/Makefile.inc +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -22,8 +22,10 @@ romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += late.c +ramstage-y += reset.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c new file mode 100644 index 0000000..7a96aa4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 554d8c7..b82409d 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 default n select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 524c2d3..831cc2e 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -23,9 +23,11 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += cfg.c ramstage-y += late.c +ramstage-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c new file mode 100644 index 0000000..7a96aa4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index aa30e56..5d3b0a1 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB900 default n select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB900 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index ebb3e3f..cc4c553 100755 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -23,10 +23,12 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += cfg.c ramstage-y += early.c ramstage-y += late.c +ramstage-y += reset.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c new file mode 100644 index 0000000..7a96aa4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} +

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Patch merged into coreboot/master: 156ff13 cpu/amd/geode_lx/cache_as_ram.inc: Use $ for constant value instead of memory reference
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 156ff1304905845736834d33b6a2d04ef5773ec5 Author: Christopher Kilgour <techie(a)whiterocker.com> Date: Sat Jun 15 23:52:36 2013 -0700 cpu/amd/geode_lx/cache_as_ram.inc: Use $ for constant value instead of memory reference An uninitialized RAM value was used to select an MSR because a $ was forgotten in front of `CPU_DM_CONFIG0`. It should be the constant value 0x1800, corresponding to CPU_DM_CONFIG0 MSR defined in `src/include/cpu/amd/lxdef.h`. Change-Id: Id53ca98b06cc4a9b55916fd8db23904f98008d45 Signed-off-by: Christopher Kilgour <techie(a)whiterocker.com> Reviewed-on: http://review.coreboot.org/3478 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> See http://review.coreboot.org/3478 for details. -gerrit

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coreboot-gerrit June 2013