coreboot-gerrit June 2013

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Patch set updated for coreboot: cdb1c6b AMD: Drop empty root_complex
by Bruce Griffith 17 Jun '13

17 Jun '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3434 -gerrit commit cdb1c6b6ced498b9c9da362eceef962846799403 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 11 17:00:11 2013 +0300 AMD: Drop empty root_complex There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dbm690t/Kconfig | 1 - src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/mahogany/Kconfig | 1 - src/mainboard/amd/parmer/Kconfig | 1 - src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/amd/serengeti_cheetah/Kconfig | 1 - src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/thatcher/Kconfig | 1 - src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/arima/hdama/Kconfig | 1 - src/mainboard/asrock/939a785gmh/Kconfig | 1 - src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asus/a8n_e/Kconfig | 1 - src/mainboard/asus/a8v-e_deluxe/Kconfig | 1 - src/mainboard/asus/a8v-e_se/Kconfig | 1 - src/mainboard/asus/f2a85-m/Kconfig | 1 - src/mainboard/asus/k8v-x/Kconfig | 1 - src/mainboard/asus/m2n-e/Kconfig | 1 - src/mainboard/asus/m2v-mx_se/Kconfig | 1 - src/mainboard/asus/m2v/Kconfig | 1 - src/mainboard/broadcom/blast/Kconfig | 1 - src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 1 - src/mainboard/gigabyte/m57sli/Kconfig | 1 - src/mainboard/hp/dl145_g1/Kconfig | 1 - src/mainboard/hp/dl145_g3/Kconfig | 1 - src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 - src/mainboard/ibm/e325/Kconfig | 1 - src/mainboard/ibm/e326/Kconfig | 1 - src/mainboard/iwill/dk8_htx/Kconfig | 1 - src/mainboard/iwill/dk8s2/Kconfig | 1 - src/mainboard/iwill/dk8x/Kconfig | 1 - src/mainboard/kontron/kt690/Kconfig | 1 - src/mainboard/lippert/frontrunner-af/Kconfig | 1 - src/mainboard/lippert/toucan-af/Kconfig | 1 - src/mainboard/msi/ms7135/Kconfig | 1 - src/mainboard/msi/ms7260/Kconfig | 1 - src/mainboard/msi/ms9185/Kconfig | 1 - src/mainboard/msi/ms9282/Kconfig | 1 - src/mainboard/newisys/khepri/Kconfig | 1 - src/mainboard/nvidia/l1_2pvv/Kconfig | 1 - src/mainboard/siemens/sitemp_g1p1/Kconfig | 1 - src/mainboard/sunw/ultra40/Kconfig | 1 - src/mainboard/supermicro/h8dme/Kconfig | 1 - src/mainboard/supermicro/h8dmr/Kconfig | 1 - src/mainboard/supermicro/h8qgi/Kconfig | 1 - src/mainboard/supermicro/h8scm/Kconfig | 1 - src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim8690/Kconfig | 1 - src/mainboard/tyan/s2850/Kconfig | 1 - src/mainboard/tyan/s2875/Kconfig | 1 - src/mainboard/tyan/s2880/Kconfig | 1 - src/mainboard/tyan/s2881/Kconfig | 1 - src/mainboard/tyan/s2882/Kconfig | 1 - src/mainboard/tyan/s2885/Kconfig | 1 - src/mainboard/tyan/s2891/Kconfig | 1 - src/mainboard/tyan/s2892/Kconfig | 1 - src/mainboard/tyan/s2895/Kconfig | 1 - src/mainboard/tyan/s2912/Kconfig | 1 - src/mainboard/tyan/s4880/Kconfig | 1 - src/mainboard/tyan/s4882/Kconfig | 1 - src/mainboard/tyan/s8226/Kconfig | 1 - src/northbridge/amd/agesa/family10/Kconfig | 3 --- .../amd/agesa/family10/root_complex/Kconfig | 2 -- src/northbridge/amd/agesa/family12/Kconfig | 1 - .../amd/agesa/family12/root_complex/Kconfig | 2 -- src/northbridge/amd/agesa/family14/Kconfig | 1 - .../amd/agesa/family14/root_complex/Kconfig | 2 -- src/northbridge/amd/agesa/family15/Kconfig | 3 --- .../amd/agesa/family15/root_complex/Kconfig | 2 -- src/northbridge/amd/agesa/family15tn/Kconfig | 1 - .../amd/agesa/family15tn/root_complex/Kconfig | 2 -- src/northbridge/amd/amdfam10/Kconfig | 3 --- src/northbridge/amd/amdfam10/root_complex/Kconfig | 3 --- src/northbridge/amd/amdk8/Kconfig | 2 -- src/northbridge/amd/amdk8/root_complex/Kconfig | 21 --------------------- util/sconfig/main.c | 9 +++++++-- 79 files changed, 7 insertions(+), 114 deletions(-) diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 74a3d66..ffa4b20 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index 9edbe7a..f35d9db 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_G34 - select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 3c1431e..e014034 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_SMSC_KBC1100 diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 2a6f4ea..36fed0f 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8718F diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 678432b..430806d 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 2e7442c..c74fd97 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_FINTEK_F81865F diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index febf265..73dbc60 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index b26803e..632cd83 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 1c5e401..a903b19 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_FINTEK_F81865F diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index f619478..225c75c 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index ac42a4f..751ee12 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR3 select DIMM_UNREGISTERED select CPU_AMD_AGESA_FAMILY12 - select NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY12 select SOUTHBRIDGE_AMD_CIMX_SB900 select SUPERIO_SMSC_KBC1100 diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index e3e4bfe..0f553b0 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_OPTION_TABLE diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 408e953..2b6f758 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_NSC_PC87360 diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index c94e69b..9d3dd5c 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_WINBOND_W83627DHG diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 4c05037..344ae5a 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 22249f6..acb528b 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_939 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 1f0d2e9..e953ed4 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index 8159a43..c5b9374 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index ad2c8b7..0a808ab 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 28c2c81..51426ac 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index b0e3146..8d60e0c 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select MCP55_USE_NIC select MCP55_USE_AZA diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index dca4984..725c75d 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8M890 diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 61ffd9a..b67b416 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index b953b6e..502576c 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index c535294..1c57840 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_SIS_SIS966 select SUPERIO_ITE_IT8716F select HAVE_OPTION_TABLE diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index daae829..d7483b7 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select MCP55_USE_NIC select MCP55_USE_AZA diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 16b5733..7e63077 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index bee23f7..f8aecbf 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index 32abeec..7250017 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 5cfc6cd..0a8442b 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_NSC_PC87366 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index c79d2c0..2016ef9 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_NSC_PC87366 diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index d6b4c63..6ccee76 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index 6476d50..d7fefd8 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index e09a27b..bdbeb69 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627THG diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index db75d87..ff58692 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 select SUPERIO_WINBOND_W83627DHG diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index d326746..1f2bc44 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_SMSC_SMSCSUPERIO diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index e8f5896..4083ef5 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 # The Toucan-AF is meant to work on any COM Express Type 6 baseboard. diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index f1577a9..14c0f49 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index efabd51..437c062 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select MCP55_USE_NIC select MCP55_USE_AZA diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index dc19d98..9f51bb6 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index d571632..63d4c60 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627EHG select HAVE_OPTION_TABLE diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 6ee4bf0..04c8ed3 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 3eae434..aba4cbd 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select MCP55_USE_NIC select MCP55_USE_AZA diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index 81ba5e7..68d1f3f 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 491e3fa..ba7aaa4 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index b8bd694..947846e 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select MCP55_USE_NIC select MCP55_USE_AZA diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index 3cc296a..079f382 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select MCP55_USE_NIC select MCP55_USE_AZA diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 1184a93..7189e74 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_G34 - select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 95e6f81..d0d3792 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_C32 - select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 720dbfa..368e4fe 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 691ebe6..27b61fe 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index 2d07423..88ab969 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index d9e7bac..8e77709 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8151 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 93dadac..c6fed4b 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index 2f10a61..fcc93f3 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 145fdfc..0a0909a 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index 595d7e0..aab6732 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8151 diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index f30e140..ddd7ed0 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index 3fab23a..ddf2901 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index 5037ca8..0201eb4 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_SMSC_LPC47B397 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index f653478..cad352b 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index 5040a6a..1299e33 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index ee67bae..2dd3a44 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 - select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 1db75b3..7729ffb 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_C32 - select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig index b45d264..244c133 100755 --- a/src/northbridge/amd/agesa/family10/Kconfig +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -23,7 +23,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY10 select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT - select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX if NORTHBRIDGE_AMD_AGESA_FAMILY10 config HT3_SUPPORT @@ -42,5 +41,3 @@ config MMCONF_BUS_NUMBER int default 256 endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 - -source "src/northbridge/amd/agesa/family10/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family10/root_complex/Kconfig b/src/northbridge/amd/agesa/family10/root_complex/Kconfig deleted file mode 100755 index 345896b..0000000 --- a/src/northbridge/amd/agesa/family10/root_complex/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX - bool diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index d51fbdd..e483fe5 100755 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12 select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT - select NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX if NORTHBRIDGE_AMD_AGESA_FAMILY12 diff --git a/src/northbridge/amd/agesa/family12/root_complex/Kconfig b/src/northbridge/amd/agesa/family12/root_complex/Kconfig deleted file mode 100755 index f6a5f4f..0000000 --- a/src/northbridge/amd/agesa/family12/root_complex/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX - bool diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 8a8a48e..e0edebc 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool select MMCONF_SUPPORT - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family14/root_complex/Kconfig b/src/northbridge/amd/agesa/family14/root_complex/Kconfig deleted file mode 100644 index f4eed4f..0000000 --- a/src/northbridge/amd/agesa/family14/root_complex/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX - bool diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig index 92de9ba..17eef08 100644 --- a/src/northbridge/amd/agesa/family15/Kconfig +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -23,7 +23,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15 select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT - select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX if NORTHBRIDGE_AMD_AGESA_FAMILY15 config HT3_SUPPORT @@ -42,5 +41,3 @@ config MMCONF_BUS_NUMBER int default 64 endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 - -source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/root_complex/Kconfig b/src/northbridge/amd/agesa/family15/root_complex/Kconfig deleted file mode 100644 index 032b836..0000000 --- a/src/northbridge/amd/agesa/family15/root_complex/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX - bool diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 72cf0c6..24fdb0d 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool select MMCONF_SUPPORT - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family15tn/root_complex/Kconfig b/src/northbridge/amd/agesa/family15tn/root_complex/Kconfig deleted file mode 100644 index 6f5621f..0000000 --- a/src/northbridge/amd/agesa/family15tn/root_complex/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX - bool diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index b61be28..73da579 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -23,7 +23,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AMDFAM10 @@ -119,5 +118,3 @@ config SVI_HIGH_FREQ at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. endif # NORTHBRIDGE_AMD_AMDFAM10 - -source src/northbridge/amd/amdfam10/root_complex/Kconfig diff --git a/src/northbridge/amd/amdfam10/root_complex/Kconfig b/src/northbridge/amd/amdfam10/root_complex/Kconfig deleted file mode 100644 index 328c4e7..0000000 --- a/src/northbridge/amd/amdfam10/root_complex/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX - bool - diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 7534232..2f3660b 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -102,5 +102,3 @@ config IOMMU default y endif #NORTHBRIDGE_AMD_K8 - -source src/northbridge/amd/amdk8/root_complex/Kconfig diff --git a/src/northbridge/amd/amdk8/root_complex/Kconfig b/src/northbridge/amd/amdk8/root_complex/Kconfig deleted file mode 100644 index a3c5ed2..0000000 --- a/src/northbridge/amd/amdk8/root_complex/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX - bool diff --git a/util/sconfig/main.c b/util/sconfig/main.c index c3f2cdf..03ba1ef 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -168,9 +168,14 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { char *chip_h = malloc(strlen(path)+18); sprintf(chip_h, "src/%s", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) { - fprintf(stderr, "ERROR: Chip component %s does not exist.\n", + if (strstr(path, "/root_complex")) { + fprintf(stderr, "WARNING: Use of deprecated chip component %s\n", path); - exit(1); + } else { + fprintf(stderr, "ERROR: Chip component %s does not exist.\n", + path); + exit(1); + } } if (scan_mode == STATIC_MODE)

1 0

New patch to review for coreboot: 59c7c7e libpayload: ahci: Fix command engine shutdown
by Nico Huber 17 Jun '13

17 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3494 -gerrit commit 59c7c7e94105a40a333916c7152763ba1bfade74 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jun 17 17:47:24 2013 +0200 libpayload: ahci: Fix command engine shutdown A timeout while waiting for a device' signature has shown that our error path wasn't correct. The shutdown of the ports command engine always timed out. Fix that by waiting for FR (FIS Receive Running) to be cleared independently from CR (Command List Running) and after clearing FRE (FIS Receive Enable). Change-Id: I50edf426ef0241424456f1489a7fc86a2cfc5753 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/storage/ahci.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index deecd2b..fe83d46 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -73,7 +73,7 @@ static inline int ahci_port_is_active(const hba_port_t *const port) static int ahci_cmdengine_start(hba_port_t *const port) { - /* Wait for the controller to clear CR. + /* CR has to be clear before starting the command engine. This shouldn't take too long, but we should time out nevertheless. */ int timeout = 1000; /* Time out after 1000 * 1us == 1ms. */ while ((port->cmd_stat & HBA_PxCMD_CR) && timeout--) @@ -92,10 +92,10 @@ static int ahci_cmdengine_stop(hba_port_t *const port) { port->cmd_stat &= ~HBA_PxCMD_ST; - /* Wait for the controller to clear FR and CR. + /* Wait for the controller to clear CR. This shouldn't take too long, but we should time out nevertheless. */ int timeout = 1000; /* Time out after 1000 * 1us == 1ms. */ - while ((port->cmd_stat & (HBA_PxCMD_FR | HBA_PxCMD_CR)) && timeout--) + while ((port->cmd_stat & HBA_PxCMD_CR) && timeout--) udelay(1); if (timeout < 0) { printf("ahci: Timeout during stopping of command engine.\n"); @@ -103,6 +103,17 @@ static int ahci_cmdengine_stop(hba_port_t *const port) } port->cmd_stat &= ~HBA_PxCMD_FRE; + + /* Wait for the controller to clear FR. + This shouldn't take too long, but we should time out nevertheless. */ + timeout = 1000; /* Time out after 1000 * 1us == 1ms. */ + while ((port->cmd_stat & HBA_PxCMD_FR) && timeout--) + udelay(1); + if (timeout < 0) { + printf("ahci: Timeout during stopping of command engine.\n"); + return 1; + } + return 0; }

1 0

New patch to review for coreboot: b4e2561 libpayload: ahci: Increase timeout for signature reading
by Nico Huber 17 Jun '13

17 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3493 -gerrit commit b4e2561f6f678f7804208423a32beb62d677af8c Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jun 17 17:42:35 2013 +0200 libpayload: ahci: Increase timeout for signature reading I've found the first SATA disk that takes ages (> 4s) to identify itself. Let's set the timeout to 5s. Also put a notice on the console, so the user knows why the signature reading failed. Change-Id: I2148258f9b0eb950b71544dafd95776ae70afac8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/storage/ahci.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 72acd0b..deecd2b 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -396,10 +396,13 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, dev->rcvd_fis = rcvd_fis; /* Wait for D2H Register FIS with device' signature. */ - int timeout = 200; /* Time out after 200 * 10ms == 2s. */ + int timeout = 500; /* Time out after 500 * 10ms == 5s. */ while ((port->taskfile_data & HBA_PxTFD_BSY) && timeout--) mdelay(10); + if (port->taskfile_data & HBA_PxTFD_BSY) + printf("ahci: Timed out waiting for device' signature.\n"); + /* Initialize device or fall through to clean up. */ switch (port->signature) { case HBA_PxSIG_ATA:

1 0

Patch merged into coreboot/master: 7fd1bee qemu: i440fx whitespace fixup
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 7fd1beeaf7a295d298b26880593840033290c329 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Mon Jun 17 10:03:17 2013 +0200 qemu: i440fx whitespace fixup Change-Id: I0d499027ffb175638cba0a9830d6ec2041a139db Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/3488 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3488 for details. -gerrit

1 0

Patch merged into coreboot/master: ee941b3 qemu: add q35 support
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit ee941b38d666f11ce5256cbccecea75f38ca86c1 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Jun 7 16:03:44 2013 +0200 qemu: add q35 support Add support for the new q35 chipset emulation added in qemu 1.4. Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/3430 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3430 for details. -gerrit

1 0

Patch merged into coreboot/master: 9839a38 qemu: add support for memory above 4G
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 9839a385bb778a87fc00a046a77334709ac78930 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Mon Jun 17 12:26:17 2013 +0200 qemu: add support for memory above 4G Change-Id: Ic83f55d01b29b43028e3b363749d64b927db5489 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/3492 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3492 for details. -gerrit

1 0

Patch merged into coreboot/master: 44b11f2 qemu: move ram ressource reservation from "set" to "read" stage
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 44b11f2fe423a04641ca1059d2ba5a188412cdc7 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Mon Jun 17 13:30:50 2013 +0200 qemu: move ram ressource reservation from "set" to "read" stage So the pci allocation code knows where memory is and doesn't try map pci devices there. We also don't have to check for overlaps between pci hole and memory then. Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/3491 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3491 for details. -gerrit

1 0

New patch to review for coreboot: 5168f49 qemu: add support for memory above 4G
by Gerd Hoffmann 17 Jun '13

17 Jun '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3492 -gerrit commit 5168f49d64f1e0a79abdc8731362d317ac1d9ef0 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Mon Jun 17 12:26:17 2013 +0200 qemu: add support for memory above 4G Change-Id: Ic83f55d01b29b43028e3b363749d64b927db5489 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-i440fx/memory.c | 5 +++++ src/mainboard/emulation/qemu-i440fx/northbridge.c | 20 ++++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 322fc49..8245ca2 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -21,9 +21,14 @@ #define CMOS_ADDR_PORT 0x70 #define CMOS_DATA_PORT 0x71 + #define HIGH_RAM_ADDR 0x35 #define LOW_RAM_ADDR 0x34 +#define HIGH_HIGHRAM_ADDR 0x5d +#define MID_HIGHRAM_ADDR 0x5c +#define LOW_HIGHRAM_ADDR 0x5b + static unsigned long qemu_get_memory_size(void) { unsigned long tomk; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index ed372b6..7cf5436 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -16,6 +16,18 @@ #include "memory.c" +static unsigned long qemu_get_high_memory_size(void) +{ + unsigned long high; + outb (HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); + high = ((unsigned long) inb(CMOS_DATA_PORT)) << 22; + outb (MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); + high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 14; + outb (LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); + high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; + return high; +} + static void cpu_pci_domain_set_resources(device_t dev) { assign_resources(dev->link_list); @@ -24,18 +36,22 @@ static void cpu_pci_domain_set_resources(device_t dev) static void cpu_pci_domain_read_resources(struct device *dev) { struct resource *res; - unsigned long tomk = 0; + unsigned long tomk = 0, high; int idx = 10; pci_domain_read_resources(dev); tomk = qemu_get_memory_size(); - printk(BIOS_DEBUG, "Detected %lu MiB RAM.\n", tomk / 1024); + high = qemu_get_high_memory_size(); + printk(BIOS_DEBUG, "Detected %lu MiB RAM below 4G.\n", tomk / 1024); + printk(BIOS_DEBUG, "Detected %lu MiB RAM above 4G.\n", high / 1024); /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); + if (high) + ram_resource(dev, idx++, 4 * 1024 * 1024, high); /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;

1 0

New patch to review for coreboot: a10b0e1 qemu: move ram ressource reservation from "set" to "read" stage
by Gerd Hoffmann 17 Jun '13

17 Jun '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3491 -gerrit commit a10b0e1177af72b577f72704f682d6dbf996e19b Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Mon Jun 17 13:30:50 2013 +0200 qemu: move ram ressource reservation from "set" to "read" stage So the pci allocation code knows where memory is and doesn't try map pci devices there. We also don't have to check for overlaps between pci hole and memory then. Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 34 ++++++++--------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index c2e4ba2..ed372b6 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -18,39 +18,29 @@ static void cpu_pci_domain_set_resources(device_t dev) { - u32 pci_tolm = find_pci_tolm(dev->link_list); - unsigned long tomk = 0, tolmk; - int idx; + assign_resources(dev->link_list); +} + +static void cpu_pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + unsigned long tomk = 0; + int idx = 10; + + pci_domain_read_resources(dev); tomk = qemu_get_memory_size(); - printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", - tomk, tomk / 1024); - - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does not overlap the memory. */ - tolmk = tomk; - } + printk(BIOS_DEBUG, "Detected %lu MiB RAM.\n", tomk / 1024); /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); + ram_resource(dev, idx++, 768, tomk - 768); /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; - assign_resources(dev->link_list); -} - -static void cpu_pci_domain_read_resources(struct device *dev) -{ - struct resource *res; - - pci_domain_read_resources(dev); - /* Reserve space for the IOAPIC. This should be in the Southbridge, * but I couldn't tell which device to put it in. */ res = new_resource(dev, 2);

1 0

Patch set updated for coreboot: 5ebd024 pnp: Add some default functions to enter/exit config state
by Nico Huber 17 Jun '13

17 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3484 -gerrit commit 5ebd024eb1aab8e9f2f51bd3ac12f363b14b0c32 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 20:33:44 2013 +0200 pnp: Add some default functions to enter/exit config state Implement some common default functions to enter and exit the configuration state. Also provide default pnp_mode_ops for common enter()/exit() function pairs. The following cocci ensures their use: @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; @ enter_match_8787 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } @ depends on enter_match_8787 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_8787, }; @ enter_match_55 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x55, dev->path.pnp.port); } @ depends on enter_match_55 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_55, }; @ depends on enter_match_8787 || enter_match_55 @ identifier mode_match.enter; @@ -enter(...) {...} @ exit_match_aa @ identifier mode_match.exit, dev; @@ exit(...) { outb(0xaa, dev->path.pnp.port); } @ depends on exit_match_aa @ identifier mode_match.exit, mode_match.ops; @@ struct pnp_mode_ops ops = { - .exit_conf_mode = exit, + .exit_conf_mode = pnp_exit_conf_mode_aa, }; @ depends on exit_match_aa @ identifier mode_match.exit; @@ -exit(...) {...} @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @ @@ #include <device/pnp.h> +#include <superio/conf_mode.h> @ mode_match_55_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_55_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_55_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; @ mode_match_8787_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_8787_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_8787_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/include/superio/conf_mode.h | 34 ++++++++++++++++++++++ src/superio/Makefile.inc | 1 + src/superio/common/conf_mode.c | 50 +++++++++++++++++++++++++++++++++ src/superio/fintek/f71805f/superio.c | 19 ++----------- src/superio/fintek/f71859/superio.c | 19 ++----------- src/superio/fintek/f71863fg/superio.c | 19 ++----------- src/superio/fintek/f71872/superio.c | 19 ++----------- src/superio/fintek/f71889/superio.c | 19 ++----------- src/superio/fintek/f81865f/superio.c | 19 ++----------- src/superio/nuvoton/nct5104d/superio.c | 19 ++----------- src/superio/smsc/kbc1100/superio.c | 21 ++------------ src/superio/smsc/lpc47b272/superio.c | 21 ++------------ src/superio/smsc/lpc47b397/superio.c | 20 ++----------- src/superio/smsc/lpc47m10x/superio.c | 21 ++------------ src/superio/smsc/lpc47m15x/superio.c | 21 ++------------ src/superio/smsc/mec1308/superio.c | 18 ++---------- src/superio/smsc/sch4037/superio.c | 21 ++------------ src/superio/smsc/sio1036/superio.c | 21 ++------------ src/superio/smsc/smscsuperio/superio.c | 34 ++-------------------- src/superio/via/vt1211/vt1211.c | 19 ++----------- src/superio/winbond/w83627dhg/superio.c | 19 ++----------- src/superio/winbond/w83627ehg/superio.c | 19 ++----------- src/superio/winbond/w83627hf/superio.c | 19 ++----------- src/superio/winbond/w83627thg/superio.c | 19 ++----------- src/superio/winbond/w83627uhg/superio.c | 19 ++----------- src/superio/winbond/w83697hf/superio.c | 19 ++----------- src/superio/winbond/w83977f/superio.c | 19 ++----------- src/superio/winbond/w83977tf/superio.c | 19 ++----------- 28 files changed, 136 insertions(+), 451 deletions(-) diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h new file mode 100644 index 0000000..b93b889 --- /dev/null +++ b/src/include/superio/conf_mode.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DEVICE_PNP_CONF_MODE_H +#define DEVICE_PNP_CONF_MODE_H + +#include <device/device.h> +#include <device/pnp.h> + +/* Common enter/exit implementations */ +void pnp_enter_conf_mode_55(device_t dev); +void pnp_enter_conf_mode_8787(device_t dev); +void pnp_exit_conf_mode_aa(device_t dev); + +extern const struct pnp_mode_ops pnp_conf_mode_55_aa; +extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; + +#endif diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index ff4d48f..e34fa89 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -28,3 +28,4 @@ subdirs-y += smsc subdirs-y += via subdirs-y += winbond +ramstage-$(CONFIG_ARCH_X86) += common/conf_mode.c diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c new file mode 100644 index 0000000..40583ff --- /dev/null +++ b/src/superio/common/conf_mode.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <superio/conf_mode.h> + +/* Common enter/exit implementations */ + +void pnp_enter_conf_mode_55(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +void pnp_enter_conf_mode_8787(device_t dev) +{ + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); +} + +void pnp_exit_conf_mode_aa(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +const struct pnp_mode_ops pnp_conf_mode_55_aa = { + .enter_conf_mode = pnp_enter_conf_mode_55, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + +const struct pnp_mode_ops pnp_conf_mode_8787_aa = { + .enter_conf_mode = pnp_enter_conf_mode_8787, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 50c3355..4a31606 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "f71805f.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71805f_init(device_t dev) { if (!dev->enabled) @@ -45,18 +35,13 @@ static void f71805f_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71805f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 1e5b6ec..2736c0b 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -22,22 +22,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "f71859.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71859_init(device_t dev) { if (!dev->enabled) @@ -46,18 +36,13 @@ static void f71859_init(device_t dev) /* TODO: Might potentially need code for HWM or FDC etc. */ } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71859_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 84a7ec1..4159e6d 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -21,23 +21,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "chip.h" #include "f71863fg.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71863fg_init(device_t dev) { struct superio_fintek_f71863fg_config *conf = dev->chip_info; @@ -55,18 +45,13 @@ static void f71863fg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71863fg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 8db22a9..55a11b1 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include "chip.h" #include "f71872.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71872_init(device_t dev) { struct superio_fintek_f71872_config *conf = dev->chip_info; @@ -52,18 +42,13 @@ static void f71872_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71872_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 8de8ae8..450f938 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -21,23 +21,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include <uart8250.h> #include "chip.h" #include "f71889.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f71889_init(device_t dev) { struct superio_fintek_f71889_config *conf = dev->chip_info; @@ -53,18 +43,13 @@ static void f71889_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f71889_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 050602c..85ac7ba 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -21,22 +21,12 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <stdlib.h> #include "chip.h" #include "f81865f.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void f81865f_init(device_t dev) { struct superio_fintek_f81865f_config *conf = dev->chip_info; @@ -52,18 +42,13 @@ static void f81865f_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f81865f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index c8b696d..5eb8991 100755 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -20,36 +20,21 @@ #include <arch/io.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <stdlib.h> #include "nct5104d.h" -static void pnp_enter_exteded_mode(device_t dev) -{ - outb(0x87,dev->path.pnp.port); - outb(0x87,dev->path.pnp.port); -} - -static void pnp_exit_extended_mode(device_t dev) -{ - outb(0xaa,dev->path.pnp.port); -} - static void nct5104d_init(device_t dev) { } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_exteded_mode, - .exit_conf_mode = pnp_exit_extended_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = nct5104d_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index a6d0ef0..c56694c 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void kbc1100_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_kbc1100_ops = { CHIP_NAME("SMSC KBC1100 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = kbc1100_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -86,13 +79,3 @@ static void kbc1100_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index d06f094..8901ec4 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -26,6 +26,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -38,9 +39,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); static void lpc47b272_init(device_t dev); - -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); // static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47b272_ops = { @@ -48,18 +46,13 @@ struct chip_operations superio_smsc_lpc47b272_ops = { .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b272_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -105,16 +98,6 @@ static void lpc47b272_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - #if 0 /** * Print the values of all of the LPC47B272's configuration registers. diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 850b7bb..ff6e405 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -32,16 +33,6 @@ #include "chip.h" #include "lpc47b397.h" -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -94,18 +85,13 @@ static void lpc47b397_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b397_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; #define HWM_INDEX 0 @@ -165,7 +151,7 @@ static struct device_operations ops_hwm = { .init = lpc47b397_init, .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 925defa..c1f3c2c 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -25,6 +25,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -37,9 +38,6 @@ /* Forward declarations */ static void enable_dev(device_t dev); static void lpc47m10x_init(device_t dev); - -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); // static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47m10x_ops = { @@ -47,18 +45,13 @@ struct chip_operations superio_smsc_lpc47m10x_ops = { .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47m10x_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -104,16 +97,6 @@ static void lpc47m10x_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - #if 0 /** * Print the values of all of the LPC47M10X2's configuration registers. diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index a3b8fc5..7e400fc 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void lpc47m15x_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_lpc47m15x_ops = { CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47m15x_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -84,13 +77,3 @@ static void lpc47m15x_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 0385b26..448800e 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -33,16 +34,6 @@ #include <arch/acpi.h> #endif -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void mec1308_init(device_t dev) { struct superio_smsc_mec1308_config *conf = dev->chip_info; @@ -61,18 +52,13 @@ static void mec1308_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = mec1308_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 254b838..96d35fe 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void sch4037_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_sch4037_ops = { CHIP_NAME("SMSC SCH4037 Super I/O") .enable_dev = enable_dev, }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = sch4037_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -85,13 +78,3 @@ static void sch4037_init(device_t dev) break; } } - -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index 2ce2af2..ff7b5d1 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> #include <string.h> @@ -35,26 +36,18 @@ static void enable_dev(device_t dev); static void sio1036_init(device_t dev); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_sio1036_ops = { CHIP_NAME("SMSC SIO1036 Super I/O") .enable_dev = enable_dev }; -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_conf_state, - .exit_conf_mode = pnp_exit_conf_state, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = sio1036_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -84,13 +77,3 @@ static void sio1036_init(device_t dev) } } -static void pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index d45a967..42a9c09 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -37,6 +37,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <uart8250.h> #include <pc80/keyboard.h> @@ -144,32 +145,6 @@ static const struct logical_devices { }; /** - * Enter the configuration state by writing 0x55 to the config port. - * - * The Super I/O configuration registers can only be modified when the chip - * is in the configuration state. Thus, to program the registers you have - * to a) enter config mode, b) program the registers, c) exit config mode. - * - * @param dev The device to use. - */ -static void smsc_pnp_enter_conf_state(device_t dev) -{ - outb(0x55, dev->path.pnp.port); -} - -/** - * Exit the configuration state by writing 0xaa to the config port. - * - * This puts the chip into the 'run' state again. - * - * @param dev The device to use. - */ -static void smsc_pnp_exit_conf_state(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - -/** * Initialize those logical devices which need a special init. * * @param dev The device to use. @@ -199,11 +174,6 @@ static void smsc_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = smsc_pnp_enter_conf_state, - .exit_conf_mode = smsc_pnp_exit_conf_state, -}; - /** Standard device operations. */ static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -211,7 +181,7 @@ static struct device_operations ops = { .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = smsc_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; /** diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 8e09e4a..68fd999 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <uart8250.h> #include <stdlib.h> #include "vt1211.h" @@ -44,17 +45,6 @@ static u8 hwm_io_regs[] = { 0x5c,0x00, 0x5f,0x33, 0x40,0x01, }; -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase) { switch (dev->path.pnp.device) { @@ -172,18 +162,13 @@ static void vt1211_pnp_set_resources(struct device *dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = vt1211_pnp_set_resources, .enable_resources = vt1211_pnp_enable_resources, .enable = pnp_alt_enable, .init = vt1211_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 1a83b3d..59020a3 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -20,23 +20,13 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> #include "chip.h" #include "w83627dhg.h" -void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83627dhg_enable_UR2(device_t dev) { u8 reg8; @@ -65,18 +55,13 @@ static void w83627dhg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627dhg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 631105b..6f2c9de 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -33,17 +34,6 @@ #include "chip.h" #include "w83627ehg.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -141,18 +131,13 @@ static void w83627ehg_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = w83627ehg_pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627ehg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 4d68c35..5a4e964 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -33,17 +34,6 @@ #include "chip.h" #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void pnp_write_index(u16 port, u8 reg, u8 value) { outb(reg, port); @@ -148,18 +138,13 @@ static void w83627hf_pnp_enable_resources(device_t dev) pnp_exit_conf_mode(dev); } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = w83627hf_pnp_enable_resources, .enable = pnp_alt_enable, .init = w83627hf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index f1c5603..257cd0a 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83627thg.h" -static void w83627thg_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83627thg_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83627thg_init(device_t dev) { struct superio_winbond_w83627thg_config *conf = dev->chip_info; @@ -55,18 +45,13 @@ static void w83627thg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83627thg_enter_ext_func_mode, - .exit_conf_mode = w83627thg_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83627thg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index d2cbdc9..3f1ca38 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <stdint.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83627uhg.h" -static void w83627uhg_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83627uhg_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - /* * Set the UART clock source. * @@ -101,18 +91,13 @@ static void w83627uhg_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83627uhg_enter_ext_func_mode, - .exit_conf_mode = w83627uhg_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83627uhg_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 9431b34..79ebcc9 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <lib.h> @@ -30,17 +31,6 @@ #include "chip.h" #include "w83697hf.h" -static void pnp_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { unsigned char enc, buf; @@ -81,18 +71,13 @@ static void w83697hf_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = w83697hf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index 8368839..6756830 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -29,17 +30,6 @@ #include "chip.h" #include "w83977f.h" -static void w83977f_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83977f_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83977f_init(device_t dev) { struct superio_winbond_w83977f_config *conf = dev->chip_info; @@ -54,18 +44,13 @@ static void w83977f_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83977f_enter_ext_func_mode, - .exit_conf_mode = w83977f_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83977f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index ff55f5d..0200d26 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <superio/conf_mode.h> #include <console/console.h> #include <string.h> #include <uart8250.h> @@ -31,17 +32,6 @@ #include "chip.h" #include "w83977tf.h" -static void w83977tf_enter_ext_func_mode(device_t dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void w83977tf_exit_ext_func_mode(device_t dev) -{ - outb(0xaa, dev->path.pnp.port); -} - static void w83977tf_init(device_t dev) { struct superio_winbond_w83977tf_config *conf = dev->chip_info; @@ -56,18 +46,13 @@ static void w83977tf_init(device_t dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = w83977tf_enter_ext_func_mode, - .exit_conf_mode = w83977tf_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = w83977tf_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = {

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coreboot-gerrit June 2013