coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 13dc976 pnp: Register implementations of enter/exit config state
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 13dc976a5288899756ec6e5d53b51b1ddf64b389 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 19:33:15 2013 +0200 pnp: Register implementations of enter/exit config state Find all the (ramstage) implementations of enter()/exit() functions for the configuration state, register and call them through the new struct pnp_mode_ops. As our standard PnP functions are aware of the pnp_mode_ops, it's not necessary to call enter()/exit() around them anymore. Patch generated with the cocci below. It's not perfect. The movement of the enter()/exit() calls is somehow fragile. So I checked the remaining calls for sense, and changed some empty lines. Also a duplicate insertion of pnp_conf_mode_ops had to be removed. /* Try to find enter and exit functions by their outb() structure and their usage around calls to our standard pnp functions: */ @ enter_match @ identifier enter; identifier dev; type device_t; @@ void enter(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ exit_match @ identifier exit; identifier dev; type device_t; @@ void exit(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ pnp_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; identifier enter_match.enter, exit_match.exit; type device_t; identifier dev; @@ void op(device_t dev) { ... enter(dev); ... pnp_op(dev); ... exit(dev); ... } /* Now add enter/exit to a pnp_mode_ops structure: */ @ depends on pnp_match @ identifier enter_match.enter; identifier exit_match.exit; identifier ops; @@ +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = enter, + .exit_conf_mode = exit, +}; + struct device_operations ops = { ..., + .ops_pnp_mode = &pnp_conf_mode_ops, }; /* Match against the new structure as we change the code and the above matches might not work anymore: */ @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; /* Replace enter()/enter() calls with new standard calls (e.g. pnp_enter_conf_mode()): */ @@ identifier mode_match.enter; expression e; @@ -enter(e) +pnp_enter_conf_mode(e) @@ identifier mode_match.exit; expression e; @@ -exit(e) +pnp_exit_conf_mode(e) /* If there are calls to standard PnP functions, (re)move the enter()/exit() calls around them: */ @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ -pnp_enter_conf_mode(e); pnp_op(e); +pnp_enter_conf_mode(e); ... pnp_exit_conf_mode(e); @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ pnp_enter_conf_mode(e); ... +pnp_exit_conf_mode(e); pnp_op(e); -pnp_exit_conf_mode(e); @@ expression e; @@ -pnp_enter_conf_mode(e); -pnp_exit_conf_mode(e); Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3482 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3482 for details. -gerrit

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Patch merged into coreboot/master: dd4715b pnp: Implement common handling for PnP config modes
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit dd4715b6a5beca80ce9655f8711327a83d05b416 Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Jun 10 22:08:35 2013 +0200 pnp: Implement common handling for PnP config modes Many super i/o chips only answer to PnP requests if they are in a configuration state (sometimes also called ext func mode). To cope with that, the code of many chips implements its own version of our default PnP functions like pnp_set_resource(), pnp_enable_resource() etc. To avoid this code duplication, this patch extends our PnP device interface with optional functions to enter and exit configuration mode. Change-Id: I9b7662a0db70ede93276764fa15020f251eb46bd Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3481 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3481 for details. -gerrit

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Patch merged into coreboot/master: f898f7b pnp: Provide alternative pnp_enable() implementation
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit f898f7ba4d10146b45241afe65fd54b3c049cc4f Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Jun 10 22:57:12 2013 +0200 pnp: Provide alternative pnp_enable() implementation The current default implementation of pnp_enable() only disables devices - if set so in the devicetree - but does not enable them. Enablement takes place in pnp_enable_resources(). Yet, many PnP chips implement their own version of pnp_enable() which also enables devices if set in the devicetree. It's arguable, if enabling those devices makes sense, before they get resources assigned. Maybe we can't write the resource registers if not, who knows? The least we can do is providing a common implementation for this behavior, and get rid of some code duplication. Used the following cocci: @@ expression e; @@ +pnp_alt_enable(e); -pnp_set_logical_device(e); ( -pnp_set_enable(e, !!e->enabled); | -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0); | -if (e->enabled) { pnp_set_enable(e, 1); } -else { pnp_set_enable(e, 0); } ) Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3480 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3480 for details. -gerrit

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Patch merged into coreboot/master: a00f983 libpayload: ahci: Fix command engine shutdown
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit a00f9830fb58d3f5061aab71be8553f3ff2e1f70 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jun 17 17:47:24 2013 +0200 libpayload: ahci: Fix command engine shutdown A timeout while waiting for a device' signature has shown that our error path wasn't correct. The shutdown of the ports command engine always timed out. Fix that by waiting for FR (FIS Receive Running) to be cleared independently from CR (Command List Running) and after clearing FRE (FIS Receive Enable). Change-Id: I50edf426ef0241424456f1489a7fc86a2cfc5753 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3494 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3494 for details. -gerrit

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Patch set updated for coreboot: a7eef7f AMD Hudson: Add config option to enable XHCI
by Dave Frodin 17 Jun '13

17 Jun '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3464 -gerrit commit a7eef7fe6e5a3df01a72c1af1095bf67918f7981 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Jun 14 07:11:40 2013 -0600 AMD Hudson: Add config option to enable XHCI To have USB 3.0 support the XHCI controller needs to be enabled and the xhci.bin firmware needs to be added to CBFS. Change-Id: I0b641b30b67163b7dc73ee7ae67efe678e11c000 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 7aa3405..b346863 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -40,11 +40,21 @@ config EHCI_DEBUG_OFFSET hex default 0xe0 +config HUDSON_XHCI_ENABLE + bool "Enable Hudson XHCI Controller" + default y + help + The XHCI controller must be enabled and the XHCI firmware + must be added in order to have USB 3.0 support configured + by coreboot. The OS will be responsible for enabling the XHCI + controller if the the XHCI firmware is available but the + XHCI controller is not enabled by coreboot. + config HUDSON_XHCI_FWM bool "Add xhci firmware" default y - help - Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0 + help + Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 config HUDSON_IMC_FWM bool "Add imc firmware"

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Patch set updated for coreboot: ddf62b9 Add support for XHCI (USB 3.0)
by Dave Frodin 17 Jun '13

17 Jun '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3465 -gerrit commit ddf62b9f5f6e04274fb720bc60e50bfa568eb388 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jun 13 17:30:48 2013 -0600 Add support for XHCI (USB 3.0) CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the amd/parmer and asus/f2a85-m mainboards. The XHCI ports on amd/thatcher are not wired to USB jacks so always disable the flags. This was tested on amd/parmer using a USB 3.0 thumbdrive. Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 8 ++++++++ src/mainboard/amd/parmer/agesawrapper.c | 4 ++++ src/mainboard/amd/thatcher/agesawrapper.c | 2 ++ src/mainboard/asus/f2a85-m/BiosCallOuts.c | 5 +++++ src/mainboard/asus/f2a85-m/agesawrapper.c | 4 ++++ 5 files changed, 23 insertions(+) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 9592c9d..ba33b85 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -293,6 +293,14 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) /* Fan Control */ oem_fan_control(FchParams_env); + /* XHCI configuration */ +#if CONFIG_HUDSON_XHCI_ENABLE + FchParams_env->Usb.Xhci0Enable = TRUE; +#else + FchParams_env->Usb.Xhci0Enable = FALSE; +#endif + FchParams_env->Usb.Xhci1Enable = FALSE; + /* sata configuration */ } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index a81a997..c160106 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -202,6 +202,10 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; +#if !CONFIG_HUDSON_XHCI_ENABLE + AmdResetParams.FchInterface.Xhci0Enable = FALSE; +#endif + AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index f7577fd..9480bdc 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -202,6 +202,8 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; + AmdResetParams.FchInterface.Xhci0Enable = FALSE; + AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index e913896..cc3ed72 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -117,8 +117,13 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ /* XHCI configuration */ +#if CONFIG_HUDSON_XHCI_ENABLE FchParams_env->Usb.Xhci0Enable = TRUE; FchParams_env->Usb.Xhci1Enable = TRUE; +#else + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; +#endif } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index df45148..66b8d4f 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -202,6 +202,10 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; +#if !CONFIG_HUDSON_XHCI_ENABLE + AmdResetParams.FchInterface.Xhci0Enable = FALSE; + AmdResetParams.FchInterface.Xhci1Enable = FALSE; +#endif status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);

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Patch merged into coreboot/master: 3cc151e Make intel blob locations configurable
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 3cc151ede0677776f891c959568b92a79b9ecd9a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jun 13 15:07:02 2013 +0200 Make intel blob locations configurable They were hard-coded to be copied from 3rdparty/ which isn't always the right choice. Since the defaults stay the same, this should be compatible. Change-Id: If2173bef86ad1fcf2335e13472ea8ca41eb41f3d Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/3453 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/3453 for details. -gerrit

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Patch set updated for coreboot: 5ca8b28 AMD Hudson: Add config option to enable XHCI
by Dave Frodin 17 Jun '13

17 Jun '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3464 -gerrit commit 5ca8b2827e0972796cf0256714bb7a521fc1948f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Jun 14 07:11:40 2013 -0600 AMD Hudson: Add config option to enable XHCI To have USB 3.0 support the XHCI controller needs to be enabled and the xhci.bin firmware needs to be added to CBFS. Change-Id: I0b641b30b67163b7dc73ee7ae67efe678e11c000 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 7aa3405..2488b9a 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -40,11 +40,21 @@ config EHCI_DEBUG_OFFSET hex default 0xe0 +config HUDSON_XHCI_ENABLE + bool "Enable Hudson XHCI Controller" + default y + help + The XHCI controller must be enabled and the XHCI firmware + must be added in order to have USB 3.0 support configured + by coreboot. The OS will be responsible for enabling the XHCI + controller if the the XHCI firmware is available but the + XHCI controller is not enabled by coreboot. + config HUDSON_XHCI_FWM bool "Add xhci firmware" default y - help - Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0 + help + Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 config HUDSON_IMC_FWM bool "Add imc firmware"

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Patch set updated for coreboot: d15925d Add support for XHCI (USB 3.0)
by Dave Frodin 17 Jun '13

17 Jun '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3465 -gerrit commit d15925d09b625c7dd495be2a05403e8b4ae5f8a8 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jun 13 17:30:48 2013 -0600 Add support for XHCI (USB 3.0) CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the amd/parmer and asus/f2a85-m mainboards. The XHCI ports on amd/thatcher are not wired to USB jacks so always disable the flags. This was tested on amd/parmer using a USB 3.0 thumbdrive. Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 8 ++++++++ src/mainboard/amd/parmer/agesawrapper.c | 4 ++++ src/mainboard/amd/thatcher/agesawrapper.c | 2 ++ src/mainboard/asus/f2a85-m/BiosCallOuts.c | 5 +++++ src/mainboard/asus/f2a85-m/agesawrapper.c | 4 ++++ 5 files changed, 23 insertions(+) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 9592c9d..ba33b85 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -293,6 +293,14 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) /* Fan Control */ oem_fan_control(FchParams_env); + /* XHCI configuration */ +#if CONFIG_HUDSON_XHCI_ENABLE + FchParams_env->Usb.Xhci0Enable = TRUE; +#else + FchParams_env->Usb.Xhci0Enable = FALSE; +#endif + FchParams_env->Usb.Xhci1Enable = FALSE; + /* sata configuration */ } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index a81a997..c160106 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -202,6 +202,10 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; +#if !CONFIG_HUDSON_XHCI_ENABLE + AmdResetParams.FchInterface.Xhci0Enable = FALSE; +#endif + AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index f7577fd..9480bdc 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -202,6 +202,8 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; + AmdResetParams.FchInterface.Xhci0Enable = FALSE; + AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index e913896..cc3ed72 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -117,8 +117,13 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ /* XHCI configuration */ +#if CONFIG_HUDSON_XHCI_ENABLE FchParams_env->Usb.Xhci0Enable = TRUE; FchParams_env->Usb.Xhci1Enable = TRUE; +#else + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; +#endif } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index df45148..66b8d4f 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -202,6 +202,10 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; +#if !CONFIG_HUDSON_XHCI_ENABLE + AmdResetParams.FchInterface.Xhci0Enable = FALSE; + AmdResetParams.FchInterface.Xhci1Enable = FALSE; +#endif status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);

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Patch merged into coreboot/master: 9cb0941 pnp: Unify some alignment to ease autogenerating patches
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 9cb0941cb2f4ceb77b470c4de617ca915896d9f3 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 15:30:19 2013 +0200 pnp: Unify some alignment to ease autogenerating patches Most PnP drivers align the initialization of their `device_operations` with spaces. Unify this, so next autogenerated patches always match the alignment. Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3479 for details. -gerrit

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coreboot-gerrit June 2013