coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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744 discussions

Patch set updated for coreboot: 6e36351 libpayload: ahci: Increase timeout for signature reading
by Nico Huber 17 Jun '13

17 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3493 -gerrit commit 6e363515919fdc22aacbd028ab8dfa353792c60b Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jun 17 17:42:35 2013 +0200 libpayload: ahci: Increase timeout for signature reading We can't read the drives signature before it's ready, i.e. spun up. So set the timeout to the standard 30s. Also put a notice on the console, so the user knows why the signature reading failed. Change-Id: I2148258f9b0eb950b71544dafd95776ae70afac8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/storage/ahci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 72acd0b..893ef07 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -395,11 +395,17 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, dev->cmdtable = cmdtable; dev->rcvd_fis = rcvd_fis; - /* Wait for D2H Register FIS with device' signature. */ - int timeout = 200; /* Time out after 200 * 10ms == 2s. */ + /* + * Wait for D2H Register FIS with device' signature. + * The drive has to spin up here, so wait up to 30s. + */ + int timeout = 3 * 1000; /* Time out after 3,000 * 10ms == 30s. */ while ((port->taskfile_data & HBA_PxTFD_BSY) && timeout--) mdelay(10); + if (port->taskfile_data & HBA_PxTFD_BSY) + printf("ahci: Timed out waiting for device to spin up.\n"); + /* Initialize device or fall through to clean up. */ switch (port->signature) { case HBA_PxSIG_ATA:

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Patch merged into coreboot/master: 5acc76c am335x: Add pinmux support based on the functions in U-Boot
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 5acc76cd3e097e86768c2addc0963ea521f19a49 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jun 17 01:17:55 2013 -0700 am335x: Add pinmux support based on the functions in U-Boot I was unable to find documentation that said what mode numbers correspond to what functionality, so I translated over what U-Boot does. Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3489 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3489 for details. -gerrit

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Patch set updated for coreboot: c9f4cc6 am335x: Add pinmux support based on the functions in U-Boot
by Stefan Reinauer 17 Jun '13

17 Jun '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3489 -gerrit commit c9f4cc6a02d410bb38dac8d3576b71e06bd63fda Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jun 17 01:17:55 2013 -0700 am335x: Add pinmux support based on the functions in U-Boot I was unable to find documentation that said what mode numbers correspond to what functionality, so I translated over what U-Boot does. Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 1 + src/cpu/ti/am335x/pinmux.c | 190 +++++++++++++++++++++++++++++ src/cpu/ti/am335x/pinmux.h | 268 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 459 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 9279c69..e1220fa 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += dmtimer.c bootblock-y += nand.c +bootblock-y += pinmux.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += nand.c diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c new file mode 100644 index 0000000..292865a --- /dev/null +++ b/src/cpu/ti/am335x/pinmux.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "pinmux.h" + +#include <arch/io.h> +#include <config.h> + +static struct am335x_pinmux_regs *regs = + (struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR; + +void am335x_pinmux_uart0(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart0_rxd); + writel(MODE(0) | PULLUDEN, &regs->uart0_txd); +} + +void am335x_pinmux_uart1(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart1_rxd); + writel(MODE(0) | PULLUDEN, &regs->uart1_txd); +} + +void am335x_pinmux_uart2(void) +{ + // UART2_RXD + writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_sclk); + // UART2_TXD + writel(MODE(1) | PULLUDEN, &regs->spi0_d0); +} + +void am335x_pinmux_uart3(void) +{ + // UART3_RXD + writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_cs1); + // UART3_TXD + writel(MODE(1) | PULLUDEN, &regs->ecap0_in_pwm0_out); +} + +void am335x_pinmux_uart4(void) +{ + // UART4_RXD + writel(MODE(6) | PULLUP_EN | RXACTIVE, &regs->gpmc_wait0); + // UART4_TXD + writel(MODE(6) | PULLUDEN, &regs->gpmc_wpn); +} + +void am335x_pinmux_uart5(void) +{ + // UART5_RXD + writel(MODE(4) | PULLUP_EN | RXACTIVE, &regs->lcd_data9); + // UART5_TXD + writel(MODE(4) | PULLUDEN, &regs->lcd_data8); +} + +void am335x_pinmux_mmc0(int cd, int sk_evm) +{ + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat0); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat1); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat2); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat3); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_clk); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_cmd); + if (!sk_evm) { + // MMC0_WP + writel(MODE(4) | RXACTIVE, &regs->mcasp0_aclkr); + } + if (cd) { + // MMC0_CD + writel(MODE(5) | RXACTIVE | PULLUP_EN, &regs->spi0_cs1); + } +} + +void am335x_pinmux_mmc1(void) +{ + // MMC1_DAT0 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad0); + // MMC1_DAT1 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad1); + // MMC1_DAT2 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad2); + // MMC1_DAT3 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad3); + // MMC1_CLK + writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn1); + // MMC1_CMD + writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn2); + // MMC1_WP + writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn0); + // MMC1_CD + writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_advn_ale); +} + +void am335x_pinmux_i2c0(void) +{ + writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_sda); + writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_scl); +} + +void am335x_pinmux_i2c1(void) +{ + // I2C_DATA + writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_d1); + // I2C_SCLK + writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_cs0); +} + +void am335x_pinmux_spi0(void) +{ + writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_sclk); + writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_d0); + writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_d1); + writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_cs0); +} + +void am335x_pinmux_gpio0_7(void) +{ + writel(MODE(7) | PULLUDEN, &regs->ecap0_in_pwm0_out); +} + +void am335x_pinmux_rgmii1(void) +{ + writel(MODE(2), &regs->mii1_txen); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxdv); + writel(MODE(2), &regs->mii1_txd0); + writel(MODE(2), &regs->mii1_txd1); + writel(MODE(2), &regs->mii1_txd2); + writel(MODE(2), &regs->mii1_txd3); + writel(MODE(2), &regs->mii1_txclk); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxclk); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd0); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd1); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd2); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd3); +} + +void am335x_pinmux_mii1(void) +{ + writel(MODE(0) | RXACTIVE, &regs->mii1_rxerr); + writel(MODE(0), &regs->mii1_txen); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxdv); + writel(MODE(0), &regs->mii1_txd0); + writel(MODE(0), &regs->mii1_txd1); + writel(MODE(0), &regs->mii1_txd2); + writel(MODE(0), &regs->mii1_txd3); + writel(MODE(0) | RXACTIVE, &regs->mii1_txclk); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxclk); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd0); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd1); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd2); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd3); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mdio_data); + writel(MODE(0) | PULLUP_EN, &regs->mdio_clk); +} + +void am335x_pinmux_nand(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad0); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad1); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad2); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad3); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad4); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad5); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad6); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad7); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->gpmc_wait0); + writel(MODE(7) | PULLUP_EN | RXACTIVE, &regs->gpmc_wpn); + writel(MODE(0) | PULLUDEN, &regs->gpmc_csn0); + writel(MODE(0) | PULLUDEN, &regs->gpmc_advn_ale); + writel(MODE(0) | PULLUDEN, &regs->gpmc_oen_ren); + writel(MODE(0) | PULLUDEN, &regs->gpmc_wen); + writel(MODE(0) | PULLUDEN, &regs->gpmc_be0n_cle); +} diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h new file mode 100644 index 0000000..69c1459 --- /dev/null +++ b/src/cpu/ti/am335x/pinmux.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_TI_AM335X_PINMUX_H +#define __CPU_TI_AM335X_PINMUX_H + +#include <stdint.h> + +// PAD Control Fields +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLDOWN_EN (0x0 << 4) // Pull down +#define PULLUP_EN (0x1 << 4) // Pull up +#define PULLUDEN (0x0 << 3) // Pull up enabled +#define PULLUDDIS (0x1 << 3) // Pull up disabled +#define MODE(val) val + +void am335x_pinmux_uart0(void); +void am335x_pinmux_uart1(void); +void am335x_pinmux_uart2(void); +void am335x_pinmux_uart3(void); +void am335x_pinmux_uart4(void); +void am335x_pinmux_uart5(void); + +void am335x_pinmux_mmc0(int cd, int sk_evm); +void am335x_pinmux_mmc1(void); + +void am335x_pinmux_i2c0(void); +void am335x_pinmux_i2c1(void); + +void am335x_pinmux_spi0(void); + +void am335x_pinmux_gpio0_7(void); + +void am335x_pinmux_rgmii1(void); +void am335x_pinmux_mii1(void); + +void am335x_pinmux_nand(void); + +#define AM335X_PINMUX_REG_ADDR 0x44e10000 + +struct am335x_pinmux_regs { + uint32_t gpmc_ad0; + uint32_t gpmc_ad1; + uint32_t gpmc_ad2; + uint32_t gpmc_ad3; + uint32_t gpmc_ad4; + uint32_t gpmc_ad5; + uint32_t gpmc_ad6; + uint32_t gpmc_ad7; + uint32_t gpmc_ad8; + uint32_t gpmc_ad9; + uint32_t gpmc_ad10; + uint32_t gpmc_ad11; + uint32_t gpmc_ad12; + uint32_t gpmc_ad13; + uint32_t gpmc_ad14; + uint32_t gpmc_ad15; + uint32_t gpmc_a0; + uint32_t gpmc_a1; + uint32_t gpmc_a2; + uint32_t gpmc_a3; + uint32_t gpmc_a4; + uint32_t gpmc_a5; + uint32_t gpmc_a6; + uint32_t gpmc_a7; + uint32_t gpmc_a8; + uint32_t gpmc_a9; + uint32_t gpmc_a10; + uint32_t gpmc_a11; + uint32_t gpmc_wait0; + uint32_t gpmc_wpn; + uint32_t gpmc_be1n; + uint32_t gpmc_csn0; + uint32_t gpmc_csn1; + uint32_t gpmc_csn2; + uint32_t gpmc_csn3; + uint32_t gpmc_clk; + uint32_t gpmc_advn_ale; + uint32_t gpmc_oen_ren; + uint32_t gpmc_wen; + uint32_t gpmc_be0n_cle; + uint32_t lcd_data0; + uint32_t lcd_data1; + uint32_t lcd_data2; + uint32_t lcd_data3; + uint32_t lcd_data4; + uint32_t lcd_data5; + uint32_t lcd_data6; + uint32_t lcd_data7; + uint32_t lcd_data8; + uint32_t lcd_data9; + uint32_t lcd_data10; + uint32_t lcd_data11; + uint32_t lcd_data12; + uint32_t lcd_data13; + uint32_t lcd_data14; + uint32_t lcd_data15; + uint32_t lcd_vsync; + uint32_t lcd_hsync; + uint32_t lcd_pclk; + uint32_t lcd_ac_bias_en; + uint32_t mmc0_dat3; + uint32_t mmc0_dat2; + uint32_t mmc0_dat1; + uint32_t mmc0_dat0; + uint32_t mmc0_clk; + uint32_t mmc0_cmd; + uint32_t mii1_col; + uint32_t mii1_crs; + uint32_t mii1_rxerr; + uint32_t mii1_txen; + uint32_t mii1_rxdv; + uint32_t mii1_txd3; + uint32_t mii1_txd2; + uint32_t mii1_txd1; + uint32_t mii1_txd0; + uint32_t mii1_txclk; + uint32_t mii1_rxclk; + uint32_t mii1_rxd3; + uint32_t mii1_rxd2; + uint32_t mii1_rxd1; + uint32_t mii1_rxd0; + uint32_t rmii1_refclk; + uint32_t mdio_data; + uint32_t mdio_clk; + uint32_t spi0_sclk; + uint32_t spi0_d0; + uint32_t spi0_d1; + uint32_t spi0_cs0; + uint32_t spi0_cs1; + uint32_t ecap0_in_pwm0_out; + uint32_t uart0_ctsn; + uint32_t uart0_rtsn; + uint32_t uart0_rxd; + uint32_t uart0_txd; + uint32_t uart1_ctsn; + uint32_t uart1_rtsn; + uint32_t uart1_rxd; + uint32_t uart1_txd; + uint32_t i2c0_sda; + uint32_t i2c0_scl; + uint32_t mcasp0_aclkx; + uint32_t mcasp0_fsx; + uint32_t mcasp0_axr0; + uint32_t mcasp0_ahclkr; + uint32_t mcasp0_aclkr; + uint32_t mcasp0_fsr; + uint32_t mcasp0_axr1; + uint32_t mcasp0_ahclkx; + uint32_t xdma_event_intr0; + uint32_t xdma_event_intr1; + uint32_t nresetin_out; + uint32_t porz; + uint32_t nnmi; + uint32_t osc0_in; + uint32_t osc0_out; + uint32_t rsvd1; + uint32_t tms; + uint32_t tdi; + uint32_t tdo; + uint32_t tck; + uint32_t ntrst; + uint32_t emu0; + uint32_t emu1; + uint32_t osc1_in; + uint32_t osc1_out; + uint32_t pmic_power_en; + uint32_t rtc_porz; + uint32_t rsvd2; + uint32_t ext_wakeup; + uint32_t enz_kaldo_1p8v; + uint32_t usb0_dm; + uint32_t usb0_dp; + uint32_t usb0_ce; + uint32_t usb0_id; + uint32_t usb0_vbus; + uint32_t usb0_drvvbus; + uint32_t usb1_dm; + uint32_t usb1_dp; + uint32_t usb1_ce; + uint32_t usb1_id; + uint32_t usb1_vbus; + uint32_t usb1_drvvbus; + uint32_t ddr_resetn; + uint32_t ddr_csn0; + uint32_t ddr_cke; + uint32_t ddr_ck; + uint32_t ddr_nck; + uint32_t ddr_casn; + uint32_t ddr_rasn; + uint32_t ddr_wen; + uint32_t ddr_ba0; + uint32_t ddr_ba1; + uint32_t ddr_ba2; + uint32_t ddr_a0; + uint32_t ddr_a1; + uint32_t ddr_a2; + uint32_t ddr_a3; + uint32_t ddr_a4; + uint32_t ddr_a5; + uint32_t ddr_a6; + uint32_t ddr_a7; + uint32_t ddr_a8; + uint32_t ddr_a9; + uint32_t ddr_a10; + uint32_t ddr_a11; + uint32_t ddr_a12; + uint32_t ddr_a13; + uint32_t ddr_a14; + uint32_t ddr_a15; + uint32_t ddr_odt; + uint32_t ddr_d0; + uint32_t ddr_d1; + uint32_t ddr_d2; + uint32_t ddr_d3; + uint32_t ddr_d4; + uint32_t ddr_d5; + uint32_t ddr_d6; + uint32_t ddr_d7; + uint32_t ddr_d8; + uint32_t ddr_d9; + uint32_t ddr_d10; + uint32_t ddr_d11; + uint32_t ddr_d12; + uint32_t ddr_d13; + uint32_t ddr_d14; + uint32_t ddr_d15; + uint32_t ddr_dqm0; + uint32_t ddr_dqm1; + uint32_t ddr_dqs0; + uint32_t ddr_dqsn0; + uint32_t ddr_dqs1; + uint32_t ddr_dqsn1; + uint32_t ddr_vref; + uint32_t ddr_vtp; + uint32_t ddr_strben0; + uint32_t ddr_strben1; + uint32_t ain7; + uint32_t ain6; + uint32_t ain5; + uint32_t ain4; + uint32_t ain3; + uint32_t ain2; + uint32_t ain1; + uint32_t ain0; + uint32_t vrefp; + uint32_t vrefn; +}; + +#endif

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Patch set updated for coreboot: 8b2dee9 am335x: Add pinmux support based on the functions in U-Boot
by Stefan Reinauer 17 Jun '13

17 Jun '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3489 -gerrit commit 8b2dee9e5ea9f8798bc70fb5d9b5de32d85cb86e Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jun 17 01:17:55 2013 -0700 am335x: Add pinmux support based on the functions in U-Boot I was unable to find documentaiton that said what mode numbers correspond to what functionality, so I translated over what U-Boot does. Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 1 + src/cpu/ti/am335x/pinmux.c | 190 +++++++++++++++++++++++++++++ src/cpu/ti/am335x/pinmux.h | 268 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 459 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 9279c69..e1220fa 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += dmtimer.c bootblock-y += nand.c +bootblock-y += pinmux.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += nand.c diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c new file mode 100644 index 0000000..292865a --- /dev/null +++ b/src/cpu/ti/am335x/pinmux.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "pinmux.h" + +#include <arch/io.h> +#include <config.h> + +static struct am335x_pinmux_regs *regs = + (struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR; + +void am335x_pinmux_uart0(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart0_rxd); + writel(MODE(0) | PULLUDEN, &regs->uart0_txd); +} + +void am335x_pinmux_uart1(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart1_rxd); + writel(MODE(0) | PULLUDEN, &regs->uart1_txd); +} + +void am335x_pinmux_uart2(void) +{ + // UART2_RXD + writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_sclk); + // UART2_TXD + writel(MODE(1) | PULLUDEN, &regs->spi0_d0); +} + +void am335x_pinmux_uart3(void) +{ + // UART3_RXD + writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_cs1); + // UART3_TXD + writel(MODE(1) | PULLUDEN, &regs->ecap0_in_pwm0_out); +} + +void am335x_pinmux_uart4(void) +{ + // UART4_RXD + writel(MODE(6) | PULLUP_EN | RXACTIVE, &regs->gpmc_wait0); + // UART4_TXD + writel(MODE(6) | PULLUDEN, &regs->gpmc_wpn); +} + +void am335x_pinmux_uart5(void) +{ + // UART5_RXD + writel(MODE(4) | PULLUP_EN | RXACTIVE, &regs->lcd_data9); + // UART5_TXD + writel(MODE(4) | PULLUDEN, &regs->lcd_data8); +} + +void am335x_pinmux_mmc0(int cd, int sk_evm) +{ + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat0); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat1); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat2); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat3); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_clk); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_cmd); + if (!sk_evm) { + // MMC0_WP + writel(MODE(4) | RXACTIVE, &regs->mcasp0_aclkr); + } + if (cd) { + // MMC0_CD + writel(MODE(5) | RXACTIVE | PULLUP_EN, &regs->spi0_cs1); + } +} + +void am335x_pinmux_mmc1(void) +{ + // MMC1_DAT0 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad0); + // MMC1_DAT1 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad1); + // MMC1_DAT2 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad2); + // MMC1_DAT3 + writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad3); + // MMC1_CLK + writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn1); + // MMC1_CMD + writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn2); + // MMC1_WP + writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn0); + // MMC1_CD + writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_advn_ale); +} + +void am335x_pinmux_i2c0(void) +{ + writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_sda); + writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_scl); +} + +void am335x_pinmux_i2c1(void) +{ + // I2C_DATA + writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_d1); + // I2C_SCLK + writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_cs0); +} + +void am335x_pinmux_spi0(void) +{ + writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_sclk); + writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_d0); + writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_d1); + writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_cs0); +} + +void am335x_pinmux_gpio0_7(void) +{ + writel(MODE(7) | PULLUDEN, &regs->ecap0_in_pwm0_out); +} + +void am335x_pinmux_rgmii1(void) +{ + writel(MODE(2), &regs->mii1_txen); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxdv); + writel(MODE(2), &regs->mii1_txd0); + writel(MODE(2), &regs->mii1_txd1); + writel(MODE(2), &regs->mii1_txd2); + writel(MODE(2), &regs->mii1_txd3); + writel(MODE(2), &regs->mii1_txclk); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxclk); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd0); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd1); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd2); + writel(MODE(2) | RXACTIVE, &regs->mii1_rxd3); +} + +void am335x_pinmux_mii1(void) +{ + writel(MODE(0) | RXACTIVE, &regs->mii1_rxerr); + writel(MODE(0), &regs->mii1_txen); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxdv); + writel(MODE(0), &regs->mii1_txd0); + writel(MODE(0), &regs->mii1_txd1); + writel(MODE(0), &regs->mii1_txd2); + writel(MODE(0), &regs->mii1_txd3); + writel(MODE(0) | RXACTIVE, &regs->mii1_txclk); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxclk); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd0); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd1); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd2); + writel(MODE(0) | RXACTIVE, &regs->mii1_rxd3); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mdio_data); + writel(MODE(0) | PULLUP_EN, &regs->mdio_clk); +} + +void am335x_pinmux_nand(void) +{ + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad0); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad1); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad2); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad3); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad4); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad5); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad6); + writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad7); + writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->gpmc_wait0); + writel(MODE(7) | PULLUP_EN | RXACTIVE, &regs->gpmc_wpn); + writel(MODE(0) | PULLUDEN, &regs->gpmc_csn0); + writel(MODE(0) | PULLUDEN, &regs->gpmc_advn_ale); + writel(MODE(0) | PULLUDEN, &regs->gpmc_oen_ren); + writel(MODE(0) | PULLUDEN, &regs->gpmc_wen); + writel(MODE(0) | PULLUDEN, &regs->gpmc_be0n_cle); +} diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h new file mode 100644 index 0000000..69c1459 --- /dev/null +++ b/src/cpu/ti/am335x/pinmux.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_TI_AM335X_PINMUX_H +#define __CPU_TI_AM335X_PINMUX_H + +#include <stdint.h> + +// PAD Control Fields +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLDOWN_EN (0x0 << 4) // Pull down +#define PULLUP_EN (0x1 << 4) // Pull up +#define PULLUDEN (0x0 << 3) // Pull up enabled +#define PULLUDDIS (0x1 << 3) // Pull up disabled +#define MODE(val) val + +void am335x_pinmux_uart0(void); +void am335x_pinmux_uart1(void); +void am335x_pinmux_uart2(void); +void am335x_pinmux_uart3(void); +void am335x_pinmux_uart4(void); +void am335x_pinmux_uart5(void); + +void am335x_pinmux_mmc0(int cd, int sk_evm); +void am335x_pinmux_mmc1(void); + +void am335x_pinmux_i2c0(void); +void am335x_pinmux_i2c1(void); + +void am335x_pinmux_spi0(void); + +void am335x_pinmux_gpio0_7(void); + +void am335x_pinmux_rgmii1(void); +void am335x_pinmux_mii1(void); + +void am335x_pinmux_nand(void); + +#define AM335X_PINMUX_REG_ADDR 0x44e10000 + +struct am335x_pinmux_regs { + uint32_t gpmc_ad0; + uint32_t gpmc_ad1; + uint32_t gpmc_ad2; + uint32_t gpmc_ad3; + uint32_t gpmc_ad4; + uint32_t gpmc_ad5; + uint32_t gpmc_ad6; + uint32_t gpmc_ad7; + uint32_t gpmc_ad8; + uint32_t gpmc_ad9; + uint32_t gpmc_ad10; + uint32_t gpmc_ad11; + uint32_t gpmc_ad12; + uint32_t gpmc_ad13; + uint32_t gpmc_ad14; + uint32_t gpmc_ad15; + uint32_t gpmc_a0; + uint32_t gpmc_a1; + uint32_t gpmc_a2; + uint32_t gpmc_a3; + uint32_t gpmc_a4; + uint32_t gpmc_a5; + uint32_t gpmc_a6; + uint32_t gpmc_a7; + uint32_t gpmc_a8; + uint32_t gpmc_a9; + uint32_t gpmc_a10; + uint32_t gpmc_a11; + uint32_t gpmc_wait0; + uint32_t gpmc_wpn; + uint32_t gpmc_be1n; + uint32_t gpmc_csn0; + uint32_t gpmc_csn1; + uint32_t gpmc_csn2; + uint32_t gpmc_csn3; + uint32_t gpmc_clk; + uint32_t gpmc_advn_ale; + uint32_t gpmc_oen_ren; + uint32_t gpmc_wen; + uint32_t gpmc_be0n_cle; + uint32_t lcd_data0; + uint32_t lcd_data1; + uint32_t lcd_data2; + uint32_t lcd_data3; + uint32_t lcd_data4; + uint32_t lcd_data5; + uint32_t lcd_data6; + uint32_t lcd_data7; + uint32_t lcd_data8; + uint32_t lcd_data9; + uint32_t lcd_data10; + uint32_t lcd_data11; + uint32_t lcd_data12; + uint32_t lcd_data13; + uint32_t lcd_data14; + uint32_t lcd_data15; + uint32_t lcd_vsync; + uint32_t lcd_hsync; + uint32_t lcd_pclk; + uint32_t lcd_ac_bias_en; + uint32_t mmc0_dat3; + uint32_t mmc0_dat2; + uint32_t mmc0_dat1; + uint32_t mmc0_dat0; + uint32_t mmc0_clk; + uint32_t mmc0_cmd; + uint32_t mii1_col; + uint32_t mii1_crs; + uint32_t mii1_rxerr; + uint32_t mii1_txen; + uint32_t mii1_rxdv; + uint32_t mii1_txd3; + uint32_t mii1_txd2; + uint32_t mii1_txd1; + uint32_t mii1_txd0; + uint32_t mii1_txclk; + uint32_t mii1_rxclk; + uint32_t mii1_rxd3; + uint32_t mii1_rxd2; + uint32_t mii1_rxd1; + uint32_t mii1_rxd0; + uint32_t rmii1_refclk; + uint32_t mdio_data; + uint32_t mdio_clk; + uint32_t spi0_sclk; + uint32_t spi0_d0; + uint32_t spi0_d1; + uint32_t spi0_cs0; + uint32_t spi0_cs1; + uint32_t ecap0_in_pwm0_out; + uint32_t uart0_ctsn; + uint32_t uart0_rtsn; + uint32_t uart0_rxd; + uint32_t uart0_txd; + uint32_t uart1_ctsn; + uint32_t uart1_rtsn; + uint32_t uart1_rxd; + uint32_t uart1_txd; + uint32_t i2c0_sda; + uint32_t i2c0_scl; + uint32_t mcasp0_aclkx; + uint32_t mcasp0_fsx; + uint32_t mcasp0_axr0; + uint32_t mcasp0_ahclkr; + uint32_t mcasp0_aclkr; + uint32_t mcasp0_fsr; + uint32_t mcasp0_axr1; + uint32_t mcasp0_ahclkx; + uint32_t xdma_event_intr0; + uint32_t xdma_event_intr1; + uint32_t nresetin_out; + uint32_t porz; + uint32_t nnmi; + uint32_t osc0_in; + uint32_t osc0_out; + uint32_t rsvd1; + uint32_t tms; + uint32_t tdi; + uint32_t tdo; + uint32_t tck; + uint32_t ntrst; + uint32_t emu0; + uint32_t emu1; + uint32_t osc1_in; + uint32_t osc1_out; + uint32_t pmic_power_en; + uint32_t rtc_porz; + uint32_t rsvd2; + uint32_t ext_wakeup; + uint32_t enz_kaldo_1p8v; + uint32_t usb0_dm; + uint32_t usb0_dp; + uint32_t usb0_ce; + uint32_t usb0_id; + uint32_t usb0_vbus; + uint32_t usb0_drvvbus; + uint32_t usb1_dm; + uint32_t usb1_dp; + uint32_t usb1_ce; + uint32_t usb1_id; + uint32_t usb1_vbus; + uint32_t usb1_drvvbus; + uint32_t ddr_resetn; + uint32_t ddr_csn0; + uint32_t ddr_cke; + uint32_t ddr_ck; + uint32_t ddr_nck; + uint32_t ddr_casn; + uint32_t ddr_rasn; + uint32_t ddr_wen; + uint32_t ddr_ba0; + uint32_t ddr_ba1; + uint32_t ddr_ba2; + uint32_t ddr_a0; + uint32_t ddr_a1; + uint32_t ddr_a2; + uint32_t ddr_a3; + uint32_t ddr_a4; + uint32_t ddr_a5; + uint32_t ddr_a6; + uint32_t ddr_a7; + uint32_t ddr_a8; + uint32_t ddr_a9; + uint32_t ddr_a10; + uint32_t ddr_a11; + uint32_t ddr_a12; + uint32_t ddr_a13; + uint32_t ddr_a14; + uint32_t ddr_a15; + uint32_t ddr_odt; + uint32_t ddr_d0; + uint32_t ddr_d1; + uint32_t ddr_d2; + uint32_t ddr_d3; + uint32_t ddr_d4; + uint32_t ddr_d5; + uint32_t ddr_d6; + uint32_t ddr_d7; + uint32_t ddr_d8; + uint32_t ddr_d9; + uint32_t ddr_d10; + uint32_t ddr_d11; + uint32_t ddr_d12; + uint32_t ddr_d13; + uint32_t ddr_d14; + uint32_t ddr_d15; + uint32_t ddr_dqm0; + uint32_t ddr_dqm1; + uint32_t ddr_dqs0; + uint32_t ddr_dqsn0; + uint32_t ddr_dqs1; + uint32_t ddr_dqsn1; + uint32_t ddr_vref; + uint32_t ddr_vtp; + uint32_t ddr_strben0; + uint32_t ddr_strben1; + uint32_t ain7; + uint32_t ain6; + uint32_t ain5; + uint32_t ain4; + uint32_t ain3; + uint32_t ain2; + uint32_t ain1; + uint32_t ain0; + uint32_t vrefp; + uint32_t vrefn; +}; + +#endif

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Patch merged into coreboot/master: 56892fc AMD southbridges: Move HAVE_HARD_RESET
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 56892fc475d61a5e6bfb912098dca8975ecf9b94 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 16 17:12:37 2013 +0300 AMD southbridges: Move HAVE_HARD_RESET All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3486 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/3486 for details. -gerrit

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Patch merged into coreboot/master: d715105 AMD: Use same sourcecode for reset in romstage as ramstage
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit d715105d30c2b37a63d783eda45166505b483e7d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 17 01:09:07 2013 +0300 AMD: Use same sourcecode for reset in romstage as ramstage Confusingly, romstage compiled in different copy of soft_reset() than ramstage. Use source in reset.c for both. Change-Id: I2e4b6d1b89c859c7cf5d9e9c8f7748b43d369775 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3487 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/3487 for details. -gerrit

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Patch merged into coreboot/master: 397ca61 AMD boards: Clean use of Kconfig options
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 397ca6176c70f5d8c1db7cdcb0b3dedaa74c3cbd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 16 17:30:29 2013 +0300 AMD boards: Clean use of Kconfig options The chip component is unconditionally selected for the mainboard so these uses are superfluous. Change-Id: I84b053ab47f7b1f68e88d968cf305e24bc95f4da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3485 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/3485 for details. -gerrit

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Patch merged into coreboot/master: 0fd6a65 Add support for XHCI (USB 3.0)
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 0fd6a65243e184e4cdef6c04e20f5d4aeab514aa Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jun 13 17:30:48 2013 -0600 Add support for XHCI (USB 3.0) CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the amd/parmer and asus/f2a85-m mainboards. The XHCI ports on amd/thatcher are not wired to USB jacks so always disable the flags. This was tested on amd/parmer using a USB 3.0 thumbdrive. Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3465 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3465 for details. -gerrit

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Patch merged into coreboot/master: 1fa1904 AMD Hudson: Add config option to enable XHCI
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 1fa1904e53cd009b1031948f34caa38ae9bcf23f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Jun 14 07:11:40 2013 -0600 AMD Hudson: Add config option to enable XHCI To have USB 3.0 support the XHCI controller needs to be enabled and the xhci.bin firmware needs to be added to CBFS. Change-Id: I0b641b30b67163b7dc73ee7ae67efe678e11c000 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3464 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3464 for details. -gerrit

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Patch merged into coreboot/master: 0b2ee93 pnp: Remove now plain wrappers for default PnP functions
by gerrit＠coreboot.org 17 Jun '13

17 Jun '13

the following patch was just integrated into master: commit 0b2ee9391079a5092eb99dce764e3836eeb92cd9 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jun 15 19:58:35 2013 +0200 pnp: Remove now plain wrappers for default PnP functions After removing the enter()/exit() functions for configuration mode, most wrappers for our standard PnP functions just call the underlying default implementation. Remove those with a little cocci: @ op_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; type device_t; identifier dev; @@ static void op(device_t dev) { pnp_op(dev); } @@ identifier op_match.op; @@ -op(...) {...} /* Three rules to match the alignment, hmmp... */ @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .set_resources = op, + .set_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable_resources = op, + .enable_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable = op, + .enable = pnp_op, }; Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3483 for details. -gerrit

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coreboot-gerrit June 2013