coreboot-gerrit December 2013

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Patch set updated for coreboot: 69d88ad Calculate transcoder flags based on pipe config
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4402 -gerrit commit 69d88adb7f2fa400f4664b9ea44f65fea1ee15d0 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 30 12:41:08 2013 -0700 Calculate transcoder flags based on pipe config Works fine with all three panels with the change of 6 bits per color. Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e Reviewed-on: https://gerrit.chromium.org/gerrit/63762 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/gma/i915.h | 24 +++++++++++++ src/drivers/intel/gma/i915_reg.h | 1 + src/drivers/intel/gma/intel_ddi.c | 66 ++++++++++++++++++++++++++++++++++++ src/lib/edid.c | 1 + src/mainboard/google/slippy/gma.c | 12 +++++-- src/mainboard/google/slippy/i915io.c | 2 +- 6 files changed, 103 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 62fe023..1aed2bf 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -40,6 +40,22 @@ #define PRB0_START 0x02038 #define PRB0_CTL 0x0203c +enum port { + PORT_A = 0, + PORT_B, + PORT_C, + PORT_D, + PORT_E, + I915_NUM_PORTS +}; + +enum pipe { + PIPE_A = 0, + PIPE_B, + PIPE_C, + I915_NUM_PIPES +}; + /* debug enums. These are for printks that, due to their place in the * middle of graphics device IO, might change timing. Use with care * or not at all. @@ -143,6 +159,7 @@ struct intel_dp { u32 pipesrc; u32 stride; struct intel_dp_m_n m_n; + u32 flags; }; /* we may yet need these. */ @@ -197,3 +214,10 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel, unsigned int pixel_clock, unsigned int link_clock, struct intel_dp_m_n *m_n); + +u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, + enum port port, + enum pipe pipe, + int type, + int lane_count, + int pf_sz); diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 27a3d2b..d0c8c85 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -4554,6 +4554,7 @@ #define DDI_BUF_EMP_MASK (0xf<<24) #define DDI_BUF_IS_IDLE (1<<7) #define DDI_A_4_LANES (1<<4) +#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) #define DDI_PORT_WIDTH_X1 (0<<1) #define DDI_PORT_WIDTH_X2 (1<<1) #define DDI_PORT_WIDTH_X4 (3<<1) diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 220bd47..f1a40f1 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -157,3 +157,69 @@ void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port) udelay(600); } + +u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, + enum port port, + enum pipe pipe, + int type, + int lane_count, + int pf_sz) +{ + u32 temp; + + temp = TRANS_DDI_FUNC_ENABLE; + temp |= TRANS_DDI_SELECT_PORT(port); + + switch (pipe_bpp) { + case 18: + temp |= TRANS_DDI_BPC_6; + break; + case 24: + temp |= TRANS_DDI_BPC_8; + break; + case 30: + temp |= TRANS_DDI_BPC_10; + break; + case 36: + temp |= TRANS_DDI_BPC_12; + break; + default: + printk(BIOS_ERR, "Invalid pipe_bpp: %d, *** Initialization will not succeed *** \n", pipe_bpp); + } + + if (port == PORT_A) { + switch (pipe) { + case PIPE_A: + if (pf_sz) + temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; + else + temp |= TRANS_DDI_EDP_INPUT_A_ON; + break; + case PIPE_B: + temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; + break; + case PIPE_C: + temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; + break; + default: + printk(BIOS_ERR, "Invalid pipe %d\n", pipe); + } + } + + /* We need to check for TRANS_DDI_PVSYNC and TRANS_DDI_PHSYNC -- How? */ + + if (type == INTEL_OUTPUT_HDMI) { + /* Need to understand when to set TRANS_DDI_MODE_SELECT_HDMI / TRANS_DDI_MODE_SELECT_DVI */ + } else if (type == INTEL_OUTPUT_ANALOG) { + /* Set TRANS_DDI_MODE_SELECT_FDI with lane_count */ + } else if (type == INTEL_OUTPUT_DISPLAYPORT || + type == INTEL_OUTPUT_EDP) { + temp |= TRANS_DDI_MODE_SELECT_DP_SST; + + temp |= DDI_PORT_WIDTH(lane_count); + } else { + printk(BIOS_ERR, "Invalid type %d for pipe\n", type); + } + + return temp; +} diff --git a/src/lib/edid.c b/src/lib/edid.c index dd7c46a..b2bd9b7 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -475,6 +475,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) * we have yet to see a case where that will happen. */ out->bpp = 32; + out->x_resolution = ALIGN(out->ha * ((out->bpp + 7) / 8),64) / (out->bpp/8); out->y_resolution = out->va; out->bytes_per_line = ALIGN(out->ha * ((out->bpp + 7) / 8),64); diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index 52a7b0b..99dcbc5 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -288,6 +288,13 @@ void dp_init_dim_regs(struct intel_dp *dp) dp->pfa_sz = (edid->ha << 16) | (edid->va); + dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */ + dp->port, + dp->pipe, + dp->type, + dp->lane_count, + dp->pfa_sz); + intel_dp_compute_m_n(dp->bpp, dp->lane_count, dp->edid.pixel_clock, @@ -310,6 +317,7 @@ void dp_init_dim_regs(struct intel_dp *dp) printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m); printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m); printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n); + printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags); } int intel_dp_bw_code_to_link_rate(u8 link_bw); @@ -363,8 +371,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, dp->panel_power_down_delay = 600; dp->panel_power_up_delay = 200; dp->panel_power_cycle_delay = 600; - dp->pipe = 0; - dp->port = 0; + dp->pipe = PIPE_A; + dp->port = PORT_A; dp->clock = 160000; dp->bpp = 32; dp->type = INTEL_OUTPUT_EDP; diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c index c1e0547..e3f7f30 100644 --- a/src/mainboard/google/slippy/i915io.c +++ b/src/mainboard/google/slippy/i915io.c @@ -151,7 +151,7 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD"); io_i915_write32(0x00230000,TRANS_DDI_FUNC_CTL_EDP); io_i915_write32(0x00000010,0x7f008); - io_i915_write32(0x82234000,TRANS_DDI_FUNC_CTL_EDP); + io_i915_write32(dp->flags,TRANS_DDI_FUNC_CTL_EDP); io_i915_write32(0x80000010,0x7f008); intel_dp_wait_panel_power_control(0xabcd000a);

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Patch set updated for coreboot: 77aab14 Add cpu transcoder attribute to intel dp
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4422 -gerrit commit 77aab14ae3647bead5c5d2babdb7fa209e5e446b Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 31 16:47:31 2013 -0700 Add cpu transcoder attribute to intel dp Also, used this attribute in the calculation of htotal and other registers Added intel_dp_* functions for m,n registers and dimension register calculations Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a Reviewed-on: https://gerrit.chromium.org/gerrit/64001 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/gma/i915.h | 14 ++++++++++++++ src/drivers/intel/gma/i915_reg.h | 3 +++ src/drivers/intel/gma/intel_ddi.c | 8 ++++++++ src/drivers/intel/gma/intel_dp.c | 22 ++++++++++++++++++++++ src/mainboard/google/slippy/gma.c | 3 +++ src/mainboard/google/slippy/i915io.c | 27 ++++++--------------------- 6 files changed, 56 insertions(+), 21 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 1aed2bf..12a7ee0 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -56,6 +56,13 @@ enum pipe { I915_NUM_PIPES }; +enum transcoder { + TRANSCODER_A = 0, + TRANSCODER_B, + TRANSCODER_C, + TRANSCODER_EDP = 0xF, +}; + /* debug enums. These are for printks that, due to their place in the * middle of graphics device IO, might change timing. Use with care * or not at all. @@ -160,6 +167,7 @@ struct intel_dp { u32 stride; struct intel_dp_m_n m_n; u32 flags; + u32 transcoder; }; /* we may yet need these. */ @@ -221,3 +229,9 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, int type, int lane_count, int pf_sz); + +enum transcoder intel_ddi_get_transcoder(enum port port, + enum pipe pipe); + +void intel_dp_set_m_n_regs(struct intel_dp *intel_dp); +void intel_dp_set_resolution(struct intel_dp *intel_dp); diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index d0c8c85..8c08d9f 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -3839,6 +3839,9 @@ #define _TRANSACONF 0xf0008 #define _TRANSBCONF 0xf1008 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) +#define _PCH_TRANSACONF 0xf0008 +#define _PCH_TRANSBCONF 0xf1008 +#define PCH_TRANSCONF(plane) _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF) #define TRANS_DISABLE (0<<31) #define TRANS_ENABLE (1<<31) #define TRANS_STATE_MASK (1<<30) diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index f1a40f1..ff8ad4c 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -223,3 +223,11 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, return temp; } + +enum transcoder intel_ddi_get_transcoder(enum port port, + enum pipe pipe) +{ + if (port == PORT_A) + return TRANSCODER_EDP; + return (enum transcoder)pipe; +} diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c index 0def771..419e49e 100644 --- a/src/drivers/intel/gma/intel_dp.c +++ b/src/drivers/intel/gma/intel_dp.c @@ -1739,3 +1739,25 @@ intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread) return 1; } +void intel_dp_set_m_n_regs(struct intel_dp *intel_dp) +{ + io_i915_write32(0x7e4a0000, PIPE_DATA_M1(intel_dp->transcoder)); + /* io_i915_write32(0x00800000,0x6f034); */ + /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important. + However, with our formula we always see values 0x7e43yyyy (1366 panel) and + 0x7e42yyy (1280 panel) */ + /* io_i915_write32(TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m,PIPE_DATA_M1(intel_dp->transcoder)); */ + io_i915_write32(intel_dp->m_n.gmch_n, PIPE_DATA_N1(intel_dp->transcoder)); + io_i915_write32(intel_dp->m_n.link_m, PIPE_LINK_M1(intel_dp->transcoder)); + io_i915_write32(intel_dp->m_n.link_n, PIPE_LINK_N1(intel_dp->transcoder)); +} + +void intel_dp_set_resolution(struct intel_dp *intel_dp) +{ + io_i915_write32(intel_dp->htotal, HTOTAL(intel_dp->transcoder)); + io_i915_write32(intel_dp->hblank, HBLANK(intel_dp->transcoder)); + io_i915_write32(intel_dp->hsync, HSYNC(intel_dp->transcoder)); + io_i915_write32(intel_dp->vtotal, VTOTAL(intel_dp->transcoder)); + io_i915_write32(intel_dp->vblank, VBLANK(intel_dp->transcoder)); + io_i915_write32(intel_dp->vsync, VSYNC(intel_dp->transcoder)); +} diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index 99dcbc5..026bba1 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -295,6 +295,9 @@ void dp_init_dim_regs(struct intel_dp *dp) dp->lane_count, dp->pfa_sz); + dp->transcoder = intel_ddi_get_transcoder(dp->port, + dp->pipe); + intel_dp_compute_m_n(dp->bpp, dp->lane_count, dp->edid.pixel_clock, diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c index e3f7f30..cf57430 100644 --- a/src/mainboard/google/slippy/i915io.c +++ b/src/mainboard/google/slippy/i915io.c @@ -115,27 +115,12 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD"); unpack_aux(auxout, &msg[0], 4); intel_dp_aux_ch(dp, msg, 4, auxin, 0); - /* undocumented. */ - io_i915_write32(0x7e4a0000,0x6f030); - /* io_i915_write32(0x00800000,0x6f034); */ - /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important. - However, with our formula we always see values 0x7e43yyyy (1366 panel) and - 0x7e42yyy (1280 panel) */ - /* io_i915_write32(TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m,0x6f030); */ - io_i915_write32(dp->m_n.gmch_n,0x6f034); - io_i915_write32(dp->m_n.link_m,0x6f040); - io_i915_write32(dp->m_n.link_n,0x6f044); - - /* leave as is for now. */ - io_i915_write32(dp->htotal,0x6f000); - io_i915_write32(dp->hblank,0x6f004); - io_i915_write32(dp->hsync,0x6f008); - io_i915_write32(dp->vtotal,0x6f00c); - io_i915_write32(dp->vblank,0x6f010); - io_i915_write32(dp->vsync,0x6f014); - io_i915_write32(dp->pipesrc,_PIPEASRC); - io_i915_write32(0x00000000,0x7f008); - io_i915_write32(0x00000000,_TRANSACONF); + intel_dp_set_m_n_regs(dp); + + intel_dp_set_resolution(dp); + io_i915_write32(dp->pipesrc,PIPESRC(dp->pipe)); + io_i915_write32(0x00000000, PIPECONF(dp->transcoder)); + io_i915_write32(0x00000000, PCH_TRANSCONF(dp->pipe)); io_i915_write32(0x20000000,PORT_CLK_SEL_A); io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x14000000,_DSPACNTR);

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Patch set updated for coreboot: 9d36fa3 Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4423 -gerrit commit 9d36fa31225f4270d5062d919f35eeb32697f659 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 1 13:58:17 2013 -0700 Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags Depending upon the values decoded from edid, the function decides the appropriate bits to be set in flags parameter (Important for fastboot to work correctly in kernel) Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856 Reviewed-on: https://gerrit.chromium.org/gerrit/64265 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/gma/i915.h | 4 +++- src/drivers/intel/gma/intel_ddi.c | 10 ++++++++-- src/mainboard/google/slippy/gma.c | 4 +++- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 12a7ee0..9a6314e 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -228,7 +228,9 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, enum pipe pipe, int type, int lane_count, - int pf_sz); + int pf_sz, + u8 phsync, + u8 pvsync); enum transcoder intel_ddi_get_transcoder(enum port port, enum pipe pipe); diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index ff8ad4c..9ddd781 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -163,7 +163,9 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, enum pipe pipe, int type, int lane_count, - int pf_sz) + int pf_sz, + u8 phsync, + u8 pvsync) { u32 temp; @@ -206,7 +208,11 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, } } - /* We need to check for TRANS_DDI_PVSYNC and TRANS_DDI_PHSYNC -- How? */ + if (phsync) + temp |= TRANS_DDI_PHSYNC; + + if (pvsync) + temp |= TRANS_DDI_PVSYNC; if (type == INTEL_OUTPUT_HDMI) { /* Need to understand when to set TRANS_DDI_MODE_SELECT_HDMI / TRANS_DDI_MODE_SELECT_DVI */ diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index 026bba1..1d79d78 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -293,7 +293,9 @@ void dp_init_dim_regs(struct intel_dp *dp) dp->pipe, dp->type, dp->lane_count, - dp->pfa_sz); + dp->pfa_sz, + dp->edid.phsync == '+'?1:0, + dp->edid.pvsync == '+'?1:0); dp->transcoder = intel_ddi_get_transcoder(dp->port, dp->pipe);

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Patch merged into coreboot/master: 05e6742 Enable CAR migration on Exynos 5250 and 5420
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 05e6742abdd742b73229ed6904eeefb83f486c98 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 16 11:03:27 2013 -0700 Enable CAR migration on Exynos 5250 and 5420 Despite calling romstage memory CAR in this case, the variables actually do live in SRAM on the Exynos CPUs. However, in order to share as much generic code as possible, we're using the same infrastructure here. Change-Id: I85173c37099a25f3e55980e88120401826cdf29c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62188 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> See http://review.coreboot.org/4394 for details. -gerrit

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Patch set updated for coreboot: 05e6742 Enable CAR migration on Exynos 5250 and 5420
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4394 -gerrit commit 05e6742abdd742b73229ed6904eeefb83f486c98 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 16 11:03:27 2013 -0700 Enable CAR migration on Exynos 5250 and 5420 Despite calling romstage memory CAR in this case, the variables actually do live in SRAM on the Exynos CPUs. However, in order to share as much generic code as possible, we're using the same infrastructure here. Change-Id: I85173c37099a25f3e55980e88120401826cdf29c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62188 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/arch/armv7/romstage.ld | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0555fc4..146ba77 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -52,10 +52,28 @@ SECTIONS *(.rodata); *(.machine_param); *(.data); - . = ALIGN(8); + . = ALIGN(16); + _car_migrate_start = .; + *(.car.migrate); + _car_migrate_end = .; + . = ALIGN(16); _erom = .; } + .car.data . (NOLOAD) : { + _car_data_start = .; + *(.car.global_data); + /* The cbmem_console section comes last to take advantage of + * a zero-sized array to hold the memconsole contents that + * grows to a bound of CONFIG_CONSOLE_CAR_BUFFER_SIZE. However, + * collisions within the cache-as-ram region cannot be + * statically checked because the cache-as-ram region usage is + * cpu/chipset dependent. */ + *(.car.cbmem_console); + _car_data_end = .; + } + + __image_copy_end = .; /* bss does not contain data, it is just a space that should be zero

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Patch set updated for coreboot: 29edbff Exynos 5250: Enable dynamic CBMEM
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4390 -gerrit commit 29edbff9423d734e409daa2c5c326d013b8298c7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 15:54:19 2013 -0700 Exynos 5250: Enable dynamic CBMEM ... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59326 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Kconfig | 1 + src/cpu/samsung/exynos5250/Makefile.inc | 2 ++ src/cpu/samsung/exynos5250/cbmem.c | 28 ++++++++++++++++++++++++++++ src/cpu/samsung/exynos5250/cpu.c | 32 +++++++++++++------------------- src/cpu/samsung/exynos5250/cpu.h | 10 ++++++++++ src/mainboard/google/snow/mainboard.c | 5 +++-- src/mainboard/google/snow/romstage.c | 3 +++ 7 files changed, 60 insertions(+), 21 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 38be2d4..6731bb6 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -3,6 +3,7 @@ config CPU_SAMSUNG_EXYNOS5250 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select EARLY_CONSOLE + select DYNAMIC_CBMEM bool default n diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 9b346c6..e029c67 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += gpio.c romstage-y += timer.c romstage-y += i2c.c #romstage-y += wdt.c +romstage-y += cbmem.c ramstage-y += spi.c ramstage-y += clock.c @@ -50,6 +51,7 @@ ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c ramstage-y += usb.c +ramstage-y += cbmem.c exynos5250_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5250 BL1\n" diff --git a/src/cpu/samsung/exynos5250/cbmem.c b/src/cpu/samsung/exynos5250/cbmem.c new file mode 100644 index 0000000..e77af99 --- /dev/null +++ b/src/cpu/samsung/exynos5250/cbmem.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> +#include "cpu.h" + +void *cbmem_top(void) +{ + return (void *)(get_fb_base_kb() * KiB); +} + diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 61f937b..c363274 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -32,9 +32,6 @@ #include "usb.h" #include "chip.h" -#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) -#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) - static unsigned int cpu_id; static unsigned int cpu_rev; @@ -62,7 +59,8 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev) +static void exynos_displayport_init(device_t dev, u32 lcdbase, + unsigned long fb_size) { int ret; struct cpu_samsung_exynos5250_config *conf = dev->chip_info; @@ -70,9 +68,6 @@ static void exynos_displayport_init(device_t dev) * this code to a pre-ram stage, it will be much easier. */ struct exynos5_fimd_panel panel; - unsigned long int fb_size; - u32 lcdbase; - memset(&panel, 0, sizeof(panel)); panel.is_dp = 1; /* Display I/F is eDP */ @@ -93,11 +88,7 @@ static void exynos_displayport_init(device_t dev) panel.xres = conf->xres; panel.yres = conf->yres; - /* The size is a magic number from hardware. */ - fb_size = conf->xres * conf->yres * (conf->bpp / 8); - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); - printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); - + printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ /* @@ -111,23 +102,26 @@ static void exynos_displayport_init(device_t dev) */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + dcache_clean_invalidate_by_mva(lower, upper - lower); - mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); + mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); + + printk(BIOS_DEBUG, "Initializing Exynos LCD.\n"); - mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); - printk(BIOS_DEBUG, - "Initializing Exynos VGA, base %p\n", (void *)lcdbase); ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_enable(device_t dev) { - exynos_displayport_init(dev); + unsigned long fb_size = FB_SIZE_KB * KiB; + u32 lcdbase = get_fb_base_kb() * KiB; - ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); + mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); - set_cpu_id(); + exynos_displayport_init(dev, lcdbase, fb_size); + set_cpu_id(); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 7b12c94..254106a 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -125,4 +125,14 @@ void exynos5250_config_l2_cache(void); extern struct tmu_info exynos5250_tmu_info; +/* TODO clean up defines. */ +#define FB_SIZE_KB 4096 +#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) +#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) + +static inline u32 get_fb_base_kb(void) +{ + return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; +} + #endif /* _EXYNOS5250_CPU_H */ diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 0d194b4..bac31b3 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -213,7 +213,7 @@ static void mainboard_init(device_t dev) .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &dp_video_info, }; - void *fb_addr; + void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); @@ -228,7 +228,6 @@ static void mainboard_init(device_t dev) /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); - fb_addr = cbmem_find(CBMEM_ID_CONSOLE); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); @@ -277,8 +276,10 @@ static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; +#if !CONFIG_DYNAMIC_CBMEM /* set up coreboot tables */ cbmem_initialize(); +#endif /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7442f7a..f69fb1f 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -21,6 +21,7 @@ #include <armv7.h> #include <cbfs.h> +#include <cbmem.h> #include <arch/cache.h> #include <cpu/samsung/exynos5250/i2c.h> @@ -189,6 +190,8 @@ void main(void) /* Set SPI (primary CBFS media) clock to 50MHz. */ clock_set_rate(PERIPH_ID_SPI1, 50000000); + cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); }

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Patch set updated for coreboot: 2bfdbe0 Exynos 5420: Enable dynamic CBMEM
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4391 -gerrit commit 2bfdbe0365b528473dced00e51b5eb2af428734c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 29 15:52:23 2013 -0700 Exynos 5420: Enable dynamic CBMEM ... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63657 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/Kconfig | 1 + src/cpu/samsung/exynos5420/Makefile.inc | 2 ++ src/cpu/samsung/exynos5420/cbmem.c | 28 +++++++++++++++++++++++++++ src/cpu/samsung/exynos5420/cpu.c | 34 ++++++++++++++------------------- src/cpu/samsung/exynos5420/cpu.h | 10 ++++++++++ src/mainboard/google/pit/mainboard.c | 5 +++-- src/mainboard/google/pit/romstage.c | 4 ++++ 7 files changed, 62 insertions(+), 22 deletions(-) diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 4f102d1..df721ae 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -3,6 +3,7 @@ config CPU_SAMSUNG_EXYNOS5420 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select EARLY_CONSOLE + select DYNAMIC_CBMEM bool default n diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index b92a23f..704a346 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += gpio.c romstage-y += timer.c romstage-y += i2c.c #romstage-y += wdt.c +romstage-y += cbmem.c ramstage-y += spi.c ramstage-y += clock.c @@ -50,6 +51,7 @@ ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c ramstage-y += usb.c +ramstage-y += cbmem.c exynos5420_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5420 BL1\n" diff --git a/src/cpu/samsung/exynos5420/cbmem.c b/src/cpu/samsung/exynos5420/cbmem.c new file mode 100644 index 0000000..e77af99 --- /dev/null +++ b/src/cpu/samsung/exynos5420/cbmem.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> +#include "cpu.h" + +void *cbmem_top(void) +{ + return (void *)(get_fb_base_kb() * KiB); +} + diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 744f7ae..f686b11 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -32,9 +32,6 @@ #include "usb.h" #include "chip.h" -#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) -#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) - static unsigned int cpu_id; static unsigned int cpu_rev; @@ -62,16 +59,14 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev) +static void exynos_displayport_init(device_t dev, u32 lcdbase, + unsigned long fb_size) { struct cpu_samsung_exynos5420_config *conf = dev->chip_info; /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. */ struct exynos5_fimd_panel panel; - unsigned long int fb_size; - u32 lcdbase; - memset(&panel, 0, sizeof(panel)); panel.is_dp = 1; /* Display I/F is eDP */ @@ -92,11 +87,7 @@ static void exynos_displayport_init(device_t dev) panel.xres = conf->xres; panel.yres = conf->yres; - /* The size is a magic number from hardware. */ - fb_size = conf->xres * conf->yres * (conf->bpp / 8); - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); - printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); - + printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ /* @@ -110,23 +101,26 @@ static void exynos_displayport_init(device_t dev) */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + dcache_clean_invalidate_by_mva(lower, upper - lower); - mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); + mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); - mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); - printk(BIOS_DEBUG, - "Initializing Exynos VGA, base %p\n", (void *)lcdbase); - lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); + printk(BIOS_DEBUG, "Initializing Exynos LCD.\n"); + + ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_enable(device_t dev) { - exynos_displayport_init(dev); + unsigned long fb_size = FB_SIZE_KB * KiB; + u32 lcdbase = get_fb_base_kb() * KiB; - ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); + mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); - set_cpu_id(); + exynos_displayport_init(dev, lcdbase, fb_size); + set_cpu_id(); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 0d588da..8913120 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -202,4 +202,14 @@ void exynos5420_config_l2_cache(void); extern struct tmu_info exynos5420_tmu_info; +/* TODO clean up defines. */ +#define FB_SIZE_KB 4096 +#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) +#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) + +static inline u32 get_fb_base_kb(void) +{ + return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; +} + #endif /* _EXYNOS5420_CPU_H */ diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 2870467..042ced0 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -311,7 +311,7 @@ static void mainboard_init(device_t dev) .base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE, .video_info = &dp_video_info, }; - void *fb_addr; + void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); @@ -323,7 +323,6 @@ static void mainboard_init(device_t dev) /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); - fb_addr = cbmem_find(CBMEM_ID_CONSOLE); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); @@ -353,8 +352,10 @@ static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; +#if !CONFIG_DYNAMIC_CBMEM /* set up coreboot tables */ cbmem_initialize(); +#endif /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index b582f3e..255f292 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -22,6 +22,7 @@ #include <armv7.h> #include <cbfs.h> +#include <cbmem.h> #include <arch/cache.h> #include <cpu/samsung/exynos5420/i2c.h> @@ -270,6 +271,9 @@ void main(void) /* if this is uncommented SPI will not work correctly. */ clock_set_rate(PERIPH_ID_SPI1, 50000000); simple_spi_test(); + + cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); simple_spi_test(); stage_exit(entry);

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Patch merged into coreboot/master: a149b50 peppy: Set optimal DTLE register values
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit a149b50d85e3a0fe03f34f7ef271d081d213ef43 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Aug 13 10:50:15 2013 -0700 peppy: Set optimal DTLE register values Empirical testing shows that 0x5 is the optimal setting for DTLE DATA / EDGE on Peppy. Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65717 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/4476 for details. -gerrit

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Patch set updated for coreboot: a149b50 peppy: Set optimal DTLE register values
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4476 -gerrit commit a149b50d85e3a0fe03f34f7ef271d081d213ef43 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Aug 13 10:50:15 2013 -0700 peppy: Set optimal DTLE register values Empirical testing shows that 0x5 is the optimal setting for DTLE DATA / EDGE on Peppy. Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65717 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/google/peppy/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 06ca93c..b19f04b 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -70,6 +70,10 @@ chip northbridge/intel/haswell register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + register "sio_acpi_mode" = "0" register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V

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Patch merged into coreboot/master: 272a7ca lynxpoint: Add configuration option for SATA gen3 DTLE registers
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 272a7ca741b33f5b4120b7b9d67a9384c44e18d2 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Aug 13 10:45:21 2013 -0700 lynxpoint: Add configuration option for SATA gen3 DTLE registers Allow DTLE DATA / EDGE registers to be configured in board-specific devicetree. Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65716 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/4475 for details. -gerrit

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coreboot-gerrit December 2013