coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 347bfd9 Exynos 5420: Enable dynamic CBMEM
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4391 -gerrit commit 347bfd92ce6092ca20ec223e7d819c4a2471dd39 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 29 15:52:23 2013 -0700 Exynos 5420: Enable dynamic CBMEM ... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63657 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/Kconfig | 1 + src/cpu/samsung/exynos5420/Makefile.inc | 2 ++ src/cpu/samsung/exynos5420/cbmem.c | 28 ++++++++++++++++++++++++++++ src/cpu/samsung/exynos5420/cpu.c | 32 +++++++++++++------------------- src/cpu/samsung/exynos5420/cpu.h | 10 ++++++++++ src/mainboard/google/pit/mainboard.c | 7 +++++-- src/mainboard/google/pit/romstage.c | 4 ++++ 7 files changed, 63 insertions(+), 21 deletions(-) diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 4f102d1..df721ae 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -3,6 +3,7 @@ config CPU_SAMSUNG_EXYNOS5420 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select EARLY_CONSOLE + select DYNAMIC_CBMEM bool default n diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index b92a23f..704a346 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += gpio.c romstage-y += timer.c romstage-y += i2c.c #romstage-y += wdt.c +romstage-y += cbmem.c ramstage-y += spi.c ramstage-y += clock.c @@ -50,6 +51,7 @@ ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c ramstage-y += usb.c +ramstage-y += cbmem.c exynos5420_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5420 BL1\n" diff --git a/src/cpu/samsung/exynos5420/cbmem.c b/src/cpu/samsung/exynos5420/cbmem.c new file mode 100644 index 0000000..e77af99 --- /dev/null +++ b/src/cpu/samsung/exynos5420/cbmem.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> +#include "cpu.h" + +void *cbmem_top(void) +{ + return (void *)(get_fb_base_kb() * KiB); +} + diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 744f7ae..27fa08d 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -32,9 +32,6 @@ #include "usb.h" #include "chip.h" -#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) -#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) - static unsigned int cpu_id; static unsigned int cpu_rev; @@ -62,16 +59,14 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev) +static void exynos_displayport_init(device_t dev, u32 lcdbase, + unsigned long fb_size) { struct cpu_samsung_exynos5420_config *conf = dev->chip_info; /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. */ struct exynos5_fimd_panel panel; - unsigned long int fb_size; - u32 lcdbase; - memset(&panel, 0, sizeof(panel)); panel.is_dp = 1; /* Display I/F is eDP */ @@ -92,11 +87,7 @@ static void exynos_displayport_init(device_t dev) panel.xres = conf->xres; panel.yres = conf->yres; - /* The size is a magic number from hardware. */ - fb_size = conf->xres * conf->yres * (conf->bpp / 8); - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); - printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); - + printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ /* @@ -110,23 +101,26 @@ static void exynos_displayport_init(device_t dev) */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + dcache_clean_invalidate_by_mva(lower, upper - lower); - mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); + mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); + + printk(BIOS_DEBUG, "Initializing Exynos LCD.\n"); - mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); - printk(BIOS_DEBUG, - "Initializing Exynos VGA, base %p\n", (void *)lcdbase); lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_enable(device_t dev) { - exynos_displayport_init(dev); + unsigned long fb_size = FB_SIZE_KB * KiB; + u32 lcdbase = get_fb_base_kb() * KiB; - ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); + mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); - set_cpu_id(); + exynos_displayport_init(dev, lcdbase, fb_size); + set_cpu_id(); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 0d588da..8913120 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -202,4 +202,14 @@ void exynos5420_config_l2_cache(void); extern struct tmu_info exynos5420_tmu_info; +/* TODO clean up defines. */ +#define FB_SIZE_KB 4096 +#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) +#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) + +static inline u32 get_fb_base_kb(void) +{ + return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; +} + #endif /* _EXYNOS5420_CPU_H */ diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 2870467..d8206e7 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -311,7 +311,7 @@ static void mainboard_init(device_t dev) .base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE, .video_info = &dp_video_info, }; - void *fb_addr; + void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); @@ -323,7 +323,6 @@ static void mainboard_init(device_t dev) /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); - fb_addr = cbmem_find(CBMEM_ID_CONSOLE); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); @@ -341,6 +340,7 @@ static void mainboard_init(device_t dev) // gpio_info(); } +#if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) { *size = CONFIG_COREBOOT_TABLES_SIZE; @@ -348,13 +348,16 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - CONFIG_COREBOOT_TABLES_SIZE; } +#endif static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; +#if !CONFIG_DYNAMIC_CBMEM /* set up coreboot tables */ cbmem_initialize(); +#endif /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index b582f3e..255f292 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -22,6 +22,7 @@ #include <armv7.h> #include <cbfs.h> +#include <cbmem.h> #include <arch/cache.h> #include <cpu/samsung/exynos5420/i2c.h> @@ -270,6 +271,9 @@ void main(void) /* if this is uncommented SPI will not work correctly. */ clock_set_rate(PERIPH_ID_SPI1, 50000000); simple_spi_test(); + + cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); simple_spi_test(); stage_exit(entry);

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Patch merged into coreboot/master: 0c7f810 google/pit: disable SYSMMU for graphics
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 0c7f8100be30caa9d40672a657568e0df8c883cb Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Jul 16 17:30:16 2013 -0700 google/pit: disable SYSMMU for graphics It's not needed and it's a potential problem source. Change-Id: Ic4cafe74e7fc3a9031d852895ad7fd5e5cd64d11 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62279 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/4410 for details. -gerrit

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Patch set updated for coreboot: 0c7f810 google/pit: disable SYSMMU for graphics
by Stefan Reinauer 21 Dec '13

21 Dec '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4410 -gerrit commit 0c7f8100be30caa9d40672a657568e0df8c883cb Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Jul 16 17:30:16 2013 -0700 google/pit: disable SYSMMU for graphics It's not needed and it's a potential problem source. Change-Id: Ic4cafe74e7fc3a9031d852895ad7fd5e5cd64d11 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62279 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/pit/mainboard.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 2870467..d0230e2 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -326,6 +326,15 @@ static void mainboard_init(device_t dev) fb_addr = cbmem_find(CBMEM_ID_CONSOLE); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + /* + * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 + * should be 0 according to the datasheet, but has experimentally + * been found to come up as 3. This means FIMD SYSMMU is on by + * default on Exynos5420. For now we are disabling FIMD SYSMMU. + */ + writel(0x0, (void *)0x14640000); + writel(0x0, (void *)0x14680000); + lcd_vdd(); parade_dp_bridge_setup();

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Patch merged into coreboot/master: 87d1eb9 max77802: update header
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 87d1eb9abca12a82f375db5bca24b21255be93f0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 1 18:48:26 2013 -0700 max77802: update header This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6 Reviewed-on: https://gerrit.chromium.org/gerrit/64303 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/4426 for details. -gerrit

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Patch merged into coreboot/master: a1d1be0 Refactor code containing aux calls
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit a1d1be04ae9ed15ea13353cb1b00fcebe8fa7592 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 31 13:17:30 2013 -0700 Refactor code containing aux calls Moved a lot of code from i915io.c to intel_dp.c with specific function calls Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc Reviewed-on: https://gerrit.chromium.org/gerrit/63950 Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> See http://review.coreboot.org/4429 for details. -gerrit

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Patch merged into coreboot/master: 9d36fa3 Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 9d36fa31225f4270d5062d919f35eeb32697f659 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 1 13:58:17 2013 -0700 Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags Depending upon the values decoded from edid, the function decides the appropriate bits to be set in flags parameter (Important for fastboot to work correctly in kernel) Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856 Reviewed-on: https://gerrit.chromium.org/gerrit/64265 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> See http://review.coreboot.org/4423 for details. -gerrit

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Patch merged into coreboot/master: 77aab14 Add cpu transcoder attribute to intel dp
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 77aab14ae3647bead5c5d2babdb7fa209e5e446b Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 31 16:47:31 2013 -0700 Add cpu transcoder attribute to intel dp Also, used this attribute in the calculation of htotal and other registers Added intel_dp_* functions for m,n registers and dimension register calculations Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a Reviewed-on: https://gerrit.chromium.org/gerrit/64001 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> See http://review.coreboot.org/4422 for details. -gerrit

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Patch merged into coreboot/master: 69d88ad Calculate transcoder flags based on pipe config
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 69d88adb7f2fa400f4664b9ea44f65fea1ee15d0 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 30 12:41:08 2013 -0700 Calculate transcoder flags based on pipe config Works fine with all three panels with the change of 6 bits per color. Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e Reviewed-on: https://gerrit.chromium.org/gerrit/63762 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> See http://review.coreboot.org/4402 for details. -gerrit

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Patch set updated for coreboot: 87d1eb9 max77802: update header
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4426 -gerrit commit 87d1eb9abca12a82f375db5bca24b21255be93f0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 1 18:48:26 2013 -0700 max77802: update header This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6 Reviewed-on: https://gerrit.chromium.org/gerrit/64303 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/drivers/maxim/max77802/max77802.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/drivers/maxim/max77802/max77802.h b/src/drivers/maxim/max77802/max77802.h index 80a105d..beb7195 100644 --- a/src/drivers/maxim/max77802/max77802.h +++ b/src/drivers/maxim/max77802/max77802.h @@ -196,15 +196,17 @@ enum { }; /* Buck1 1.0 volt value (P1.0V_AP_MIF) */ -#define MAX77802_BUCK1DVS1_1V 0x3E +#define MAX77802_BUCK1DVS1_1V 0x3E /* Buck2 1.0 volt value (P1.0V_VDD_ARM) */ -#define MAX77802_BUCK2DVS1_1V 0x40 +#define MAX77802_BUCK2DVS1_1V 0x40 +/* Buck2 1.2625 volt value (P1.2625V_VDD_ARM) */ +#define MAX77802_BUCK2DVS1_1_2625V 0x6A /* Buck3 1.0 volt value (P1.0V_VDD_INT) */ -#define MAX77802_BUCK3DVS1_1V 0x40 +#define MAX77802_BUCK3DVS1_1V 0x40 /* Buck4 1.0 volt value (P1.0V_VDD_G3D) */ -#define MAX77802_BUCK4DVS1_1V 0x40 +#define MAX77802_BUCK4DVS1_1V 0x40 /* Buck6 1.0 volt value (P1.0V_AP_KFC) */ -#define MAX77802_BUCK6DVS1_1V 0x3E +#define MAX77802_BUCK6DVS1_1V 0x3E /* * Different Bucks use different bits to control power. There are two types, @@ -222,6 +224,9 @@ enum { #define MAX77802_LDO35CTRL1_1_2V (1 << 4) #define MAX77802_LOD35CTRL1_ON (1 << 6) +/* Disable Boost Mode*/ +#define MAX77802_BOOSTCTRL_OFF 0x09 + /* * MAX77802_REG_PMIC_32KHZ set to 32KH CP * output is activated

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Patch set updated for coreboot: a1d1be0 Refactor code containing aux calls
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4429 -gerrit commit a1d1be04ae9ed15ea13353cb1b00fcebe8fa7592 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 31 13:17:30 2013 -0700 Refactor code containing aux calls Moved a lot of code from i915io.c to intel_dp.c with specific function calls Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc Reviewed-on: https://gerrit.chromium.org/gerrit/63950 Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/gma/i915.h | 27 ++++++ src/drivers/intel/gma/intel_dp.c | 83 +++++++++++++++++- src/mainboard/google/slippy/gma.c | 25 ++++++ src/mainboard/google/slippy/i915io.c | 162 ++++------------------------------- 4 files changed, 148 insertions(+), 149 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 9a6314e..ef770dc 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -237,3 +237,30 @@ enum transcoder intel_ddi_get_transcoder(enum port port, void intel_dp_set_m_n_regs(struct intel_dp *intel_dp); void intel_dp_set_resolution(struct intel_dp *intel_dp); + +int intel_dp_i2c_write(struct intel_dp *intel_dp, + u8 val); + +int intel_dp_i2c_read(struct intel_dp *intel_dp, + u8 *val); + +int intel_dp_set_bw(struct intel_dp *intel_dp); +int intel_dp_set_lane_count(struct intel_dp *intel_dp); +int intel_dp_set_training_lane0(struct intel_dp *intel_dp, + u8 val); +int intel_dp_set_training_pattern(struct intel_dp *intel_dp, + u8 pat); + +int intel_dp_get_link_status(struct intel_dp *intel_dp, + uint8_t link_status[DP_LINK_STATUS_SIZE]); + +int intel_dp_get_training_pattern(struct intel_dp *intel_dp, + u8 *recv); + +int intel_dp_get_lane_count(struct intel_dp *intel_dp, + u8 *recv); + +int intel_dp_get_lane_align_status(struct intel_dp *intel_dp, + u8 *recv); + + diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c index 419e49e..b824cb7 100644 --- a/src/drivers/intel/gma/intel_dp.c +++ b/src/drivers/intel/gma/intel_dp.c @@ -250,6 +250,40 @@ intel_dp_aux_native_write_1(struct intel_dp *intel_dp, return intel_dp_aux_native_write(intel_dp, address, &byte, 1); } +int intel_dp_set_bw(struct intel_dp *intel_dp) +{ + printk(BIOS_SPEW, "DP_LINK_BW_SET"); + return intel_dp_aux_native_write_1(intel_dp, + DP_LINK_BW_SET, + intel_dp->link_bw); +} + +int intel_dp_set_lane_count(struct intel_dp *intel_dp) +{ + printk(BIOS_SPEW, "DP_LANE_COUNT_SET"); + return intel_dp_aux_native_write_1(intel_dp, + DP_LANE_COUNT_SET, + intel_dp->lane_count); +} + +int intel_dp_set_training_pattern(struct intel_dp *intel_dp, + u8 pat) +{ + printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); + return intel_dp_aux_native_write_1(intel_dp, + DP_TRAINING_PATTERN_SET, + pat); +} + +int intel_dp_set_training_lane0(struct intel_dp *intel_dp, + u8 val) +{ + printk(BIOS_SPEW, "DP_TRAINING_LANE0_SET"); + return intel_dp_aux_native_write_1(intel_dp, + DP_TRAINING_LANE0_SET, + val); +} + /* read bytes from a native aux channel */ static int intel_dp_aux_native_read(struct intel_dp *intel_dp, @@ -381,6 +415,24 @@ intel_dp_i2c_aux_ch(struct intel_dp *intel_dp, return -1; } +int intel_dp_i2c_write(struct intel_dp *intel_dp, + u8 val) +{ + return intel_dp_i2c_aux_ch(intel_dp, + MODE_I2C_WRITE, + val, + NULL); +} + +int intel_dp_i2c_read(struct intel_dp *intel_dp, + u8 *val) +{ + return intel_dp_i2c_aux_ch(intel_dp, + MODE_I2C_READ, + 0, + val); +} + int intel_dp_i2c_init(struct intel_dp *intel_dp) { @@ -990,7 +1042,7 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, * Fetch AUX CH registers 0x202 - 0x207 which contain * link status information */ -static int +int intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) { @@ -1728,7 +1780,7 @@ int intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread) { int got, want = 1; - got = intel_dp_aux_native_read_retry(intel_dp, 0x000, max_downspread, + got = intel_dp_aux_native_read_retry(intel_dp, DP_MAX_DOWNSPREAD, max_downspread, want); if (got < want) { printk(BIOS_SPEW, "%s: got %d, wanted %d\n", __func__, got, want); @@ -1761,3 +1813,30 @@ void intel_dp_set_resolution(struct intel_dp *intel_dp) io_i915_write32(intel_dp->vblank, VBLANK(intel_dp->transcoder)); io_i915_write32(intel_dp->vsync, VSYNC(intel_dp->transcoder)); } + +int intel_dp_get_training_pattern(struct intel_dp *intel_dp, + u8 *recv) +{ + return intel_dp_aux_native_read_retry(intel_dp, + DP_TRAINING_PATTERN_SET, + recv, + 0); +} + +int intel_dp_get_lane_count(struct intel_dp *intel_dp, + u8 *recv) +{ + return intel_dp_aux_native_read_retry(intel_dp, + DP_LANE_COUNT_SET, + recv, + 0); +} + +int intel_dp_get_lane_align_status(struct intel_dp *intel_dp, + u8 *recv) +{ + return intel_dp_aux_native_read_retry(intel_dp, + DP_LANE_ALIGN_STATUS_UPDATED, + recv, + 0); +} diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index 1d79d78..e698fc9 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -340,6 +340,31 @@ int intel_dp_bw_code_to_link_rate(u8 link_bw) } } +void mainboard_train_link(struct intel_dp *intel_dp); +void mainboard_train_link(struct intel_dp *intel_dp) +{ + u8 read_val; + u8 link_status[DP_LINK_STATUS_SIZE]; + + io_i915_write32(0x80040000,DP_TP_CTL_A); + io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A); + + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); + intel_dp_get_lane_count(intel_dp, &read_val); + intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); + intel_dp_get_link_status(intel_dp, link_status); + + io_i915_write32(0x80040100,DP_TP_CTL_A); + + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); + intel_dp_get_link_status(intel_dp, link_status); + intel_dp_get_lane_align_status(intel_dp, &read_val); + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); +} + int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, unsigned int gfx); diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c index cf57430..668094f 100644 --- a/src/mainboard/google/slippy/i915io.c +++ b/src/mainboard/google/slippy/i915io.c @@ -33,11 +33,15 @@ u32 auxout; u8 auxin[20]; u8 msg[32]; +extern void mainboard_train_link(struct intel_dp *intel_dp); + /* this function will either be renamed or subsumed into ./gma.c:i915_lightup */ void runio(struct intel_dp *dp); void runio(struct intel_dp *dp) { + u8 read_val; + intel_dp_wait_panel_power_control(0xabcd0008); /* vbios spins at this point. Some haswell weirdness? */ @@ -109,11 +113,8 @@ void runio(struct intel_dp *dp) io_i915_write32(0x00000001,0x4f008); io_i915_write32(0x00000012,0x4f014); - /* replace with a function: unsigned int intel_dp_get_max_downspread(dp); */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_MAX_DOWNSPREAD<<8|0x0|0x90000300; -printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); + + intel_dp_get_max_downspread(dp, &read_val); intel_dp_set_m_n_regs(dp); @@ -142,38 +143,12 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD"); intel_dp_wait_panel_power_control(0xabcd000a); /* what is this doing? Not sure yet. */ - /* each block here needs to be a call to a function */ - auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000; - unpack_aux(auxout, &msg[0], 4); - auxout = 0x00000000; - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x3|0x10005003; - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 3); - - auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000; - unpack_aux(auxout, &msg[0], 4); - auxout = 0x04000000; - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x3|0x10005003; - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 3); - - - auxout = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x50<<8|0x0|0x40005000; - unpack_aux(auxout, &msg[0], 4); - auxout = 0x7e000000; - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - - auxout = 0<<31 /* i2c */|0<<30|0x1<<28/*R*/|0x50<<8|0x0|0x10005000; - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); + intel_dp_i2c_write(dp, 0x0); + intel_dp_i2c_read(dp, &read_val); + intel_dp_i2c_write(dp, 0x04); + intel_dp_i2c_read(dp, &read_val); + intel_dp_i2c_write(dp, 0x7e); + intel_dp_i2c_read(dp, &read_val); /* this needs to be a call to a function */ io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A); @@ -185,115 +160,10 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD"); io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a,PCH_PP_ON_DELAYS); io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a,PCH_PP_ON_DELAYS); + intel_dp_set_bw(dp); + intel_dp_set_lane_count(dp); - /* create function: intel_dp_set_bw(dp, u8 bw); */ - auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x0|0x80010000; - printk(BIOS_SPEW, "DP_LINK_BW_SET"); - unpack_aux(auxout, &msg[0], 4); - auxout = 0x0a000480; - /*( DP_LINK_BW_2_7 &0xa)|0xffffffff8004000a*/ - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - /* this info whould have been goten in intel_dp_get_dpcd. So that function should - * set dp->lane_count but does not yet. - */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_MAX_LANE_COUNT<<8|0x0|0x90000200; -printk(BIOS_SPEW, "DP_MAX_LANE_COUNT"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); - - /* create a function: intel_dp_set_lane_count(dp); gets lane count from dp->lane_count */ - auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_LANE_COUNT_SET<<8|0x0|0x80010100; -printk(BIOS_SPEW, "DP_LANE_COUNT_SET"); - unpack_aux(auxout, &msg[0], 4); - auxout = 0x81000000; - /*0x00000081*/ - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - io_i915_write32(0x80040000,DP_TP_CTL_A); - io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A); - - /* find or create: intel_dp_set_training_pattern(dp, pattern); */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200; -printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); - - /* why did they do it twice? */ - auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200; -printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); - unpack_aux(auxout, &msg[0], 4); - auxout = 0x01000000; - /* DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000001*/ - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - /* create a function */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE_COUNT_SET<<8|0x0|0x90010100; -printk(BIOS_SPEW, "DP_LANE_COUNT_SET"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); - - /* create a function */ - auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x0|0x80010300; -printk(BIOS_SPEW, "DP_TRAINING_LANE0_SET"); - unpack_aux(auxout, &msg[0], 4); - auxout = 0x00000000; - /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - /* create a function */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x1|0x90020201; -printk(BIOS_SPEW, "DP_LANE0_1_STATUS"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 1); - - io_i915_write32(0x80040100,DP_TP_CTL_A); - - /* create a function */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200; -printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); - - /* create a function */ - auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200; -printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); - unpack_aux(auxout, &msg[0], 4); - auxout = 0x02000000; - /* DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000002*/ - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); - - /* create a function */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x1|0x90020201; -printk(BIOS_SPEW, "DP_LANE0_1_STATUS"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 1); - - /* create a function */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE_ALIGN_STATUS_UPDATED<<8|0x0|0x90020400; -printk(BIOS_SPEW, "DP_LANE_ALIGN_STATUS_UPDATED"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); - - /* create a function */ - auxout = 1<<31 /* dp */|0x1<<28/*R*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x90010200; -printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); - unpack_aux(auxout, &msg[0], 4); - intel_dp_aux_ch(dp, msg, 4, auxin, 0); - - /* create a function */ - auxout = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0|0x80010200; -printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); - unpack_aux(auxout, &msg[0], 4); - auxout = 0x00000000; - /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ - unpack_aux(auxout, &msg[4], 4); - intel_dp_aux_ch(dp, msg, 5, auxin, 0); + mainboard_train_link(dp); /* need a function: intel_ddi_set_tp or similar */ io_i915_write32(0x80040200,DP_TP_CTL_A); @@ -302,11 +172,9 @@ printk(BIOS_SPEW, "DP_TRAINING_PATTERN_SET"); io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2); io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1); - io_i915_write32(0x00000400,0x4f044); io_i915_write32(0x00000000,0x4f044); - /* some of this is not needed. */ io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30); io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);

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coreboot-gerrit December 2013