coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 42f835a exynos5250: Add a pinmux function to set up i2s bus 0
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4438 -gerrit commit 42f835aa7fa8314b0363c4ffbcfdd3f37a284426 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Aug 5 22:15:21 2013 -0700 exynos5250: Add a pinmux function to set up i2s bus 0 This bus is hooked up on snow and, as it's the only bus hooked up on some other boards, having it available in firmware to test is handy. Change-Id: Icb48b9af4a67d382bd6fbce1e4c6a320d811d365 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64877 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/samsung/exynos5250/pinmux.c | 10 ++++++++++ src/cpu/samsung/exynos5250/pinmux.h | 1 + 2 files changed, 11 insertions(+) diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c index ab1b25e..b5406af 100644 --- a/src/cpu/samsung/exynos5250/pinmux.c +++ b/src/cpu/samsung/exynos5250/pinmux.c @@ -244,6 +244,16 @@ void exynos_pinmux_dphpd(void) gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); } +void exynos_pinmux_i2s0(void) +{ + int i; + + for (i = 0; i < 5; i++) { + gpio_cfg_pin(GPIO_Z0 + i, GPIO_FUNC(0x02)); + gpio_set_pull(GPIO_Z0 + i, GPIO_PULL_NONE); + } +} + void exynos_pinmux_i2s1(void) { int i; diff --git a/src/cpu/samsung/exynos5250/pinmux.h b/src/cpu/samsung/exynos5250/pinmux.h index e5cf699..227a280 100644 --- a/src/cpu/samsung/exynos5250/pinmux.h +++ b/src/cpu/samsung/exynos5250/pinmux.h @@ -52,6 +52,7 @@ void exynos_pinmux_i2c7(void); void exynos_pinmux_dphpd(void); +void exynos_pinmux_i2s0(void); void exynos_pinmux_i2s1(void); #endif

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Patch set updated for coreboot: bb45c62 arm: Remove __image_copy_end from the ARM linker script
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4399 -gerrit commit bb45c62db90cd14ba8876b6156626d7631c3b85d Author: Gabe Black <gabeblack(a)google.com> Date: Tue Jul 30 13:46:58 2013 -0700 arm: Remove __image_copy_end from the ARM linker script That symbol isn't used by anything and doesn't appear in other linker scripts. Change-Id: Iab54ecb3be2e262d7674ef8ee7ed13ea2e5b56f3 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63776 Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/romstage.ld | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 146ba77..14c5bde 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -73,9 +73,6 @@ SECTIONS _car_data_end = .; } - - __image_copy_end = .; - /* bss does not contain data, it is just a space that should be zero * initialized on startup. (typically uninitialized global variables) * crt0.S fills between _bss and _ebss with zeroes.

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Patch set updated for coreboot: 8487484 exynos5250: Implement support to boot with USB A-A firmware upload
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4456 -gerrit commit 8487484b7afbd003e57acd1178cc450438bdabd1 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Aug 6 16:00:37 2013 -0700 exynos5250: Implement support to boot with USB A-A firmware upload This patch implements the basic infrastructure required to use the USB A-A firmware upload feature on Exynos5 processors with Coreboot. It will require a corresponding host-side script that activates the feature and uploads the correct image parts in the correct order to harcoded target addresses, as described in the comments of alternate_cbfs.c. Also fixes a bug in the Google Snow mainboard where it would not correctly initialize the pinmux configuration for the SPI flash bus. During a normal SPI boot the IROM would already do that for you, but when booting from USB you have to do it yourself. Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64875 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 3 - src/cpu/samsung/exynos5250/Makefile.inc | 6 +- src/cpu/samsung/exynos5250/alternate_cbfs.c | 110 ++++++++++++++++++++++++++++ src/cpu/samsung/exynos5250/alternate_cbfs.h | 44 +++++++++++ src/cpu/samsung/exynos5250/cpu.h | 16 ---- src/cpu/samsung/exynos5250/pinmux.c | 5 +- src/cpu/samsung/exynos5250/spi.c | 7 -- src/mainboard/google/snow/romstage.c | 3 +- 8 files changed, 163 insertions(+), 31 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 541175c..6ed63ce 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -55,9 +55,6 @@ void main(void) /* * Re-enable icache and branch prediction. MMU and dcache will be * set up later. - * - * Note: If booting from USB, we need to disable branch prediction - * before copying from USB into RAM (FIXME: why?) */ sctlr = read_sctlr(); sctlr |= SCTLR_Z | SCTLR_I; diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e029c67..6d7ae16 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += spi.c +bootblock-y += spi.c alternate_cbfs.c bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c @@ -16,7 +16,7 @@ bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c -romstage-y += spi.c +romstage-y += spi.c alternate_cbfs.c romstage-y += clock.c romstage-y += clock_init.c romstage-y += pinmux.c # required by s3c24x0_i2c and uart. @@ -35,7 +35,7 @@ romstage-y += i2c.c #romstage-y += wdt.c romstage-y += cbmem.c -ramstage-y += spi.c +ramstage-y += spi.c alternate_cbfs.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.c b/src/cpu/samsung/exynos5250/alternate_cbfs.c new file mode 100644 index 0000000..1549486 --- /dev/null +++ b/src/cpu/samsung/exynos5250/alternate_cbfs.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <assert.h> +#include <cbfs.h> /* This driver serves as a CBFS media source. */ +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include "alternate_cbfs.h" +#include "spi.h" + +/* This allows USB A-A firmware upload from a compatible host in four parts: + * The first two are the bare BL1 and the Coreboot boot block, which are just + * written to their respective loading addresses. These transfers are initiated + * by the IROM / BL1, so this code has nothing to do with them. + * + * The third transfer is a valid CBFS image that contains only the romstage, + * and must be small enough to fit into alternate_cbfs_size[__BOOT_BLOCK__] in + * IRAM. It is loaded when this function gets called in the boot block, and + * the normal CBFS code extracts the romstage from it. + * + * The fourth transfer is also a CBFS image, but can be of arbitrary size and + * should contain all available stages/payloads/etc. It is loaded when this + * function is called a second time at the end of the romstage, and copied to + * alternate_cbfs_buffer[!__BOOT_BLOCK__] in DRAM. It will reside there for the + * rest of the firmware's lifetime and all subsequent stages (which will not + * have __PRE_RAM__ defined) can just directly reference it there. + */ +static int usb_cbfs_open(struct cbfs_media *media) { +#ifdef __PRE_RAM__ + static int first_run = 1; + int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; + + if (!first_run) + return 0; + + if (!irom_load_usb()) { + printk(BIOS_ERR, "Unable to load CBFS image via USB!\n"); + return -1; + } + + /* + * We need to trust the host/irom to copy the image to our + * alternate_cbfs_buffer address... there is no way to control or even + * check the transfer size or target address from our side. + */ + + printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now" + " be at %p\n", alternate_cbfs_buffer); + first_run = 0; +#endif + return 0; +} + +static int alternate_cbfs_close(struct cbfs_media *media) { return 0; } + +static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest, + size_t offset, size_t count) { + ASSERT(offset + count < alternate_cbfs_size); + memcpy(dest, alternate_cbfs_buffer + offset, count); + return count; +} + +static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset, + size_t count) { + ASSERT(offset + count < alternate_cbfs_size); + return alternate_cbfs_buffer + offset; +} + +static void *alternate_cbfs_unmap(struct cbfs_media *media, + const void *buffer) { return 0; } + +static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media) { + printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n"); + + media->open = usb_cbfs_open; + media->close = alternate_cbfs_close; + media->read = alternate_cbfs_read; + media->map = alternate_cbfs_map; + media->unmap = alternate_cbfs_unmap; + + return 0; +} + +int init_default_cbfs_media(struct cbfs_media *media) { + if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) + return initialize_exynos_usb_cbfs_media(media); + + /* TODO: implement SDMMC (and possibly other) boot mode */ + + return initialize_exynos_spi_cbfs_media(media, + (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE); +} diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.h b/src/cpu/samsung/exynos5250/alternate_cbfs.h new file mode 100644 index 0000000..a26fe61 --- /dev/null +++ b/src/cpu/samsung/exynos5250/alternate_cbfs.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H +#define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H + +/* These are pointers to function pointers. Double indirection! */ +void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030; +void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044; +void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048; +void * * const irom_spi_sf_read_ptr = (void * *)0x02020058; +void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070; + +#define SECONDARY_BASE_BOOT_USB 0xfeed0002 +u32 * const iram_secondary_base = (u32 *)0x02020018; + +#if defined(__BOOT_BLOCK__) + /* A small space in IRAM to hold the romstage-only image */ + void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS; + size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE; +#else + /* Just put this anywhere in RAM that's far enough from anything else */ + /* TODO: Find a better way to "reserve" this region? */ + void * const alternate_cbfs_buffer = (void *)0x77400000; + size_t const alternate_cbfs_size = 0xc00000; +#endif + +#endif diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 149de6a..f4ab3ed 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -26,22 +26,6 @@ #define EXYNOS_PRO_ID 0x10000000 -/* Address of address of function that copys data from SD or MMC */ -#define EXYNOS_COPY_MMC_FNPTR_ADDR 0x02020030 - -/* Address of address of function that copys data from SPI */ -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 - -/* Address of address of function that copys data through USB */ -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 - -/* Boot mode values */ -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 - -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 - -#define EXYNOS_I2C_SPACING 0x10000 - /* EXYNOS5 */ #define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */ #define EXYNOS5_PRO_ID 0x10000000 diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c index b5406af..89ce23e 100644 --- a/src/cpu/samsung/exynos5250/pinmux.c +++ b/src/cpu/samsung/exynos5250/pinmux.c @@ -134,8 +134,11 @@ static void exynos_pinmux_spi(int start, int cfg) { int i; - for (i = 0; i < 4; i++) + for (i = 0; i < 4; i++) { gpio_cfg_pin(start + i, GPIO_FUNC(cfg)); + gpio_set_pull(start + i, GPIO_PULL_NONE); + gpio_set_drv(start + i, GPIO_DRV_3X); + } } void exynos_pinmux_spi0(void) diff --git a/src/cpu/samsung/exynos5250/spi.c b/src/cpu/samsung/exynos5250/spi.c index 1c365dc..e8b68b4 100644 --- a/src/cpu/samsung/exynos5250/spi.c +++ b/src/cpu/samsung/exynos5250/spi.c @@ -214,10 +214,3 @@ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, return 0; } - -int init_default_cbfs_media(struct cbfs_media *media) { - return initialize_exynos_spi_cbfs_media( - media, - (void*)CONFIG_CBFS_CACHE_ADDRESS, - CONFIG_CBFS_CACHE_SIZE); -} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 92fa21e..d45b861 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -180,7 +180,8 @@ void main(void) setup_gpio(); setup_graphics(); - /* Set SPI (primary CBFS media) clock to 50MHz. */ + /* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */ + exynos_pinmux_spi1(); clock_set_rate(PERIPH_ID_SPI1, 50000000); cbmem_initialize_empty();

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Patch set updated for coreboot: 8016adf exynos5420: Configure the UART pins unconditionally
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4457 -gerrit commit 8016adf9248c5a807fdf6e8c93da3191f656c783 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Aug 9 00:31:09 2013 -0700 exynos5420: Configure the UART pins unconditionally Configure the pins for the UART unconditionally in the mainboard code (when we know which UART to configure) instead of in the UART driver. This also means the UART will work if later software wants to use it without setting up the pins. Built and booted on pit with the serial turned off and some serial init in the kernel decompression stub fixed. Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65299 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/uart.c | 3 --- src/mainboard/google/pit/romstage.c | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index de71b80..c5c8a8c 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -93,9 +93,6 @@ static void exynos5_init_dev(void) { struct s5p_uart *uart = (struct s5p_uart *)base_port; - // TODO initialize with correct peripheral id by base_port. - exynos_pinmux_uart3(); - /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 853e24d..b74c27f 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -250,6 +250,7 @@ void main(void) * to re-initialize serial console drivers again. */ system_clock_init(); + exynos_pinmux_uart3(); console_init(); setup_power(is_resume);

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Patch set updated for coreboot: ff281bd exynos5420: add a peripheral clock select --> PLL decoder
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4462 -gerrit commit ff281bdb4eaea3cc365e888fec26b28387fed412 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 19:03:03 2013 -0700 exynos5420: add a peripheral clock select --> PLL decoder This adds a helper function to translate between peripheral clock select fields in clock source registers and PLLs. Some of this was already done to handle a few special cases, this generalizes the earlier work so that follow-up patches can do further clean-up. Unfortunately, the PLLs represented by clock select fields in various modules are not uniformly ordered. So for now we focus on peripheral clock sources only. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff Reviewed-on: https://gerrit.chromium.org/gerrit/65283 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 12 ++------ src/cpu/samsung/exynos5420/clock.c | 59 ++++++++++++++++++++++++++++++++------ 2 files changed, 52 insertions(+), 19 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index b37c076..c5e7f58 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -25,6 +25,7 @@ enum periph_id; +/* This master list of PLLs is ordered arbitrarily. */ #define APLL 0 #define MPLL 1 #define EPLL 2 @@ -35,16 +36,7 @@ enum periph_id; #define SPLL 7 #define CPLL 8 #define DPLL 9 - -enum pll_src_bit { - EXYNOS_SRC_CPLL = 1, - EXYNOS_SRC_DPLL = 2, - EXYNOS_SRC_MPLL = 3, - EXYNOS_SRC_SPLL = 4, - EXYNOS_SRC_IPLL = 5, - EXYNOS_SRC_EPLL = 6, - EXYNOS_SRC_RPLL = 7, -}; +#define IPLL 10 /* * * This structure is to store the src bit, div bit and prediv bit diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index b8e27ff..82b1813 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -151,6 +151,50 @@ unsigned long get_pll_clk(int pllreg) return fout; } +enum peripheral_clock_select { + PERIPH_SRC_CPLL = 1, + PERIPH_SRC_DPLL = 2, + PERIPH_SRC_MPLL = 3, + PERIPH_SRC_SPLL = 4, + PERIPH_SRC_IPLL = 5, + PERIPH_SRC_EPLL = 6, + PERIPH_SRC_RPLL = 7, +}; + +static int clock_select_to_pll(enum peripheral_clock_select sel) +{ + int pll; + + switch (sel) { + case PERIPH_SRC_CPLL: + pll = CPLL; + break; + case PERIPH_SRC_DPLL: + pll = DPLL; + break; + case PERIPH_SRC_MPLL: + pll = MPLL; + break; + case PERIPH_SRC_SPLL: + pll = SPLL; + break; + case PERIPH_SRC_IPLL: + pll = IPLL; + break; + case PERIPH_SRC_EPLL: + pll = EPLL; + break; + case PERIPH_SRC_RPLL: + pll = RPLL; + break; + default: + pll = -1; + break; + } + + return pll; +} + unsigned long clock_get_periph_rate(enum periph_id peripheral) { struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; @@ -206,17 +250,14 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) src = (src >> bit_info->src_bit) & 0xf; - switch (src) { - case EXYNOS_SRC_MPLL: - sclk = get_pll_clk(MPLL); - break; - case EXYNOS_SRC_EPLL: - sclk = get_pll_clk(EPLL); - break; - default: - return 0; + src = clock_select_to_pll(src); + if (src < 0) { + printk(BIOS_DEBUG, "%s: cannot determine source PLL", __func__); + return -1; } + sclk = get_pll_clk(src); + /* Ratio clock division for this peripheral */ sub_div = (div >> bit_info->div_bit) & 0xf; sub_clk = sclk / (sub_div + 1);

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Patch set updated for coreboot: 500d077 exynos5420: re-factor clock_get_periph_rate()
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4463 -gerrit commit 500d077f9488c8df90ce044232189f87b2723e88 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 20:45:53 2013 -0700 exynos5420: re-factor clock_get_periph_rate() This re-factors clock_get_periph_rate() to be a simpler and also make a few corrections along the way. To summarize: - clk_bit_info is no longer used. It had numerous errors and was really painful anyway since it was just a bunch of opaque magic numbers that made bugs non-obvious. - Clock source bitfields for peripherals handled in the switch statement are 3 bits, not 4. Some divider values are 3 bits, some are 4. The earlier code always assumed 4 bits for both which included reserved bits in many cases. - UART source clock and divider shift values were wrong. - PWM clock divider was being read from the wrong register. - SPI3 divider value was being read from the wrong register. - There was a really confusing calculation for SDMMC0 and SDMMC2 clock rates, but it was never actually used since the switch statement never handled PERIPH_ID_SDMMC{0,2} and would thus return if they were ever passed into this function. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b Reviewed-on: https://gerrit.chromium.org/gerrit/65284 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 10 ----- src/cpu/samsung/exynos5420/clock.c | 86 +++++++++++++++----------------------- 2 files changed, 33 insertions(+), 63 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index c5e7f58..3f97319 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -38,16 +38,6 @@ enum periph_id; #define DPLL 9 #define IPLL 10 -/* * - * This structure is to store the src bit, div bit and prediv bit - * positions of the peripheral clocks of the src and div registers - */ -struct clk_bit_info { - s8 src_bit; /* offset in register to clock source field */ - s8 div_bit; - s8 prediv_bit; -}; - unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_pwm_clk(void); diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 82b1813..783679a 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -29,32 +29,6 @@ /* input clock of PLL: SMDK5420 has 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 -/* src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { - {0, 0, -1}, - {4, 4, -1}, - {8, 8, -1}, - {12, 12, -1}, - {0, 0, 8}, - {4, 16, 24}, - {8, 0, 8}, - {12, 16, 24}, - {-1, -1, -1}, - {16, 0, 8}, /* PERIPH_ID_SROMC */ - {20, 20, 24}, - {24, 24, 8}, - {28, 28, 4}, - {4, 12, 16}, - {-1, -1, -1}, - {-1, -1, -1}, - [PERIPH_ID_DPHPD] - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, -}; - /* Epll Clock division values to achive different frequency output */ static struct st_epll_con_val epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -197,37 +171,54 @@ static int clock_select_to_pll(enum peripheral_clock_select sel) unsigned long clock_get_periph_rate(enum periph_id peripheral) { - struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; - unsigned long sclk, sub_clk; - unsigned int src, div, sub_div; + unsigned long sclk; + unsigned int src, div; struct exynos5420_clock *clk = samsung_get_base_clock(); switch (peripheral) { case PERIPH_ID_UART0: + src = (readl(&clk->clk_src_peric0) >> 4) & 0x7; + div = (readl(&clk->clk_div_peric0) >> 8) & 0xf; + break; case PERIPH_ID_UART1: + src = (readl(&clk->clk_src_peric0) >> 8) & 0x7; + div = (readl(&clk->clk_div_peric0) >> 12) & 0xf; + break; case PERIPH_ID_UART2: + src = (readl(&clk->clk_src_peric0) >> 12) & 0x7; + div = (readl(&clk->clk_div_peric0) >> 16) & 0xf; + break; case PERIPH_ID_UART3: - src = readl(&clk->clk_src_peric0); - div = readl(&clk->clk_div_peric0); + src = (readl(&clk->clk_src_peric0) >> 16) & 0x7; + div = (readl(&clk->clk_div_peric0) >> 20) & 0xf; break; case PERIPH_ID_PWM0: case PERIPH_ID_PWM1: case PERIPH_ID_PWM2: case PERIPH_ID_PWM3: case PERIPH_ID_PWM4: - src = readl(&clk->clk_src_peric0); - div = readl(&clk->clk_div_peric3); + src = (readl(&clk->clk_src_peric0) >> 24) & 0x7; + div = (readl(&clk->clk_div_peric0) >> 28) & 0x7; break; case PERIPH_ID_SPI0: + src = (readl(&clk->clk_src_peric1) >> 20) & 0x7; + div = (readl(&clk->clk_div_peric1) >> 20) & 0xf; + break; case PERIPH_ID_SPI1: + src = (readl(&clk->clk_src_peric1) >> 24) & 0x7; + div = (readl(&clk->clk_div_peric1) >> 24) & 0xf; + break; case PERIPH_ID_SPI2: - src = readl(&clk->clk_src_peric1); - div = readl(&clk->clk_div_peric1); + src = (readl(&clk->clk_src_peric1) >> 28) & 0x7; + div = (readl(&clk->clk_div_peric1) >> 28) & 0xf; break; - case PERIPH_ID_SPI3: - case PERIPH_ID_SPI4: - src = readl(&clk->clk_src_isp); - div = readl(&clk->clk_div_isp1); + case PERIPH_ID_SPI3: /* aka SPI0_ISP */ + src = (readl(&clk->clk_src_isp) >> 16) & 0x7; + div = (readl(&clk->clk_div_isp0) >> 0) & 0x7; + break; + case PERIPH_ID_SPI4: /* aka SPI1_ISP */ + src = (readl(&clk->clk_src_isp) >> 12) & 0x7; + div = (readl(&clk->clk_div_isp1) >> 4) & 0x7; break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -244,12 +235,11 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1; return sclk / div; default: - printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral); + printk(BIOS_DEBUG, "%s: invalid peripheral %d", + __func__, peripheral); return -1; }; - src = (src >> bit_info->src_bit) & 0xf; - src = clock_select_to_pll(src); if (src < 0) { printk(BIOS_DEBUG, "%s: cannot determine source PLL", __func__); @@ -258,17 +248,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) sclk = get_pll_clk(src); - /* Ratio clock division for this peripheral */ - sub_div = (div >> bit_info->div_bit) & 0xf; - sub_clk = sclk / (sub_div + 1); - - /* Pre-ratio clock division for SDMMC0 and 2 */ - if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { - div = (div >> bit_info->prediv_bit) & 0xff; - return sub_clk / (div + 1); - } - - return sub_clk; + return sclk / (div + 1); } /* exynos5: return ARM clock frequency */

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Patch set updated for coreboot: 8f57885 exynos5420: correct the PMS value for CPLL
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4460 -gerrit commit 8f5788517c43fc4636a4e94f9b5baff530af03fe Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 16:04:07 2013 -0700 exynos5420: correct the PMS value for CPLL This patch matches the User Manual Table 7-2 about the PMS value for CPLL. This doesn't change the PLL frequency (before and after both make 666MHz) but this is the suggested PMSK values for obtaining 666. (Suggested as per user manual). This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/ Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: Ia33e1971ab88da761000d443792560476514626b Reviewed-on: https://gerrit.chromium.org/gerrit/65281 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 3521636..07bf5d9 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -113,7 +113,7 @@ void system_clock_init(void) /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(0x6f, 0x2, 0x1); + val = set_pll(0xde, 0x4, 0x1); writel(val, &clk->cpll_con0); while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) ;

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Patch set updated for coreboot: ec47443 exynos5420: add CPLL and DPLL to the known list of PLLs
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4461 -gerrit commit ec47443fab163372374dd71b1e5f7b3880667c35 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 16:16:40 2013 -0700 exynos5420: add CPLL and DPLL to the known list of PLLs This patch adds CPLL and DPLL to the known list of PLLs. This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/ Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af Reviewed-on: https://gerrit.chromium.org/gerrit/65282 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 2 ++ src/cpu/samsung/exynos5420/clock.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index a4e538d..b37c076 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -33,6 +33,8 @@ enum periph_id; #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 enum pll_src_bit { EXYNOS_SRC_CPLL = 1, diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index ed5b102..b8e27ff 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -103,6 +103,12 @@ unsigned long get_pll_clk(int pllreg) case SPLL: r = readl(&clk->spll_con0); break; + case CPLL: + r = readl(&clk->cpll_con0); + break; + case DPLL: + r = readl(&clk->dpll_con0); + break; default: printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); return 0;

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Patch set updated for coreboot: 2856aba kirby: Clean some cruft from mainboard.c
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4413 -gerrit commit 2856aba496675f16d442e58cfddb870fff903653 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Jul 30 22:43:47 2013 -0700 kirby: Clean some cruft from mainboard.c 1. Kirby doesn't have a backlight enable GPIO on the AP since that's handled entirely by the DP-to-LVDS bridge. 2. There is no tps65090 on the other side of the EC who's settings need to be adjusted. If we need to turn on the LCD or backlight power manually, it will have to be done in a different way. 3. The PMIC doesn't provide a 32KHz output for the audio codec. Change-Id: Iadc5f3aec4818805edf3f2517da9e6fee87085dc Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63883 Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/kirby/mainboard.c | 33 +-------------------------------- 1 file changed, 1 insertion(+), 32 deletions(-) diff --git a/src/mainboard/google/kirby/mainboard.c b/src/mainboard/google/kirby/mainboard.c index 9975202..064d0f1 100644 --- a/src/mainboard/google/kirby/mainboard.c +++ b/src/mainboard/google/kirby/mainboard.c @@ -172,7 +172,6 @@ static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */ static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */ static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ -static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ static void parade_dp_bridge_setup(void) { @@ -224,12 +223,6 @@ static void backlight_pwm(void) udelay(LCD_T6_DELAY_MS * 1000); } -static void backlight_en(void) -{ - /* Configure GPIO for LCD_BL_EN */ - gpio_direction_output(bl_en, 1); -} - //static struct video_info smdk5420_dp_config = { static struct video_info dp_video_info = { /* FIXME: fix video_info struct to use const for name */ @@ -273,33 +266,12 @@ static void gpio_init(void) exynos_pinmux_i2c10(); } -enum { - FET_CTRL_WAIT = 3 << 2, - FET_CTRL_ADENFET = 1 << 1, - FET_CTRL_ENFET = 1 << 0 -}; - -static void tps65090_thru_ec_fet_set(int index) -{ - uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET; - - if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { - printk(BIOS_ERR, - "Error sending i2c pass through command to EC.\n"); - return; - } -} - static void lcd_vdd(void) { - /* Enable FET6, lcd panel */ - tps65090_thru_ec_fet_set(6); } static void backlight_vdd(void) { - /* Enable FET1, backlight */ - tps65090_thru_ec_fet_set(1); } /* this happens after cpu_init where exynos resources are set */ @@ -332,7 +304,6 @@ static void mainboard_init(device_t dev) backlight_vdd(); backlight_pwm(); - backlight_en(); // Uncomment to get excessive GPIO output: // gpio_info(); @@ -372,11 +343,9 @@ static void mainboard_enable(device_t dev) clock_epll_set_rate(epll_hz); clock_select_i2s_clk_source(); clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); - - power_enable_xclkout(); } struct chip_operations mainboard_ops = { - .name = "Samsung/Google ARM Chromebook", + .name = "Google ARM Chromebook", .enable_dev = mainboard_enable, };

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Patch set updated for coreboot: 030e05a kirby: Neutralize wakeup.c and delete the mostly unused exynos5420.h
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4412 -gerrit commit 030e05afc255360c8433a0e5b9b535b1dc1fc5e8 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Jul 30 22:41:13 2013 -0700 kirby: Neutralize wakeup.c and delete the mostly unused exynos5420.h The function in wakeup.c isn't applicable on kirby. The only constant in exynos5420.h that was used was the speed of the 4th i2c bus. Instead of having a whole header file for that one constant used in one place, the constant is just moved inline along with the comment it had in the header. Change-Id: I5ad50c5eeaecbbf7865d76afb31a12d36c3371ee Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63882 Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/kirby/exynos5420.h | 34 --------------------------------- src/mainboard/google/kirby/mainboard.c | 2 -- src/mainboard/google/kirby/romstage.c | 4 +--- src/mainboard/google/kirby/wakeup.c | 4 +--- 4 files changed, 2 insertions(+), 42 deletions(-) diff --git a/src/mainboard/google/kirby/exynos5420.h b/src/mainboard/google/kirby/exynos5420.h deleted file mode 100644 index 21b704c..0000000 --- a/src/mainboard/google/kirby/exynos5420.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* I2C */ -#define I2C_0_SPEED 100000 -#define I2C_4_SPEED 1000000 /* 1MHz */ -#define I2C_SLAVE 0 - -/* Voltages */ -#define VDD_ARM_MV 1300 // 1.3V -#define VDD_INT_UV 1012500 // 1.0125V -#define VDD_MIF_MV 1000 // 1.0V -#define VDD_G3D_MV 1200 // 1.2V -#define VDD_LDO2_MV 1500 // 1.5V -#define VDD_LDO3_MV 1800 // 1.8V -#define VDD_LDO5_MV 1800 // 1.8V -#define VDD_LDO10_MV 1800 // 1.8V - diff --git a/src/mainboard/google/kirby/mainboard.c b/src/mainboard/google/kirby/mainboard.c index 98e591a..9975202 100644 --- a/src/mainboard/google/kirby/mainboard.c +++ b/src/mainboard/google/kirby/mainboard.c @@ -38,8 +38,6 @@ #include <ec/google/chromeec/ec.h> #include <stdlib.h> -#include "exynos5420.h" - /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB diff --git a/src/mainboard/google/kirby/romstage.c b/src/mainboard/google/kirby/romstage.c index 255f292..c11f712 100644 --- a/src/mainboard/google/kirby/romstage.c +++ b/src/mainboard/google/kirby/romstage.c @@ -40,8 +40,6 @@ #include <drivers/maxim/max77802/max77802.h> #include <device/i2c.h> -#include "exynos5420.h" - #define MMC0_GPIO_PIN (58) struct pmic_write @@ -89,7 +87,7 @@ static void setup_power(int is_resume) /* Initialize I2C bus to configure PMIC. */ exynos_pinmux_i2c4(); - i2c_init(4, I2C_4_SPEED, 0x00); + i2c_init(4, 1000000, 0x00); /* 1MHz */ printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); diff --git a/src/mainboard/google/kirby/wakeup.c b/src/mainboard/google/kirby/wakeup.c index a82b632..43bad6f 100644 --- a/src/mainboard/google/kirby/wakeup.c +++ b/src/mainboard/google/kirby/wakeup.c @@ -22,8 +22,6 @@ int wakeup_need_reset(void) { - /* The "wake up" event is not reliable (known as "bad wakeup") and needs - * reset if GPIO value is high. */ - return gpio_get_value(GPIO_Y10); + return 0; }

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coreboot-gerrit December 2013