coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 034c32f ARMv7: Fix location of CBMEM console in romstage
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4428 -gerrit commit 034c32ffa36dadaeb7977efee2b571881601ad90 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 31 16:28:44 2013 -0700 ARMv7: Fix location of CBMEM console in romstage The CBMEM console pointer in romstage is actually a zero byte array. This means CBMEM area has to live at the end of the allocations or else CBMEM console will overwrite whatever comes after it. Change-Id: Icc59e982b724a2d396370c3a5abd8898e08baf26 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63997 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/arch/armv7/romstage.ld | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 14c5bde..11a91cf 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -60,9 +60,25 @@ SECTIONS _erom = .; } + /* bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + .bss . : { + . = ALIGN(8); + _bss = .; + *(.bss) + *(.sbss) + *(COMMON) + } + + _ebss = .; + .car.data . (NOLOAD) : { + . = ALIGN(8); _car_data_start = .; *(.car.global_data); + . = ALIGN(8); /* The cbmem_console section comes last to take advantage of * a zero-sized array to hold the memconsole contents that * grows to a bound of CONFIG_CONSOLE_CAR_BUFFER_SIZE. However, @@ -73,20 +89,17 @@ SECTIONS _car_data_end = .; } - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - .bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; _end = .; + /* TODO: check if we are running out of SRAM. Below check is not good + * enough though because SRAM has different size on different CPUs + * and not all SRAM is available to the romstage. On Exynos, some is + * used for BL1, the bootblock and the stack. + * + * _bogus = ASSERT((_end - _start + EXPECTED_CBMEM_CONSOLE_SIZE <= \ + * 0x54000), "SRAM area is too full"); + */ + /* Discard the sections we don't need/want */ /DISCARD/ : { *(.comment)

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Patch set updated for coreboot: eab1516 Pit: correctly initialize trust zone
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4430 -gerrit commit eab1516aa51b6d7b80abdbe2eda927a1b6aa25e4 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Aug 5 15:56:37 2013 -0700 Pit: correctly initialize trust zone This ensures that various trust zone things are reset, which is important because the kernel assumes they are. Change-Id: Ie02ea89885621f58a3ccc4f1729617208a264153 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64697 Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.c | 23 ++++++++++++++++++ src/cpu/samsung/exynos5420/cpu.h | 51 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 49e1692..e95b438 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,6 +36,26 @@ static unsigned int cpu_id; static unsigned int cpu_rev; +/* Setting TZPC[TrustZone Protection Controller] + * We pretty much disable it all, as the kernel + * expects it that way -- and that's not the default. + */ +static void tzpc_init(void) +{ + struct exynos_tzpc *tzpc; + unsigned int addr; + + for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { + tzpc = (struct exynos_tzpc *)addr; + if (addr == TZPC0_BASE) + writel(R0SIZE, &tzpc->r0size); + writel(DECPROTXSET, &tzpc->decprot0set); + writel(DECPROTXSET, &tzpc->decprot1set); + writel(DECPROTXSET, &tzpc->decprot2set); + writel(DECPROTXSET, &tzpc->decprot3set); + } +} + static void set_cpu_id(void) { u32 pro_id = (read32((void *)EXYNOS_PRO_ID) & 0x00FFF000) >> 12; @@ -133,6 +154,8 @@ static void cpu_enable(device_t dev) exynos_displayport_init(dev, lcdbase, fb_size); set_cpu_id(); + + tzpc_init(); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 8913120..1cc6e6d 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -92,6 +92,31 @@ /* Distance between each Trust Zone PC register set */ #define TZPC_BASE_OFFSET 0x10000 +/* TZPC : Register Offsets */ +#define TZPC0_BASE 0x10100000 +#define TZPC1_BASE 0x10110000 +#define TZPC2_BASE 0x10120000 +#define TZPC3_BASE 0x10130000 +#define TZPC4_BASE 0x10140000 +#define TZPC5_BASE 0x10150000 +#define TZPC6_BASE 0x10160000 +#define TZPC7_BASE 0x10170000 +#define TZPC8_BASE 0x10180000 +#define TZPC9_BASE 0x10190000 +#define TZPC10_BASE 0x100E0000 +#define TZPC11_BASE 0x100F0000 + +/* + * TZPC Register Value : + * R0SIZE: 0x0 : Size of secured ram + */ +#define R0SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF /* EXYNOS5420 Common*/ #define EXYNOS5420_I2C_SPACING 0x10000 @@ -207,6 +232,32 @@ extern struct tmu_info exynos5420_tmu_info; #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) +struct exynos_tzpc { + u32 r0size; + u8 res1[0x7FC]; + u32 decprot0stat; + u32 decprot0set; + u32 decprot0clr; + u32 decprot1stat; + u32 decprot1set; + u32 decprot1clr; + u32 decprot2stat; + u32 decprot2set; + u32 decprot2clr; + u32 decprot3stat; + u32 decprot3set; + u32 decprot3clr; + u8 res2[0x7B0]; + u32 periphid0; + u32 periphid1; + u32 periphid2; + u32 periphid3; + u32 pcellid0; + u32 pcellid1; + u32 pcellid2; + u32 pcellid3; +}; + static inline u32 get_fb_base_kb(void) { return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;

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Patch set updated for coreboot: 9612c73 Snow: correctly disable trust zone hardware
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4431 -gerrit commit 9612c732fccf92d52e6023f8ffe2b7089a79a57f Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Aug 5 17:18:44 2013 -0700 Snow: correctly disable trust zone hardware The kernel assumes that trust zone is disabled. Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64722 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 25 ++++++++++++++++++++ src/cpu/samsung/exynos5250/cpu.h | 51 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index c363274..2354be1 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,6 +36,28 @@ static unsigned int cpu_id; static unsigned int cpu_rev; +/* Setting TZPC[TrustZone Protection Controller] */ +static void tzpc_init(void) +{ + struct exynos_tzpc *tzpc; + unsigned int addr; + + for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { + tzpc = (struct exynos_tzpc *)addr; + + if (addr == TZPC0_BASE) + writel(R0SIZE, &tzpc->r0size); + + writel(DECPROTXSET, &tzpc->decprot0set); + writel(DECPROTXSET, &tzpc->decprot1set); + + if (addr != TZPC9_BASE) { + writel(DECPROTXSET, &tzpc->decprot2set); + writel(DECPROTXSET, &tzpc->decprot3set); + } + } +} + static void set_cpu_id(void) { cpu_id = readl((void *)EXYNOS_PRO_ID); @@ -122,6 +145,8 @@ static void cpu_enable(device_t dev) exynos_displayport_init(dev, lcdbase, fb_size); set_cpu_id(); + + tzpc_init(); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 254106a..149de6a 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -91,6 +91,31 @@ /* Distance between each Trust Zone PC register set */ #define TZPC_BASE_OFFSET 0x10000 +/* TZPC : Register Offsets */ +#define TZPC0_BASE 0x10100000 +#define TZPC1_BASE 0x10110000 +#define TZPC2_BASE 0x10120000 +#define TZPC3_BASE 0x10130000 +#define TZPC4_BASE 0x10140000 +#define TZPC5_BASE 0x10150000 +#define TZPC6_BASE 0x10160000 +#define TZPC7_BASE 0x10170000 +#define TZPC8_BASE 0x10180000 +#define TZPC9_BASE 0x10190000 +#define TZPC10_BASE 0x100E0000 +#define TZPC11_BASE 0x100F0000 + +/* + * TZPC Register Value : + * R0SIZE: 0x0 : Size of secured ram + */ +#define R0SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF #define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE) #define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE) @@ -130,6 +155,32 @@ extern struct tmu_info exynos5250_tmu_info; #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) +struct exynos_tzpc { + u32 r0size; + u8 res1[0x7FC]; + u32 decprot0stat; + u32 decprot0set; + u32 decprot0clr; + u32 decprot1stat; + u32 decprot1set; + u32 decprot1clr; + u32 decprot2stat; + u32 decprot2set; + u32 decprot2clr; + u32 decprot3stat; + u32 decprot3set; + u32 decprot3clr; + u8 res2[0x7B0]; + u32 periphid0; + u32 periphid1; + u32 periphid2; + u32 periphid3; + u32 pcellid0; + u32 pcellid1; + u32 pcellid2; + u32 pcellid3; +}; + static inline u32 get_fb_base_kb(void) { return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;

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Patch set updated for coreboot: f6d868a exynos5250: Add mct_start to the timer init blob in timer_monotonic_get
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4419 -gerrit commit f6d868a8b49c9801e016eb07834deeceeff02dcc Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jul 31 22:50:21 2013 -0700 exynos5250: Add mct_start to the timer init blob in timer_monotonic_get A previous change removed init_timer from timer_monotonic_get because its old implementation set up the PWM based timer which was going away. It would still be a good idea to initialize the timer at that point, just not the pwm. Change-Id: I4816710ec2c9d5ca53b704c6b9397bcfac183fdc Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64160 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/monotonic_timer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/samsung/exynos5250/monotonic_timer.c b/src/cpu/samsung/exynos5250/monotonic_timer.c index d46d02a..57e3ae3 100644 --- a/src/cpu/samsung/exynos5250/monotonic_timer.c +++ b/src/cpu/samsung/exynos5250/monotonic_timer.c @@ -37,6 +37,7 @@ void timer_monotonic_get(struct mono_time *mt) uint64_t usecs_elapsed; if (!mono_counter.initialized) { + mct_start(); mono_counter.last_value = mct_raw_value(); mono_counter.initialized = 1; }

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Patch set updated for coreboot: 54494f0 pit: Get rid of the mostly unnecessary exynos5420.h
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4420 -gerrit commit 54494f082349bf2893126743ad631a769cf7ca28 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jul 31 23:21:34 2013 -0700 pit: Get rid of the mostly unnecessary exynos5420.h Like on kirby, this header had a single constant in it that was actually used. This change moves that constant inline and gets rid of the header file. Change-Id: Ibe380396f72fddb121fb6ceb3cee24f1b9a85738 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64163 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/exynos5420.h | 34 ---------------------------------- src/mainboard/google/pit/mainboard.c | 2 -- src/mainboard/google/pit/romstage.c | 4 +--- 3 files changed, 1 insertion(+), 39 deletions(-) diff --git a/src/mainboard/google/pit/exynos5420.h b/src/mainboard/google/pit/exynos5420.h deleted file mode 100644 index 21b704c..0000000 --- a/src/mainboard/google/pit/exynos5420.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* I2C */ -#define I2C_0_SPEED 100000 -#define I2C_4_SPEED 1000000 /* 1MHz */ -#define I2C_SLAVE 0 - -/* Voltages */ -#define VDD_ARM_MV 1300 // 1.3V -#define VDD_INT_UV 1012500 // 1.0125V -#define VDD_MIF_MV 1000 // 1.0V -#define VDD_G3D_MV 1200 // 1.2V -#define VDD_LDO2_MV 1500 // 1.5V -#define VDD_LDO3_MV 1800 // 1.8V -#define VDD_LDO5_MV 1800 // 1.8V -#define VDD_LDO10_MV 1800 // 1.8V - diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 827c18b..5c67df2 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -38,8 +38,6 @@ #include <ec/google/chromeec/ec.h> #include <stdlib.h> -#include "exynos5420.h" - /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 255f292..c11f712 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -40,8 +40,6 @@ #include <drivers/maxim/max77802/max77802.h> #include <device/i2c.h> -#include "exynos5420.h" - #define MMC0_GPIO_PIN (58) struct pmic_write @@ -89,7 +87,7 @@ static void setup_power(int is_resume) /* Initialize I2C bus to configure PMIC. */ exynos_pinmux_i2c4(); - i2c_init(4, I2C_4_SPEED, 0x00); + i2c_init(4, 1000000, 0x00); /* 1MHz */ printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__);

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Patch set updated for coreboot: 379e890 kirby: pit: Fix up wakeup_need_reset
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4421 -gerrit commit 379e890d2580ab3e41ff9151359dc884264514fd Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jul 31 23:40:55 2013 -0700 kirby: pit: Fix up wakeup_need_reset In a previous commit the contents of wakeup_need_reset were removed because the GPIO it referred to wasn't connected to anything on pit. I didn't realize at that time that that could have been because we hadn't tried getting suspend/resume working on pit and hadn't updated that file. On snow, the GPIO is the recovery mode pin. This change updates pit to have the right GPIO, kirby to read that GPIO, and makes the comments for both pit and kirby more explicit and spells out the fact that this is the recovery mode GPIO. Having a check here at all may still be a holdover from snow that isn't applicable to pit or kirby, but since there is a parallel as far as the recovery mode GPIO we might as well make them match while waiting for more information. Change-Id: Ic1f3f605a0fddf89e8f5668c7a8df30bdfb91d94 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64164 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/kirby/wakeup.c | 4 +++- src/mainboard/google/pit/wakeup.c | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/kirby/wakeup.c b/src/mainboard/google/kirby/wakeup.c index 43bad6f..02305b5 100644 --- a/src/mainboard/google/kirby/wakeup.c +++ b/src/mainboard/google/kirby/wakeup.c @@ -22,6 +22,8 @@ int wakeup_need_reset(void) { - return 0; + /* The "wake up" event is not reliable (known as "bad wakeup") and needs + * reset if the TPM reset mask GPIO value is high. */ + return gpio_get_value(GPIO_X06); } diff --git a/src/mainboard/google/pit/wakeup.c b/src/mainboard/google/pit/wakeup.c index a82b632..02305b5 100644 --- a/src/mainboard/google/pit/wakeup.c +++ b/src/mainboard/google/pit/wakeup.c @@ -23,7 +23,7 @@ int wakeup_need_reset(void) { /* The "wake up" event is not reliable (known as "bad wakeup") and needs - * reset if GPIO value is high. */ - return gpio_get_value(GPIO_Y10); + * reset if the TPM reset mask GPIO value is high. */ + return gpio_get_value(GPIO_X06); }

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Patch set updated for coreboot: 877f1ec exynos5420: set L2ACTLR parameters for A15 cores
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4441 -gerrit commit 877f1ec399f44d791aab1a78ac5ab9834b671277 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Aug 6 18:05:55 2013 -0700 exynos5420: set L2ACTLR parameters for A15 cores This patch does the following for the A15 cores: - Disable clean/evict push to external - Enable hazard detect timout - Prevent gating the L2 logic clock This is ported from https://gerrit.chromium.org/gerrit/#/c/60154 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536 Reviewed-on: https://gerrit.chromium.org/gerrit/64862 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 1940b88..bda46de 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -198,4 +198,20 @@ void exynos5420_config_l2_cache(void) */ val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); write_l2ctlr(val); + + val = read_l2actlr(); + + /* L2ACTLR[3]: Disable clean/evict push to external */ + val |= (1 << 3); + + /* L2ACTLR[7]: Enable hazard detect timeout for A15 */ + val |= (1 << 7); + + /* L2ACTLR[27]: Prevents stopping the L2 logic clock */ + val |= (1 << 27); + + write_l2actlr(val); + + /* Read the l2 control register to force things to take effect? */ + val = read_l2ctlr(); }

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Patch set updated for coreboot: 26a3098 snow: Set up the i2s0 pins during boot
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4440 -gerrit commit 26a30987b7103c8762bfc94a1e2c9d30da0d7551 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Aug 5 22:19:36 2013 -0700 snow: Set up the i2s0 pins during boot Change-Id: I6729a139091b40d8fd9ba2aa7a8c4e14216d95c5 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64879 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/google/snow/mainboard.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index b493652..aa11487 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -202,6 +202,7 @@ static void gpio_init(void) gpio_direction_output(GPIO_X15, 1); /* Set up the I2S busses. */ + exynos_pinmux_i2s0(); exynos_pinmux_i2s1(); }

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Patch set updated for coreboot: 0fbe5cd exynos5420: init APLL at 1800MHz
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4443 -gerrit commit 0fbe5cd1434abc9f745f98f135e1feed524267c8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 5 21:09:32 2013 -0700 exynos5420: init APLL at 1800MHz This initializes the APLL at 1800MHz. Change-Id: I366bf4e75510847ab93d9c9f214a49c731cca08a Reviewed-on: https://gerrit.chromium.org/gerrit/64745 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index b62ebe4..3521636 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -65,7 +65,7 @@ void system_clock_init(void) /* Set APLL */ writel(APLL_CON1_VAL, &clk->apll_con1); - val = set_pll(0xc8, 0x3, 0x1); + val = set_pll(225, 3, 0); /* FOUT=1800MHz */ writel(val, &clk->apll_con0); while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0) ;

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Patch set updated for coreboot: 0ecda28 exynos5xxx: use oscillator clock when changing ARM frequency
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4442 -gerrit commit 0ecda28b0d20dd466be652048cc75d04894c6ffa Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Aug 6 15:17:37 2013 -0700 exynos5xxx: use oscillator clock when changing ARM frequency Switch ARM clock source when changing the APLL frequency to avoid stability issues. This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8 Reviewed-on: https://gerrit.chromium.org/gerrit/64838 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/clock_init.c | 6 ++++++ src/cpu/samsung/exynos5250/setup.h | 2 ++ src/cpu/samsung/exynos5420/clock_init.c | 12 ++++++++++++ src/cpu/samsung/exynos5420/setup.h | 3 +++ 4 files changed, 23 insertions(+) diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 2cfdaf4..bfcf844 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -102,6 +102,9 @@ void system_clock_init(struct mem_timings *mem, val = readl(&clk->div_stat_cpu1); } while (0 != val); + /* switch A15 clock source to OSC clock before changing APLL */ + clrbits_le32(&clk->src_cpu, APLL_FOUT); + /* Set APLL */ writel(APLL_CON1_VAL, &clk->apll_con1); val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, @@ -110,6 +113,9 @@ void system_clock_init(struct mem_timings *mem, while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) ; + /* now it is safe to switch to APLL */ + setbits_le32(&clk->src_cpu, APLL_FOUT); + /* Set MPLL */ writel(MPLL_CON1_VAL, &clk->mpll_con1); val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 2ed4f22..c65747b 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -38,6 +38,8 @@ struct exynos5_phy_control; #define TZPC8_BASE 0x10180000 #define TZPC9_BASE 0x10190000 +#define APLL_FOUT (1 << 0) + /* APLL_CON1 */ #define APLL_CON1_VAL (0x00203800) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 069fd8f..b62ebe4 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -60,6 +60,9 @@ void system_clock_init(void) writel(HPM_RATIO, &clk->clk_div_cpu1); writel(CLK_DIV_CPU0_VAL, &clk->clk_div_cpu0); + /* switch A15 clock source to OSC clock before changing APLL */ + clrbits_le32(&clk->clk_src_cpu, APLL_FOUT); + /* Set APLL */ writel(APLL_CON1_VAL, &clk->apll_con1); val = set_pll(0xc8, 0x3, 0x1); @@ -67,9 +70,15 @@ void system_clock_init(void) while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0) ; + /* now it is safe to switch to APLL */ + setbits_le32(&clk->clk_src_cpu, APLL_FOUT); + writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc); writel(CLK_DIV_KFC_VAL, &clk->clk_div_kfc0); + /* switch A7 clock source to OSC clock before changing KPLL */ + clrbits_le32(&clk->clk_src_kfc, KPLL_FOUT); + /* Set KPLL*/ writel(KPLL_CON1_VAL, &clk->kpll_con1); val = set_pll(0xc8, 0x2, 0x2); @@ -77,6 +86,9 @@ void system_clock_init(void) while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) ; + /* now it is safe to switch to KPLL */ + setbits_le32(&clk->clk_src_kfc, KPLL_FOUT); + /* Set MPLL */ writel(MPLL_CON1_VAL, &clk->mpll_con1); val = set_pll(0xc8, 0x3, 0x1); diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index e89ed8e..c2f69d2 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -45,6 +45,9 @@ struct exynos5_phy_control; #define TZPC8_BASE 0x10180000 #define TZPC9_BASE 0x10190000 +#define APLL_FOUT (1 << 0) +#define KPLL_FOUT (1 << 0) + /* APLL_CON1 */ #define APLL_CON1_VAL (0x0020f300)

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coreboot-gerrit December 2013