coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: dad3433 exynos5420: correct the PMS value for CPLL
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4460 -gerrit commit dad3433a759d0aac43027c1292420f468247cb8e Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 16:04:07 2013 -0700 exynos5420: correct the PMS value for CPLL This patch matches the User Manual Table 7-2 about the PMS value for CPLL. This doesn't change the PLL frequency (before and after both make 666MHz) but this is the suggested PMSK values for obtaining 666. (Suggested as per user manual). This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/ Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: Ia33e1971ab88da761000d443792560476514626b Reviewed-on: https://gerrit.chromium.org/gerrit/65281 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 3521636..07bf5d9 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -113,7 +113,7 @@ void system_clock_init(void) /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(0x6f, 0x2, 0x1); + val = set_pll(0xde, 0x4, 0x1); writel(val, &clk->cpll_con0); while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) ;

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Patch set updated for coreboot: b0170fe exynos5420: add CPLL and DPLL to the known list of PLLs
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4461 -gerrit commit b0170fe293efde2baa70d2f8baff9645b73593ab Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 8 16:16:40 2013 -0700 exynos5420: add CPLL and DPLL to the known list of PLLs This patch adds CPLL and DPLL to the known list of PLLs. This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/ Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af Reviewed-on: https://gerrit.chromium.org/gerrit/65282 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 2 ++ src/cpu/samsung/exynos5420/clock.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index a4e538d..b37c076 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -33,6 +33,8 @@ enum periph_id; #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 enum pll_src_bit { EXYNOS_SRC_CPLL = 1, diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index ed5b102..b8e27ff 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -103,6 +103,12 @@ unsigned long get_pll_clk(int pllreg) case SPLL: r = readl(&clk->spll_con0); break; + case CPLL: + r = readl(&clk->cpll_con0); + break; + case DPLL: + r = readl(&clk->dpll_con0); + break; default: printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); return 0;

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Patch set updated for coreboot: c31eb36 exynos5420: Set SPLL to 400MHz
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4464 -gerrit commit c31eb3619d09671960d6fa2614c53fc5dfa2e4cf Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 9 18:59:02 2013 -0700 exynos5420: Set SPLL to 400MHz Increase SPLL to 400MHz from 300MHz as we set SPLL as the switching parent for ARM and KFC. This value is as per recommendation of the hardware team. This is ported from https://gerrit.chromium.org/gerrit/62618 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223 Reviewed-on: https://gerrit.chromium.org/gerrit/65432 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 07bf5d9..8be286d 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -141,7 +141,7 @@ void system_clock_init(void) /* Set SPLL */ writel(SPLL_CON1_VAL, &clk->spll_con1); - val = set_pll(0xc8, 0x2, 0x3); + val = set_pll(200, 0x3, 0x2); /* 400MHz */ writel(val, &clk->spll_con0); while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) ;

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Patch set updated for coreboot: c0ab219 pit: disable LCD FETs before doing any graphics init
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4470 -gerrit commit c0ab219040be9329a5b233da7513e54be5ec3c60 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 1 19:09:21 2013 -0700 pit: disable LCD FETs before doing any graphics init This ensures that the LCD FETs are off before we do graphics init. FIXME: The location of the code is sub-optimal and should probably be done in romstage, but there are __PRE_RAM__ considerations to take into account. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I0844030d0a0e51eee1d29f1762f0b495777268df Reviewed-on: https://gerrit.chromium.org/gerrit/64305 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index bda46de..5ff345e 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -33,6 +33,8 @@ #include "usb.h" #include "chip.h" +#include <ec/google/chromeec/ec.h> + static unsigned int cpu_id; static unsigned int cpu_rev; @@ -141,6 +143,17 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); } +static void tps65090_thru_ec_fet_disable(int index) +{ + uint8_t value = 0; + + if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { + printk(BIOS_ERR, + "Error sending i2c pass through command to EC.\n"); + return; + } +} + static void cpu_enable(device_t dev) { unsigned long fb_size = FB_SIZE_KB * KiB; @@ -149,6 +162,14 @@ static void cpu_enable(device_t dev) ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); + /* + * Disable LCD FETs before we do anything with the display. + * FIXME(dhendrix): This is a gross hack and should be done + * elsewhere (romstage?). + */ + tps65090_thru_ec_fet_disable(1); + tps65090_thru_ec_fet_disable(6); + exynos_displayport_init(dev, lcdbase, fb_size); set_cpu_id();

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Patch set updated for coreboot: b1b9e4e exynos5420: Assign corect parent PLLs
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4469 -gerrit commit b1b9e4e583a451b97fbd379e2b1f8ecc16e12119 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 12 14:52:45 2013 -0700 exynos5420: Assign corect parent PLLs Assign correct parent PLL's for the following clocks: ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz) PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz) MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz) ACLK_266 (DPLL->MPLL) (300 -> 266MHz) ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz) ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz) ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz) MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz) MUX_MPHY_REFCLK (MPLL->OSC) MUX_UNIPRO (MPLL->OSC) MUX_MIPI1 (EPLL->OSC) MUX_DP1_EXT_VID (EPLL->OSC) MUX_FIMD1_OPT (EPLL->OSC) MUX_IPLL(IPLL->OSC) This also corrects the clock dividers for few of the clocks, as the clock parent changes affect the final frequency of the clocks. This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/ Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8 Reviewed-on: https://gerrit.chromium.org/gerrit/65620 Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- src/cpu/samsung/exynos5420/setup.h | 17 +++++++++-------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 8be286d..658b255 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -214,7 +214,7 @@ void system_clock_init(void) writel(CLK_DIV_G2D, &clk->clk_div_g2d); writel(CLK_SRC_CPU_VAL, &clk->clk_src_cpu); - writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top6); + writel(CLK_SRC_TOP6_VAL, &clk->clk_src_top6); writel(CLK_SRC_CDREX_VAL, &clk->clk_src_cdrex); writel(CLK_SRC_KFC_VAL, &clk->clk_src_kfc); } diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index c2f69d2..794d4e1 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -225,18 +225,19 @@ struct exynos5_phy_control; #define CLK_DIV_CPU0_VAL 0x01440020 /* CLK_SRC_TOP */ -#define CLK_SRC_TOP0_VAL 0x12222222 -#define CLK_SRC_TOP1_VAL 0x00100200 -#define CLK_SRC_TOP2_VAL 0x11101000 +#define CLK_SRC_TOP0_VAL 0x11101102 +#define CLK_SRC_TOP1_VAL 0x00200000 +#define CLK_SRC_TOP2_VAL 0x11101010 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111110 +#define CLK_SRC_TOP5_VAL 0x11111111 +#define CLK_SRC_TOP6_VAL 0x11110111 #define CLK_SRC_TOP7_VAL 0x00022200 /* CLK_DIV_TOP */ -#define CLK_DIV_TOP0_VAL 0x23713311 -#define CLK_DIV_TOP1_VAL 0x13100B00 -#define CLK_DIV_TOP2_VAL 0x11101100 +#define CLK_DIV_TOP0_VAL 0x22512211 +#define CLK_DIV_TOP1_VAL 0x13200900 +#define CLK_DIV_TOP2_VAL 0x11101110 /* APLL_LOCK */ #define APLL_LOCK_VAL (0x320) @@ -439,7 +440,7 @@ struct exynos5_phy_control; #define CLK_DIV_ISP2_VAL 0x1 /* CLK_SRC_DISP1_0 */ -#define CLK_SRC_DISP1_0_VAL 0x10666600 +#define CLK_SRC_DISP1_0_VAL 0x10006000 #define CLK_DIV_DISP1_0_VAL 0x01050210 /*

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Patch set updated for coreboot: 50214f8 exynos5420: don't assume MPLL for i2c parent clock
by Patrick Georgi 21 Dec '13

21 Dec '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4468 -gerrit commit 50214f893dd0dd58911bcf3760265c4a58c92d3d Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 12 13:24:24 2013 -0700 exynos5420: don't assume MPLL for i2c parent clock This reads the clock select field for MUX_ACLK_66_SEL in the CLK_SRC_TOP1 register in order to obtain the source clock rate for I2C peripherals. Before we were always assuming that the source was the MPLL. Unfortunately not all fields in the CLK_SRC_TOPn registers are enumerated the same with regard to clock select. So this is just a one-off for now. This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f Reviewed-on: https://gerrit.chromium.org/gerrit/65611 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5420/clock.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 783679a..34d3fb5 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -231,7 +231,23 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case PERIPH_ID_I2C8: case PERIPH_ID_I2C9: case PERIPH_ID_I2C10: - sclk = get_pll_clk(MPLL); + /* + * I2C block parent clock selection is different from other + * peripherals, so we handle it all here. + * TODO: Add a helper function like with the peripheral clock + * select fields? + */ + src = (readl(&clk->clk_src_top1) >> 8) & 0x3; + if (src == 0x0) + src = CPLL; + else if (src == 0x1) + src = DPLL; + else if (src == 0x2) + src = MPLL; + else + return -1; + + sclk = get_pll_clk(src); div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1; return sclk / div; default:

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Patch merged into coreboot/master: caa4568 Snow: correctly disable trust zone hardware
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit caa4568964966df172a6beebc1761d779869d1be Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Aug 5 17:18:44 2013 -0700 Snow: correctly disable trust zone hardware The kernel assumes that trust zone is disabled. Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64722 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> See http://review.coreboot.org/4431 for details. -gerrit

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Patch merged into coreboot/master: f7bae4b Pit: correctly initialize trust zone
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit f7bae4bdf1fa6668228900a4976c21bbde2ef6bf Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Aug 5 15:56:37 2013 -0700 Pit: correctly initialize trust zone This ensures that various trust zone things are reset, which is important because the kernel assumes they are. Change-Id: Ie02ea89885621f58a3ccc4f1729617208a264153 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64697 Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/4430 for details. -gerrit

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Patch merged into coreboot/master: a660e87 ARMv7: Fix location of CBMEM console in romstage
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit a660e87a3b8dff7bfbea6b2890ad9e446a1f2a95 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 31 16:28:44 2013 -0700 ARMv7: Fix location of CBMEM console in romstage The CBMEM console pointer in romstage is actually a zero byte array. This means CBMEM area has to live at the end of the allocations or else CBMEM console will overwrite whatever comes after it. Change-Id: Icc59e982b724a2d396370c3a5abd8898e08baf26 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63997 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> See http://review.coreboot.org/4428 for details. -gerrit

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Patch merged into coreboot/master: 8a136a8 pit: update PMIC write sequence in romstage
by gerrit＠coreboot.org 21 Dec '13

21 Dec '13

the following patch was just integrated into master: commit 8a136a87e38dfcbdfb5284914dcd70b56eb18599 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 1 18:57:52 2013 -0700 pit: update PMIC write sequence in romstage This update the PMIC write sequence to be correct for newer board revisions. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I2210b0d1945fb19c96a674c8fad1b0ff5a4a381e Reviewed-on: https://gerrit.chromium.org/gerrit/64304 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/4427 for details. -gerrit

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coreboot-gerrit December 2013