Idwer Vollering (vidwer@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6160 -gerrit commit 1ffc56df8e63dd1d083efa893ad512df563ea3e3 Author: Idwer Vollering <vidwer@gmail.com> Date: Mon Jun 30 03:03:00 2014 +0200 [4/4] HP DL120G5: add the mainboard Change-Id: I73719ab59fe15847830c6785410b0474e86a797f Signed-off-by: Ruud Schramp <schramp@holmes.nl> Signed-off-by: Idwer Vollering <vidwer@gmail.com> --- SerialICE/Kconfig | 4 + SerialICE/mainboard/hp_dl120_g5.c | 162 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 1a3a78c..0e1e27a 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -137,6 +137,9 @@ config BOARD_JETWAY_NF81_T56N_LF bool "Jetway NF81-T56N-LF" select BUILD_XMMSTACK +config BOARD_HP_DL120G5 + bool "HP DL120 G5" + endchoice config BOARD_INIT @@ -172,6 +175,7 @@ config BOARD_INIT default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 default "jetway_nf81_t56n_lf.c" if BOARD_JETWAY_NF81_T56N_LF + default "hp_dl120_g5.c" if BOARD_HP_DL120G5 config SOUTHBRIDGE_INIT string diff --git a/SerialICE/mainboard/hp_dl120_g5.c b/SerialICE/mainboard/hp_dl120_g5.c new file mode 100644 index 0000000..b5a0912 --- /dev/null +++ b/SerialICE/mainboard/hp_dl120_g5.c @@ -0,0 +1,162 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2011 Netherlands Forensic Institute + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="HP DL120 G5 "; + +#include "../bmc/ipmi.c" + +/* Hardware specific functions */ + +#define RCBA 0xfed1c000 +#define GCS 0x3410 +#define RCBA32(x) *((volatile u32 *)(RCBA + x)) + +/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ +static void pnp_enter_ext_func_mode_pilot(u16 dev) +{ +outb(0x5A, dev); +} + +static void pnp_exit_ext_func_mode_pilot(u16 dev) +{ +outb(0xA5, dev); +} + + + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + // Set up RCBA (CHECKED RUUD) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); + +#if 1 + // port80 writes go to LPC: + reg32 = RCBA32(GCS); + reg32 = reg32 & ~0x04; + RCBA32(GCS) = reg32; + outb(0x23, 0x80); +#endif + + // Enable Serial IRQ +#define SIRQ_CNTL 0x64 + pci_write_config8(PCI_ADDR(0, 0x1f, 0, SIRQ_CNTL), 0xd0); + // Set COM1 decode range + // (COMA DECODE RANGE 3F8, COMB DECODE RANGE 2F8) +#define LPC_IO_DEC 0x80 + pci_write_config16(PCI_ADDR(0, 0x1f, 0, LPC_IO_DEC), 0x0010); + +#define LPC_EN 0x82 + // Enable COM1 (RUUD: why not COMB as well?) + // COMA enable, COMB disable LPT enable, FDD enable, KPOC enable, + // superIO enable +// pci_write_config16(PCI_ADDR(0, 0x1f, 0, LPC_EN), 0x140d); + pci_write_config16(PCI_ADDR(0, 0x1f, 0, LPC_EN), 0x3f0f); + + // Enable SIO PM Events at 0x680 + // bit0: enable=1 + // bit2-15 range (0xCA1) + // bit18-23 mask (0x000) +#define GEN1_DEC 0x84 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, GEN1_DEC), 0x00000CA1); + // bit0: enable=1 + // bit2-15 range (0x680) + // bit18-23 mask (0x07c) +#define GEN2_DEC 0x88 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, GEN2_DEC), 0x007c0681); +#define GEN3_DEC 0x8C +// pci_write_config32(PCI_ADDR(0, 0x1f, 0, GEN3_DEC), 0x000F00A1); + + + // Disable watchdog +#define PMBASE 0x500 +#define TCOBASE (PMBASE + 0x60) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); + reg16 = inw(TCOBASE + 0x08); + reg16 |= (1 << 11); + outw(reg16, TCOBASE + 0x08); + outw(0x0008, TCOBASE + 0x04); + outw(0x0002, TCOBASE + 0x06); +} + +static void superio_init(void) +{ + pnp_enter_ext_func_mode_pilot(0x2e); + + pnp_set_logical_device(0x2e, 2); // COM-A + pnp_set_enable(0x2e, 0); + pnp_set_iobase0(0x2e, 0x3f8); + pnp_set_irq0(0x2e, 4); + pnp_set_enable(0x2e, 1); + + pnp_exit_ext_func_mode_pilot(0x2e); + pnp_enter_ext_func_mode_pilot(0x2e); + + pnp_set_logical_device(0x2e, 8 ); // IPMI ?? protocol + pnp_set_enable(0x2e, 0); + pnp_set_iobase0(0x2e, 0xCA0); + pnp_set_iobase1(0x2e, 0xCA1); + pnp_set_enable(0x2e, 1); + + pnp_exit_ext_func_mode_pilot(0x2e); + pnp_enter_ext_func_mode_pilot(0x2e); + + pnp_set_logical_device(0x2e, 9 ); // IPMI kb protocol + pnp_set_enable(0x2e, 0); + pnp_set_iobase0(0x2e, 0xCA2); + pnp_set_iobase1(0x2e, 0xCA3); + pnp_set_enable(0x2e, 1); +/* + outb(pnp_read_register(0x2e,0x60),0x80); + outb(pnp_read_register(0x2e,0x61),0x80); + outb(pnp_read_register(0x2e,0x62),0x80); + outb(pnp_read_register(0x2e,0x63),0x80); + READBACK TEST gives expected result +*/ + pnp_exit_ext_func_mode_pilot(0x2e); + +} + +static void chipset_init(void) +{ + outb(0x01,0x80); + southbridge_init(); + outb(0x02,0x80); + superio_init(); + outb(0x03,0x80); + setup_early_ipmi_serial(); + outb(0x04,0x80); +/* + { + int b; + for (b=0;b<0x10;b++) + { + outb(b,0x80); + int c; + for(c=0;c<32000;c++) + (void) inb(0x80); + }; + }; +*/ +} +